From 93878a4dccd7dd4cb2fb3848bd25cf82e24c6c26 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Sat, 29 Oct 2022 00:30:35 +0200 Subject: [PATCH] code cleanup in transition --- code/tomcat_tools.vhd | 129 +++++++++++++++++++----------------------- 1 file changed, 58 insertions(+), 71 deletions(-) diff --git a/code/tomcat_tools.vhd b/code/tomcat_tools.vhd index 1bb517b..21b65f1 100644 --- a/code/tomcat_tools.vhd +++ b/code/tomcat_tools.vhd @@ -3,9 +3,8 @@ library ieee; use ieee.numeric_std.all; library work; - use work.trb_net_components.all; +-- use work.trb_net_components.all; use work.trb_net_std.all; - use work.trb3_components.all; use work.config.all; entity tomcat_tools is @@ -46,38 +45,38 @@ end entity; architecture tomcat_tools_arch of tomcat_tools is -signal bus_debug_rx_out, bus_flash_rx_out, busflash_rx, - busflashset_rx, busctrl_rx, busi2c_rx : CTRLBUS_RX; -signal bus_debug_tx_in, bus_flash_tx_in, busflash_tx, - busflashset_tx, busctrl_tx, busi2c_tx : CTRLBUS_TX; + signal bus_debug_rx_out, bus_flash_rx_out, busflash_rx, + busflashset_rx, busctrl_rx, busi2c_rx : CTRLBUS_RX; + signal bus_debug_tx_in, bus_flash_tx_in, busflash_tx, + busflashset_tx, busctrl_tx, busi2c_tx : CTRLBUS_TX; -signal flashset_active, debug_active : std_logic; -signal flash_cs_i, flash_clk_i, flash_out_i : std_logic; -signal flash_cs_s, flash_clk_s, flash_out_s : std_logic; + signal flashset_active, debug_active : std_logic; + signal flash_cs_i, flash_clk_i, flash_out_i : std_logic; + signal flash_cs_s, flash_clk_s, flash_out_s : std_logic; -signal debug_rx : std_logic; -signal debug_tx : std_logic; -signal debug_status : std_logic_vector(31 downto 0); -signal debug_spi : std_logic_vector(31 downto 0); + signal debug_rx : std_logic; + signal debug_tx : std_logic; + signal debug_status : std_logic_vector(31 downto 0); + signal debug_spi : std_logic_vector(31 downto 0); -signal i2c_reg0_i : std_logic_vector(31 downto 0) := x"0000_0000"; -signal i2c_reg1_i : std_logic_vector(31 downto 0) := x"0000_0000"; -signal i2c_reg2_i : std_logic_vector(31 downto 0) := x"0000_0000"; -signal i2c_reg3_i : std_logic_vector(31 downto 0) := x"0000_003f"; -signal i2c_status_i : std_logic_vector(31 downto 0); -signal sda_drv : std_logic; -signal scl_drv : std_logic; -signal i2c_start_x : std_logic; -signal i2c_start : std_logic; + signal i2c_reg0_i : std_logic_vector(31 downto 0) := x"0000_0000"; + signal i2c_reg1_i : std_logic_vector(31 downto 0) := x"0000_0000"; + signal i2c_reg2_i : std_logic_vector(31 downto 0) := x"0000_0000"; + signal i2c_reg3_i : std_logic_vector(31 downto 0) := x"0000_003f"; + signal i2c_status_i : std_logic_vector(31 downto 0); + signal sda_drv : std_logic; + signal scl_drv : std_logic; + signal i2c_start_x : std_logic; + signal i2c_start : std_logic; -signal add_reg0_i : std_logic_vector(31 downto 0) := x"0000_0000"; -signal add_reg1_i : std_logic_vector(31 downto 0) := x"0000_0000"; -signal add_reg2_i : std_logic_vector(31 downto 0) := x"0000_0000"; -signal add_reg3_i : std_logic_vector(31 downto 0) := x"0000_0000"; -signal add_reg4_i : std_logic_vector(31 downto 0) := x"0000_0000"; -signal add_reg5_i : std_logic_vector(31 downto 0) := x"0000_0000"; -signal add_reg6_i : std_logic_vector(31 downto 0) := x"0000_0000"; -signal add_reg7_i : std_logic_vector(31 downto 0) := x"0000_0000"; + signal add_reg0_i : std_logic_vector(31 downto 0) := x"0000_0000"; + signal add_reg1_i : std_logic_vector(31 downto 0) := x"0000_0000"; + signal add_reg2_i : std_logic_vector(31 downto 0) := x"0000_0000"; + signal add_reg3_i : std_logic_vector(31 downto 0) := x"0000_0000"; + signal add_reg4_i : std_logic_vector(31 downto 0) := x"0000_0000"; + signal add_reg5_i : std_logic_vector(31 downto 0) := x"0000_0000"; + signal add_reg6_i : std_logic_vector(31 downto 0) := x"0000_0000"; + signal add_reg7_i : std_logic_vector(31 downto 0) := x"0000_0000"; begin @@ -93,20 +92,18 @@ begin ) -- 0 flash, 1 flashset, 2 ctrl, 3 I2C port map( - CLK => CLK, - RESET => RESET, - - REGIO_RX => BUS_RX, - REGIO_TX => BUS_TX, - - BUS_RX(0) => busflash_rx, - BUS_RX(1) => busflashset_rx, - BUS_RX(2) => busctrl_rx, - BUS_RX(3) => busi2c_rx, - BUS_TX(0) => busflash_tx, - BUS_TX(1) => busflashset_tx, - BUS_TX(2) => busctrl_tx, - BUS_TX(3) => busi2c_tx, + CLK => CLK, + RESET => RESET, + REGIO_RX => BUS_RX, + REGIO_TX => BUS_TX, + BUS_RX(0) => busflash_rx, + BUS_RX(1) => busflashset_rx, + BUS_RX(2) => busctrl_rx, + BUS_RX(3) => busi2c_rx, + BUS_TX(0) => busflash_tx, + BUS_TX(1) => busflashset_tx, + BUS_TX(2) => busctrl_tx, + BUS_TX(3) => busi2c_tx, STAT_DEBUG => open ); @@ -117,13 +114,10 @@ begin port map( CLK_IN => CLK, RESET_IN => RESET, - BUS_RX => busflash_rx, BUS_TX => busflash_tx, - DO_REBOOT_IN => REBOOT_IN, PROGRAMN => PROGRAMN, - SPI_CS_OUT => flash_cs_i, SPI_SCK_OUT => flash_clk_i, SPI_SDO_OUT => flash_out_i, @@ -140,15 +134,11 @@ begin port map( CLK => CLK, RST => RESET, - BUS_RX => busflashset_rx, BUS_TX => busflashset_tx, - IS_ACTIVE => flashset_active, - BUS_MASTER_TX => bus_flash_rx_out, BUS_MASTER_RX => bus_flash_tx_in, - SPI_MOSI => flash_out_s, SPI_MISO => FLASH_IN, SPI_SCK => flash_clk_s, @@ -169,38 +159,35 @@ begin --------------------------------------------------------------------------- -- Debug Connection --------------------------------------------------------------------------- -gen_debug : if INCLUDE_DEBUG_INTERFACE = 1 generate +GEN_DEBUG : if( INCLUDE_DEBUG_INTERFACE = 1 ) generate THE_DEBUG : entity work.debuguart port map( - CLK => CLK, - RESET => RESET, - - RX_IN => debug_rx, - TX_OUT => debug_tx, - - DEBUG_ACTIVE => debug_active, - - BUS_DEBUG_TX => bus_debug_tx_in, - BUS_DEBUG_RX => bus_debug_rx_out, + CLK => CLK, + RESET => RESET, + RX_IN => debug_rx, + TX_OUT => debug_tx, + DEBUG_ACTIVE => debug_active, + BUS_DEBUG_TX => bus_debug_tx_in, + BUS_DEBUG_RX => bus_debug_rx_out, STATUS => debug_status ); -end generate; +end generate GEN_DEBUG; -gen_nodebug : if INCLUDE_DEBUG_INTERFACE = 0 generate +GEN_NODEBUG : if( INCLUDE_DEBUG_INTERFACE = 0 ) generate bus_debug_rx_out.write <= '0'; bus_debug_rx_out.read <= '0'; bus_debug_rx_out.timeout <= '0'; bus_debug_rx_out.addr <= (others => '0'); bus_debug_rx_out.data <= (others => '0'); - debug_tx <= 'Z'; - debug_active <= '0'; -end generate; + debug_tx <= 'Z'; + debug_active <= '0'; +end generate GEN_NODEBUG; --------------------------------------------------------------------------- -- Additional registers --------------------------------------------------------------------------- - THE_ADD_REG_PROC: process( CLK ) + PROC_ADD_REG: process( CLK ) begin if( rising_edge(CLK) ) then busctrl_tx.ack <= '0'; @@ -233,7 +220,7 @@ end generate; busctrl_tx.ack <= '1'; end if; end if; - end process THE_ADD_REG_PROC; + end process PROC_ADD_REG; ADDITIONAL_REG <= add_reg0_i; CTRL_REG <= add_reg1_i; @@ -249,7 +236,7 @@ end generate; --------------------------------------------------------------------------- -- I2C --------------------------------------------------------------------------- - THE_I2C_REG_PROC: process( CLK ) + PROC_I2C_REG: process( CLK ) begin if( rising_edge(CLK) ) then busi2c_tx.ack <= '0'; @@ -275,7 +262,7 @@ end generate; busi2c_tx.ack <= '1'; end if; end if; - end process THE_I2C_REG_PROC; + end process PROC_I2C_REG; i2c_start_x <= '1' when ((busi2c_rx.addr(1 downto 0) = b"10") and (busi2c_rx.write = '1')) else '0'; -- 2.43.0