From 93c6677be5e647eba8ed491f3406d647e5127129 Mon Sep 17 00:00:00 2001 From: Andreas Neiser Date: Wed, 18 Feb 2015 10:19:02 +0100 Subject: [PATCH] another fix --- ADC/sim/dqsinput_dummy.vhd | 4 ---- 1 file changed, 4 deletions(-) diff --git a/ADC/sim/dqsinput_dummy.vhd b/ADC/sim/dqsinput_dummy.vhd index 50146ed..a3d63af 100644 --- a/ADC/sim/dqsinput_dummy.vhd +++ b/ADC/sim/dqsinput_dummy.vhd @@ -25,8 +25,6 @@ end entity dqsinput_dummy; architecture arch of dqsinput_dummy is signal sclk_int : std_logic := '0'; signal q : std_logic_vector(19 downto 0) := (others => '0'); - type ch_t is array (0 to CHANNELS) of std_logic_vector(3 downto 0); - signal ch : ch_t; signal start_read, read_done : std_logic; signal readwords : integer; @@ -48,8 +46,6 @@ begin gen_data_mapping_bits : for k in 0 to 3 generate q_0(k * (CHANNELS + 1) + j) <= q(j * 4 + 3 - k); end generate; - -- finally, ch(i) is 4bits of 10bit ADC stream (MSB first) - q(4 * (j + 1) - 1 downto 4 * j) <= ch(j); end generate; datareader : process is -- 2.43.0