From 9473836e409b28b1ebbb9eba1aa3bb01e3c08da3 Mon Sep 17 00:00:00 2001
From: hadeshyp <hadeshyp>
Date: Tue, 19 Oct 2010 16:43:16 +0000
Subject: [PATCH] The ddr_off entity (DDR OBUF) for the med_IC component Boris

---
 xilinx/virtex4/ddr_off.vhd | 46 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 xilinx/virtex4/ddr_off.vhd

diff --git a/xilinx/virtex4/ddr_off.vhd b/xilinx/virtex4/ddr_off.vhd
new file mode 100644
index 0000000..5f1ec9e
--- /dev/null
+++ b/xilinx/virtex4/ddr_off.vhd
@@ -0,0 +1,46 @@
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.ALL;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+
+
+entity ddr_off is
+	port(
+      Clk: in  std_logic;
+      Data: in  std_logic_vector(1 downto 0);
+      Q: out  std_logic_vector(0 downto 0)
+	);
+end entity;
+
+
+
+architecture ddr_off_arch of ddr_off is
+
+
+
+
+
+begin
+
+
+	ODDR_inst : ODDR
+	generic map(
+		DDR_CLK_EDGE => "OPPOSITE_EDGE", 	-- "OPPOSITE_EDGE" or "SAME_EDGE"
+		INIT => '0',   						-- Initial value for Q port ('1' or '0')
+		SRTYPE => "SYNC") 					-- Reset Type ("ASYNC" or "SYNC")
+	port map (
+		Q => Q(0),   							-- 1-bit DDR output
+		C => Clk,    						-- 1-bit clock input
+		CE => '1',  						-- 1-bit clock enable input
+		D1 => Data(0),  					-- 1-bit data input (positive edge)
+		D2 => Data(1),  					-- 1-bit data input (negative edge)
+		R => '0',    						-- 1-bit reset input
+		S => '0'     						-- 1-bit set input
+	);
+
+
+
+end architecture;
\ No newline at end of file
-- 
2.43.0