From 9509076c81c9e94ecf79013a22c5a2eb6d9eb115 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 17 Aug 2017 16:05:55 +0200 Subject: [PATCH] Remove clock renaming to clk_200 in media interfaces --- media_interfaces/med_ecp3_sfp_sync.vhd | 13 ++++------ media_interfaces/med_ecp3_sfp_sync_4.vhd | 25 ++++++++----------- .../med_ecp3_sfp_sync_4_slave3.vhd | 24 ++++++++---------- media_interfaces/med_ecp5_sfp_sync.vhd | 12 ++++----- 4 files changed, 32 insertions(+), 42 deletions(-) diff --git a/media_interfaces/med_ecp3_sfp_sync.vhd b/media_interfaces/med_ecp3_sfp_sync.vhd index 6343359..b6a8265 100644 --- a/media_interfaces/med_ecp3_sfp_sync.vhd +++ b/media_interfaces/med_ecp3_sfp_sync.vhd @@ -58,7 +58,6 @@ architecture med_ecp3_sfp_sync_arch of med_ecp3_sfp_sync is attribute syn_hier of med_ecp3_sfp_sync_arch : architecture is "hard"; -- signal clk_200_i : std_logic; -signal clk_200_ref : std_logic; signal clk_rx_full, clk_rx_half : std_logic; signal clk_tx_full, clk_tx_half : std_logic; @@ -104,8 +103,6 @@ attribute nopad of hdinp, hdinn, hdoutp, hdoutn : signal is "true"; begin -clk_200_ref <= CLK_REF_FULL; - SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready -- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate @@ -127,7 +124,7 @@ gen_pcs0 : if SERDES_NUM = 0 generate hdinn_ch0 => hdinn, hdoutp_ch0 => hdoutp, hdoutn_ch0 => hdoutn, - txiclk_ch0 => clk_200_ref, + txiclk_ch0 => CLK_REF_FULL, rx_full_clk_ch0 => clk_rx_full, rx_half_clk_ch0 => clk_rx_half, tx_full_clk_ch0 => clk_tx_full, @@ -162,7 +159,7 @@ gen_pcs0 : if SERDES_NUM = 0 generate SCI_RD => sci_read_i, SCI_WRN => sci_write_i, - fpga_txrefclk => clk_200_ref, + fpga_txrefclk => CLK_REF_FULL, tx_serdes_rst_c => '0', tx_pll_lol_qd_s => tx_pll_lol, rst_qd_c => rst_qd, @@ -178,7 +175,7 @@ gen_pcs3 : if SERDES_NUM = 3 generate hdinn_ch3 => hdinn, hdoutp_ch3 => hdoutp, hdoutn_ch3 => hdoutn, - txiclk_ch3 => clk_200_ref, --clk_tx_full, --JM06 clk_tx_fullclk_200_i, JM150706 + txiclk_ch3 => CLK_REF_FULL, --clk_tx_full, --JM06 clk_tx_fullclk_200_i, JM150706 rx_full_clk_ch3 => clk_rx_full, rx_half_clk_ch3 => clk_rx_half, tx_full_clk_ch3 => clk_tx_full, @@ -213,7 +210,7 @@ gen_pcs3 : if SERDES_NUM = 3 generate SCI_RD => sci_read_i, SCI_WRN => sci_write_i, - fpga_txrefclk => clk_200_ref, + fpga_txrefclk => CLK_REF_FULL, tx_serdes_rst_c => '0', tx_pll_lol_qd_s => tx_pll_lol, rst_qd_c => rst_qd, @@ -238,7 +235,7 @@ THE_MED_CONTROL : entity work.med_sync_control CLK_SYS => SYSCLK, CLK_RXI => clk_rx_full, --clk_rx_full, CLK_RXHALF => clk_rx_half, - CLK_TXI => clk_200_ref, --clk_200_internal, --clk_tx_full, JM150706 + CLK_TXI => CLK_REF_FULL, --clk_200_internal, --clk_tx_full, JM150706 CLK_REF => CLK_INTERNAL_FULL, RESET => RESET, CLEAR => CLEAR, diff --git a/media_interfaces/med_ecp3_sfp_sync_4.vhd b/media_interfaces/med_ecp3_sfp_sync_4.vhd index 6d6100e..9501288 100644 --- a/media_interfaces/med_ecp3_sfp_sync_4.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_4.vhd @@ -61,7 +61,6 @@ architecture med_ecp3_sfp_sync_4_arch of med_ecp3_sfp_sync_4 is attribute syn_hier of med_ecp3_sfp_sync_4_arch : architecture is "hard"; signal clk_200_i : std_logic; -signal clk_200_ref : std_logic; signal clk_rx_full, clk_rx_half : std_logic_vector(3 downto 0); signal clk_tx_full, clk_tx_half : std_logic_vector(3 downto 0); @@ -106,8 +105,6 @@ attribute nopad of hdinp, hdinn, hdoutp, hdoutn : signal is "true"; begin -clk_200_ref <= CLK_REF_FULL; - -- SD_TXDIS_OUT <= (others =>'0'); --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready SD_TXDIS_OUT <= (others => RESET); ------------------------------------------------- @@ -119,8 +116,8 @@ SD_TXDIS_OUT <= (others => RESET); hdinn_ch0 => hdinn (0), hdoutp_ch0 => hdoutp(0), hdoutn_ch0 => hdoutn(0), - txiclk_ch0 => clk_200_ref, --clk_tx_full(0), - rxiclk_ch0 => clk_rx_full(0), --clk_200_ref, + txiclk_ch0 => CLK_REF_FULL, --clk_tx_full(0), + rxiclk_ch0 => clk_rx_full(0), --CLK_REF_FULL, rx_full_clk_ch0 => clk_rx_full(0), rx_half_clk_ch0 => clk_rx_half(0), tx_full_clk_ch0 => clk_tx_full(0), @@ -151,8 +148,8 @@ SD_TXDIS_OUT <= (others => RESET); hdinn_ch1 => hdinn (1), hdoutp_ch1 => hdoutp(1), hdoutn_ch1 => hdoutn(1), - txiclk_ch1 => clk_200_ref, --clk_tx_full(1), - rxiclk_ch1 => clk_rx_full(1), --clk_200_ref, + txiclk_ch1 => CLK_REF_FULL, --clk_tx_full(1), + rxiclk_ch1 => clk_rx_full(1), --CLK_REF_FULL, rx_full_clk_ch1 => clk_rx_full(1), rx_half_clk_ch1 => clk_rx_half(1), tx_full_clk_ch1 => clk_tx_full(1), @@ -183,8 +180,8 @@ SD_TXDIS_OUT <= (others => RESET); hdinn_ch2 => hdinn (2), hdoutp_ch2 => hdoutp(2), hdoutn_ch2 => hdoutn(2), - txiclk_ch2 => clk_200_ref, --clk_tx_full(2), - rxiclk_ch2 => clk_rx_full(2), --clk_200_ref, + txiclk_ch2 => CLK_REF_FULL, --clk_tx_full(2), + rxiclk_ch2 => clk_rx_full(2), --CLK_REF_FULL, rx_full_clk_ch2 => clk_rx_full(2), rx_half_clk_ch2 => clk_rx_half(2), tx_full_clk_ch2 => clk_tx_full(2), @@ -215,8 +212,8 @@ SD_TXDIS_OUT <= (others => RESET); hdinn_ch3 => hdinn (3), hdoutp_ch3 => hdoutp(3), hdoutn_ch3 => hdoutn(3), - txiclk_ch3 => clk_200_ref, --clk_tx_full(3), - rxiclk_ch3 => clk_rx_full(3), --clk_200_ref, --clk_tx_full(3), + txiclk_ch3 => CLK_REF_FULL, --clk_tx_full(3), + rxiclk_ch3 => clk_rx_full(3), --CLK_REF_FULL, --clk_tx_full(3), rx_full_clk_ch3 => clk_rx_full(3), rx_half_clk_ch3 => clk_rx_half(3), tx_full_clk_ch3 => clk_tx_full(3), @@ -254,7 +251,7 @@ SD_TXDIS_OUT <= (others => RESET); SCI_RD => sci_read_i, SCI_WRN => sci_write_i, - fpga_txrefclk => clk_200_ref, + fpga_txrefclk => CLK_REF_FULL, tx_serdes_rst_c => '0', tx_pll_lol_qd_s => tx_pll_lol, rst_qd_c => rst_qd(0), @@ -276,9 +273,9 @@ gen_control : for i in 0 to 3 generate ) port map( CLK_SYS => SYSCLK, - CLK_RXI => clk_rx_full(i), --clk_200_ref, + CLK_RXI => clk_rx_full(i), --CLK_REF_FULL, CLK_RXHALF => clk_rx_half(i), - CLK_TXI => clk_200_ref, --clk_tx_full(i), + CLK_TXI => CLK_REF_FULL, --clk_tx_full(i), CLK_REF => CLK_INTERNAL_FULL, RESET => RESET, CLEAR => CLEAR, diff --git a/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd b/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd index e2c807f..ad185b4 100644 --- a/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd @@ -60,8 +60,6 @@ architecture med_ecp3_sfp_sync_4_arch of med_ecp3_sfp_sync_4_slave3 is attribute syn_hier : string; attribute syn_hier of med_ecp3_sfp_sync_4_arch : architecture is "hard"; -signal clk_200_i : std_logic; -signal clk_200_ref : std_logic; signal clk_rx_full, clk_rx_half : std_logic_vector(3 downto 0); signal clk_tx_full, clk_tx_half : std_logic_vector(3 downto 0); signal clk_rxi : std_logic_vector(3 downto 0); @@ -107,8 +105,6 @@ attribute nopad of hdinp, hdinn, hdoutp, hdoutn : signal is "true"; begin -clk_200_ref <= CLK_REF_FULL; - SD_TXDIS_OUT <= (others =>'0'); --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready ------------------------------------------------- @@ -120,8 +116,8 @@ SD_TXDIS_OUT <= (others =>'0'); --not (rx_allow_q or not IS_SLAVE); --slave on hdinn_ch0 => hdinn (0), hdoutp_ch0 => hdoutp(0), hdoutn_ch0 => hdoutn(0), - txiclk_ch0 => clk_200_ref, --clk_tx_full(0), - rxiclk_ch0 => clk_rx_full(0), --clk_200_ref, + txiclk_ch0 => CLK_REF_FULL, --clk_tx_full(0), + rxiclk_ch0 => clk_rx_full(0), --CLK_REF_FULL, rx_full_clk_ch0 => clk_rx_full(0), rx_half_clk_ch0 => clk_rx_half(0), tx_full_clk_ch0 => clk_tx_full(0), @@ -152,8 +148,8 @@ SD_TXDIS_OUT <= (others =>'0'); --not (rx_allow_q or not IS_SLAVE); --slave on hdinn_ch1 => hdinn (1), hdoutp_ch1 => hdoutp(1), hdoutn_ch1 => hdoutn(1), - txiclk_ch1 => clk_200_ref, --clk_tx_full(1), - rxiclk_ch1 => clk_rx_full(1), --clk_200_ref, + txiclk_ch1 => CLK_REF_FULL, --clk_tx_full(1), + rxiclk_ch1 => clk_rx_full(1), --CLK_REF_FULL, rx_full_clk_ch1 => clk_rx_full(1), rx_half_clk_ch1 => clk_rx_half(1), tx_full_clk_ch1 => clk_tx_full(1), @@ -184,8 +180,8 @@ SD_TXDIS_OUT <= (others =>'0'); --not (rx_allow_q or not IS_SLAVE); --slave on hdinn_ch2 => hdinn (2), hdoutp_ch2 => hdoutp(2), hdoutn_ch2 => hdoutn(2), - txiclk_ch2 => clk_200_ref, --clk_tx_full(2), - rxiclk_ch2 => clk_rx_full(2), --clk_200_ref, + txiclk_ch2 => CLK_REF_FULL, --clk_tx_full(2), + rxiclk_ch2 => clk_rx_full(2), --CLK_REF_FULL, rx_full_clk_ch2 => clk_rx_full(2), rx_half_clk_ch2 => clk_rx_half(2), tx_full_clk_ch2 => clk_tx_full(2), @@ -216,7 +212,7 @@ SD_TXDIS_OUT <= (others =>'0'); --not (rx_allow_q or not IS_SLAVE); --slave on hdinn_ch3 => hdinn (3), hdoutp_ch3 => hdoutp(3), hdoutn_ch3 => hdoutn(3), - txiclk_ch3 => clk_200_ref, --clk_tx_full(3), + txiclk_ch3 => CLK_REF_FULL, --clk_tx_full(3), rx_full_clk_ch3 => clk_rx_full(3), --clk_rx_full(3), rx_half_clk_ch3 => clk_rx_half(3), tx_full_clk_ch3 => clk_tx_full(3), @@ -254,7 +250,7 @@ SD_TXDIS_OUT <= (others =>'0'); --not (rx_allow_q or not IS_SLAVE); --slave on SCI_RD => sci_read_i, SCI_WRN => sci_write_i, - fpga_txrefclk => clk_200_ref, + fpga_txrefclk => CLK_REF_FULL, tx_serdes_rst_c => '0', tx_pll_lol_qd_s => tx_pll_lol, rst_qd_c => rst_qd(0), @@ -264,7 +260,7 @@ SD_TXDIS_OUT <= (others =>'0'); --not (rx_allow_q or not IS_SLAVE); --slave on ); -clk_rxi <= (0 => clk_200_ref,1 => clk_200_ref,2 => clk_200_ref,3 => clk_rx_full(3)); +-- clk_rxi <= (0 => CLK_REF_FULL,1 => CLK_REF_FULL,2 => CLK_REF_FULL,3 => clk_rx_full(3)); gen_control : for i in 0 to 3 generate @@ -278,7 +274,7 @@ gen_control : for i in 0 to 3 generate CLK_SYS => SYSCLK, CLK_RXI => clk_rx_full(i), --clk_rxi(i), CLK_RXHALF => clk_rx_half(i), - CLK_TXI => clk_200_ref, --clk_tx_full(i), + CLK_TXI => CLK_REF_FULL, --clk_tx_full(i), CLK_REF => CLK_INTERNAL_FULL, RESET => RESET, CLEAR => CLEAR, diff --git a/media_interfaces/med_ecp5_sfp_sync.vhd b/media_interfaces/med_ecp5_sfp_sync.vhd index 033e235..08cca7d 100644 --- a/media_interfaces/med_ecp5_sfp_sync.vhd +++ b/media_interfaces/med_ecp5_sfp_sync.vhd @@ -131,7 +131,7 @@ gen_pcs0 : if SERDES_NUM = 0 generate serdes_sync_0_hdinn => hdinn, serdes_sync_0_hdoutp => hdoutp, serdes_sync_0_hdoutn => hdoutn, - serdes_sync_0_rxrefclk => clk_200_ref, + serdes_sync_0_rxrefclk => CLK_INTERNAL_FULL, serdes_sync_0_rx_pclk => clk_rx_full, serdes_sync_0_tx_pclk => clk_tx_full, @@ -173,7 +173,7 @@ gen_pcs0 : if SERDES_NUM = 0 generate serdes_sync_0_serdes_pdb => '1', serdes_sync_0_tx_serdes_rst_c => tx_serdes_rst, - serdes_sync_0_pll_refclki => clk_200_ref, + serdes_sync_0_pll_refclki => CLK_REF_FULL, -- sli_rst => '0', serdes_sync_0_pll_lol => tx_pll_lol, serdes_sync_0_rsl_disable => '1', @@ -199,7 +199,7 @@ THE_MED_CONTROL : entity work.med_sync_control CLK_RXI => clk_rx_full, --clk_rx_full, CLK_RXHALF => '0', CLK_TXI => clk_tx_full, --clk_200_ref, --clk_200_internal, --clk_tx_full, JM150706 - CLK_REF => clk_200_ref, --CLK_INTERNAL_FULL, + CLK_REF => CLK_INTERNAL_FULL, RESET => RESET, CLEAR => CLEAR, @@ -272,9 +272,9 @@ THE_SCI_READER : entity work.sci_reader -- STAT_DEBUG(31 downto 0) <= debug_rx_control_i(31 downto 0); STAT_DEBUG(3 downto 0) <= debug_med_sync_control_i(3 downto 0); STAT_DEBUG(7 downto 4) <= rx_los_low & lsm_status & rx_cdr_lol & tx_pll_lol; - STAT_DEBUG(9) <= clk_200_ref; - STAT_DEBUG(10) <= clk_rx_full; - STAT_DEBUG(11) <= clk_tx_full; +-- STAT_DEBUG(9) <= CLK_REF_FULL; +-- STAT_DEBUG(10) <= clk_rx_full; +-- STAT_DEBUG(11) <= clk_tx_full; stat_med(0) <= rst_qd; -- 2.43.0