From 9520a6ea85b7723c0f6fe8393ca1c694a875514d Mon Sep 17 00:00:00 2001 From: Thomas Gessler Date: Fri, 7 Aug 2020 10:08:24 +0200 Subject: [PATCH] Overhaul UltraScale DNA read-out --- xilinx/xcku/read_dna_address.vhd | 266 ++++++++++--------------------- xilinx/xcku/trb_net_xdna.vhd | 121 ++++++++------ 2 files changed, 149 insertions(+), 238 deletions(-) diff --git a/xilinx/xcku/read_dna_address.vhd b/xilinx/xcku/read_dna_address.vhd index cab8234..956cbc8 100644 --- a/xilinx/xcku/read_dna_address.vhd +++ b/xilinx/xcku/read_dna_address.vhd @@ -1,197 +1,91 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -Library UNISIM; -use UNISIM.vcomponents.all; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library unisim; +use unisim.vcomponents.all; entity read_dna_address is - generic (SIM_DNA_VALUE : std_logic_vector := X"80000000BEEF000000000002" ); port ( - SYSCLK : in std_logic; - SYS_RESET : in std_logic; - SRL_O : out std_logic_vector(95 downto 0); - DNA_VALID : out std_logic; - DS_OUT : out std_logic_vector(15 downto 0); - DS_ADDR : out std_logic_vector(1 downto 0); - DS_WR : out std_logic -); -end read_dna_address; + CLK : in std_logic; + RESET : in std_logic; + DNA : out std_logic_vector(95 downto 0); + VALID : out std_logic + ); +end entity read_dna_address; -architecture Behavioral of read_dna_address is +architecture behavioral of read_dna_address is + type read_state_type is (read_reset, read_load, read_shift, read_done); -------------State Type Declaration---------------------------- -type CONTROLLER_STATE is (S_RESET,S_DNA,S_DONE); - -------------DNA Component Declaration------------------- - -COMPONENT DNA_PORTE2 is - generic ( - SIM_DNA_VALUE : std_logic_vector -- Specifies a sample 96-bit DNA value for simulation - ); - PORT ( - DOUT : out std_logic; --std_logic_vector(95 downto 0); -- 1-bit output: DNA output data - CLK : in std_logic; -- 1-bit input: Clock input - DIN : in std_logic; -- 1-bit input: User data input pin - READ : in std_logic; -- 1-bit input: Active-High load DNA, active-Low read input - SHIFT : in std_logic -- 1-bit input: Active-High shift enable input - ); -END COMPONENT; - - - -------------Signal Declarations---------------------------- -signal CURR_STATE, NEXT_STATE : CONTROLLER_STATE; --- State Signals -signal O: std_logic; --- DNA Output -signal CLK: std_logic; --- Clock signal -signal I: std_logic := '0'; --- DNA Input -signal RD: std_logic := '0'; --- DNA Read -signal SFT: std_logic := '0'; --- DNA Shift -signal RESET: std_logic := '1'; --- Reset Control - -signal SFT_cnt : integer range 0 to 94 := 0; --Shift assert count -signal COUNT : integer range 0 to 3 := 0; --- FSM Count -signal DONE_DNA : std_logic := '0'; - - -signal SLR_tmp : std_logic_vector(95 downto 0); + signal read_state : read_state_type := read_reset; + signal read_state_next : read_state_type; + signal read_count : unsigned(6 downto 0) := (others => '0'); + signal read_count_next : unsigned(6 downto 0); + signal dna_sreg : std_logic_vector(95 downto 0) := (others => '0'); + signal dna_sreg_next : std_logic_vector(95 downto 0); + signal dna_dout : std_logic; + signal dna_read : std_logic; + signal dna_shift : std_logic; begin - - DNA_VALID <= DONE_DNA; - SRL_O <= SLR_tmp; - CLK <= SYSCLK; - - - DNA_PORTE2_inst : DNA_PORTE2 - generic map ( - SIM_DNA_VALUE => X"5000_0000_BEEF_0000_1234_0001" -- Specifies a sample 96-bit DNA value for simulation - ) - port map ( - DOUT => O, -- 1-bit output: DNA output data - CLK => CLK, -- 1-bit input: Clock input - DIN => I, -- 1-bit input: User data input pin - READ => RD, -- 1-bit input: Active-High load DNA, active-Low read input - SHIFT => SFT -- 1-bit input: Active-High shift enable input - ); - -SYNC_PROC: process(SYSCLK) + DNA_PORTE2_i : DNA_PORTE2 + generic map ( + SIM_DNA_VALUE => x"0B_0A_09_08_07_06_05_04_03_02_01_00" + ) + port map ( + DOUT => dna_dout, + CLK => CLK, + DIN => '0', + READ => dna_read, + SHIFT => dna_shift + ); + + process (CLK) is begin - if(Rising_edge(SYSCLK)) then - if (RESET = '1') then - CURR_STATE <= S_RESET; - else - CURR_STATE <= NEXT_STATE; - end if; - end if; -end process SYNC_PROC; - -MAIN_PROC: process(CURR_STATE,SYS_RESET,DONE_DNA) -begin - case CURR_STATE is - when S_RESET => - if(SYS_RESET = '1') then - NEXT_STATE <= S_RESET;--S_DNA; - else - NEXT_STATE <= S_DNA;--S_RESET; - end if; - when S_DNA => - if(DONE_DNA = '1') then - NEXT_STATE <= S_DONE; - else - NEXT_STATE <= S_DNA; - end if; - when S_DONE => - NEXT_STATE <= S_DONE; - - when others=> - end case;--NEXT_STATE -end process MAIN_PROC; - - ------Process to read DNA----------- - -PROC: process(SYSCLK) -begin - if(Rising_edge(SYSCLK)) then - case NEXT_STATE is - when S_RESET => - RD <= '0'; - SFT <= '0'; - RESET <= '0'; --de-assert reset (initially asserted) - when S_DNA => - case COUNT is - when 0 => - RD <= '1'; --Assert read Parallel loads output shift register - SFT <= '1'; - COUNT <= COUNT + 1; - when 1 => - RD <= '0'; -- Read should be deasserted after 1 CLK - SFT <= '1'; - COUNT <= COUNT + 1; - when 2 => - RD <= '0'; - SFT <= '1'; --Assert SHIFT, hold asserted for 96 CLKs - IF (SFT_cnt < 94) THEN - SFT_cnt <= SFT_cnt + 1; - COUNT <= 2; - ELSE - COUNT <= COUNT + 1; - SFT <= '0'; - END IF; - when 3 => - RD <= '0'; - SFT <= '0'; - DONE_DNA <= '1'; - COUNT <= COUNT + 1; - - when others=> - COUNT <= COUNT + 1; - end case; - - when S_DONE => - RD <= '0'; - SFT <= '0'; - - when others => - RESET <= '1'; --re-assert reset - end case; - end if; -end process PROC; - ----SIPO SRL---- - -THE_SIPO_SLR : process -begin - wait until rising_edge(SYSCLK); - if SFT = '1' then - SLR_tmp <= O & SLR_tmp (95 downto 1); - end if; -end process; - - ---small output (16 bit) for trbnet entity -THE_SMALL_DATA : process -begin - wait until rising_edge(SYSCLK); - DS_OUT <= SLR_tmp(95 downto 80); - DS_ADDR <= "00"; - DS_WR <= '0'; - if SFT_cnt = 15 then --DNA ADDRESS (15:00) - DS_ADDR <= "00"; - DS_WR <= '1'; - elsif SFT_cnt = 31 then --DNA ADDRESS (31:16) - DS_ADDR <= "01"; - DS_WR <= '1'; - elsif SFT_cnt = 47 then --DNA ADDRESS (47:32) - DS_ADDR <= "10"; - DS_WR <= '1'; - elsif SFT_cnt = 63 then --DNA ADDRESS (63:48) - DS_ADDR <= "11"; - DS_WR <= '1'; - end if; -end process; - - -end Behavioral; + if rising_edge(CLK) then + if RESET = '1' then + read_state <= read_reset; + else + read_state <= read_state_next; + end if; + + read_count <= read_count_next; + dna_sreg <= dna_sreg_next; + end if; + end process; + + process (read_state, read_count, dna_sreg, dna_dout) is + begin + read_state_next <= read_state; + read_count_next <= read_count; + dna_sreg_next <= dna_sreg; + + dna_read <= '0'; + dna_shift <= '0'; + VALID <= '0'; + + case read_state is + when read_reset => + read_state_next <= read_load; + read_count_next <= (others => '0'); + dna_sreg_next <= (others => '0'); + when read_load => + read_state_next <= read_shift; + dna_read <= '1'; + when read_shift => + if read_count = 95 then + read_state_next <= read_done; + end if; + read_count_next <= read_count + 1; + dna_sreg_next <= dna_dout & dna_sreg(95 downto 1); + dna_shift <= '1'; + when read_done => + read_state_next <= read_done; + VALID <= '1'; + end case; + end process; + + DNA <= dna_sreg; +end architecture behavioral; diff --git a/xilinx/xcku/trb_net_xdna.vhd b/xilinx/xcku/trb_net_xdna.vhd index 79ba2ce..e0ec0a9 100644 --- a/xilinx/xcku/trb_net_xdna.vhd +++ b/xilinx/xcku/trb_net_xdna.vhd @@ -1,59 +1,76 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -library UNISIM; -use UNISIM.VComponents.all; +library ieee; +use ieee.std_logic_1164.all; entity trb_net_xdna is -port( - CLK : in std_logic; - RESET : in std_logic; - DATA_OUT : out std_logic_vector(15 downto 0); - ADDR_OUT : out std_logic_vector( 2 downto 0); - WRITE_OUT : out std_logic; - TEMP_OUT : out std_logic_vector(11 downto 0); - ID_OUT : out std_logic_vector(63 downto 0) - ); -end trb_net_xdna; - -architecture Behavioral of trb_net_xdna is + port ( + CLK : in std_logic; + RESET : in std_logic; + DATA_OUT : out std_logic_vector(15 downto 0); + ADDR_OUT : out std_logic_vector( 2 downto 0); + WRITE_OUT : out std_logic; + TEMP_OUT : out std_logic_vector(11 downto 0); + ID_OUT : out std_logic_vector(63 downto 0) + ); +end entity trb_net_xdna; - signal address : std_logic_vector(95 downto 0); - signal dna_valid : std_logic; - signal ds_out : std_logic_vector(15 downto 0); - signal ds_addr : std_logic_vector( 1 downto 0); - signal ds_wr : std_logic; +architecture behavioral of trb_net_xdna is + type state is (wait_dna, put_0, put_1, put_2, put_3, done); + signal cur_state : state := wait_dna; + signal dna_valid : std_logic; + signal dna : std_logic_vector(95 downto 0); begin + THE_XDNA : entity work.read_dna_address + port map ( + CLK => CLK, + RESET => RESET, + DNA => dna, + VALID => dna_valid + ); - THE_XDNA : entity work.read_dna_address - port map( - SYSCLK => CLK, - SYS_RESET => RESET, - SRL_O => address, - DNA_VALID => dna_valid, - DS_OUT => ds_out, - DS_ADDR => ds_addr, - DS_WR => ds_wr - ); - - PROC_STORE_ID : process begin - wait until rising_edge(CLK); - if ds_wr = '1' then - case ds_addr is - when "00" => ID_OUT(15 downto 0) <= ds_out; - when "01" => ID_OUT(31 downto 16) <= ds_out; - when "10" => ID_OUT(47 downto 32) <= ds_out; - when "11" => ID_OUT(63 downto 48) <= ds_out; - when others => null; - end case; - end if; - end process; - - DATA_OUT <= ds_out; - ADDR_OUT <= '0'& ds_addr; - WRITE_OUT <= ds_wr; - TEMP_OUT <= (others => '0'); + PROC_STORE_ID: + process(CLK) is + begin + if rising_edge(CLK) then + DATA_OUT <= x"0000"; + ADDR_OUT <= "000"; + WRITE_OUT <= '0'; + if RESET = '1' then + cur_state <= wait_dna; + ID_OUT <= x"FF00_ABAD_1DEA_00FF"; + else + case cur_state is + when wait_dna => + if dna_valid = '1' then + cur_state <= put_0; + ID_OUT <= dna(63 downto 0); + end if; + when put_0 => + cur_state <= put_1; + DATA_OUT <= dna(15 downto 0); + ADDR_OUT <= "000"; + WRITE_OUT <= '1'; + when put_1 => + cur_state <= put_2; + DATA_OUT <= dna(31 downto 16); + ADDR_OUT <= "001"; + WRITE_OUT <= '1'; + when put_2 => + cur_state <= put_3; + DATA_OUT <= dna(47 downto 32); + ADDR_OUT <= "010"; + WRITE_OUT <= '1'; + when put_3 => + cur_state <= done; + DATA_OUT <= dna(63 downto 48); + ADDR_OUT <= "011"; + WRITE_OUT <= '1'; + when done => + null; + end case; + end if; + end if; + end process PROC_STORE_ID; -end Behavioral; + TEMP_OUT <= x"000"; +end architecture behavioral; -- 2.43.0