From 953730be1a46d8a84e9ede65a21939e0f85df3f2 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 5 Oct 2010 09:33:05 +0000 Subject: [PATCH] *** empty log message *** --- media_interfaces/trb_net16_med_ecp_fot.vhd | 6 +- .../trb_net16_med_ecp_fot_4_ctc.vhd | 15 +++-- .../trb_net16_rx_comma_handler.vhd | 2 +- media_interfaces/trb_net16_tx_control.vhd | 5 +- testbenches/error_check.vhd | 45 +++++++------- testbenches/error_generator.vhd | 47 +++++++-------- testbenches/tb_trb_net16_rxtx_control.vhd | 33 ++++++----- trb_net_CRC8.vhd | 58 +++++++++++++++++++ 8 files changed, 140 insertions(+), 71 deletions(-) create mode 100644 trb_net_CRC8.vhd diff --git a/media_interfaces/trb_net16_med_ecp_fot.vhd b/media_interfaces/trb_net16_med_ecp_fot.vhd index 202d74f..6be346e 100644 --- a/media_interfaces/trb_net16_med_ecp_fot.vhd +++ b/media_interfaces/trb_net16_med_ecp_fot.vhd @@ -639,13 +639,15 @@ MED_PACKET_NUM_OUT <= buf_med_packet_num_out; STAT_DEBUG(40) <= rx_fifo_write_en; STAT_DEBUG(48 downto 41) <= last_rx_fifo_dout; STAT_DEBUG(49) <= tx_k; - STAT_DEBUG(62 downto 50) <= debug_txcontrol_i(12 downto 0); + STAT_DEBUG(61 downto 50) <= debug_txcontrol_i(11 downto 0); + STAT_DEBUG(62) <= buf_rx_k; STAT_DEBUG(63) <= tx_lane_reset; PROC_LED : process(ff_rxfullclk) begin if rising_edge(ff_rxfullclk) then - buf_rx_data_reg <= rx_data_reg; + buf_rx_data_reg <= rx_data; + buf_rx_k <= rx_k; end if; end process; diff --git a/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd b/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd index 744c2db..3ff5163 100644 --- a/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd +++ b/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd @@ -844,11 +844,16 @@ end generate; STAT_OP(i*16+14) <= FSM_STAT_OP(i*16+14); STAT_OP(i*16+15) <= send_reset_words(i); - STAT_DEBUG(i*64+17 downto i*64+0) <= FSM_STAT_DEBUG(i*32+17 downto i*32); - STAT_DEBUG(i*64+25 downto i*64+18) <= rx_data(i*8+7 downto i*8); - STAT_DEBUG(i*64+26) <= rx_k(i); - STAT_DEBUG(i*64+48 downto i*64+27) <= debug_txcontrol_i(i*32+21 downto i*32); - STAT_DEBUG(i*64+63 downto i*64+49) <= debug_rxcontrol_i(i*16+14 downto i*16+0); + process(CLK) + begin + if rising_edge(CLK) then + STAT_DEBUG(i*64+17 downto i*64+0) <= FSM_STAT_DEBUG(i*32+17 downto i*32); + STAT_DEBUG(i*64+25 downto i*64+18) <= rx_data(i*8+7 downto i*8); + STAT_DEBUG(i*64+26) <= rx_k(i); + STAT_DEBUG(i*64+31 downto i*64+27) <= debug_txcontrol_i(i*32+4 downto i*32); + STAT_DEBUG(i*64+63 downto i*64+32) <= debug_rxcontrol_i(i*32+31 downto i*32+0); + end if; + end process; STAT_REG_OUT(128*i+31 downto 128*i+0) <= statreg_txcontrol_i(32*i+31 downto 32*i); STAT_REG_OUT(128*i+95 downto 128*i+32) <= statreg_rxcontrol_i(64*i+63 downto 64*i); diff --git a/media_interfaces/trb_net16_rx_comma_handler.vhd b/media_interfaces/trb_net16_rx_comma_handler.vhd index 7e96392..2eb4361 100644 --- a/media_interfaces/trb_net16_rx_comma_handler.vhd +++ b/media_interfaces/trb_net16_rx_comma_handler.vhd @@ -252,7 +252,7 @@ debug(12) <= c_reset; debug(11) <= reset_word_cnt(4); debug(10 downto 0) <= (others => '0'); -STAT_REG_OUT(4 downto 0) <= reset_word_cnt; +STAT_REG_OUT(4 downto 0) <= std_logic_vector(reset_word_cnt); STAT_REG_OUT(5) <= fifo_inhibit; STAT_REG_OUT(6) <= comma_locked; STAT_REG_OUT(7) <= '0'; diff --git a/media_interfaces/trb_net16_tx_control.vhd b/media_interfaces/trb_net16_tx_control.vhd index 53d904e..99cc2f9 100644 --- a/media_interfaces/trb_net16_tx_control.vhd +++ b/media_interfaces/trb_net16_tx_control.vhd @@ -14,6 +14,7 @@ port( RESET_IN : in std_logic; TX_DATA_IN : in std_logic_vector(15 downto 0); + TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0); TX_WRITE_IN : in std_logic; TX_READ_OUT : out std_logic; @@ -423,8 +424,8 @@ ct_fifo_read <= tx_allow_qtx and not ram_afull and not ct_fifo_empty; process(SYSCLK_IN) begin if rising_edge(SYSCLK_IN) then - STAT_REG_OUT(7 downto 0) <= ram_fill_level; - STAT_REG_OUT(15 downto 8) <= ram_read_addr; + STAT_REG_OUT(7 downto 0) <= std_logic_vector(ram_fill_level); + STAT_REG_OUT(15 downto 8) <= std_logic_vector(ram_read_addr); STAT_REG_OUT(16) <= ram_afull; STAT_REG_OUT(17) <= ram_empty; STAT_REG_OUT(18) <= tx_allow_qtx; diff --git a/testbenches/error_check.vhd b/testbenches/error_check.vhd index 4163959..3d210ea 100644 --- a/testbenches/error_check.vhd +++ b/testbenches/error_check.vhd @@ -20,19 +20,19 @@ port( end entity; architecture arch of error_check is - + component fifo_18x2k_oreg is port ( - Data: in std_logic_vector(17 downto 0); - Clock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - AmFullThresh: in std_logic_vector(10 downto 0); - Q: out std_logic_vector(17 downto 0); - WCNT: out std_logic_vector(11 downto 0); - Empty: out std_logic; - Full: out std_logic; + Data: in std_logic_vector(17 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + AmFullThresh: in std_logic_vector(10 downto 0); + Q: out std_logic_vector(17 downto 0); + WCNT: out std_logic_vector(11 downto 0); + Empty: out std_logic; + Full: out std_logic; AlmostFull: out std_logic); end component; @@ -42,7 +42,7 @@ signal data_q : std_logic_vector(15 downto 0); signal data_qq : std_logic_vector(15 downto 0); signal check_q : std_logic; signal check_qq : std_logic; - +signal dummy : std_logic_vector(1 downto 0); begin @@ -50,9 +50,9 @@ SYNC_PROC : process begin wait until rising_edge(RXCLK_IN); data_q <= data_qq; - data_qq <= DATA2_IN; + data_qq <= DATA_RX_IN; check_q <= check_qq; - check_qq <= DATA2_VALID_IN; + check_qq <= DATA_RX_VALID_IN; end process; @@ -61,14 +61,14 @@ fifo_wr_en <= '1' when DATA_TX_DATAREADY_IN = '1' and DATA_TX_READ_IN = '1' else fifo : fifo_18x2k_oreg port map( Data(15 downto 0) => DATA_TX_IN, - data(17 downto 16) => "00"; + data(17 downto 16) => "00", Clock => RXCLK_IN, WrEn => fifo_wr_en, RdEn => DATA_RX_VALID_IN, Reset => RESET_IN, - AmFullThresh => open, + AmFullThresh => (others => '1'), Q(15 downto 0) => fifo_q, - Q(17 downto 16) => open, + Q(17 downto 16) => dummy(1 downto 0), WCNT => open, Empty => open, Full => open, @@ -79,11 +79,12 @@ CHECK_PROC : process begin wait until rising_edge(RXCLK_IN); - assert - ((check_qq = '1') and - (fifo_q(15 downto 4) /= data_q(15 downto 4)) and - (fifo_q(2 downto 0) /= data_q(2 downto 0))) - report "data invalid" severity warning; + if check_q = '1' then + assert + (fifo_q(15 downto 5) = data_q(15 downto 5)) and + (fifo_q(3 downto 0) = data_q(3 downto 0)) + report "data invalid" severity error; + end if; end process; diff --git a/testbenches/error_generator.vhd b/testbenches/error_generator.vhd index b5c4b04..17d183d 100644 --- a/testbenches/error_generator.vhd +++ b/testbenches/error_generator.vhd @@ -50,7 +50,7 @@ begin UNIFORM(seed1, seed2, rand); int_rand := INTEGER(TRUNC(rand * 1000000.0)); - if( (int_rand MOD 500) = 0 ) then + if( (int_rand MOD 100) = 0 ) then buf_RX1_CV_OUT <= not RX1_CV_IN; assert false report "RX1_CV" severity note; wait for 40 ns; @@ -122,6 +122,7 @@ process begin wait until rising_edge(RXCLK_IN); buf_RX1_DATA_OUT <= RX1_DATA_IN; + buf_RX1_K_OUT <= RX1_K_IN; end process; RX1_DATA_OUT <= transport buf_RX1_DATA_OUT after 200 ns; @@ -164,31 +165,31 @@ RX2_DATA_OUT <= RX2_DATA_IN; RX2_CV_OUT <= RX2_CV_IN; RX2_K_OUT <= RX2_K_IN; -K1_PROC : process -variable seed1 : positive; -variable seed2 : positive := 5; -variable rand : real; -variable int_rand : integer; -begin - - wait until rising_edge(RXCLK_IN); - - UNIFORM(seed1, seed2, rand); - int_rand := INTEGER(TRUNC(rand * 1000000.0)); - - if( (int_rand MOD 10000) = 0 ) then - buf_RX1_K_OUT <= not RX1_K_IN; - assert false report "RX1_K" severity note; --- assert false report int_rand'image(integer) severity note; - wait for 39 ns; - buf_RX1_K_OUT <= RX1_K_IN; - else - buf_RX1_K_OUT <= RX1_K_IN; - end if; +-- K1_PROC : process +-- variable seed1 : positive; +-- variable seed2 : positive := 5; +-- variable rand : real; +-- variable int_rand : integer; +-- begin +-- +-- wait until rising_edge(RXCLK_IN); +-- +-- UNIFORM(seed1, seed2, rand); +-- int_rand := INTEGER(TRUNC(rand * 1000000.0)); +-- +-- if( (int_rand MOD 10000) = 0 ) then +-- buf_RX1_K_OUT <= not RX1_K_IN; +-- assert false report "RX1_K" severity note; +-- -- assert false report int_rand'image(integer) severity note; +-- wait for 39 ns; +-- buf_RX1_K_OUT <= RX1_K_IN; +-- else +-- buf_RX1_K_OUT <= RX1_K_IN; +-- end if; -- wait for 400 ns; -end process; +-- end process; -- K2_PROC : process -- variable seed1 : positive; diff --git a/testbenches/tb_trb_net16_rxtx_control.vhd b/testbenches/tb_trb_net16_rxtx_control.vhd index 90578b6..6e5f5e5 100644 --- a/testbenches/tb_trb_net16_rxtx_control.vhd +++ b/testbenches/tb_trb_net16_rxtx_control.vhd @@ -99,18 +99,19 @@ architecture arch of rxtxtb is ); end component; -component error_check is -port( - RXCLK_IN : in std_logic; - RESET_IN : in std_logic; + component error_check is + port( + RXCLK_IN : in std_logic; + RESET_IN : in std_logic; - DATA1_IN : in std_logic_vector(15 downto 0); - DATA1_WR_EN_IN : in std_logic; - DATA2_IN : in std_logic_vector(15 downto 0); - DATA2_VALID_IN : in std_logic + DATA_TX_IN : in std_logic_vector(15 downto 0); + DATA_TX_DATAREADY_IN : in std_logic; + DATA_TX_READ_IN : in std_logic; + DATA_RX_IN : in std_logic_vector(15 downto 0); + DATA_RX_VALID_IN : in std_logic - ); -end component; + ); + end component; signal clk : std_logic := '1'; @@ -436,14 +437,14 @@ THE_ERROR : error_generator end if; end process; - data1 <= (counter1(7 downto 0)) & (counter1(7 downto 0)); + data1 <= (counter1(7 downto 6) & "00" & counter1(3 downto 0) & counter1(7 downto 6) & "00" & counter1(3 downto 0)); --------------------------------------------------------------------- -- Data input 2 --------------------------------------------------------------------- - data2 <= (counter2(7 downto 0)) & (counter2(7 downto 0)); + data2 <= (counter2(7 downto 6) & "00" & counter2(3 downto 0) & counter2(7 downto 6) & "00" & counter2(3 downto 0)); process(clk) begin @@ -572,8 +573,8 @@ port map( RXCLK_IN => clk, RESET_IN => reset, - DATA_TX_IN => data1 - DATA_TX_DATA_READY_IN => dataready1, + DATA_TX_IN => data1, + DATA_TX_DATAREADY_IN => dataready1, DATA_TX_READ_IN => read1, DATA_RX_IN => rxdata1, DATA_RX_VALID_IN => rxdataready1 @@ -585,8 +586,8 @@ port map( RXCLK_IN => clk, RESET_IN => reset, - DATA_TX_IN => data2 - DATA_TX_DATA_READY_IN => dataready2, + DATA_TX_IN => data2, + DATA_TX_DATAREADY_IN => dataready2, DATA_TX_READ_IN => read2, DATA_RX_IN => rxdata2, DATA_RX_VALID_IN => rxdataready2 diff --git a/trb_net_CRC8.vhd b/trb_net_CRC8.vhd new file mode 100644 index 0000000..9f11c3e --- /dev/null +++ b/trb_net_CRC8.vhd @@ -0,0 +1,58 @@ +------------------------------------------------------------------------------- +-- Copyright (C) 2009 OutputLogic.com +-- This source file may be used and distributed without restriction +-- provided that this copyright statement is not removed from the file +-- and that any derivative work contains the original copyright notice +-- and the associated disclaimer. +-- +-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. +------------------------------------------------------------------------------- +-- CRC module for data(7:0) +-- lfsr(7:0)=1+x^4+x^5+x^8; +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; + +library work; +use work.trb_net_std.all; + +entity trb_net_CRC8 is + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + DATA_IN : in std_logic_vector(7 downto 0); + CRC_OUT : out std_logic_vector(7 downto 0); + CRC_match : out std_logic + ); +end entity; + +architecture imp_crc of trb_net_CRC8 is + signal lfsr_q: std_logic_vector (7 downto 0); + signal lfsr_c: std_logic_vector (7 downto 0); +begin + CRC_OUT <= lfsr_q; + CRC_match <= not and_all(lfrs_q); + + lfsr_c(0) <= lfsr_q(0) xor lfsr_q(3) xor lfsr_q(4) xor lfsr_q(6) xor data_in(0) xor data_in(3) xor data_in(4) xor data_in(6); + lfsr_c(1) <= lfsr_q(1) xor lfsr_q(4) xor lfsr_q(5) xor lfsr_q(7) xor data_in(1) xor data_in(4) xor data_in(5) xor data_in(7); + lfsr_c(2) <= lfsr_q(2) xor lfsr_q(5) xor lfsr_q(6) xor data_in(2) xor data_in(5) xor data_in(6); + lfsr_c(3) <= lfsr_q(3) xor lfsr_q(6) xor lfsr_q(7) xor data_in(3) xor data_in(6) xor data_in(7); + lfsr_c(4) <= lfsr_q(0) xor lfsr_q(3) xor lfsr_q(6) xor lfsr_q(7) xor data_in(0) xor data_in(3) xor data_in(6) xor data_in(7); + lfsr_c(5) <= lfsr_q(0) xor lfsr_q(1) xor lfsr_q(3) xor lfsr_q(6) xor lfsr_q(7) xor data_in(0) xor data_in(1) xor data_in(3) xor data_in(6) xor data_in(7); + lfsr_c(6) <= lfsr_q(1) xor lfsr_q(2) xor lfsr_q(4) xor lfsr_q(7) xor data_in(1) xor data_in(2) xor data_in(4) xor data_in(7); + lfsr_c(7) <= lfsr_q(2) xor lfsr_q(3) xor lfsr_q(5) xor data_in(2) xor data_in(3) xor data_in(5); + + + process (CLK,RESET) begin + if (RESET = '1') then + lfsr_q <= b"00000000"; + elsif rising_edge(CLK) then + if (CLK_EN = '1') then + lfsr_q <= lfsr_c; + end if; + end if; + end process; +end architecture imp_crc; \ No newline at end of file -- 2.43.0