From 953cead65d13e0aa3a85f5539fb5e470fac3a538 Mon Sep 17 00:00:00 2001
From: Tobias Weber <toweber86@gmail.com>
Date: Tue, 22 Aug 2017 18:14:51 +0200
Subject: [PATCH] synchronous reset

---
 mupix/sources/spi_if.vhd | 127 ++++++++++++++++++---------------------
 1 file changed, 60 insertions(+), 67 deletions(-)

diff --git a/mupix/sources/spi_if.vhd b/mupix/sources/spi_if.vhd
index 939a0fa..28acdda 100644
--- a/mupix/sources/spi_if.vhd
+++ b/mupix/sources/spi_if.vhd
@@ -54,73 +54,66 @@ architecture rtl of spi_if is
 begin
 
 
-  process(clk, reset)
-
-  begin
-    if(reset = '1') then
-      ckdiv        <= (others => '0');
-      cyclecounter <= (others => '0');
-      spi_data     <= '0';
-      spi_clk      <= '0';
-      spi_ld       <= '0';
-      state        <= waiting;
-    elsif(clk'event and clk = '1') then
-      case state is
-        when waiting =>
-          ckdiv        <= (others => '0');
-          cyclecounter <= (others => '0');
-          spi_data     <= '0';
-          spi_clk      <= '0';
-          spi_ld       <= '0';
-          state        <= waiting;
-
-          if(wren = '1' or write_again = '1') then
-            shiftregister <= injection2_reg & injection1_reg & threshold_reg;
-            state         <= writing;
-            write_again   <= '0';
-          end if;
-        when writing =>
-          if(wren = '1') then
-            write_again <= '1';
-          end if;
-
-          ckdiv <= ckdiv + 1;
-          if(ckdiv = "000000") then
-            cyclecounter <= cyclecounter + 1;
-            if(cyclecounter(0) = '0') then  -- even cycles: push data, clock at '0'
-              spi_data                   <= shiftregister(47);
-              shiftregister(47 downto 1) <= shiftregister(46 downto 0);
-              shiftregister(0)           <= '0';
-              spi_clk                    <= '0';
-            end if;
-            if(cyclecounter(0) = '1') then  --odd cycles: 
-              spi_clk <= '1';
-            end if;
-            if(cyclecounter = "01100000") then  -- we are done...
-              state        <= loading;
-              spi_clk      <= '1';
-              cyclecounter <= "00000000";
-            end if;
-          end if;
-        when loading =>
-          if(wren = '1') then
-            write_again <= '1';
-          end if;
-          ckdiv <= ckdiv + 1;
-          if(ckdiv = "00000") then
-            cyclecounter <= cyclecounter + 1;
-            if(cyclecounter = "00000000") then
-              spi_ld <= '1';
-            elsif(cyclecounter = "00000001") then
-              spi_clk <= '0';
-            elsif(cyclecounter = "00000010") then
-              spi_ld <= '0';
-              state  <= waiting;
-            end if;
-          end if;
-      end case;
-    end if;
-  end process;
+  process(clk)
+	begin
+		if rising_edge(clk) then
+			if (reset = '1') then
+				ckdiv        <= (others => '0');
+				cyclecounter <= (others => '0');
+				spi_data     <= '0';
+				spi_clk      <= '0';
+				spi_ld       <= '0';
+				state        <= waiting;
+			else
+				case state is
+					when waiting =>
+						ckdiv        <= (others => '0');
+						cyclecounter <= (others => '0');
+						spi_data     <= '0';
+						spi_clk      <= '0';
+						spi_ld       <= '0';
+						state        <= waiting;
+						if wren = '1' then
+							shiftregister <= injection2_reg & injection1_reg & threshold_reg;
+							state         <= writing;
+							write_again   <= '0';
+						end if;
+					when writing =>
+						ckdiv <= ckdiv + 1;
+						if (ckdiv = "000000") then
+							cyclecounter <= cyclecounter + 1;
+							if (cyclecounter(0) = '0') then -- even cycles: push data, clock at '0'
+								spi_data                   <= shiftregister(47);
+								shiftregister(47 downto 1) <= shiftregister(46 downto 0);
+								shiftregister(0)           <= '0';
+								spi_clk                    <= '0';
+							end if;
+							if (cyclecounter(0) = '1') then --odd cycles: 
+								spi_clk <= '1';
+							end if;
+							if (cyclecounter = "01100000") then -- we are done...
+								state        <= loading;
+								spi_clk      <= '1';
+								cyclecounter <= "00000000";
+							end if;
+						end if;
+					when loading =>
+						ckdiv <= ckdiv + 1;
+						if (ckdiv = "00000") then
+							cyclecounter <= cyclecounter + 1;
+							if (cyclecounter = "00000000") then
+								spi_ld <= '1';
+							elsif (cyclecounter = "00000001") then
+								spi_clk <= '0';
+							elsif (cyclecounter = "00000010") then
+								spi_ld <= '0';
+								state  <= waiting;
+							end if;
+						end if;
+				end case;
+			end if;
+		end if;
+	end process;
 
   -----------------------------------------------------------------------------
   --TRB slave bus
-- 
2.43.0