From 9562799a44615fc6a2ccc9571fa5e4bd68bb9f4a Mon Sep 17 00:00:00 2001 From: Andreas Neiser Date: Thu, 26 Feb 2015 17:56:00 +0100 Subject: [PATCH] enabling multicycles again --- ADC/trb3_periph_adc_constraints.lpf | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/ADC/trb3_periph_adc_constraints.lpf b/ADC/trb3_periph_adc_constraints.lpf index 853ea91..d3ce6c1 100644 --- a/ADC/trb3_periph_adc_constraints.lpf +++ b/ADC/trb3_periph_adc_constraints.lpf @@ -84,10 +84,12 @@ USE PRIMARY NET "CLK_PCLK_RIGHT_c"; #USE PRIMARY2EDGE NET "THE_ADC/clk_adcfast_i_0"; #USE PRIMARY2EDGE NET "THE_ADC/clk_adcfast_i_1"; -#MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "gen_reallogic_THE_ADC/adc_clk_right_c" 2 X; +MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "gen_reallogic_THE_ADC/adc_clk_right_c" 2 X; #MULTICYCLE FROM CLKNET "gen_reallogic_THE_ADC/adc_clk_right_c" TO CLKNET "clk_100_i_c" 2 X; -#MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "P_CLOCK_c" 2 X; +MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "P_CLOCK_c" 2 X; #MULTICYCLE FROM CLKNET "P_CLOCK_c" TO CLKNET "clk_100_i_c" 2 X; +MULTICYCLE FROM CLKNET "gen_reallogic_THE_ADC/THE_ADC_LEFT/clk_data_c" TO CLKNET "P_CLOCK_c" 2 X; +MULTICYCLE FROM CLKNET "gen_reallogic_THE_ADC/THE_ADC_RIGHT/clk_data" TO CLKNET "gen_reallogic_THE_ADC/adc_clk_right_c" 2 X; # we define everything doubled to make it work with all lattice/synplify versions # due to _ vs . notation of generate statements args... -- 2.43.0