From 95647c02886e27429201345344d8123be65b2099 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Wed, 27 Apr 2022 14:29:55 +0200 Subject: [PATCH] phaserbox added --- cts/trb3sc_cts.prj | 1 + cts/trb3sc_cts.vhd | 82 +++++++++++++++------------------------------- 2 files changed, 27 insertions(+), 56 deletions(-) diff --git a/cts/trb3sc_cts.prj b/cts/trb3sc_cts.prj index bba0af2..009c826 100644 --- a/cts/trb3sc_cts.prj +++ b/cts/trb3sc_cts.prj @@ -147,6 +147,7 @@ add_file -vhdl -lib work "../../trbnet/special/statistics.vhd" add_file -vhdl -lib work "../../trbnet/special/clockbox.vhd" add_file -vhdl -lib work "../../trbnet/special/clockpoint.vhd" add_file -vhdl -lib work "../../trb3sc/cores/statmem.vhd" +add_file -vhdl -lib work "../../trbnet/special/phaserbox.vhd" #TrbNet Endpoint add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd index 61c4a7a..276edae 100644 --- a/cts/trb3sc_cts.vhd +++ b/cts/trb3sc_cts.vhd @@ -299,8 +299,8 @@ architecture trb3sc_arch of trb3sc_cts is signal phaser_start : std_logic; signal coarse_delay_data : std_logic_vector(31 downto 0); - signal cal_phase_q : std_logic; + signal debug_phaser : std_logic_vector(15 downto 0); signal rj_io_q : std_logic_vector(1 downto 0); @@ -573,61 +573,31 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate LOCK => open ); - THE_CLOCKBOX: entity clockbox + THE_PHASERBOX: entity phaserbox port map( - SAMPLE_CLK => clk_sample, - PING_IN => ping_i, - CLK_PING => master_clk_i, - PONG_IN => pong_i, - CLK_PONG => pong_clk_i, - PING_OUT => ping_iq, - PONG_OUT => pong_iq - ); - - THE_DDMTD: entity ddmtd - port map( - AUXCLK => clk_sample, - RESET => reset_i, - PING_IN => ping_iq, - PONG_IN => pong_iq, - PING_OUT => ping_stretched_i, - PONG_OUT => pong_stretched_i, - START_PING_OUT => start_ping_i, - START_PONG_OUT => start_pong_i, - TOGGLE_OUT => open, - DELAY_VALUE_OUT => delay_value_int, - DELAY_VALID_OUT => delay_valid_int, - FSM_ACTIVE_IN => fsm_active_int, - FSM_CE_IN => fsm_ce_int, - FSM_RST_IN => fsm_rst_int, - FSM_CLR_DONE_OUT => fsm_clr_done_int - ); - - cal_phase_q <= (ping_i xor pong_i) when rising_edge(master_clk_i); - - THE_STATISTICS: entity statistics - port map( - AUXCLK => clk_sample, + SAMPLE_CLK => clk_sample, RESET => reset_i, - DELAY_CLK => master_clk_i, - DELAY_START_IN => tx_dlm_i, - DELAY_STOP_IN => rx_dlm_i, - DELAY_COARSE_OUT => coarse_delay_data, -- BUG - DELAY_VALUE_IN => delay_value_int, - DELAY_VALID_IN => delay_valid_int, - FSM_START_IN => phaser_start, - FSM_CLR_DONE_IN => fsm_clr_done_int, - FSM_ACTIVE_OUT => fsm_active_int, - FSM_CE_OUT => fsm_ce_int, - FSM_RST_OUT => fsm_rst_int, - FSM_DONE_OUT => phaser_data(31), - RD_CLK => clk_sys, - RD_ADDRESS_IN => busddmtd_rx.addr(9 downto 0), - RD_DATA_OUT => phaser_data(17 downto 0) + -- input signals + TX_SYNC_IN => ping_i, + TX_CLK_IN => master_clk_i, + RX_SYNC_IN => pong_i, + RX_CLK_IN => pong_clk_i, + START_DELAY_IN => tx_dlm_i, + STOP_DELAY_IN => rx_dlm_i, + -- histogram + HISTO_CLK => clk_sys, + HISTO_START_IN => phaser_start, + HISTO_DONE_OUT => phaser_data(31), + HISTO_ADDR_IN => busddmtd_rx.addr(9 downto 0), + HISTO_DATA_OUT => phaser_data(17 downto 0), + -- + COARSE_DELAY_OUT => coarse_delay_data, + -- + DEBUG_OUT => debug_phaser ); phaser_data(30 downto 18) <= (others => '0'); - + -- simple readout THE_ACK_DELAY_PROC: process( clk_sys ) begin @@ -685,7 +655,7 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate SP => '1', CD => '0', SCLK => clk_sample, - D => ping_stretched_i, + D => debug_phaser(0), Q => ping_stretched_q ); @@ -694,7 +664,7 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate SP => '1', CD => '0', SCLK => clk_sample, - D => pong_stretched_i, + D => debug_phaser(1), Q => pong_stretched_q ); @@ -703,7 +673,7 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate SP => '1', CD => '0', SCLK => clk_sample, - D => start_ping_i, + D => debug_phaser(4), Q => start_ping_q ); @@ -712,7 +682,7 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate SP => '1', CD => '0', SCLK => clk_sample, - D => start_pong_i, + D => debug_phaser(5), Q => start_pong_q ); @@ -760,7 +730,7 @@ end generate; -- bussci3_tx.unknown <= bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys); -- can be used for simple readback on debugging - bussci3_tx.data <= cal_phase_q & coarse_delay_data(30 downto 0); + bussci3_tx.data <= coarse_delay_data; bussci3_tx.ack <= bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys); bussci3_tx.nack <= '0'; bussci3_tx.unknown <= '0'; -- 2.43.0