From 957bd2830c676eaa026fee4a0284bdfdf533e6b7 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 13 Jun 2012 17:56:11 +0000 Subject: [PATCH] *** empty log message *** --- base/trb3_periph_multitest.lpf | 40 ++++- multitest/compile_frankfurt.pl | 156 +++++++++++++++++ multitest/trb3_periph_multitest.p2t | 20 +++ multitest/trb3_periph_multitest.prj | 162 ++++++++++++++++++ {base => multitest}/trb3_periph_multitest.vhd | 61 ++++++- .../trb3_periph_multitest_constraints.lpf | 35 ++++ 6 files changed, 460 insertions(+), 14 deletions(-) create mode 100755 multitest/compile_frankfurt.pl create mode 100644 multitest/trb3_periph_multitest.p2t create mode 100644 multitest/trb3_periph_multitest.prj rename {base => multitest}/trb3_periph_multitest.vhd (91%) create mode 100644 multitest/trb3_periph_multitest_constraints.lpf diff --git a/base/trb3_periph_multitest.lpf b/base/trb3_periph_multitest.lpf index 9559c4b..8f7771f 100644 --- a/base/trb3_periph_multitest.lpf +++ b/base/trb3_periph_multitest.lpf @@ -262,9 +262,9 @@ IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12; LOCATE COMP "KONR_ADC_N_2" SITE "L1"; #DQUL3_7 #67 -LOCA TE COMP "LVDS_IO_16" SITE "J23"; #DQUR0_0 #105 + LOCATE COMP "LVDS_IO_16" SITE "J23"; #DQUR0_0 #105 # LOCATE COMP "LVDS_IO_N_16" SITE "H23"; #DQUR0_1 #107 -LOCA TE COMP "LVDS_IO_17" SITE "G26"; #DQUR0_2 #109 + LOCATE COMP "LVDS_IO_17" SITE "G26"; #DQUR0_2 #109 # LOCATE COMP "LVDS_IO_N_17" SITE "F26"; #DQUR0_3 #111 LOCATE COMP "MADC2_SCLK" SITE "H26"; #DQUR0_4 #113 LOCATE COMP "MADC2_SDIO" SITE "H25"; #DQUR0_5 #115 @@ -291,7 +291,7 @@ LOCA TE COMP "LVDS_IO_17" SITE "G26"; #DQUR0_2 #109 LOCATE COMP "SFP1_LOS" SITE "K26"; #DQUR2_1 #132 LOCATE COMP "RJ45_LVDS_3" SITE "N23"; #DQUR2_2 #134 # LOCATE COMP "RJ45_LVDS_N_3" SITE "N22"; #DQUR2_3 #136 -LOCATE C OMP "RJ45_LVDS_2" SITE "K19"; #DQUR2_4 #138 + LOCATE COMP "RJ45_LVDS_2" SITE "K19"; #DQUR2_4 #138 # LOCATE COMP "RJ45_LVDS_N_2" SITE "L19"; #DQUR2_5 #140 LOCATE COMP "SFP1_TXDIS" SITE "P23"; #DQSUR2_T #142 LOCATE COMP "SFP1_MOD_0" SITE "R22"; #DQSUR2_C #144 @@ -300,8 +300,38 @@ LOCATE C OMP "RJ45_LVDS_2" SITE "K19"; #DQUR2_4 #138 LOCATE COMP "RJ45_LVDS_1" SITE "P21"; #DQUR2_8 #150 # LOCATE COMP "RJ45_LVDS_N_1" SITE "P22"; #DQUR2_9 #152 -# DEFINE PORT GROUP "DQ_group" "DQ*" ; -# IOBUF GROUP "DQ_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN; +DEFINE PORT GROUP "LVDS_group" "LVDS*" ; +IOBUF GROUP "LVDS_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; +DEFINE PORT GROUP "RJ_group" "RJ*" ; +IOBUF GROUP "RJ_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + +DEFINE PORT GROUP "SFP_group" "SFP*" ; +IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP; + +DEFINE PORT GROUP "MADC_LVIN_group" "MADC1_D*" "MADC1_FCO" "MADC1_DC*" "MADC2_D*" "MADC2_FCO" "MADC2_DC*" ; +IOBUF GROUP "MADC_LVIN_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + +DEFINE PORT GROUP "MADC_LVOUT_group" "MADC1_CLK" "MADC2_CLK" ; +IOBUF GROUP "MADC_LVOUT_group" IO_TYPE=LVDS25; + +DEFINE PORT GROUP "MADC_CMOS_group" "MADC1_CSB" "MADC1_PDWN" "MADC1_SCLK" "MADC1_SDIO" "MADC2_CSB" "MADC2_PDWN" "MADC2_SCLK" "MADC2_SDIO"; +IOBUF GROUP "MADC_CMOS_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN; + +IOBUF PORT "KONR_ADC_1" IO_TYPE=LVDS25 DIFFRESISTOR=off; +IOBUF PORT "KONR_ADC_2" IO_TYPE=LVDS25 DIFFRESISTOR=off; +IOBUF PORT "KONR_ADC_DISCH_1" IO_TYPE=LVCMOS25; +IOBUF PORT "KONR_ADC_DISCH_2" IO_TYPE=LVCMOS25; +IOBUF PORT "KONR_ADC_N_1" IO_TYPE=LVCMOS25; +IOBUF PORT "KONR_ADC_N_2" IO_TYPE=LVCMOS25; +IOBUF PORT "KONR_ADC_THR_1" IO_TYPE=LVCMOS25; +IOBUF PORT "KONR_ADC_THR_2" IO_TYPE=LVCMOS25; +IOBUF PORT "WU_RAMP" IO_TYPE=LVDS25; + +DEFINE PORT GROUP "DAC_group" "DAC*" ; +IOBUF GROUP "DAC_group" IO_TYPE=LVCMOS25 PULLMODE=UP; + +DEFINE PORT GROUP "PWM_group" "PWM*" ; +IOBUF GROUP "PWM_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN; ################################################################# # Additional Lines to AddOn diff --git a/multitest/compile_frankfurt.pl b/multitest/compile_frankfurt.pl new file mode 100755 index 0000000..08ed30b --- /dev/null +++ b/multitest/compile_frankfurt.pl @@ -0,0 +1,156 @@ +#!/usr/bin/perl +use Data::Dumper; +use warnings; +use strict; + + + + +################################################################################### +#Settings for this project +my $TOPNAME = "trb3_periph_multitest"; #Name of top-level entity +my $lattice_path = '/d/jspc29/lattice/diamond/1.4.2.105'; +my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/'; +my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; +my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; +################################################################################### + + + + + + + + +use FileHandle; + +$ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; + + + + +my $FAMILYNAME="LatticeECP3"; +my $DEVICENAME="LFE3-150EA"; +my $PACKAGE="FPBGA672"; +my $SPEEDGRADE="8"; + + +#create full lpf file +system("cp ../base/$TOPNAME.lpf workdir/$TOPNAME.lpf"); +system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); + + +#set -e +#set -o errexit + +#generate timestamp +my $t=time; +my $fh = new FileHandle(">version.vhd"); +die "could not open file" if (! defined $fh); +print $fh <close; + +system("env| grep LM_"); +my $r = ""; + +my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; +$r=execute($c, "do_not_exit" ); + + +chdir "workdir"; +$fh = new FileHandle("<$TOPNAME".".srr"); +my @a = <$fh>; +$fh -> close; + + + +foreach (@a) +{ + if(/\@E:/) + { + print "\n"; + $c="cat $TOPNAME.srr | grep \"\@E\""; + system($c); + print "\n\n"; + exit 129; + } +} + + +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; + + +$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; +execute($c); + +my $tpmap = $TOPNAME . "_map" ; + +$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; +execute($c); + +system("rm $TOPNAME.ncd"); + + +$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +execute($c); + +# IOR IO Timing Report +# $c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; +# execute($c); + +# TWR Timing Report +$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|; +# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +chdir ".."; + +exit; + +sub execute { + my ($c, $op) = @_; + #print "option: $op \n"; + $op = "" if(!$op); + print "\n\ncommand to execute: $c \n"; + $r=system($c); + if($r) { + print "$!"; + if($op ne "do_not_exit") { + exit; + } + } + + return $r; + +} diff --git a/multitest/trb3_periph_multitest.p2t b/multitest/trb3_periph_multitest.p2t new file mode 100644 index 0000000..995161f --- /dev/null +++ b/multitest/trb3_periph_multitest.p2t @@ -0,0 +1,20 @@ +-w +-i 15 +-l 5 +-n 1 +-y +-s 12 +-t 11 +-c 1 +-e 2 +-m nodelist.txt +# -w +# -i 6 +# -l 5 +# -n 1 +# -t 1 +# -s 1 +# -c 0 +# -e 0 +# +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1: diff --git a/multitest/trb3_periph_multitest.prj b/multitest/trb3_periph_multitest.prj new file mode 100644 index 0000000..f531255 --- /dev/null +++ b/multitest/trb3_periph_multitest.prj @@ -0,0 +1,162 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology LATTICE-ECP3 +set_option -part LFE3_150EA +set_option -package FN672C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb3_periph_multitest" +set_option -resource_sharing true + +# map options +set_option -frequency 200 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 0 +set_option -pipe 0 +#set_option -force_gsr +set_option -force_gsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true + + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb3_periph_multitest.edf" + +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + + + +#add_file options + +add_file -vhdl -lib work "version.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib "work" "../base/trb3_components.vhd" + +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" + +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" + +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" + +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" + +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" + +add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" + +add_file -vhdl -lib "work" "trb3_periph_multitest.vhd" + +# add_file -vhdl -lib "work" "source/Adder_304.vhd" +# add_file -vhdl -lib "work" "source/bit_sync.vhd" +# add_file -vhdl -lib "work" "source/Channel.vhd" +# add_file -vhdl -lib "work" "source/ddr_off.vhd" +# add_file -vhdl -lib "work" "source/Encoder_304_Bit.vhd" +# add_file -vhdl -lib "work" "source/FIFO_32x512_OutReg.vhd" +# add_file -vhdl -lib "work" "source/MB_SPI.vhd" +# add_file -vhdl -lib "work" "source/pll_100_in_5_out.vhd" +# add_file -vhdl -lib "work" "source/pll_100_in_40_out.vhd" +# add_file -vhdl -lib "work" "source/Reference_channel.vhd" +# +# #add_file -vhdl -lib "work" "source/ROM_Encoder.vhd" +# #add_file -vhdl -lib "work" "source/ROM_encoder_2.vhd" +# add_file -vhdl -lib "work" "source/ROM_encoder_3.vhd" +# +# add_file -vhdl -lib "work" "source/ROM_FIFO.vhd" +# add_file -vhdl -lib "work" "source/TDC.vhd" +# add_file -vhdl -lib "work" "source/trb3_periph.vhd" +# add_file -vhdl -lib "work" "source/up_counter.vhd" + diff --git a/base/trb3_periph_multitest.vhd b/multitest/trb3_periph_multitest.vhd similarity index 91% rename from base/trb3_periph_multitest.vhd rename to multitest/trb3_periph_multitest.vhd index 289af06..41b580f 100644 --- a/base/trb3_periph_multitest.vhd +++ b/multitest/trb3_periph_multitest.vhd @@ -10,7 +10,7 @@ use work.version.all; -entity trb3_periph is +entity trb3_periph_multitest is port( --Clocks CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz @@ -149,7 +149,7 @@ entity trb3_periph is end entity; -architecture trb3_periph_arch of trb3_periph is +architecture trb3_periph_arch of trb3_periph_multitest is --Constants constant REGIO_NUM_STAT_REGS : integer := 2; constant REGIO_NUM_CTRL_REGS : integer := 2; @@ -255,7 +255,13 @@ architecture trb3_periph_arch of trb3_periph is signal spi_bram_rd_d : std_logic_vector(7 downto 0); signal spi_bram_we : std_logic; - + signal dac_read_en : std_logic; + signal dac_write_en : std_logic; + signal dac_data_in : std_logic_vector(31 downto 0); + signal dac_addr : std_logic_vector(4 downto 0); + signal dac_data_out : std_logic_vector(31 downto 0); + signal dac_ack : std_logic; + signal dac_busy : std_logic; --FPGA Test signal time_counter : unsigned(31 downto 0); @@ -305,7 +311,8 @@ begin generic map( SERDES_NUM => 1, --number of serdes in quad EXT_CLOCK => c_NO, --use internal clock - USE_200_MHZ => c_YES --run on 200 MHz clock + USE_200_MHZ => c_YES, --run on 200 MHz clock + USE_CTC => c_NO ) port map( CLK => clk_200_i, @@ -457,14 +464,17 @@ begin --------------------------------------------------------------------------- +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Bus Handler --------------------------------------------------------------------------- THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 2, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", others => x"0000"), - PORT_ADDR_MASK => (0 => 1, 1 => 6, others => 0) + PORT_NUMBER => 3, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", others => x"0000"), + PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, others => 0) ) port map( CLK => clk_100_i, @@ -505,7 +515,18 @@ begin BUS_WRITE_ACK_IN(1) => spimem_ack, BUS_NO_MORE_DATA_IN(1) => '0', BUS_UNKNOWN_ADDR_IN(1) => '0', - + --DAC + BUS_READ_ENABLE_OUT(2) => dac_read_en, + BUS_WRITE_ENABLE_OUT(2) => dac_write_en, + BUS_DATA_OUT(2*32+31 downto 2*32) => dac_data_in, + BUS_ADDR_OUT(2*16+4 downto 2*16) => dac_addr, + BUS_ADDR_OUT(2*16+15 downto 2*16+5) => open, + BUS_TIMEOUT_OUT(2) => open, + BUS_DATA_IN(2*32+31 downto 2*32) => dac_data_out, + BUS_DATAREADY_IN(2) => dac_ack, + BUS_WRITE_ACK_IN(2) => dac_ack, + BUS_NO_MORE_DATA_IN(2) => dac_busy, + BUS_UNKNOWN_ADDR_IN(2) => '0', STAT_DEBUG => open ); @@ -571,8 +592,30 @@ begin PROGRAMN => PROGRAMN ); +--------------------------------------------------------------------------- +-- DAC +--------------------------------------------------------------------------- + THE_DAC_SPI : spi_ltc2600 + port map( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_ADDR_IN => dac_addr, + BUS_READ_IN => dac_read_en, + BUS_WRITE_IN => dac_write_en, + BUS_ACK_OUT => dac_ack, + BUS_BUSY_OUT => dac_busy, + BUS_DATA_IN => dac_data_in, + BUS_DATA_OUT => dac_data_out, + -- SPI connections + SPI_CS_OUT => DAC12_CSB, + SPI_SDI_IN => DAC12_SDO, + SPI_SDO_OUT => DAC12_SDI, + SPI_SCK_OUT => DAC12_SCK + ); - + DAC12_CLRB <= '0'; + --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- diff --git a/multitest/trb3_periph_multitest_constraints.lpf b/multitest/trb3_periph_multitest_constraints.lpf new file mode 100644 index 0000000..7fe6870 --- /dev/null +++ b/multitest/trb3_periph_multitest_constraints.lpf @@ -0,0 +1,35 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Basic Settings +################################################################# + + SYSCONFIG MCCLK_FREQ = 2.1; + + FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; + FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; + FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; + FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; + +################################################################# +# Reset Nets +################################################################# +GSR_NET NET "GSR_N"; + + + + +################################################################# +# Locate Serdes and media interfaces +################################################################# +LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; + + +REGION "MEDIA_UPLINK" "R102C95D" 13 25; +LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; + +MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; +MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; + -- 2.43.0