From 9588ca5216270c03e45832d69dce8e2bc3976951 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 26 Nov 2018 15:22:29 +0100 Subject: [PATCH] add MBS slave to Trb3sc CTS --- cts/config.vhd | 36 ++++++++++++++++++------------------ cts/trb3sc_cts.prj | 1 + cts/trb3sc_cts.vhd | 43 ++++++++++++++++++++++++++++++++++++++++--- 3 files changed, 59 insertions(+), 21 deletions(-) diff --git a/cts/config.vhd b/cts/config.vhd index e38424b..2ffda18 100644 --- a/cts/config.vhd +++ b/cts/config.vhd @@ -75,12 +75,12 @@ package config is --TODO: -- constant INCLUDE_MBS_MASTER : integer range c_NO to c_YES := c_NO; --Which external trigger module (ETM) to use? --- constant INCLUDE_ETM : integer range c_NO to c_YES := c_NO; --- type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2, ETM_CHOICE_CBMNET, ETM_CHOICE_M26); --- constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MBS_VULOM; --- constant ETM_ID : std_logic_vector(7 downto 0); + constant INCLUDE_ETM : integer range c_NO to c_YES := c_YES; + type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2, ETM_CHOICE_CBMNET, ETM_CHOICE_M26); + constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MBS_VULOM; + constant ETM_ID : std_logic_vector(7 downto 0); - constant INCLUDE_TIMESTAMP_GENERATOR : integer := c_YES; + constant INCLUDE_TIMESTAMP_GENERATOR : integer := c_NO; @@ -145,7 +145,7 @@ package config is ------------------------------------------------------------------------------ --Select settings by configuration ------------------------------------------------------------------------------ - constant cts_rdo_additional_ports : integer := INCLUDE_TDC + INCLUDE_TIMESTAMP_GENERATOR; --for TDC + constant cts_rdo_additional_ports : integer := INCLUDE_TDC + INCLUDE_TIMESTAMP_GENERATOR + INCLUDE_ETM; --for TDC constant HW_INFO_BASE : unsigned(31 downto 0) := x"9500A000"; @@ -176,18 +176,18 @@ package body config is constant IS_DOWNLINK : hub_ct := IS_DOWNLINK_ARR(CFG_MODE); constant IS_UPLINK_ONLY : hub_ct := IS_UPLINK_ONLY_ARR(CFG_MODE); --- function etm_id_func return std_logic_vector is --- variable res : unsigned(7 downto 0); --- begin --- res := x"00"; --- if INCLUDE_ETM=c_YES then --- res := x"60"; --- res := res + TO_UNSIGNED(ETM_CHOICE_type'pos(ETM_CHOICE), 4); --- end if; --- return std_logic_vector(res); --- end function; + function etm_id_func return std_logic_vector is + variable res : unsigned(7 downto 0); + begin + res := x"00"; + if INCLUDE_ETM=c_YES then + res := x"60"; + res := res + TO_UNSIGNED(ETM_CHOICE_type'pos(ETM_CHOICE), 4); + end if; + return std_logic_vector(res); + end function; - constant ETM_ID : std_logic_vector(7 downto 0) := x"00";--etm_id_func; + constant ETM_ID : std_logic_vector(7 downto 0) := etm_id_func; function generateIncludedFeatures return std_logic_vector is @@ -195,7 +195,7 @@ function generateIncludedFeatures return std_logic_vector is begin t := (others => '0'); t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1 - t(3 downto 0) := x"0"; --std_logic_vector(TO_UNSIGNED(ETM_CHOICE_type'pos(ETM_CHOICE), 4)); + t(3 downto 0) := std_logic_vector(TO_UNSIGNED(ETM_CHOICE_type'pos(ETM_CHOICE), 4)); t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4)); t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); t(15 downto 15) := std_logic_vector(to_unsigned(INCLUDE_TDC,1)); --TDC diff --git a/cts/trb3sc_cts.prj b/cts/trb3sc_cts.prj index 0938f50..847efd6 100644 --- a/cts/trb3sc_cts.prj +++ b/cts/trb3sc_cts.prj @@ -264,6 +264,7 @@ add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_coin.vhd" add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_pseudorand_pulser.vhd" add_file -vhdl -lib work "../../trb3/cts/source/cts_trigger.vhd" add_file -vhdl -lib work "../../trb3/cts/source/cts.vhd" +add_file -vhdl -lib work "../../trb3/base/code/mbs_vulom_recv.vhd" #TDC add_file -vhdl -lib work "../../trb3sc/tdc_release/tdc_version.vhd" diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd index 2de603b..1e60ddb 100644 --- a/cts/trb3sc_cts.vhd +++ b/cts/trb3sc_cts.vhd @@ -222,6 +222,7 @@ architecture trb3sc_arch of trb3sc_cts is signal reset_via_gbe_long, reset_via_gbe_timer, last_reset_via_gbe_long, make_reset : std_logic; signal hit_in_i : std_logic_vector(64 downto 1); + signal mbs_async_out : std_logic; attribute syn_keep of GSR_N : signal is true; attribute syn_preserve of GSR_N : signal is true; @@ -670,7 +671,7 @@ end generate; ADDON_GROUP_ACTIVITY_OUT => open, ADDON_GROUP_SELECTED_OUT => open, - EXT_TRIGGER_IN => '0', + EXT_TRIGGER_IN => cts_ext_trigger, EXT_STATUS_IN => (others => '0'), EXT_CONTROL_OUT => open, EXT_HEADER_BITS_IN => (others => '0'), @@ -716,7 +717,6 @@ end generate; FEE_DATA_FINISHED_OUT => cts_rdo_finished ); - cts_addon_triggers_in(1 downto 0) <= SPARE_IN(1 downto 0); cts_addon_triggers_in(17 downto 2) <= INP(79 downto 64); buscts_tx.nack <= '0'; @@ -740,6 +740,43 @@ end generate; ); end generate; + assert not(INCLUDE_ETM = c_YES and INCLUDE_TIMESTAMP_GENERATOR = c_YES) report "Timestamp generator and ETM can not be implemented at the same time (TODO: fix this)" severity failure; + +--------------------------------------------------------------------------- +-- MBS receiver +--------------------------------------------------------------------------- + +-- MBS Module + gen_mbs_vulom_as_etm : if ETM_CHOICE = ETM_CHOICE_MBS_VULOM and INCLUDE_ETM = c_YES generate + THE_MBS : entity work.mbs_vulom_recv + port map ( + CLK => clk_sys, + RESET_IN => reset_i, + + MBS_IN => INP(80), + CLK_200 => clk_full, + + TRG_ASYNC_OUT => mbs_async_out, --TODO MBS async connect to TDC + TRG_SYNC_OUT => cts_ext_trigger, + + TRIGGER_IN => cts_rdo_rx.data_valid, + TRG_NUMBER_IN => cts_trg_number, + TRG_CODE_IN => cts_trg_code, + TIMING_TRG_IN => cts_trigger_out, + + DATA_OUT => cts_rdo_additional(0).data, + WRITE_OUT => cts_rdo_additional(0).data_write, + FINISHED_OUT => cts_rdo_additional(0).data_finished, + STATUSBIT_OUT => cts_rdo_additional(0).statusbits, + + CONTROL_REG_IN => cts_ext_control, + STATUS_REG_OUT => cts_ext_status, + HEADER_REG_OUT => cts_ext_header, + + DEBUG => cts_ext_debug + ); + end generate; + --------------------------------------------------------------------------- -- Bus Handler @@ -915,7 +952,7 @@ end generate; HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC -- Trigger signals from handler BUSRDO_RX => cts_rdo_rx, - BUSRDO_TX => cts_rdo_additional(INCLUDE_TIMESTAMP_GENERATOR), + BUSRDO_TX => cts_rdo_additional(INCLUDE_TIMESTAMP_GENERATOR + INCLUDE_ETM), -- Slow control bus BUS_RX => bustdc_rx, BUS_TX => bustdc_tx, -- 2.43.0