From 95a3319a55985a6b36d407f07481cb19347926c4 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 4 Oct 2011 08:18:48 +0000 Subject: [PATCH] *** empty log message *** --- gbe_ecp2m/ipcores/fifo_2048x8.lpc | 94 +- gbe_ecp2m/ipcores/fifo_2048x8.vhd | 3328 +++---- gbe_ecp2m/ipcores/fifo_2048x8_tmpl.vhd | 36 +- gbe_ecp2m/ipcores/fifo_32kx16x8_mb.lpc | 94 +- gbe_ecp2m/ipcores/fifo_32kx16x8_mb.vhd | 2616 ++---- gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.lpc | 16 +- gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.srp | 12 +- gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.vhd | 4255 +++------ .../ipcores/fifo_32kx16x8_mb2_generate.log | 10 +- gbe_ecp2m/ipcores/fifo_32kx16x8_mb2_tmpl.vhd | 4 +- gbe_ecp2m/ipcores/fifo_32kx16x8_mb_tmpl.vhd | 6 +- gbe_ecp2m/ipcores/fifo_4096x32.lpc | 94 +- gbe_ecp2m/ipcores/fifo_4096x32.vhd | 4218 ++++----- gbe_ecp2m/ipcores/fifo_4096x32_tmpl.vhd | 36 +- gbe_ecp2m/ipcores/fifo_4096x9.lpc | 94 +- gbe_ecp2m/ipcores/fifo_4096x9.vhd | 3795 ++++---- gbe_ecp2m/ipcores/fifo_4096x9_tmpl.vhd | 36 +- gbe_ecp2m/ipcores/fifo_64kx8.lpc | 94 +- gbe_ecp2m/ipcores/fifo_64kx8.vhd | 7790 +++++++---------- gbe_ecp2m/ipcores/fifo_64kx8_tmpl.vhd | 36 +- gbe_ecp2m/ipcores/fifo_64kx9.lpc | 16 +- gbe_ecp2m/ipcores/fifo_64kx9.srp | 12 +- gbe_ecp2m/ipcores/fifo_64kx9.vhd | 3851 +++----- gbe_ecp2m/ipcores/fifo_64kx9_generate.log | 10 +- gbe_ecp2m/ipcores/fifo_64kx9_tmpl.vhd | 4 +- gbe_ecp2m/ipcores/ip_mem.lpc | 21 +- gbe_ecp2m/ipcores/ip_mem.vhd | 377 +- gbe_ecp2m/ipcores/ip_mem_tmpl.vhd | 4 +- gbe_ecp2m/ipcores/mac_init_mem.lpc | 93 +- gbe_ecp2m/ipcores/mac_init_mem.vhd | 675 +- gbe_ecp2m/ipcores/mac_init_mem_tmpl.vhd | 30 +- .../sgmii_gbe_pcs32/sgmii_gbe_pcs32.lpc | 52 +- gbe_ecp2m/ipcores/tb_fifo_2048x8_tmpl.vhd | 204 +- .../ipcores/tb_fifo_32kx16x8_mb_tmpl.vhd | 2 +- gbe_ecp2m/ipcores/tb_fifo_4096x32_tmpl.vhd | 204 +- gbe_ecp2m/ipcores/tb_fifo_4096x9_tmpl.vhd | 204 +- gbe_ecp2m/ipcores/tb_fifo_64kx8_tmpl.vhd | 204 +- gbe_ecp2m/ipcores/tb_ip_mem_tmpl.vhd | 2 +- gbe_ecp2m/ipcores/tb_mac_init_mem_tmpl.vhd | 128 +- 39 files changed, 12677 insertions(+), 20080 deletions(-) diff --git a/gbe_ecp2m/ipcores/fifo_2048x8.lpc b/gbe_ecp2m/ipcores/fifo_2048x8.lpc index 542bbe2..7c0b6de 100755 --- a/gbe_ecp2m/ipcores/fifo_2048x8.lpc +++ b/gbe_ecp2m/ipcores/fifo_2048x8.lpc @@ -1,47 +1,47 @@ -[Device] -Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-5F900C -SpeedGrade=-5 -Package=FPBGA900 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.2 -ModuleName=fifo_2048x8 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=12/26/2009 -Time=00:12:59 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=2048 -Width=8 -RDepth=2048 -RWidth=8 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_2048x8 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/22/2011 +Time=11:23:58 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=2048 +Width=8 +RDepth=2048 +RWidth=8 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/gbe_ecp2m/ipcores/fifo_2048x8.vhd b/gbe_ecp2m/ipcores/fifo_2048x8.vhd index 2b75855..82dac9a 100755 --- a/gbe_ecp2m/ipcores/fifo_2048x8.vhd +++ b/gbe_ecp2m/ipcores/fifo_2048x8.vhd @@ -1,1913 +1,1415 @@ --- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) --- Module Version: 5.2 ---/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 2048 -width 8 -depth 2048 -rdata_width 8 -no_enable -pe -1 -pf -1 -e - --- Sat Dec 26 00:12:59 2009 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp2m; -use ecp2m.components.all; --- synopsys translate_on - -entity fifo_2048x8 is - port ( - Data: in std_logic_vector(7 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(7 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_2048x8; - -architecture Structure of fifo_2048x8 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_11: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co5: std_logic; - signal wcount_11: std_logic; - signal co4: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co5_1: std_logic; - signal rcount_11: std_logic; - signal co4_1: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal wcount_r9: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r10: std_logic; - signal empty_cmp_clr: std_logic; - signal rcount_10: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w6: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal rcount_w9: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w10: std_logic; - signal full_cmp_clr: std_logic; - signal wcount_10: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1 - -- synopsys translate_off - generic (initval : in String); - -- synopsys translate_on - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KB - -- synopsys translate_off - generic (GSR : in String; WRITEMODE_B : in String; - CSDECODE_B : in std_logic_vector(2 downto 0); - CSDECODE_A : in std_logic_vector(2 downto 0); - WRITEMODE_A : in String; RESETMODE : in String; - REGMODE_B : in String; REGMODE_A : in String; - DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); - -- synopsys translate_on - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; - CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; - CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute initval : string; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute CSDECODE_B : string; - attribute CSDECODE_A : string; - attribute WRITEMODE_B : string; - attribute WRITEMODE_A : string; - attribute RESETMODE : string; - attribute REGMODE_B : string; - attribute REGMODE_A : string; - attribute DATA_WIDTH_B : string; - attribute DATA_WIDTH_A : string; - attribute GSR : string; - attribute initval of LUT4_31 : label is "0x6996"; - attribute initval of LUT4_30 : label is "0x6996"; - attribute initval of LUT4_29 : label is "0x6996"; - attribute initval of LUT4_28 : label is "0x6996"; - attribute initval of LUT4_27 : label is "0x6996"; - attribute initval of LUT4_26 : label is "0x6996"; - attribute initval of LUT4_25 : label is "0x6996"; - attribute initval of LUT4_24 : label is "0x6996"; - attribute initval of LUT4_23 : label is "0x6996"; - attribute initval of LUT4_22 : label is "0x6996"; - attribute initval of LUT4_21 : label is "0x6996"; - attribute initval of LUT4_20 : label is "0x6996"; - attribute initval of LUT4_19 : label is "0x6996"; - attribute initval of LUT4_18 : label is "0x6996"; - attribute initval of LUT4_17 : label is "0x6996"; - attribute initval of LUT4_16 : label is "0x6996"; - attribute initval of LUT4_15 : label is "0x6996"; - attribute initval of LUT4_14 : label is "0x6996"; - attribute initval of LUT4_13 : label is "0x6996"; - attribute initval of LUT4_12 : label is "0x6996"; - attribute initval of LUT4_11 : label is "0x6996"; - attribute initval of LUT4_10 : label is "0x6996"; - attribute initval of LUT4_9 : label is "0x6996"; - attribute initval of LUT4_8 : label is "0x6996"; - attribute initval of LUT4_7 : label is "0x6996"; - attribute initval of LUT4_6 : label is "0x6996"; - attribute initval of LUT4_5 : label is "0x6996"; - attribute initval of LUT4_4 : label is "0x6996"; - attribute initval of LUT4_3 : label is "0x0410"; - attribute initval of LUT4_2 : label is "0x1004"; - attribute initval of LUT4_1 : label is "0x0140"; - attribute initval of LUT4_0 : label is "0x4001"; - attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_2048x8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; - attribute CSDECODE_B of pdp_ram_0_0_0 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_0_0 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_0_0 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_0_0 : label is "NORMAL"; - attribute GSR of pdp_ram_0_0_0 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_0_0 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_0_0 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_0_0 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_0_0_0 : label is "9"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t24: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t23: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t22: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t21: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t20: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t19: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t18: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t17: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t16: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t15: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t14: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t13: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t12: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t11: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t10: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t9: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t8: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t7: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t6: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t5: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t4: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t3: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t2: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t1: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t0: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - LUT4_31: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_gcount_r211, - DO0=>w_g2b_xor_cluster_0); - - LUT4_30: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, - DO0=>w_g2b_xor_cluster_1); - - LUT4_29: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, - DO0=>w_g2b_xor_cluster_2); - - LUT4_28: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r10); - - LUT4_27: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9); - - LUT4_26: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); - - LUT4_25: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6); - - LUT4_24: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5); - - LUT4_23: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_22: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3); - - LUT4_21: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2); - - LUT4_20: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_19: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_18: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0); - - LUT4_17: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_gcount_w211, - DO0=>r_g2b_xor_cluster_0); - - LUT4_16: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_gcount_w27, - DO0=>r_g2b_xor_cluster_1); - - LUT4_15: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, - DO0=>r_g2b_xor_cluster_2); - - LUT4_14: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w10); - - LUT4_13: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_12: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); - - LUT4_11: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6); - - LUT4_10: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5); - - LUT4_9: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4); - - LUT4_8: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3); - - LUT4_7: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2); - - LUT4_6: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_5: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0); - - LUT4_3: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0410") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x1004") - -- synopsys translate_on - port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0140") - -- synopsys translate_on - port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4001") - -- synopsys translate_on - port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_0: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>scuba_vlo, DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), - DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), - DOB6=>Q(6), DOB7=>Q(7), DOB8=>open, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - FF_121: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_120: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_119: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_118: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_117: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_116: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_115: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_114: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_113: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_112: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_111: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_110: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_109: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_108: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_107: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_106: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_105: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_104: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_103: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_102: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_101: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_100: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_99: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_98: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_97: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_96: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_95: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_94: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_93: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_92: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_91: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_90: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_89: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_88: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_87: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_86: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_85: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_84: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_83: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_82: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_81: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_80: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_79: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_78: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_77: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_76: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_75: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_74: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_73: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_72: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_71: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_70: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_69: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_68: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_67: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_66: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_65: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_64: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_63: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_62: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_61: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_60: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_59: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_58: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_57: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_56: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_55: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_54: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_53: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_52: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_51: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_50: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_49: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_48: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_47: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_46: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_45: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_44: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_43: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_42: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_41: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_40: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_39: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_38: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_37: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_36: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_35: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_34: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_33: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_32: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_31: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_30: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_29: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_28: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_27: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_26: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_25: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_24: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_23: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_22: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_21: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_20: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_19: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_18: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_17: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_16: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_15: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_14: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_13: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_12: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_11: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_10: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_9: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_8: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_7: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_6: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_5: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_4: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_3: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_2: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_1: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0, - B1=>wcount_r9, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r10, - B1=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0, - B1=>rcount_w9, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w10, - B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp2m; -configuration Structure_CON of fifo_2048x8 is - for Structure - for all:AGEB2 use entity ecp2m.AGEB2(V); end for; - for all:AND2 use entity ecp2m.AND2(V); end for; - for all:CU2 use entity ecp2m.CU2(V); end for; - for all:FADD2B use entity ecp2m.FADD2B(V); end for; - for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; - for all:INV use entity ecp2m.INV(V); end for; - for all:OR2 use entity ecp2m.OR2(V); end for; - for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:XOR2 use entity ecp2m.XOR2(V); end for; - for all:DP16KB use entity ecp2m.DP16KB(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.4 +--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2048 -width 8 -depth 2048 -rdata_width 8 -no_enable -pe -1 -pf -1 -e + +-- Thu Sep 22 11:23:58 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_2048x8 is + port ( + Data: in std_logic_vector(7 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(7 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_2048x8; + +architecture Structure of fifo_2048x8 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_11: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co5: std_logic; + signal wcount_11: std_logic; + signal co4: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co5_1: std_logic; + signal rcount_11: std_logic; + signal co4_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r6: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal wcount_r9: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal wcount_r10: std_logic; + signal empty_cmp_clr: std_logic; + signal rcount_10: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal rcount_w6: std_logic; + signal rcount_w7: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w9: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_3: std_logic; + signal rcount_w10: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_10: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_2048x8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t24: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t23: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t22: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t21: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t20: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t19: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t18: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t17: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t16: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t15: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t14: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t13: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t12: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t11: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t10: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t9: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t8: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t7: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t6: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t5: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t4: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t3: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t2: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t1: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t0: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + LUT4_31: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>w_gcount_r211, + DO0=>w_g2b_xor_cluster_0); + + LUT4_30: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, + DO0=>w_g2b_xor_cluster_1); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, + DO0=>w_g2b_xor_cluster_2); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r10); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>r_gcount_w211, + DO0=>r_g2b_xor_cluster_0); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_gcount_w27, + DO0=>r_g2b_xor_cluster_1); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, + DO0=>r_g2b_xor_cluster_2); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w10); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>scuba_vlo, DO0=>rcount_w9); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w5); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w4); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w3); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>rcount_w2); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_11, AD2=>rcount_11, AD1=>w_gcount_r211, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w211, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_0: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>scuba_vlo, DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), + DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7), + DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + FF_121: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_120: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_119: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_118: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_117: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_116: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_115: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_114: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_113: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_112: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_111: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_110: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_109: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_108: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_107: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_106: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_105: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_104: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_103: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_102: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_101: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_100: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_99: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_98: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_97: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_96: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_95: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_94: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_93: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_92: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_91: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_90: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_89: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_88: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_87: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_86: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_85: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_84: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_83: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_82: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_81: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_80: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_79: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_78: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_77: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_76: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_75: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_74: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_73: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_72: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_71: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_70: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_69: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_68: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_67: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_66: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_65: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_64: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_63: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_62: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_61: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_60: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_59: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_58: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_57: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_56: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_55: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_54: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_53: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_52: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_51: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_50: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_49: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_48: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_47: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_46: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_45: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_44: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_43: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_42: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_41: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_40: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_39: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_38: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_37: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_36: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_35: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_34: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_33: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_32: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_31: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_30: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_29: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_28: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_27: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_26: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_25: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_24: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_23: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_22: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_21: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_20: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_19: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_18: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_17: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_16: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_15: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_14: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_13: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_12: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_11: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_10: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_9: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_8: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_7: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_6: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_5: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_4: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_3: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_2: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, + B1=>wcount_r7, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>w_g2b_xor_cluster_0, + B1=>wcount_r9, CI=>co3_2, GE=>co4_2); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>empty_cmp_set, B0=>wcount_r10, + B1=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w9, CI=>co3_3, GE=>co4_3); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w10, + B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_2048x8 is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/fifo_2048x8_tmpl.vhd b/gbe_ecp2m/ipcores/fifo_2048x8_tmpl.vhd index c365fcc..1a3333f 100755 --- a/gbe_ecp2m/ipcores/fifo_2048x8_tmpl.vhd +++ b/gbe_ecp2m/ipcores/fifo_2048x8_tmpl.vhd @@ -1,18 +1,18 @@ --- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) --- Module Version: 5.2 --- Sat Dec 26 00:12:59 2009 - --- parameterized module component declaration -component fifo_2048x8 - port (Data: in std_logic_vector(7 downto 0); WrClock: in std_logic; - RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; - Reset: in std_logic; RPReset: in std_logic; - Q: out std_logic_vector(7 downto 0); Empty: out std_logic; - Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_2048x8 - port map (Data(7 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(7 downto 0)=>__, Empty=>__, - Full=>__); +-- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.4 +-- Thu Sep 22 11:23:58 2011 + +-- parameterized module component declaration +component fifo_2048x8 + port (Data: in std_logic_vector(7 downto 0); WrClock: in std_logic; + RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; + Reset: in std_logic; RPReset: in std_logic; + Q: out std_logic_vector(7 downto 0); Empty: out std_logic; + Full: out std_logic); +end component; + +-- parameterized module component instance +__ : fifo_2048x8 + port map (Data(7 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, + RdEn=>__, Reset=>__, RPReset=>__, Q(7 downto 0)=>__, Empty=>__, + Full=>__); diff --git a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb.lpc b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb.lpc index 8c82306..aa233bb 100755 --- a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb.lpc +++ b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb.lpc @@ -1,47 +1,47 @@ -[Device] -Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-5F900C -SpeedGrade=-5 -Package=FPBGA900 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.3 -ModuleName=fifo_32kx16x8_mb -SourceFormat=Schematic/VHDL -ParameterFileVersion=1.0 -Date=02/05/2010 -Time=16:48:12 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=32768 -Width=16 -RDepth=65536 -RWidth=8 -regout=0 -CtrlByRdEn=0 -EmpFlg=1 -PeMode=Dynamic - Single Threshold -PeAssert=16 -PeDeassert=12 -FullFlg=1 -PfMode=Dynamic - Single Threshold -PfAssert=32752 -PfDeassert=506 -RDataCount=1 -WDataCount=1 -EnECC=0 +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_32kx16x8_mb +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/22/2011 +Time=11:22:35 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=32768 +Width=16 +RDepth=65536 +RWidth=8 +regout=0 +CtrlByRdEn=0 +EmpFlg=1 +PeMode=Dynamic - Single Threshold +PeAssert=16 +PeDeassert=12 +FullFlg=1 +PfMode=Dynamic - Single Threshold +PfAssert=32752 +PfDeassert=506 +RDataCount=1 +WDataCount=1 +EnECC=0 diff --git a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb.vhd b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb.vhd index d40ad50..a24a3e6 100755 --- a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb.vhd +++ b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb.vhd @@ -1,14 +1,14 @@ --- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41) --- Module Version: 5.3 ---X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 32768 -width 16 -depth 32768 -rdata_width 8 -no_enable -pe 0 -pf 0 -rfill -fill -e +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.4 +--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32768 -width 16 -depth 32768 -rdata_width 8 -no_enable -pe 0 -pf 0 -rfill -fill -e --- Fri Feb 05 16:48:13 2010 +-- Thu Sep 22 11:22:35 2011 library IEEE; use IEEE.std_logic_1164.all; -- synopsys translate_off -library ecp2m; -use ecp2m.components.all; +library ecp3; +use ecp3.components.all; -- synopsys translate_on entity fifo_32kx16x8_mb is @@ -586,30 +586,18 @@ architecture Structure of fifo_32kx16x8_mb is S0: out std_logic; S1: out std_logic); end component; component FD1P3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on port (D: in std_logic; SP: in std_logic; CK: in std_logic; PD: in std_logic; Q: out std_logic); end component; component FD1P3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on port (D: in std_logic; SP: in std_logic; CK: in std_logic; CD: in std_logic; Q: out std_logic); end component; component FD1S3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on port (D: in std_logic; CK: in std_logic; PD: in std_logic; Q: out std_logic); end component; component FD1S3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on port (D: in std_logic; CK: in std_logic; CD: in std_logic; Q: out std_logic); end component; @@ -624,10 +612,8 @@ architecture Structure of fifo_32kx16x8_mb is component OR2 port (A: in std_logic; B: in std_logic; Z: out std_logic); end component; - component ROM16X1 - -- synopsys translate_off - generic (initval : in String); - -- synopsys translate_on + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; AD0: in std_logic; DO0: out std_logic); end component; @@ -640,15 +626,12 @@ architecture Structure of fifo_32kx16x8_mb is component XOR2 port (A: in std_logic; B: in std_logic; Z: out std_logic); end component; - component DP16KB - -- synopsys translate_off + component DP16KC generic (GSR : in String; WRITEMODE_B : in String; - CSDECODE_B : in std_logic_vector(2 downto 0); - CSDECODE_A : in std_logic_vector(2 downto 0); - WRITEMODE_A : in String; RESETMODE : in String; - REGMODE_B : in String; REGMODE_A : in String; - DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); - -- synopsys translate_on + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); port (DIA0: in std_logic; DIA1: in std_logic; DIA2: in std_logic; DIA3: in std_logic; DIA4: in std_logic; DIA5: in std_logic; @@ -665,8 +648,8 @@ architecture Structure of fifo_32kx16x8_mb is ADA8: in std_logic; ADA9: in std_logic; ADA10: in std_logic; ADA11: in std_logic; ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; - CSA0: in std_logic; CSA1: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; CSA2: in std_logic; RSTA: in std_logic; DIB0: in std_logic; DIB1: in std_logic; DIB2: in std_logic; DIB3: in std_logic; @@ -684,8 +667,8 @@ architecture Structure of fifo_32kx16x8_mb is ADB8: in std_logic; ADB9: in std_logic; ADB10: in std_logic; ADB11: in std_logic; ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; - CSB0: in std_logic; CSB1: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; CSB2: in std_logic; RSTB: in std_logic; DOA0: out std_logic; DOA1: out std_logic; DOA2: out std_logic; DOA3: out std_logic; @@ -706,456 +689,106 @@ architecture Structure of fifo_32kx16x8_mb is DOB14: out std_logic; DOB15: out std_logic; DOB16: out std_logic; DOB17: out std_logic); end component; - attribute initval : string; attribute MEM_LPC_FILE : string; attribute MEM_INIT_FILE : string; - attribute CSDECODE_B : string; - attribute CSDECODE_A : string; - attribute WRITEMODE_B : string; - attribute WRITEMODE_A : string; attribute RESETMODE : string; - attribute REGMODE_B : string; - attribute REGMODE_A : string; - attribute DATA_WIDTH_B : string; - attribute DATA_WIDTH_A : string; attribute GSR : string; - attribute initval of LUT4_52 : label is "0x6996"; - attribute initval of LUT4_51 : label is "0x6996"; - attribute initval of LUT4_50 : label is "0x6996"; - attribute initval of LUT4_49 : label is "0x6996"; - attribute initval of LUT4_48 : label is "0x6996"; - attribute initval of LUT4_47 : label is "0x6996"; - attribute initval of LUT4_46 : label is "0x6996"; - attribute initval of LUT4_45 : label is "0x6996"; - attribute initval of LUT4_44 : label is "0x6996"; - attribute initval of LUT4_43 : label is "0x6996"; - attribute initval of LUT4_42 : label is "0x6996"; - attribute initval of LUT4_41 : label is "0x6996"; - attribute initval of LUT4_40 : label is "0x6996"; - attribute initval of LUT4_39 : label is "0x6996"; - attribute initval of LUT4_38 : label is "0x6996"; - attribute initval of LUT4_37 : label is "0x6996"; - attribute initval of LUT4_36 : label is "0x6996"; - attribute initval of LUT4_35 : label is "0x6996"; - attribute initval of LUT4_34 : label is "0x6996"; - attribute initval of LUT4_33 : label is "0x6996"; - attribute initval of LUT4_32 : label is "0x6996"; - attribute initval of LUT4_31 : label is "0x6996"; - attribute initval of LUT4_30 : label is "0x6996"; - attribute initval of LUT4_29 : label is "0x6996"; - attribute initval of LUT4_28 : label is "0x6996"; - attribute initval of LUT4_27 : label is "0x6996"; - attribute initval of LUT4_26 : label is "0x6996"; - attribute initval of LUT4_25 : label is "0x6996"; - attribute initval of LUT4_24 : label is "0x6996"; - attribute initval of LUT4_23 : label is "0x6996"; - attribute initval of LUT4_22 : label is "0x6996"; - attribute initval of LUT4_21 : label is "0x6996"; - attribute initval of LUT4_20 : label is "0x6996"; - attribute initval of LUT4_19 : label is "0x6996"; - attribute initval of LUT4_18 : label is "0x6996"; - attribute initval of LUT4_17 : label is "0x6996"; - attribute initval of LUT4_16 : label is "0x6996"; - attribute initval of LUT4_15 : label is "0x6996"; - attribute initval of LUT4_14 : label is "0x6996"; - attribute initval of LUT4_13 : label is "0x6996"; - attribute initval of LUT4_12 : label is "0x6996"; - attribute initval of LUT4_11 : label is "0x6996"; - attribute initval of LUT4_10 : label is "0x6996"; - attribute initval of LUT4_9 : label is "0x6996"; - attribute initval of LUT4_8 : label is "0x6996"; - attribute initval of LUT4_7 : label is "0x6996"; - attribute initval of LUT4_6 : label is "0x6996"; - attribute initval of LUT4_5 : label is "0x6996"; - attribute initval of LUT4_4 : label is "0x6996"; - attribute initval of LUT4_3 : label is "0x0410"; - attribute initval of LUT4_2 : label is "0x1004"; - attribute initval of LUT4_1 : label is "0x0140"; - attribute initval of LUT4_0 : label is "0x4001"; attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; - attribute CSDECODE_B of pdp_ram_0_0_31 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_0_31 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_0_31 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_0_31 : label is "NORMAL"; - attribute GSR of pdp_ram_0_0_31 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_0_31 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_0_31 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_0_31 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_0_31 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_0_31 : label is "2"; + attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_0_1_30 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_0_1_30 : label is ""; - attribute CSDECODE_B of pdp_ram_0_1_30 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_1_30 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_1_30 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_1_30 : label is "NORMAL"; - attribute GSR of pdp_ram_0_1_30 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_1_30 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_1_30 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_1_30 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_1_30 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_1_30 : label is "2"; + attribute RESETMODE of pdp_ram_0_1_30 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_0_2_29 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_0_2_29 : label is ""; - attribute CSDECODE_B of pdp_ram_0_2_29 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_2_29 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_2_29 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_2_29 : label is "NORMAL"; - attribute GSR of pdp_ram_0_2_29 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_2_29 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_2_29 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_2_29 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_2_29 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_2_29 : label is "2"; + attribute RESETMODE of pdp_ram_0_2_29 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_0_3_28 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_0_3_28 : label is ""; - attribute CSDECODE_B of pdp_ram_0_3_28 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_3_28 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_3_28 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_3_28 : label is "NORMAL"; - attribute GSR of pdp_ram_0_3_28 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_3_28 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_3_28 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_3_28 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_3_28 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_3_28 : label is "2"; + attribute RESETMODE of pdp_ram_0_3_28 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_0_4_27 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_0_4_27 : label is ""; - attribute CSDECODE_B of pdp_ram_0_4_27 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_4_27 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_4_27 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_4_27 : label is "NORMAL"; - attribute GSR of pdp_ram_0_4_27 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_4_27 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_4_27 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_4_27 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_4_27 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_4_27 : label is "2"; + attribute RESETMODE of pdp_ram_0_4_27 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_0_5_26 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_0_5_26 : label is ""; - attribute CSDECODE_B of pdp_ram_0_5_26 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_5_26 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_5_26 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_5_26 : label is "NORMAL"; - attribute GSR of pdp_ram_0_5_26 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_5_26 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_5_26 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_5_26 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_5_26 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_5_26 : label is "2"; + attribute RESETMODE of pdp_ram_0_5_26 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_0_6_25 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_0_6_25 : label is ""; - attribute CSDECODE_B of pdp_ram_0_6_25 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_6_25 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_6_25 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_6_25 : label is "NORMAL"; - attribute GSR of pdp_ram_0_6_25 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_6_25 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_6_25 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_6_25 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_6_25 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_6_25 : label is "2"; + attribute RESETMODE of pdp_ram_0_6_25 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_0_7_24 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_0_7_24 : label is ""; - attribute CSDECODE_B of pdp_ram_0_7_24 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_7_24 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_7_24 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_7_24 : label is "NORMAL"; - attribute GSR of pdp_ram_0_7_24 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_7_24 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_7_24 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_7_24 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_7_24 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_7_24 : label is "2"; + attribute RESETMODE of pdp_ram_0_7_24 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_1_0_23 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_1_0_23 : label is ""; - attribute CSDECODE_B of pdp_ram_1_0_23 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_1_0_23 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_1_0_23 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_1_0_23 : label is "NORMAL"; - attribute GSR of pdp_ram_1_0_23 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_1_0_23 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_1_0_23 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_1_0_23 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_1_0_23 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_1_0_23 : label is "2"; + attribute RESETMODE of pdp_ram_1_0_23 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_1_1_22 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_1_1_22 : label is ""; - attribute CSDECODE_B of pdp_ram_1_1_22 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_1_1_22 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_1_1_22 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_1_1_22 : label is "NORMAL"; - attribute GSR of pdp_ram_1_1_22 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_1_1_22 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_1_1_22 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_1_1_22 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_1_1_22 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_1_1_22 : label is "2"; + attribute RESETMODE of pdp_ram_1_1_22 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_1_2_21 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_1_2_21 : label is ""; - attribute CSDECODE_B of pdp_ram_1_2_21 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_1_2_21 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_1_2_21 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_1_2_21 : label is "NORMAL"; - attribute GSR of pdp_ram_1_2_21 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_1_2_21 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_1_2_21 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_1_2_21 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_1_2_21 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_1_2_21 : label is "2"; + attribute RESETMODE of pdp_ram_1_2_21 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_1_3_20 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_1_3_20 : label is ""; - attribute CSDECODE_B of pdp_ram_1_3_20 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_1_3_20 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_1_3_20 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_1_3_20 : label is "NORMAL"; - attribute GSR of pdp_ram_1_3_20 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_1_3_20 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_1_3_20 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_1_3_20 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_1_3_20 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_1_3_20 : label is "2"; + attribute RESETMODE of pdp_ram_1_3_20 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_1_4_19 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_1_4_19 : label is ""; - attribute CSDECODE_B of pdp_ram_1_4_19 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_1_4_19 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_1_4_19 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_1_4_19 : label is "NORMAL"; - attribute GSR of pdp_ram_1_4_19 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_1_4_19 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_1_4_19 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_1_4_19 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_1_4_19 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_1_4_19 : label is "2"; + attribute RESETMODE of pdp_ram_1_4_19 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_1_5_18 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_1_5_18 : label is ""; - attribute CSDECODE_B of pdp_ram_1_5_18 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_1_5_18 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_1_5_18 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_1_5_18 : label is "NORMAL"; - attribute GSR of pdp_ram_1_5_18 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_1_5_18 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_1_5_18 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_1_5_18 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_1_5_18 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_1_5_18 : label is "2"; + attribute RESETMODE of pdp_ram_1_5_18 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_1_6_17 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_1_6_17 : label is ""; - attribute CSDECODE_B of pdp_ram_1_6_17 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_1_6_17 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_1_6_17 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_1_6_17 : label is "NORMAL"; - attribute GSR of pdp_ram_1_6_17 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_1_6_17 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_1_6_17 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_1_6_17 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_1_6_17 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_1_6_17 : label is "2"; + attribute RESETMODE of pdp_ram_1_6_17 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_1_7_16 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_1_7_16 : label is ""; - attribute CSDECODE_B of pdp_ram_1_7_16 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_1_7_16 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_1_7_16 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_1_7_16 : label is "NORMAL"; - attribute GSR of pdp_ram_1_7_16 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_1_7_16 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_1_7_16 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_1_7_16 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_1_7_16 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_1_7_16 : label is "2"; + attribute RESETMODE of pdp_ram_1_7_16 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_2_0_15 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_2_0_15 : label is ""; - attribute CSDECODE_B of pdp_ram_2_0_15 : label is "0b010"; - attribute CSDECODE_A of pdp_ram_2_0_15 : label is "0b010"; - attribute WRITEMODE_B of pdp_ram_2_0_15 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_2_0_15 : label is "NORMAL"; - attribute GSR of pdp_ram_2_0_15 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_2_0_15 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_2_0_15 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_2_0_15 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_2_0_15 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_2_0_15 : label is "2"; + attribute RESETMODE of pdp_ram_2_0_15 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_2_1_14 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_2_1_14 : label is ""; - attribute CSDECODE_B of pdp_ram_2_1_14 : label is "0b010"; - attribute CSDECODE_A of pdp_ram_2_1_14 : label is "0b010"; - attribute WRITEMODE_B of pdp_ram_2_1_14 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_2_1_14 : label is "NORMAL"; - attribute GSR of pdp_ram_2_1_14 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_2_1_14 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_2_1_14 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_2_1_14 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_2_1_14 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_2_1_14 : label is "2"; + attribute RESETMODE of pdp_ram_2_1_14 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_2_2_13 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_2_2_13 : label is ""; - attribute CSDECODE_B of pdp_ram_2_2_13 : label is "0b010"; - attribute CSDECODE_A of pdp_ram_2_2_13 : label is "0b010"; - attribute WRITEMODE_B of pdp_ram_2_2_13 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_2_2_13 : label is "NORMAL"; - attribute GSR of pdp_ram_2_2_13 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_2_2_13 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_2_2_13 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_2_2_13 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_2_2_13 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_2_2_13 : label is "2"; + attribute RESETMODE of pdp_ram_2_2_13 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_2_3_12 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_2_3_12 : label is ""; - attribute CSDECODE_B of pdp_ram_2_3_12 : label is "0b010"; - attribute CSDECODE_A of pdp_ram_2_3_12 : label is "0b010"; - attribute WRITEMODE_B of pdp_ram_2_3_12 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_2_3_12 : label is "NORMAL"; - attribute GSR of pdp_ram_2_3_12 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_2_3_12 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_2_3_12 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_2_3_12 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_2_3_12 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_2_3_12 : label is "2"; + attribute RESETMODE of pdp_ram_2_3_12 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_2_4_11 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_2_4_11 : label is ""; - attribute CSDECODE_B of pdp_ram_2_4_11 : label is "0b010"; - attribute CSDECODE_A of pdp_ram_2_4_11 : label is "0b010"; - attribute WRITEMODE_B of pdp_ram_2_4_11 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_2_4_11 : label is "NORMAL"; - attribute GSR of pdp_ram_2_4_11 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_2_4_11 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_2_4_11 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_2_4_11 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_2_4_11 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_2_4_11 : label is "2"; + attribute RESETMODE of pdp_ram_2_4_11 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_2_5_10 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_2_5_10 : label is ""; - attribute CSDECODE_B of pdp_ram_2_5_10 : label is "0b010"; - attribute CSDECODE_A of pdp_ram_2_5_10 : label is "0b010"; - attribute WRITEMODE_B of pdp_ram_2_5_10 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_2_5_10 : label is "NORMAL"; - attribute GSR of pdp_ram_2_5_10 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_2_5_10 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_2_5_10 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_2_5_10 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_2_5_10 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_2_5_10 : label is "2"; + attribute RESETMODE of pdp_ram_2_5_10 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_2_6_9 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_2_6_9 : label is ""; - attribute CSDECODE_B of pdp_ram_2_6_9 : label is "0b010"; - attribute CSDECODE_A of pdp_ram_2_6_9 : label is "0b010"; - attribute WRITEMODE_B of pdp_ram_2_6_9 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_2_6_9 : label is "NORMAL"; - attribute GSR of pdp_ram_2_6_9 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_2_6_9 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_2_6_9 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_2_6_9 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_2_6_9 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_2_6_9 : label is "2"; + attribute RESETMODE of pdp_ram_2_6_9 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_2_7_8 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_2_7_8 : label is ""; - attribute CSDECODE_B of pdp_ram_2_7_8 : label is "0b010"; - attribute CSDECODE_A of pdp_ram_2_7_8 : label is "0b010"; - attribute WRITEMODE_B of pdp_ram_2_7_8 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_2_7_8 : label is "NORMAL"; - attribute GSR of pdp_ram_2_7_8 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_2_7_8 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_2_7_8 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_2_7_8 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_2_7_8 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_2_7_8 : label is "2"; + attribute RESETMODE of pdp_ram_2_7_8 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_3_0_7 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_3_0_7 : label is ""; - attribute CSDECODE_B of pdp_ram_3_0_7 : label is "0b011"; - attribute CSDECODE_A of pdp_ram_3_0_7 : label is "0b011"; - attribute WRITEMODE_B of pdp_ram_3_0_7 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_3_0_7 : label is "NORMAL"; - attribute GSR of pdp_ram_3_0_7 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_3_0_7 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_3_0_7 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_3_0_7 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_3_0_7 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_3_0_7 : label is "2"; + attribute RESETMODE of pdp_ram_3_0_7 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_3_1_6 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_3_1_6 : label is ""; - attribute CSDECODE_B of pdp_ram_3_1_6 : label is "0b011"; - attribute CSDECODE_A of pdp_ram_3_1_6 : label is "0b011"; - attribute WRITEMODE_B of pdp_ram_3_1_6 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_3_1_6 : label is "NORMAL"; - attribute GSR of pdp_ram_3_1_6 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_3_1_6 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_3_1_6 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_3_1_6 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_3_1_6 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_3_1_6 : label is "2"; + attribute RESETMODE of pdp_ram_3_1_6 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_3_2_5 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_3_2_5 : label is ""; - attribute CSDECODE_B of pdp_ram_3_2_5 : label is "0b011"; - attribute CSDECODE_A of pdp_ram_3_2_5 : label is "0b011"; - attribute WRITEMODE_B of pdp_ram_3_2_5 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_3_2_5 : label is "NORMAL"; - attribute GSR of pdp_ram_3_2_5 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_3_2_5 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_3_2_5 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_3_2_5 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_3_2_5 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_3_2_5 : label is "2"; + attribute RESETMODE of pdp_ram_3_2_5 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_3_3_4 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_3_3_4 : label is ""; - attribute CSDECODE_B of pdp_ram_3_3_4 : label is "0b011"; - attribute CSDECODE_A of pdp_ram_3_3_4 : label is "0b011"; - attribute WRITEMODE_B of pdp_ram_3_3_4 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_3_3_4 : label is "NORMAL"; - attribute GSR of pdp_ram_3_3_4 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_3_3_4 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_3_3_4 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_3_3_4 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_3_3_4 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_3_3_4 : label is "2"; + attribute RESETMODE of pdp_ram_3_3_4 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_3_4_3 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_3_4_3 : label is ""; - attribute CSDECODE_B of pdp_ram_3_4_3 : label is "0b011"; - attribute CSDECODE_A of pdp_ram_3_4_3 : label is "0b011"; - attribute WRITEMODE_B of pdp_ram_3_4_3 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_3_4_3 : label is "NORMAL"; - attribute GSR of pdp_ram_3_4_3 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_3_4_3 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_3_4_3 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_3_4_3 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_3_4_3 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_3_4_3 : label is "2"; + attribute RESETMODE of pdp_ram_3_4_3 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_3_5_2 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_3_5_2 : label is ""; - attribute CSDECODE_B of pdp_ram_3_5_2 : label is "0b011"; - attribute CSDECODE_A of pdp_ram_3_5_2 : label is "0b011"; - attribute WRITEMODE_B of pdp_ram_3_5_2 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_3_5_2 : label is "NORMAL"; - attribute GSR of pdp_ram_3_5_2 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_3_5_2 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_3_5_2 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_3_5_2 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_3_5_2 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_3_5_2 : label is "2"; + attribute RESETMODE of pdp_ram_3_5_2 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_3_6_1 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_3_6_1 : label is ""; - attribute CSDECODE_B of pdp_ram_3_6_1 : label is "0b011"; - attribute CSDECODE_A of pdp_ram_3_6_1 : label is "0b011"; - attribute WRITEMODE_B of pdp_ram_3_6_1 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_3_6_1 : label is "NORMAL"; - attribute GSR of pdp_ram_3_6_1 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_3_6_1 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_3_6_1 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_3_6_1 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_3_6_1 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_3_6_1 : label is "2"; + attribute RESETMODE of pdp_ram_3_6_1 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_3_7_0 : label is "fifo_32kx16x8_mb.lpc"; attribute MEM_INIT_FILE of pdp_ram_3_7_0 : label is ""; - attribute CSDECODE_B of pdp_ram_3_7_0 : label is "0b011"; - attribute CSDECODE_A of pdp_ram_3_7_0 : label is "0b011"; - attribute WRITEMODE_B of pdp_ram_3_7_0 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_3_7_0 : label is "NORMAL"; - attribute GSR of pdp_ram_3_7_0 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_3_7_0 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_3_7_0 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_3_7_0 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_3_7_0 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_3_7_0 : label is "2"; + attribute RESETMODE of pdp_ram_3_7_0 : label is "SYNC"; attribute GSR of FF_236 : label is "ENABLED"; attribute GSR of FF_235 : label is "ENABLED"; attribute GSR of FF_234 : label is "ENABLED"; @@ -1505,366 +1138,268 @@ begin XOR2_t6: XOR2 port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); - LUT4_52: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_52: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, AD1=>w_gcount_r214, AD0=>w_gcount_r215, DO0=>w_g2b_xor_cluster_0); - LUT4_51: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_51: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>w_gcount_r210, AD0=>w_gcount_r211, DO0=>w_g2b_xor_cluster_1); - LUT4_50: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_50: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>w_g2b_xor_cluster_2); - LUT4_49: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_49: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>w_g2b_xor_cluster_3); - LUT4_48: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_48: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r14); - LUT4_47: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_47: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13); - LUT4_46: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_46: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); - LUT4_45: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_45: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10); - LUT4_44: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_44: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9); - LUT4_43: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_43: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8); - LUT4_42: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_42: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7); - LUT4_41: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_41: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6); - LUT4_40: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_40: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_2_1); - LUT4_39: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_39: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5); - LUT4_38: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_38: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4); - LUT4_37: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_37: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3); - LUT4_36: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_36: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); - LUT4_35: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_35: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, DO0=>wcount_r2); - LUT4_34: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_34: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_2); - LUT4_33: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_33: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, DO0=>wcount_r1); - LUT4_32: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_32: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, DO0=>wcount_r0); - LUT4_31: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_31: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, AD1=>r_gcount_w215, AD0=>r_gcount_w216, DO0=>r_g2b_xor_cluster_0); - LUT4_30: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_30: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, AD1=>r_gcount_w211, AD0=>r_gcount_w212, DO0=>r_g2b_xor_cluster_1); - LUT4_29: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_29: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>r_g2b_xor_cluster_2); - LUT4_28: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_28: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>r_g2b_xor_cluster_3); - LUT4_27: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_27: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w15); - LUT4_26: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_26: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); - LUT4_25: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_25: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); - LUT4_24: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_24: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); - LUT4_23: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_23: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w10); - LUT4_22: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_22: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); - LUT4_21: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_21: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); - LUT4_20: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_20: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); - LUT4_19: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_19: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_2_1); - LUT4_18: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_18: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); - LUT4_17: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_17: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); - LUT4_16: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_16: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); - LUT4_15: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_15: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); - LUT4_14: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_14: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, DO0=>rcount_w3); - LUT4_13: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_13: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_2); - LUT4_12: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_12: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, DO0=>rcount_w2); - LUT4_11: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_11: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, DO0=>rcount_w1); - LUT4_10: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_10: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet); - LUT4_9: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_9: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_1); - LUT4_8: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_8: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_2); - LUT4_7: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_7: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_3); - LUT4_6: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_6: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>func_xor_inet_4); - LUT4_5: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_5: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, DO0=>func_xor_inet_5); - LUT4_4: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_4: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); @@ -1880,31 +1415,23 @@ begin XOR2_t2: XOR2 port map (A=>w_gcount_r215, B=>rptr_16, Z=>rfill_sub_msb); - LUT4_3: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0410") - -- synopsys translate_on + LUT4_3: ROM16X1A + generic map (initval=> X"0410") port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>empty_cmp_set); - LUT4_2: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x1004") - -- synopsys translate_on + LUT4_2: ROM16X1A + generic map (initval=> X"1004") port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>empty_cmp_clr); - LUT4_1: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0140") - -- synopsys translate_on + LUT4_1: ROM16X1A + generic map (initval=> X"0140") port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>full_cmp_set); - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4001") - -- synopsys translate_on + LUT4_0: ROM16X1A + generic map (initval=> X"4001") port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>full_cmp_clr); @@ -1917,13 +1444,11 @@ begin AND2_t0: AND2 port map (A=>rcnt_reg_16, B=>rcnt_reg_15, Z=>ae_setsig); - pdp_ram_0_0_31: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + pdp_ram_0_0_31: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -1934,7 +1459,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -1945,25 +1470,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_0, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_1_30: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_1_30: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -1974,7 +1497,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -1985,25 +1508,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_1, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_2_29: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_1, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_2_29: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -2014,7 +1535,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -2025,25 +1546,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_2, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_3_28: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_2, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_3_28: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -2054,7 +1573,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -2065,25 +1584,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_3, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_4_27: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_3, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_4_27: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -2094,7 +1611,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -2105,25 +1622,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_4, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_5_26: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_4, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_5_26: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -2134,7 +1649,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -2145,25 +1660,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_5, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_6_25: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_5, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_6_25: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -2174,7 +1687,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -2185,25 +1698,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_6, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_7_24: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_6, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_7_24: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -2214,7 +1725,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -2225,25 +1736,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_7, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_0_23: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_7, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_0_23: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -2254,7 +1763,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -2265,25 +1774,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_0, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_1_22: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_1_22: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -2294,7 +1801,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -2305,25 +1812,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_1, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_2_21: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_1, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_2_21: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -2334,7 +1839,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -2345,25 +1850,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_2, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_3_20: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_2, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_3_20: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -2374,7 +1877,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -2385,25 +1888,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_3, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_4_19: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_3, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_4_19: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -2414,7 +1915,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -2425,25 +1926,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_4, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_5_18: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_4, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_5_18: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -2454,7 +1953,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -2465,25 +1964,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_5, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_6_17: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_5, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_6_17: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -2494,7 +1991,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -2505,25 +2002,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_6, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_7_16: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_6, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_7_16: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -2534,7 +2029,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -2545,25 +2040,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_7, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_0_15: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_7, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_0_15: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -2574,7 +2067,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -2585,25 +2078,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_0, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_1_14: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_1_14: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -2614,7 +2105,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -2625,25 +2116,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_1, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_2_13: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_1, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_2_13: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -2654,7 +2143,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -2665,25 +2154,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_2, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_3_12: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_2, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_3_12: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -2694,7 +2181,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -2705,25 +2192,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_3, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_4_11: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_3, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_4_11: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -2734,7 +2219,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -2745,25 +2230,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_4, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_5_10: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_4, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_5_10: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -2774,7 +2257,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -2785,25 +2268,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_5, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_6_9: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_5, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_6_9: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -2814,7 +2295,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -2825,25 +2306,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_6, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_7_8: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_6, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_7_8: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -2854,7 +2333,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -2865,25 +2344,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_7, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_0_7: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_7, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_0_7: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(8), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -2894,7 +2371,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -2905,25 +2382,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_0, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_1_6: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_1_6: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -2934,7 +2409,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -2945,25 +2420,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_1, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_2_5: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_1, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_2_5: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(10), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -2974,7 +2447,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -2985,25 +2458,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_2, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_3_4: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_2, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_3_4: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -3014,7 +2485,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -3025,25 +2496,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_3, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_4_3: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_3, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_4_3: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(12), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -3054,7 +2523,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -3065,25 +2534,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_4, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_5_2: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_4, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_5_2: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -3094,7 +2561,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -3105,25 +2572,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_5, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_6_1: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_5, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_6_1: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(14), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -3134,7 +2599,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -3145,25 +2610,23 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_6, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_7_0: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_6, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_7_0: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, DATA_WIDTH_A=> 2) - -- synopsys translate_on port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo, DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, @@ -3174,7 +2637,7 @@ begin ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6, ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10, ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_13, CSA1=>wptr_14, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, @@ -3185,1568 +2648,857 @@ begin ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_7, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_7, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); FF_236: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, Q=>wcount_0); FF_235: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_1); FF_234: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_2); FF_233: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_3); FF_232: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_4); FF_231: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_5); FF_230: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_6); FF_229: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_7); FF_228: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_8); FF_227: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_9); FF_226: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_10); FF_225: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_11); FF_224: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_12); FF_223: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_13); FF_222: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_14); FF_221: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_15); FF_220: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_0); FF_219: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_1); FF_218: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_2); FF_217: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_3); FF_216: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_4); FF_215: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_5); FF_214: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_6); FF_213: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_7); FF_212: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_8); FF_211: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_9); FF_210: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_10); FF_209: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_11); FF_208: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_12); FF_207: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_13); FF_206: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_14); FF_205: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_15); FF_204: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_0); FF_203: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_1); FF_202: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_2); FF_201: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_3); FF_200: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_4); FF_199: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_5); FF_198: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_6); FF_197: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_7); FF_196: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_8); FF_195: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_9); FF_194: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_10); FF_193: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_11); FF_192: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_12); FF_191: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_13); FF_190: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_14); FF_189: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_15); FF_188: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, Q=>rcount_0); FF_187: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_1); FF_186: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_2); FF_185: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_3); FF_184: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_4); FF_183: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_5); FF_182: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_6); FF_181: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_7); FF_180: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_8); FF_179: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_9); FF_178: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_10); FF_177: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_11); FF_176: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_12); FF_175: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_13); FF_174: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_14); FF_173: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_15); FF_172: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_16); FF_171: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_0); FF_170: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_1); FF_169: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_2); FF_168: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_3); FF_167: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_4); FF_166: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_5); FF_165: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_6); FF_164: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_7); FF_163: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_8); FF_162: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_9); FF_161: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_10); FF_160: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_11); FF_159: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_12); FF_158: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_13); FF_157: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_14); FF_156: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_15); FF_155: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_16); FF_154: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_0); FF_153: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_1); FF_152: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_2); FF_151: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_3); FF_150: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_4); FF_149: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_5); FF_148: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_6); FF_147: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_7); FF_146: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_8); FF_145: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_9); FF_144: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_10); FF_143: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_11); FF_142: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_12); FF_141: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_13); FF_140: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_14); FF_139: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_15); FF_138: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_16); FF_137: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, Q=>rptr_14_ff); FF_136: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, Q=>rptr_15_ff); FF_135: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); FF_134: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); FF_133: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); FF_132: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); FF_131: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); FF_130: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); FF_129: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); FF_128: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); FF_127: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); FF_126: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); FF_125: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, Q=>w_gcount_r10); FF_124: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, Q=>w_gcount_r11); FF_123: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, Q=>w_gcount_r12); FF_122: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, Q=>w_gcount_r13); FF_121: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, Q=>w_gcount_r14); FF_120: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, Q=>w_gcount_r15); FF_119: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); FF_118: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); FF_117: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); FF_116: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); FF_115: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); FF_114: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); FF_113: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); FF_112: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); FF_111: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); FF_110: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); FF_109: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); FF_108: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); FF_107: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); FF_106: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); FF_105: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); FF_104: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); FF_103: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); FF_102: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r20); FF_101: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r21); FF_100: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r22); FF_99: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r23); FF_98: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r24); FF_97: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r25); FF_96: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r26); FF_95: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r27); FF_94: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r28); FF_93: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r29); FF_92: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, Q=>w_gcount_r210); FF_91: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, Q=>w_gcount_r211); FF_90: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, Q=>w_gcount_r212); FF_89: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, Q=>w_gcount_r213); FF_88: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, Q=>w_gcount_r214); FF_87: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, Q=>w_gcount_r215); FF_86: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); FF_85: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); FF_84: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); FF_83: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); FF_82: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); FF_81: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); FF_80: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); FF_79: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); FF_78: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); FF_77: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); FF_76: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w210); FF_75: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w211); FF_74: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w212); FF_73: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w213); FF_72: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w214); FF_71: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w215); FF_70: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w216); FF_69: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_0, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_0); FF_68: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_1, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_1); FF_67: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_2, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_2); FF_66: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_3, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_3); FF_65: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_4, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_4); FF_64: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_5, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_5); FF_63: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_6, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_6); FF_62: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_7, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_7); FF_61: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_8, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_8); FF_60: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_9, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_9); FF_59: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_10, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_10); FF_58: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_11, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_11); FF_57: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_12, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_12); FF_56: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_13, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_13); FF_55: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_14, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_14); FF_54: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_15, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_15); FF_53: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0); FF_52: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1); FF_51: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2); FF_50: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3); FF_49: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4); FF_48: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5); FF_47: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_6, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_6); FF_46: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_7, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_7); FF_45: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_8, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_8); FF_44: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_9, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_9); FF_43: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_10, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_10); FF_42: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_11, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_11); FF_41: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_12, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_12); FF_40: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_13, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_13); FF_39: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_14, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_14); FF_38: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_15, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_15); FF_37: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_16, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_16); FF_36: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0)); FF_35: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1)); FF_34: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2)); FF_33: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3)); FF_32: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4)); FF_31: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5)); FF_30: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6)); FF_29: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7)); FF_28: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8)); FF_27: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9)); FF_26: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10)); FF_25: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11)); FF_24: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_12, CK=>WrClock, CD=>Reset, Q=>WCNT(12)); FF_23: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_13, CK=>WrClock, CD=>Reset, Q=>WCNT(13)); FF_22: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_14, CK=>WrClock, CD=>Reset, Q=>WCNT(14)); FF_21: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_15, CK=>WrClock, CD=>Reset, Q=>WCNT(15)); FF_20: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0)); FF_19: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1)); FF_18: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2)); FF_17: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3)); FF_16: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4)); FF_15: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5)); FF_14: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6)); FF_13: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7)); FF_12: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8)); FF_11: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9)); FF_10: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_10, CK=>RdClock, CD=>rRst, Q=>RCNT(10)); FF_9: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_11, CK=>RdClock, CD=>rRst, Q=>RCNT(11)); FF_8: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_12, CK=>RdClock, CD=>rRst, Q=>RCNT(12)); FF_7: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_13, CK=>RdClock, CD=>rRst, Q=>RCNT(13)); FF_6: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_14, CK=>RdClock, CD=>rRst, Q=>RCNT(14)); FF_5: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_15, CK=>RdClock, CD=>rRst, Q=>RCNT(15)); FF_4: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_16, CK=>RdClock, CD=>rRst, Q=>RCNT(16)); FF_3: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); FF_2: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); FF_1: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty); FF_0: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>AlmostFull); w_gctr_cia: FADD2B @@ -5219,26 +3971,26 @@ begin end Structure; -- synopsys translate_off -library ecp2m; +library ecp3; configuration Structure_CON of fifo_32kx16x8_mb is for Structure - for all:AGEB2 use entity ecp2m.AGEB2(V); end for; - for all:AND2 use entity ecp2m.AND2(V); end for; - for all:CU2 use entity ecp2m.CU2(V); end for; - for all:FADD2B use entity ecp2m.FADD2B(V); end for; - for all:FSUB2B use entity ecp2m.FSUB2B(V); end for; - for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; - for all:INV use entity ecp2m.INV(V); end for; - for all:MUX41 use entity ecp2m.MUX41(V); end for; - for all:OR2 use entity ecp2m.OR2(V); end for; - for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:XOR2 use entity ecp2m.XOR2(V); end for; - for all:DP16KB use entity ecp2m.DP16KB(V); end for; + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FSUB2B use entity ecp3.FSUB2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:MUX41 use entity ecp3.MUX41(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; end for; end Structure_CON; diff --git a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.lpc b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.lpc index 44dafba..4ac80c1 100644 --- a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.lpc +++ b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.lpc @@ -1,9 +1,9 @@ [Device] -Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-5F900C -SpeedGrade=-5 -Package=FPBGA900 +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 OperatingCondition=COM Status=P @@ -14,10 +14,10 @@ CoreStatus=Demo CoreName=FIFO_DC CoreRevision=5.4 ModuleName=fifo_32kx16x8_mb2 -SourceFormat=Schematic/VHDL +SourceFormat=VHDL ParameterFileVersion=1.0 -Date=07/23/2010 -Time=21:15:52 +Date=09/22/2011 +Time=11:22:54 [Parameters] Verilog=0 diff --git a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.srp b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.srp index bff323e..2b6645f 100644 --- a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.srp +++ b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.srp @@ -1,13 +1,13 @@ -SCUBA, Version ispLever_v8.0_PROD_Build (41) -Fri Jul 23 21:15:52 2010 +SCUBA, Version Diamond_1.3_Production (92) +Thu Sep 22 11:22:54 2011 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved. +Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - Issued command : /opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n fifo_32kx16x8_mb2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 15 -data_width 18 -num_words 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill -e + Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_32kx16x8_mb2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 15 -data_width 18 -num_words 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill -e Circuit name : fifo_32kx16x8_mb2 Module type : ebfifo Module Version : 5.4 @@ -35,9 +35,9 @@ Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved. INV : 13 MUX321 : 9 OR2 : 1 - ROM16X1 : 181 + ROM16X1A : 181 XOR2 : 35 - DP16KB : 32 + DP16KC : 32 Estimated Resource Usage: LUT : 491 EBR : 32 diff --git a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.vhd b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.vhd index 7d1240d..fef0b67 100644 --- a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.vhd +++ b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2.vhd @@ -1,14 +1,14 @@ --- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41) +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) -- Module Version: 5.4 ---/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 32768 -width 18 -depth 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill -e +--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32768 -width 18 -depth 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill -e --- Fri Jul 23 21:15:52 2010 +-- Thu Sep 22 11:22:54 2011 library IEEE; use IEEE.std_logic_1164.all; -- synopsys translate_off -library ecp2m; -use ecp2m.components.all; +library ecp3; +use ecp3.components.all; -- synopsys translate_on entity fifo_32kx16x8_mb2 is @@ -983,30 +983,18 @@ architecture Structure of fifo_32kx16x8_mb2 is S0: out std_logic; S1: out std_logic); end component; component FD1P3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on port (D: in std_logic; SP: in std_logic; CK: in std_logic; PD: in std_logic; Q: out std_logic); end component; component FD1P3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on port (D: in std_logic; SP: in std_logic; CK: in std_logic; CD: in std_logic; Q: out std_logic); end component; component FD1S3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on port (D: in std_logic; CK: in std_logic; PD: in std_logic; Q: out std_logic); end component; component FD1S3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on port (D: in std_logic; CK: in std_logic; CD: in std_logic; Q: out std_logic); end component; @@ -1031,10 +1019,8 @@ architecture Structure of fifo_32kx16x8_mb2 is component OR2 port (A: in std_logic; B: in std_logic; Z: out std_logic); end component; - component ROM16X1 - -- synopsys translate_off - generic (initval : in String); - -- synopsys translate_on + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; AD0: in std_logic; DO0: out std_logic); end component; @@ -1047,15 +1033,12 @@ architecture Structure of fifo_32kx16x8_mb2 is component XOR2 port (A: in std_logic; B: in std_logic; Z: out std_logic); end component; - component DP16KB - -- synopsys translate_off + component DP16KC generic (GSR : in String; WRITEMODE_B : in String; - CSDECODE_B : in std_logic_vector(2 downto 0); - CSDECODE_A : in std_logic_vector(2 downto 0); - WRITEMODE_A : in String; RESETMODE : in String; - REGMODE_B : in String; REGMODE_A : in String; - DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); - -- synopsys translate_on + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); port (DIA0: in std_logic; DIA1: in std_logic; DIA2: in std_logic; DIA3: in std_logic; DIA4: in std_logic; DIA5: in std_logic; @@ -1072,8 +1055,8 @@ architecture Structure of fifo_32kx16x8_mb2 is ADA8: in std_logic; ADA9: in std_logic; ADA10: in std_logic; ADA11: in std_logic; ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; - CSA0: in std_logic; CSA1: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; CSA2: in std_logic; RSTA: in std_logic; DIB0: in std_logic; DIB1: in std_logic; DIB2: in std_logic; DIB3: in std_logic; @@ -1091,8 +1074,8 @@ architecture Structure of fifo_32kx16x8_mb2 is ADB8: in std_logic; ADB9: in std_logic; ADB10: in std_logic; ADB11: in std_logic; ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; - CSB0: in std_logic; CSB1: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; CSB2: in std_logic; RSTB: in std_logic; DOA0: out std_logic; DOA1: out std_logic; DOA2: out std_logic; DOA3: out std_logic; @@ -1113,584 +1096,106 @@ architecture Structure of fifo_32kx16x8_mb2 is DOB14: out std_logic; DOB15: out std_logic; DOB16: out std_logic; DOB17: out std_logic); end component; - attribute initval : string; attribute MEM_LPC_FILE : string; attribute MEM_INIT_FILE : string; - attribute CSDECODE_B : string; - attribute CSDECODE_A : string; - attribute WRITEMODE_B : string; - attribute WRITEMODE_A : string; attribute RESETMODE : string; - attribute REGMODE_B : string; - attribute REGMODE_A : string; - attribute DATA_WIDTH_B : string; - attribute DATA_WIDTH_A : string; attribute GSR : string; - attribute initval of LUT4_180 : label is "0x8000"; - attribute initval of LUT4_179 : label is "0x8000"; - attribute initval of LUT4_178 : label is "0x8000"; - attribute initval of LUT4_177 : label is "0x8000"; - attribute initval of LUT4_176 : label is "0x8000"; - attribute initval of LUT4_175 : label is "0x8000"; - attribute initval of LUT4_174 : label is "0x8000"; - attribute initval of LUT4_173 : label is "0x8000"; - attribute initval of LUT4_172 : label is "0x8000"; - attribute initval of LUT4_171 : label is "0x8000"; - attribute initval of LUT4_170 : label is "0x8000"; - attribute initval of LUT4_169 : label is "0x8000"; - attribute initval of LUT4_168 : label is "0x8000"; - attribute initval of LUT4_167 : label is "0x8000"; - attribute initval of LUT4_166 : label is "0x8000"; - attribute initval of LUT4_165 : label is "0x8000"; - attribute initval of LUT4_164 : label is "0x8000"; - attribute initval of LUT4_163 : label is "0x8000"; - attribute initval of LUT4_162 : label is "0x8000"; - attribute initval of LUT4_161 : label is "0x8000"; - attribute initval of LUT4_160 : label is "0x8000"; - attribute initval of LUT4_159 : label is "0x8000"; - attribute initval of LUT4_158 : label is "0x8000"; - attribute initval of LUT4_157 : label is "0x8000"; - attribute initval of LUT4_156 : label is "0x8000"; - attribute initval of LUT4_155 : label is "0x8000"; - attribute initval of LUT4_154 : label is "0x8000"; - attribute initval of LUT4_153 : label is "0x8000"; - attribute initval of LUT4_152 : label is "0x8000"; - attribute initval of LUT4_151 : label is "0x8000"; - attribute initval of LUT4_150 : label is "0x8000"; - attribute initval of LUT4_149 : label is "0x8000"; - attribute initval of LUT4_148 : label is "0x8000"; - attribute initval of LUT4_147 : label is "0x8000"; - attribute initval of LUT4_146 : label is "0x8000"; - attribute initval of LUT4_145 : label is "0x8000"; - attribute initval of LUT4_144 : label is "0x8000"; - attribute initval of LUT4_143 : label is "0x8000"; - attribute initval of LUT4_142 : label is "0x8000"; - attribute initval of LUT4_141 : label is "0x8000"; - attribute initval of LUT4_140 : label is "0x8000"; - attribute initval of LUT4_139 : label is "0x8000"; - attribute initval of LUT4_138 : label is "0x8000"; - attribute initval of LUT4_137 : label is "0x8000"; - attribute initval of LUT4_136 : label is "0x8000"; - attribute initval of LUT4_135 : label is "0x8000"; - attribute initval of LUT4_134 : label is "0x8000"; - attribute initval of LUT4_133 : label is "0x8000"; - attribute initval of LUT4_132 : label is "0x8000"; - attribute initval of LUT4_131 : label is "0x8000"; - attribute initval of LUT4_130 : label is "0x8000"; - attribute initval of LUT4_129 : label is "0x8000"; - attribute initval of LUT4_128 : label is "0x8000"; - attribute initval of LUT4_127 : label is "0x8000"; - attribute initval of LUT4_126 : label is "0x8000"; - attribute initval of LUT4_125 : label is "0x8000"; - attribute initval of LUT4_124 : label is "0x8000"; - attribute initval of LUT4_123 : label is "0x8000"; - attribute initval of LUT4_122 : label is "0x8000"; - attribute initval of LUT4_121 : label is "0x8000"; - attribute initval of LUT4_120 : label is "0x8000"; - attribute initval of LUT4_119 : label is "0x8000"; - attribute initval of LUT4_118 : label is "0x8000"; - attribute initval of LUT4_117 : label is "0x8000"; - attribute initval of LUT4_116 : label is "0x8000"; - attribute initval of LUT4_115 : label is "0x8000"; - attribute initval of LUT4_114 : label is "0x8000"; - attribute initval of LUT4_113 : label is "0x8000"; - attribute initval of LUT4_112 : label is "0x8000"; - attribute initval of LUT4_111 : label is "0x8000"; - attribute initval of LUT4_110 : label is "0x8000"; - attribute initval of LUT4_109 : label is "0x8000"; - attribute initval of LUT4_108 : label is "0x8000"; - attribute initval of LUT4_107 : label is "0x8000"; - attribute initval of LUT4_106 : label is "0x8000"; - attribute initval of LUT4_105 : label is "0x8000"; - attribute initval of LUT4_104 : label is "0x8000"; - attribute initval of LUT4_103 : label is "0x8000"; - attribute initval of LUT4_102 : label is "0x8000"; - attribute initval of LUT4_101 : label is "0x8000"; - attribute initval of LUT4_100 : label is "0x8000"; - attribute initval of LUT4_99 : label is "0x8000"; - attribute initval of LUT4_98 : label is "0x8000"; - attribute initval of LUT4_97 : label is "0x8000"; - attribute initval of LUT4_96 : label is "0x8000"; - attribute initval of LUT4_95 : label is "0x8000"; - attribute initval of LUT4_94 : label is "0x8000"; - attribute initval of LUT4_93 : label is "0x8000"; - attribute initval of LUT4_92 : label is "0x8000"; - attribute initval of LUT4_91 : label is "0x8000"; - attribute initval of LUT4_90 : label is "0x8000"; - attribute initval of LUT4_89 : label is "0x8000"; - attribute initval of LUT4_88 : label is "0x8000"; - attribute initval of LUT4_87 : label is "0x8000"; - attribute initval of LUT4_86 : label is "0x8000"; - attribute initval of LUT4_85 : label is "0x8000"; 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attribute MEM_INIT_FILE of pdp_ram_14_0_17 : label is ""; - attribute CSDECODE_B of pdp_ram_14_0_17 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_14_0_17 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_14_0_17 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_14_0_17 : label is "NORMAL"; - attribute GSR of pdp_ram_14_0_17 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_14_0_17 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_14_0_17 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_14_0_17 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_14_0_17 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_14_0_17 : label is "18"; + attribute RESETMODE of pdp_ram_14_0_17 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_15_0_16 : label is "fifo_32kx16x8_mb2.lpc"; attribute MEM_INIT_FILE of pdp_ram_15_0_16 : label is ""; - attribute CSDECODE_B of pdp_ram_15_0_16 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_15_0_16 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_15_0_16 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_15_0_16 : label is "NORMAL"; - attribute GSR of pdp_ram_15_0_16 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_15_0_16 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_15_0_16 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_15_0_16 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_15_0_16 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_15_0_16 : label is "18"; + attribute RESETMODE of pdp_ram_15_0_16 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_16_0_15 : label is "fifo_32kx16x8_mb2.lpc"; attribute MEM_INIT_FILE of pdp_ram_16_0_15 : label is ""; - attribute CSDECODE_B of pdp_ram_16_0_15 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_16_0_15 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_16_0_15 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_16_0_15 : label is "NORMAL"; - attribute GSR of pdp_ram_16_0_15 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_16_0_15 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_16_0_15 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_16_0_15 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_16_0_15 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_16_0_15 : label is "18"; + attribute RESETMODE of pdp_ram_16_0_15 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_17_0_14 : label is "fifo_32kx16x8_mb2.lpc"; attribute MEM_INIT_FILE of pdp_ram_17_0_14 : label is ""; - attribute CSDECODE_B of pdp_ram_17_0_14 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_17_0_14 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_17_0_14 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_17_0_14 : label is "NORMAL"; - attribute GSR of pdp_ram_17_0_14 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_17_0_14 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_17_0_14 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_17_0_14 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_17_0_14 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_17_0_14 : label is "18"; + attribute RESETMODE of pdp_ram_17_0_14 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_18_0_13 : label is "fifo_32kx16x8_mb2.lpc"; attribute MEM_INIT_FILE of pdp_ram_18_0_13 : label is ""; - attribute CSDECODE_B of pdp_ram_18_0_13 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_18_0_13 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_18_0_13 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_18_0_13 : label is "NORMAL"; - attribute GSR of pdp_ram_18_0_13 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_18_0_13 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_18_0_13 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_18_0_13 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_18_0_13 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_18_0_13 : label is "18"; + attribute RESETMODE of pdp_ram_18_0_13 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_19_0_12 : label is "fifo_32kx16x8_mb2.lpc"; attribute MEM_INIT_FILE of pdp_ram_19_0_12 : label is ""; - attribute CSDECODE_B of pdp_ram_19_0_12 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_19_0_12 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_19_0_12 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_19_0_12 : label is "NORMAL"; - attribute GSR of pdp_ram_19_0_12 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_19_0_12 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_19_0_12 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_19_0_12 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_19_0_12 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_19_0_12 : label is "18"; + attribute RESETMODE of pdp_ram_19_0_12 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_20_0_11 : label is "fifo_32kx16x8_mb2.lpc"; attribute MEM_INIT_FILE of pdp_ram_20_0_11 : label is ""; - attribute CSDECODE_B of pdp_ram_20_0_11 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_20_0_11 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_20_0_11 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_20_0_11 : label is "NORMAL"; - attribute GSR of pdp_ram_20_0_11 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_20_0_11 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_20_0_11 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_20_0_11 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_20_0_11 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_20_0_11 : label is "18"; + attribute RESETMODE of pdp_ram_20_0_11 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_21_0_10 : label is "fifo_32kx16x8_mb2.lpc"; attribute MEM_INIT_FILE of pdp_ram_21_0_10 : label is ""; - attribute CSDECODE_B of pdp_ram_21_0_10 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_21_0_10 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_21_0_10 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_21_0_10 : label is "NORMAL"; - attribute GSR of pdp_ram_21_0_10 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_21_0_10 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_21_0_10 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_21_0_10 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_21_0_10 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_21_0_10 : label is "18"; + attribute RESETMODE of pdp_ram_21_0_10 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_22_0_9 : label is "fifo_32kx16x8_mb2.lpc"; attribute MEM_INIT_FILE of pdp_ram_22_0_9 : label is ""; - attribute CSDECODE_B of pdp_ram_22_0_9 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_22_0_9 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_22_0_9 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_22_0_9 : label is "NORMAL"; - attribute GSR of pdp_ram_22_0_9 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_22_0_9 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_22_0_9 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_22_0_9 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_22_0_9 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_22_0_9 : label is "18"; + attribute RESETMODE of pdp_ram_22_0_9 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_23_0_8 : label is "fifo_32kx16x8_mb2.lpc"; attribute MEM_INIT_FILE of pdp_ram_23_0_8 : label is ""; - attribute CSDECODE_B of pdp_ram_23_0_8 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_23_0_8 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_23_0_8 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_23_0_8 : label is "NORMAL"; - attribute GSR of pdp_ram_23_0_8 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_23_0_8 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_23_0_8 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_23_0_8 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_23_0_8 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_23_0_8 : label is "18"; + attribute RESETMODE of pdp_ram_23_0_8 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_24_0_7 : label is "fifo_32kx16x8_mb2.lpc"; attribute MEM_INIT_FILE of pdp_ram_24_0_7 : label is ""; - attribute CSDECODE_B of pdp_ram_24_0_7 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_24_0_7 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_24_0_7 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_24_0_7 : label is "NORMAL"; - attribute GSR of pdp_ram_24_0_7 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_24_0_7 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_24_0_7 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_24_0_7 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_24_0_7 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_24_0_7 : label is "18"; + attribute RESETMODE of pdp_ram_24_0_7 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_25_0_6 : label is "fifo_32kx16x8_mb2.lpc"; attribute MEM_INIT_FILE of pdp_ram_25_0_6 : label is ""; - attribute CSDECODE_B of pdp_ram_25_0_6 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_25_0_6 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_25_0_6 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_25_0_6 : label is "NORMAL"; - attribute GSR of pdp_ram_25_0_6 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_25_0_6 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_25_0_6 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_25_0_6 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_25_0_6 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_25_0_6 : label is "18"; + attribute RESETMODE of pdp_ram_25_0_6 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_26_0_5 : label is "fifo_32kx16x8_mb2.lpc"; attribute MEM_INIT_FILE of pdp_ram_26_0_5 : label is ""; - attribute CSDECODE_B of pdp_ram_26_0_5 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_26_0_5 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_26_0_5 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_26_0_5 : label is "NORMAL"; - attribute GSR of pdp_ram_26_0_5 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_26_0_5 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_26_0_5 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_26_0_5 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_26_0_5 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_26_0_5 : label is "18"; + attribute RESETMODE of pdp_ram_26_0_5 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_27_0_4 : label is "fifo_32kx16x8_mb2.lpc"; attribute MEM_INIT_FILE of pdp_ram_27_0_4 : label is ""; - attribute CSDECODE_B of pdp_ram_27_0_4 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_27_0_4 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_27_0_4 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_27_0_4 : label is "NORMAL"; - attribute GSR of pdp_ram_27_0_4 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_27_0_4 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_27_0_4 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_27_0_4 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_27_0_4 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_27_0_4 : label is "18"; + attribute RESETMODE of pdp_ram_27_0_4 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_28_0_3 : label is "fifo_32kx16x8_mb2.lpc"; attribute MEM_INIT_FILE of pdp_ram_28_0_3 : label is ""; - attribute CSDECODE_B of pdp_ram_28_0_3 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_28_0_3 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_28_0_3 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_28_0_3 : label is "NORMAL"; - attribute GSR of pdp_ram_28_0_3 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_28_0_3 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_28_0_3 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_28_0_3 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_28_0_3 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_28_0_3 : label is "18"; + attribute RESETMODE of pdp_ram_28_0_3 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_29_0_2 : label is "fifo_32kx16x8_mb2.lpc"; attribute MEM_INIT_FILE of pdp_ram_29_0_2 : label is ""; - attribute CSDECODE_B of pdp_ram_29_0_2 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_29_0_2 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_29_0_2 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_29_0_2 : label is "NORMAL"; - attribute GSR of pdp_ram_29_0_2 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_29_0_2 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_29_0_2 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_29_0_2 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_29_0_2 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_29_0_2 : label is "18"; + attribute RESETMODE of pdp_ram_29_0_2 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_30_0_1 : label is "fifo_32kx16x8_mb2.lpc"; attribute MEM_INIT_FILE of pdp_ram_30_0_1 : label is ""; - attribute CSDECODE_B of pdp_ram_30_0_1 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_30_0_1 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_30_0_1 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_30_0_1 : label is "NORMAL"; - attribute GSR of pdp_ram_30_0_1 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_30_0_1 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_30_0_1 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_30_0_1 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_30_0_1 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_30_0_1 : label is "18"; + attribute RESETMODE of pdp_ram_30_0_1 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_31_0_0 : label is "fifo_32kx16x8_mb2.lpc"; attribute MEM_INIT_FILE of pdp_ram_31_0_0 : label is ""; - attribute CSDECODE_B of pdp_ram_31_0_0 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_31_0_0 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_31_0_0 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_31_0_0 : label is "NORMAL"; - attribute GSR of pdp_ram_31_0_0 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_31_0_0 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_31_0_0 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_31_0_0 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_31_0_0 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_31_0_0 : label is "18"; + attribute RESETMODE of pdp_ram_31_0_0 : label is "SYNC"; attribute GSR of FF_239 : label is "ENABLED"; attribute GSR of FF_238 : label is "ENABLED"; attribute GSR of FF_237 : label is "ENABLED"; @@ -2058,17 +1563,13 @@ begin INV_6: INV port map (A=>wptr_14, Z=>wptr_14_inv); - LUT4_180: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_180: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, AD0=>wptr_13_inv, DO0=>func_and_inet); - LUT4_179: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_179: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet, AD2=>wptr_14_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec0_p00); @@ -2087,1248 +1588,898 @@ begin INV_1: INV port map (A=>rptr_15, Z=>rptr_15_inv); - LUT4_178: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_178: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, AD0=>rptr_14_inv, DO0=>func_and_inet_1); - LUT4_177: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_177: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_1, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec1_r10); - LUT4_176: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_176: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, AD0=>wptr_13_inv, DO0=>func_and_inet_2); - LUT4_175: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_175: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_2, AD2=>wptr_14_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec2_p01); - LUT4_174: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_174: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, AD0=>rptr_14_inv, DO0=>func_and_inet_3); - LUT4_173: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_173: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_3, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec3_r11); - LUT4_172: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_172: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, AD0=>wptr_13_inv, DO0=>func_and_inet_4); - LUT4_171: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_171: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_4, AD2=>wptr_14_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec4_p02); - LUT4_170: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_170: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, AD0=>rptr_14_inv, DO0=>func_and_inet_5); - LUT4_169: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_169: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_5, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec5_r12); - LUT4_168: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_168: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, AD0=>wptr_13_inv, DO0=>func_and_inet_6); - LUT4_167: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_167: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_6, AD2=>wptr_14_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec6_p03); - LUT4_166: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_166: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, AD0=>rptr_14_inv, DO0=>func_and_inet_7); - LUT4_165: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_165: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_7, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec7_r13); - LUT4_164: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_164: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, AD0=>wptr_13_inv, DO0=>func_and_inet_8); - LUT4_163: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_163: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_8, AD2=>wptr_14_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec8_p04); - LUT4_162: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_162: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, AD0=>rptr_14_inv, DO0=>func_and_inet_9); - LUT4_161: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_161: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_9, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec9_r14); - LUT4_160: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_160: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, AD0=>wptr_13_inv, DO0=>func_and_inet_10); - LUT4_159: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_159: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_10, AD2=>wptr_14_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec10_p05); - LUT4_158: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_158: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, AD0=>rptr_14_inv, DO0=>func_and_inet_11); - LUT4_157: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_157: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_11, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec11_r15); - LUT4_156: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_156: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13_inv, DO0=>func_and_inet_12); - LUT4_155: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_155: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_12, AD2=>wptr_14_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec12_p06); - LUT4_154: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_154: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14_inv, DO0=>func_and_inet_13); - LUT4_153: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_153: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_13, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec13_r16); - LUT4_152: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_152: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13_inv, DO0=>func_and_inet_14); - LUT4_151: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_151: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_14, AD2=>wptr_14_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec14_p07); - LUT4_150: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_150: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14_inv, DO0=>func_and_inet_15); - LUT4_149: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_149: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_15, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec15_r17); - LUT4_148: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_148: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, AD0=>wptr_13, DO0=>func_and_inet_16); - LUT4_147: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_147: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_16, AD2=>wptr_14_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec16_p08); - LUT4_146: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_146: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, AD0=>rptr_14, DO0=>func_and_inet_17); - LUT4_145: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_145: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_17, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec17_r18); - LUT4_144: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_144: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, AD0=>wptr_13, DO0=>func_and_inet_18); - LUT4_143: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_143: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_18, AD2=>wptr_14_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec18_p09); - LUT4_142: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_142: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, AD0=>rptr_14, DO0=>func_and_inet_19); - LUT4_141: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_141: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_19, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec19_r19); - LUT4_140: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_140: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, AD0=>wptr_13, DO0=>func_and_inet_20); - LUT4_139: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_139: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_20, AD2=>wptr_14_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec20_p010); - LUT4_138: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_138: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, AD0=>rptr_14, DO0=>func_and_inet_21); - LUT4_137: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_137: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_21, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec21_r110); - LUT4_136: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_136: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, AD0=>wptr_13, DO0=>func_and_inet_22); - LUT4_135: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_135: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_22, AD2=>wptr_14_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec22_p011); - LUT4_134: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_134: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, AD0=>rptr_14, DO0=>func_and_inet_23); - LUT4_133: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_133: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_23, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec23_r111); - LUT4_132: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_132: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, AD0=>wptr_13, DO0=>func_and_inet_24); - LUT4_131: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_131: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_24, AD2=>wptr_14_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec24_p012); - LUT4_130: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_130: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, AD0=>rptr_14, DO0=>func_and_inet_25); - LUT4_129: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_129: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_25, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec25_r112); - LUT4_128: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_128: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, AD0=>wptr_13, DO0=>func_and_inet_26); - LUT4_127: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_127: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_26, AD2=>wptr_14_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec26_p013); - LUT4_126: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_126: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, AD0=>rptr_14, DO0=>func_and_inet_27); - LUT4_125: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_125: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_27, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec27_r113); - LUT4_124: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_124: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13, DO0=>func_and_inet_28); - LUT4_123: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_123: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_28, AD2=>wptr_14_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec28_p014); - LUT4_122: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_122: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, DO0=>func_and_inet_29); - LUT4_121: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_121: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_29, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec29_r114); - LUT4_120: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_120: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13, DO0=>func_and_inet_30); - LUT4_119: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_119: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_30, AD2=>wptr_14_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec30_p015); - LUT4_118: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_118: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, DO0=>func_and_inet_31); - LUT4_117: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_117: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_31, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec31_r115); - LUT4_116: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_116: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, AD0=>wptr_13_inv, DO0=>func_and_inet_32); - LUT4_115: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_115: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_32, AD2=>wptr_14, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec32_p016); - LUT4_114: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_114: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, AD0=>rptr_14_inv, DO0=>func_and_inet_33); - LUT4_113: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_113: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_33, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec33_r116); - LUT4_112: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_112: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, AD0=>wptr_13_inv, DO0=>func_and_inet_34); - LUT4_111: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_111: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_34, AD2=>wptr_14, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec34_p017); - LUT4_110: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_110: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, AD0=>rptr_14_inv, DO0=>func_and_inet_35); - LUT4_109: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_109: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_35, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec35_r117); - LUT4_108: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_108: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, AD0=>wptr_13_inv, DO0=>func_and_inet_36); - LUT4_107: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_107: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_36, AD2=>wptr_14, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec36_p018); - LUT4_106: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_106: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, AD0=>rptr_14_inv, DO0=>func_and_inet_37); - LUT4_105: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_105: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_37, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec37_r118); - LUT4_104: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_104: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, AD0=>wptr_13_inv, DO0=>func_and_inet_38); - LUT4_103: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_103: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_38, AD2=>wptr_14, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec38_p019); - LUT4_102: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_102: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, AD0=>rptr_14_inv, DO0=>func_and_inet_39); - LUT4_101: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_101: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_39, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec39_r119); - LUT4_100: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_100: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, AD0=>wptr_13_inv, DO0=>func_and_inet_40); - LUT4_99: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_99: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_40, AD2=>wptr_14, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec40_p020); - LUT4_98: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_98: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, AD0=>rptr_14_inv, DO0=>func_and_inet_41); - LUT4_97: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_97: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_41, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec41_r120); - LUT4_96: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_96: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, AD0=>wptr_13_inv, DO0=>func_and_inet_42); - LUT4_95: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_95: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_42, AD2=>wptr_14, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec42_p021); - LUT4_94: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_94: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, AD0=>rptr_14_inv, DO0=>func_and_inet_43); - LUT4_93: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_93: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_43, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec43_r121); - LUT4_92: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_92: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13_inv, DO0=>func_and_inet_44); - LUT4_91: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_91: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_44, AD2=>wptr_14, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec44_p022); - LUT4_90: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_90: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14_inv, DO0=>func_and_inet_45); - LUT4_89: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_89: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_45, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec45_r122); - LUT4_88: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_88: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13_inv, DO0=>func_and_inet_46); - LUT4_87: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_87: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_46, AD2=>wptr_14, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec46_p023); - LUT4_86: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_86: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14_inv, DO0=>func_and_inet_47); - LUT4_85: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_85: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_47, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec47_r123); - LUT4_84: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_84: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, AD0=>wptr_13, DO0=>func_and_inet_48); - LUT4_83: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_83: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_48, AD2=>wptr_14, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec48_p024); - LUT4_82: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_82: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, AD0=>rptr_14, DO0=>func_and_inet_49); - LUT4_81: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_81: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_49, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec49_r124); - LUT4_80: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_80: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, AD0=>wptr_13, DO0=>func_and_inet_50); - LUT4_79: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_79: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_50, AD2=>wptr_14, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec50_p025); - LUT4_78: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_78: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, AD0=>rptr_14, DO0=>func_and_inet_51); - LUT4_77: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_77: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_51, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec51_r125); - LUT4_76: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_76: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, AD0=>wptr_13, DO0=>func_and_inet_52); - LUT4_75: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_75: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_52, AD2=>wptr_14, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec52_p026); - LUT4_74: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_74: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, AD0=>rptr_14, DO0=>func_and_inet_53); - LUT4_73: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_73: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_53, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec53_r126); - LUT4_72: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_72: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, AD0=>wptr_13, DO0=>func_and_inet_54); - LUT4_71: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_71: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_54, AD2=>wptr_14, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec54_p027); - LUT4_70: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_70: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, AD0=>rptr_14, DO0=>func_and_inet_55); - LUT4_69: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_69: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_55, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec55_r127); - LUT4_68: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_68: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, AD0=>wptr_13, DO0=>func_and_inet_56); - LUT4_67: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_67: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_56, AD2=>wptr_14, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec56_p028); - LUT4_66: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_66: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, AD0=>rptr_14, DO0=>func_and_inet_57); - LUT4_65: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_65: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_57, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec57_r128); - LUT4_64: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_64: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, AD0=>wptr_13, DO0=>func_and_inet_58); - LUT4_63: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_63: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_58, AD2=>wptr_14, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec58_p029); - LUT4_62: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_62: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, AD0=>rptr_14, DO0=>func_and_inet_59); - LUT4_61: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_61: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_59, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec59_r129); - LUT4_60: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_60: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13, DO0=>func_and_inet_60); - LUT4_59: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_59: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_60, AD2=>wptr_14, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec60_p030); - LUT4_58: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_58: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, DO0=>func_and_inet_61); - LUT4_57: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_57: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_61, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec61_r130); - LUT4_56: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_56: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13, DO0=>func_and_inet_62); - LUT4_55: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_55: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_62, AD2=>wptr_14, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec62_p031); - LUT4_54: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_54: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, DO0=>func_and_inet_63); - LUT4_53: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_53: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_63, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec63_r131); - LUT4_52: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_52: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, AD1=>w_gcount_r214, AD0=>w_gcount_r215, DO0=>w_g2b_xor_cluster_0); - LUT4_51: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_51: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>w_gcount_r210, AD0=>w_gcount_r211, DO0=>w_g2b_xor_cluster_1); - LUT4_50: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_50: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>w_g2b_xor_cluster_2); - LUT4_49: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_49: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>w_g2b_xor_cluster_3); - LUT4_48: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_48: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r14); - LUT4_47: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_47: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13); - LUT4_46: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_46: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); - LUT4_45: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_45: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10); - LUT4_44: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_44: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9); - LUT4_43: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_43: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8); - LUT4_42: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_42: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7); - LUT4_41: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_41: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6); - LUT4_40: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_40: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_2_1); - LUT4_39: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_39: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5); - LUT4_38: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_38: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4); - LUT4_37: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_37: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3); - LUT4_36: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_36: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); - LUT4_35: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_35: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, DO0=>wcount_r2); - LUT4_34: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_34: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_2); - LUT4_33: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_33: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, DO0=>wcount_r1); - LUT4_32: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_32: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, DO0=>wcount_r0); - LUT4_31: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_31: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, AD1=>r_gcount_w215, AD0=>r_gcount_w216, DO0=>r_g2b_xor_cluster_0); - LUT4_30: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_30: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, AD1=>r_gcount_w211, AD0=>r_gcount_w212, DO0=>r_g2b_xor_cluster_1); - LUT4_29: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_29: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>r_g2b_xor_cluster_2); - LUT4_28: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_28: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>r_g2b_xor_cluster_3); - LUT4_27: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_27: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w15); - LUT4_26: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_26: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); - LUT4_25: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_25: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); - LUT4_24: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_24: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); - LUT4_23: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_23: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w10); - LUT4_22: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_22: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); - LUT4_21: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_21: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); - LUT4_20: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_20: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); - LUT4_19: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_19: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_2_1); - LUT4_18: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_18: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); - LUT4_17: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_17: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); - LUT4_16: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_16: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); - LUT4_15: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_15: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); - LUT4_14: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_14: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, DO0=>rcount_w3); - LUT4_13: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_13: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_2); - LUT4_12: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_12: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, DO0=>rcount_w2); - LUT4_11: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_11: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, DO0=>rcount_w1); - LUT4_10: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_10: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet); - LUT4_9: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_9: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_1); - LUT4_8: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_8: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_2); - LUT4_7: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_7: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_3); - LUT4_6: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_6: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>func_xor_inet_4); - LUT4_5: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_5: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, DO0=>func_xor_inet_5); - LUT4_4: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_4: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); @@ -3344,31 +2495,23 @@ begin XOR2_t2: XOR2 port map (A=>w_gcount_r215, B=>rptr_16, Z=>rfill_sub_msb); - LUT4_3: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0410") - -- synopsys translate_on + LUT4_3: ROM16X1A + generic map (initval=> X"0410") port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>empty_cmp_set); - LUT4_2: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x1004") - -- synopsys translate_on + LUT4_2: ROM16X1A + generic map (initval=> X"1004") port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>empty_cmp_clr); - LUT4_1: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0140") - -- synopsys translate_on + LUT4_1: ROM16X1A + generic map (initval=> X"0140") port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>full_cmp_set); - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4001") - -- synopsys translate_on + LUT4_0: ROM16X1A + generic map (initval=> X"4001") port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>full_cmp_clr); @@ -3381,13 +2524,11 @@ begin AND2_t0: AND2 port map (A=>rcnt_reg_16, B=>rcnt_reg_15, Z=>ae_setsig); - pdp_ram_0_0_31: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + pdp_ram_0_0_31: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -3397,37 +2538,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec0_p00, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec1_r10, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, - DOB1=>mdout1_0_1, DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, - DOB4=>mdout1_0_4, DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, - DOB7=>mdout1_0_7, DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_1_0_30: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec0_p00, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec1_r10, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, + DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, + DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, + DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_0_30: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -3437,37 +2577,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec2_p01, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec3_r11, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, - DOB1=>mdout1_1_1, DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, - DOB4=>mdout1_1_4, DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, - DOB7=>mdout1_1_7, DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_2_0_29: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec2_p01, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec3_r11, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, + DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, + DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, + DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_0_29: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -3477,37 +2616,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec4_p02, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec5_r12, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, - DOB1=>mdout1_2_1, DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, - DOB4=>mdout1_2_4, DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, - DOB7=>mdout1_2_7, DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_3_0_28: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec4_p02, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec5_r12, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1, + DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4, + DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7, + DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_0_28: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -3517,37 +2655,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec6_p03, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec7_r13, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, - DOB1=>mdout1_3_1, DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, - DOB4=>mdout1_3_4, DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, - DOB7=>mdout1_3_7, DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_4_0_27: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec6_p03, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec7_r13, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1, + DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4, + DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7, + DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_4_0_27: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -3557,37 +2694,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec8_p04, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec9_r14, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_4_0, - DOB1=>mdout1_4_1, DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, - DOB4=>mdout1_4_4, DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, - DOB7=>mdout1_4_7, DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_5_0_26: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec8_p04, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec9_r14, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_4_0, DOB1=>mdout1_4_1, + DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, DOB4=>mdout1_4_4, + DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, DOB7=>mdout1_4_7, + DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_5_0_26: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -3597,37 +2733,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec10_p05, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec11_r15, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_5_0, - DOB1=>mdout1_5_1, DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, - DOB4=>mdout1_5_4, DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, - DOB7=>mdout1_5_7, DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_6_0_25: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec10_p05, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec11_r15, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_5_0, DOB1=>mdout1_5_1, + DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, DOB4=>mdout1_5_4, + DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, DOB7=>mdout1_5_7, + DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_6_0_25: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -3637,37 +2772,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec12_p06, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec13_r16, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_6_0, - DOB1=>mdout1_6_1, DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, - DOB4=>mdout1_6_4, DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, - DOB7=>mdout1_6_7, DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_7_0_24: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec12_p06, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec13_r16, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_6_0, DOB1=>mdout1_6_1, + DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, DOB4=>mdout1_6_4, + DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, DOB7=>mdout1_6_7, + DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_7_0_24: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -3677,37 +2811,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec14_p07, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec15_r17, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_7_0, - DOB1=>mdout1_7_1, DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, - DOB4=>mdout1_7_4, DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, - DOB7=>mdout1_7_7, DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_8_0_23: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec14_p07, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec15_r17, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_7_0, DOB1=>mdout1_7_1, + DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, DOB4=>mdout1_7_4, + DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, DOB7=>mdout1_7_7, + DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_8_0_23: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -3717,37 +2850,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec16_p08, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec17_r18, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_8_0, - DOB1=>mdout1_8_1, DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, - DOB4=>mdout1_8_4, DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, - DOB7=>mdout1_8_7, DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_9_0_22: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec16_p08, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec17_r18, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_8_0, DOB1=>mdout1_8_1, + DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, DOB4=>mdout1_8_4, + DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, DOB7=>mdout1_8_7, + DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_9_0_22: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -3757,37 +2889,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec18_p09, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec19_r19, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_9_0, - DOB1=>mdout1_9_1, DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, - DOB4=>mdout1_9_4, DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, - DOB7=>mdout1_9_7, DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_10_0_21: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec18_p09, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec19_r19, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_9_0, DOB1=>mdout1_9_1, + DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, DOB4=>mdout1_9_4, + DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, DOB7=>mdout1_9_7, + DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_10_0_21: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -3797,37 +2928,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec20_p010, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec21_r110, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_10_0, - DOB1=>mdout1_10_1, DOB2=>mdout1_10_2, DOB3=>mdout1_10_3, - DOB4=>mdout1_10_4, DOB5=>mdout1_10_5, DOB6=>mdout1_10_6, - DOB7=>mdout1_10_7, DOB8=>mdout1_10_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_11_0_20: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec20_p010, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec21_r110, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_10_0, DOB1=>mdout1_10_1, + DOB2=>mdout1_10_2, DOB3=>mdout1_10_3, DOB4=>mdout1_10_4, + DOB5=>mdout1_10_5, DOB6=>mdout1_10_6, DOB7=>mdout1_10_7, + DOB8=>mdout1_10_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_11_0_20: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -3837,37 +2967,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec22_p011, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec23_r111, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_11_0, - DOB1=>mdout1_11_1, DOB2=>mdout1_11_2, DOB3=>mdout1_11_3, - DOB4=>mdout1_11_4, DOB5=>mdout1_11_5, DOB6=>mdout1_11_6, - DOB7=>mdout1_11_7, DOB8=>mdout1_11_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_12_0_19: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec22_p011, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec23_r111, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_11_0, DOB1=>mdout1_11_1, + DOB2=>mdout1_11_2, DOB3=>mdout1_11_3, DOB4=>mdout1_11_4, + DOB5=>mdout1_11_5, DOB6=>mdout1_11_6, DOB7=>mdout1_11_7, + DOB8=>mdout1_11_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_12_0_19: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -3877,37 +3006,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec24_p012, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec25_r112, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_12_0, - DOB1=>mdout1_12_1, DOB2=>mdout1_12_2, DOB3=>mdout1_12_3, - DOB4=>mdout1_12_4, DOB5=>mdout1_12_5, DOB6=>mdout1_12_6, - DOB7=>mdout1_12_7, DOB8=>mdout1_12_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_13_0_18: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec24_p012, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec25_r112, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_12_0, DOB1=>mdout1_12_1, + DOB2=>mdout1_12_2, DOB3=>mdout1_12_3, DOB4=>mdout1_12_4, + DOB5=>mdout1_12_5, DOB6=>mdout1_12_6, DOB7=>mdout1_12_7, + DOB8=>mdout1_12_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_13_0_18: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -3917,37 +3045,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec26_p013, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec27_r113, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_13_0, - DOB1=>mdout1_13_1, DOB2=>mdout1_13_2, DOB3=>mdout1_13_3, - DOB4=>mdout1_13_4, DOB5=>mdout1_13_5, DOB6=>mdout1_13_6, - DOB7=>mdout1_13_7, DOB8=>mdout1_13_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_14_0_17: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec26_p013, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec27_r113, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_13_0, DOB1=>mdout1_13_1, + DOB2=>mdout1_13_2, DOB3=>mdout1_13_3, DOB4=>mdout1_13_4, + DOB5=>mdout1_13_5, DOB6=>mdout1_13_6, DOB7=>mdout1_13_7, + DOB8=>mdout1_13_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_14_0_17: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -3957,37 +3084,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec28_p014, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec29_r114, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_14_0, - DOB1=>mdout1_14_1, DOB2=>mdout1_14_2, DOB3=>mdout1_14_3, - DOB4=>mdout1_14_4, DOB5=>mdout1_14_5, DOB6=>mdout1_14_6, - DOB7=>mdout1_14_7, DOB8=>mdout1_14_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_15_0_16: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec28_p014, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec29_r114, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_14_0, DOB1=>mdout1_14_1, + DOB2=>mdout1_14_2, DOB3=>mdout1_14_3, DOB4=>mdout1_14_4, + DOB5=>mdout1_14_5, DOB6=>mdout1_14_6, DOB7=>mdout1_14_7, + DOB8=>mdout1_14_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_15_0_16: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -3997,37 +3123,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec30_p015, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec31_r115, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_15_0, - DOB1=>mdout1_15_1, DOB2=>mdout1_15_2, DOB3=>mdout1_15_3, - DOB4=>mdout1_15_4, DOB5=>mdout1_15_5, DOB6=>mdout1_15_6, - DOB7=>mdout1_15_7, DOB8=>mdout1_15_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_16_0_15: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec30_p015, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec31_r115, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_15_0, DOB1=>mdout1_15_1, + DOB2=>mdout1_15_2, DOB3=>mdout1_15_3, DOB4=>mdout1_15_4, + DOB5=>mdout1_15_5, DOB6=>mdout1_15_6, DOB7=>mdout1_15_7, + DOB8=>mdout1_15_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_16_0_15: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -4037,37 +3162,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec32_p016, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec33_r116, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_16_0, - DOB1=>mdout1_16_1, DOB2=>mdout1_16_2, DOB3=>mdout1_16_3, - DOB4=>mdout1_16_4, DOB5=>mdout1_16_5, DOB6=>mdout1_16_6, - DOB7=>mdout1_16_7, DOB8=>mdout1_16_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_17_0_14: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec32_p016, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec33_r116, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_16_0, DOB1=>mdout1_16_1, + DOB2=>mdout1_16_2, DOB3=>mdout1_16_3, DOB4=>mdout1_16_4, + DOB5=>mdout1_16_5, DOB6=>mdout1_16_6, DOB7=>mdout1_16_7, + DOB8=>mdout1_16_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_17_0_14: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -4077,37 +3201,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec34_p017, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec35_r117, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_17_0, - DOB1=>mdout1_17_1, DOB2=>mdout1_17_2, DOB3=>mdout1_17_3, - DOB4=>mdout1_17_4, DOB5=>mdout1_17_5, DOB6=>mdout1_17_6, - DOB7=>mdout1_17_7, DOB8=>mdout1_17_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_18_0_13: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec34_p017, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec35_r117, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_17_0, DOB1=>mdout1_17_1, + DOB2=>mdout1_17_2, DOB3=>mdout1_17_3, DOB4=>mdout1_17_4, + DOB5=>mdout1_17_5, DOB6=>mdout1_17_6, DOB7=>mdout1_17_7, + DOB8=>mdout1_17_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_18_0_13: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -4117,37 +3240,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec36_p018, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec37_r118, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_18_0, - DOB1=>mdout1_18_1, DOB2=>mdout1_18_2, DOB3=>mdout1_18_3, - DOB4=>mdout1_18_4, DOB5=>mdout1_18_5, DOB6=>mdout1_18_6, - DOB7=>mdout1_18_7, DOB8=>mdout1_18_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_19_0_12: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec36_p018, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec37_r118, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_18_0, DOB1=>mdout1_18_1, + DOB2=>mdout1_18_2, DOB3=>mdout1_18_3, DOB4=>mdout1_18_4, + DOB5=>mdout1_18_5, DOB6=>mdout1_18_6, DOB7=>mdout1_18_7, + DOB8=>mdout1_18_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_19_0_12: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -4157,37 +3279,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec38_p019, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec39_r119, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_19_0, - DOB1=>mdout1_19_1, DOB2=>mdout1_19_2, DOB3=>mdout1_19_3, - DOB4=>mdout1_19_4, DOB5=>mdout1_19_5, DOB6=>mdout1_19_6, - DOB7=>mdout1_19_7, DOB8=>mdout1_19_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_20_0_11: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec38_p019, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec39_r119, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_19_0, DOB1=>mdout1_19_1, + DOB2=>mdout1_19_2, DOB3=>mdout1_19_3, DOB4=>mdout1_19_4, + DOB5=>mdout1_19_5, DOB6=>mdout1_19_6, DOB7=>mdout1_19_7, + DOB8=>mdout1_19_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_20_0_11: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -4197,37 +3318,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec40_p020, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec41_r120, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_20_0, - DOB1=>mdout1_20_1, DOB2=>mdout1_20_2, DOB3=>mdout1_20_3, - DOB4=>mdout1_20_4, DOB5=>mdout1_20_5, DOB6=>mdout1_20_6, - DOB7=>mdout1_20_7, DOB8=>mdout1_20_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_21_0_10: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec40_p020, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec41_r120, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_20_0, DOB1=>mdout1_20_1, + DOB2=>mdout1_20_2, DOB3=>mdout1_20_3, DOB4=>mdout1_20_4, + DOB5=>mdout1_20_5, DOB6=>mdout1_20_6, DOB7=>mdout1_20_7, + DOB8=>mdout1_20_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_21_0_10: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -4237,37 +3357,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec42_p021, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec43_r121, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_21_0, - DOB1=>mdout1_21_1, DOB2=>mdout1_21_2, DOB3=>mdout1_21_3, - DOB4=>mdout1_21_4, DOB5=>mdout1_21_5, DOB6=>mdout1_21_6, - DOB7=>mdout1_21_7, DOB8=>mdout1_21_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_22_0_9: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec42_p021, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec43_r121, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_21_0, DOB1=>mdout1_21_1, + DOB2=>mdout1_21_2, DOB3=>mdout1_21_3, DOB4=>mdout1_21_4, + DOB5=>mdout1_21_5, DOB6=>mdout1_21_6, DOB7=>mdout1_21_7, + DOB8=>mdout1_21_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_22_0_9: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -4277,37 +3396,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec44_p022, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec45_r122, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_22_0, - DOB1=>mdout1_22_1, DOB2=>mdout1_22_2, DOB3=>mdout1_22_3, - DOB4=>mdout1_22_4, DOB5=>mdout1_22_5, DOB6=>mdout1_22_6, - DOB7=>mdout1_22_7, DOB8=>mdout1_22_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_23_0_8: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec44_p022, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec45_r122, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_22_0, DOB1=>mdout1_22_1, + DOB2=>mdout1_22_2, DOB3=>mdout1_22_3, DOB4=>mdout1_22_4, + DOB5=>mdout1_22_5, DOB6=>mdout1_22_6, DOB7=>mdout1_22_7, + DOB8=>mdout1_22_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_23_0_8: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -4317,37 +3435,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec46_p023, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec47_r123, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_23_0, - DOB1=>mdout1_23_1, DOB2=>mdout1_23_2, DOB3=>mdout1_23_3, - DOB4=>mdout1_23_4, DOB5=>mdout1_23_5, DOB6=>mdout1_23_6, - DOB7=>mdout1_23_7, DOB8=>mdout1_23_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_24_0_7: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec46_p023, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec47_r123, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_23_0, DOB1=>mdout1_23_1, + DOB2=>mdout1_23_2, DOB3=>mdout1_23_3, DOB4=>mdout1_23_4, + DOB5=>mdout1_23_5, DOB6=>mdout1_23_6, DOB7=>mdout1_23_7, + DOB8=>mdout1_23_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_24_0_7: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -4357,37 +3474,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec48_p024, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec49_r124, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_24_0, - DOB1=>mdout1_24_1, DOB2=>mdout1_24_2, DOB3=>mdout1_24_3, - DOB4=>mdout1_24_4, DOB5=>mdout1_24_5, DOB6=>mdout1_24_6, - DOB7=>mdout1_24_7, DOB8=>mdout1_24_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_25_0_6: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec48_p024, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec49_r124, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_24_0, DOB1=>mdout1_24_1, + DOB2=>mdout1_24_2, DOB3=>mdout1_24_3, DOB4=>mdout1_24_4, + DOB5=>mdout1_24_5, DOB6=>mdout1_24_6, DOB7=>mdout1_24_7, + DOB8=>mdout1_24_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_25_0_6: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -4397,37 +3513,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec50_p025, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec51_r125, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_25_0, - DOB1=>mdout1_25_1, DOB2=>mdout1_25_2, DOB3=>mdout1_25_3, - DOB4=>mdout1_25_4, DOB5=>mdout1_25_5, DOB6=>mdout1_25_6, - DOB7=>mdout1_25_7, DOB8=>mdout1_25_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_26_0_5: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec50_p025, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec51_r125, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_25_0, DOB1=>mdout1_25_1, + DOB2=>mdout1_25_2, DOB3=>mdout1_25_3, DOB4=>mdout1_25_4, + DOB5=>mdout1_25_5, DOB6=>mdout1_25_6, DOB7=>mdout1_25_7, + DOB8=>mdout1_25_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_26_0_5: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -4437,37 +3552,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec52_p026, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec53_r126, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_26_0, - DOB1=>mdout1_26_1, DOB2=>mdout1_26_2, DOB3=>mdout1_26_3, - DOB4=>mdout1_26_4, DOB5=>mdout1_26_5, DOB6=>mdout1_26_6, - DOB7=>mdout1_26_7, DOB8=>mdout1_26_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_27_0_4: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec52_p026, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec53_r126, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_26_0, DOB1=>mdout1_26_1, + DOB2=>mdout1_26_2, DOB3=>mdout1_26_3, DOB4=>mdout1_26_4, + DOB5=>mdout1_26_5, DOB6=>mdout1_26_6, DOB7=>mdout1_26_7, + DOB8=>mdout1_26_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_27_0_4: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -4477,37 +3591,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec54_p027, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec55_r127, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_27_0, - DOB1=>mdout1_27_1, DOB2=>mdout1_27_2, DOB3=>mdout1_27_3, - DOB4=>mdout1_27_4, DOB5=>mdout1_27_5, DOB6=>mdout1_27_6, - DOB7=>mdout1_27_7, DOB8=>mdout1_27_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_28_0_3: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec54_p027, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec55_r127, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_27_0, DOB1=>mdout1_27_1, + DOB2=>mdout1_27_2, DOB3=>mdout1_27_3, DOB4=>mdout1_27_4, + DOB5=>mdout1_27_5, DOB6=>mdout1_27_6, DOB7=>mdout1_27_7, + DOB8=>mdout1_27_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_28_0_3: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -4517,37 +3630,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec56_p028, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec57_r128, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_28_0, - DOB1=>mdout1_28_1, DOB2=>mdout1_28_2, DOB3=>mdout1_28_3, - DOB4=>mdout1_28_4, DOB5=>mdout1_28_5, DOB6=>mdout1_28_6, - DOB7=>mdout1_28_7, DOB8=>mdout1_28_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_29_0_2: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec56_p028, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec57_r128, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_28_0, DOB1=>mdout1_28_1, + DOB2=>mdout1_28_2, DOB3=>mdout1_28_3, DOB4=>mdout1_28_4, + DOB5=>mdout1_28_5, DOB6=>mdout1_28_6, DOB7=>mdout1_28_7, + DOB8=>mdout1_28_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_29_0_2: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -4557,37 +3669,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec58_p029, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec59_r129, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_29_0, - DOB1=>mdout1_29_1, DOB2=>mdout1_29_2, DOB3=>mdout1_29_3, - DOB4=>mdout1_29_4, DOB5=>mdout1_29_5, DOB6=>mdout1_29_6, - DOB7=>mdout1_29_7, DOB8=>mdout1_29_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_30_0_1: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec58_p029, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec59_r129, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_29_0, DOB1=>mdout1_29_1, + DOB2=>mdout1_29_2, DOB3=>mdout1_29_3, DOB4=>mdout1_29_4, + DOB5=>mdout1_29_5, DOB6=>mdout1_29_6, DOB7=>mdout1_29_7, + DOB8=>mdout1_29_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_30_0_1: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -4597,37 +3708,36 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec60_p030, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec61_r130, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_30_0, - DOB1=>mdout1_30_1, DOB2=>mdout1_30_2, DOB3=>mdout1_30_3, - DOB4=>mdout1_30_4, DOB5=>mdout1_30_5, DOB6=>mdout1_30_6, - DOB7=>mdout1_30_7, DOB8=>mdout1_30_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_31_0_0: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec60_p030, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec61_r130, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_30_0, DOB1=>mdout1_30_1, + DOB2=>mdout1_30_2, DOB3=>mdout1_30_3, DOB4=>mdout1_30_4, + DOB5=>mdout1_30_5, DOB6=>mdout1_30_6, DOB7=>mdout1_30_7, + DOB8=>mdout1_30_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_31_0_0: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 18) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), @@ -4637,1601 +3747,882 @@ begin ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, - CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>dec62_p031, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec63_r131, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_31_0, - DOB1=>mdout1_31_1, DOB2=>mdout1_31_2, DOB3=>mdout1_31_3, - DOB4=>mdout1_31_4, DOB5=>mdout1_31_5, DOB6=>mdout1_31_6, - DOB7=>mdout1_31_7, DOB8=>mdout1_31_8, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec62_p031, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec63_r131, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_31_0, DOB1=>mdout1_31_1, + DOB2=>mdout1_31_2, DOB3=>mdout1_31_3, DOB4=>mdout1_31_4, + DOB5=>mdout1_31_5, DOB6=>mdout1_31_6, DOB7=>mdout1_31_7, + DOB8=>mdout1_31_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); FF_239: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, Q=>wcount_0); FF_238: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_1); FF_237: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_2); FF_236: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_3); FF_235: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_4); FF_234: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_5); FF_233: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_6); FF_232: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_7); FF_231: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_8); FF_230: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_9); FF_229: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_10); FF_228: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_11); FF_227: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_12); FF_226: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_13); FF_225: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_14); FF_224: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_15); FF_223: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_0); FF_222: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_1); FF_221: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_2); FF_220: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_3); FF_219: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_4); FF_218: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_5); FF_217: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_6); FF_216: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_7); FF_215: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_8); FF_214: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_9); FF_213: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_10); FF_212: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_11); FF_211: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_12); FF_210: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_13); FF_209: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_14); FF_208: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_15); FF_207: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_0); FF_206: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_1); FF_205: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_2); FF_204: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_3); FF_203: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_4); FF_202: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_5); FF_201: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_6); FF_200: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_7); FF_199: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_8); FF_198: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_9); FF_197: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_10); FF_196: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_11); FF_195: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_12); FF_194: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_13); FF_193: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_14); FF_192: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_15); FF_191: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, Q=>rcount_0); FF_190: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_1); FF_189: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_2); FF_188: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_3); FF_187: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_4); FF_186: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_5); FF_185: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_6); FF_184: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_7); FF_183: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_8); FF_182: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_9); FF_181: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_10); FF_180: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_11); FF_179: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_12); FF_178: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_13); FF_177: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_14); FF_176: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_15); FF_175: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_16); FF_174: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_0); FF_173: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_1); FF_172: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_2); FF_171: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_3); FF_170: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_4); FF_169: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_5); FF_168: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_6); FF_167: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_7); FF_166: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_8); FF_165: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_9); FF_164: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_10); FF_163: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_11); FF_162: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_12); FF_161: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_13); FF_160: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_14); FF_159: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_15); FF_158: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_16); FF_157: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_0); FF_156: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_1); FF_155: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_2); FF_154: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_3); FF_153: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_4); FF_152: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_5); FF_151: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_6); FF_150: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_7); FF_149: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_8); FF_148: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_9); FF_147: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_10); FF_146: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_11); FF_145: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_12); FF_144: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_13); FF_143: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_14); FF_142: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_15); FF_141: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_16); FF_140: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, Q=>rptr_11_ff); FF_139: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, Q=>rptr_12_ff); FF_138: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, Q=>rptr_13_ff); FF_137: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, Q=>rptr_14_ff); FF_136: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, Q=>rptr_15_ff); FF_135: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); FF_134: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); FF_133: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); FF_132: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); FF_131: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); FF_130: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); FF_129: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); FF_128: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); FF_127: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); FF_126: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); FF_125: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, Q=>w_gcount_r10); FF_124: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, Q=>w_gcount_r11); FF_123: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, Q=>w_gcount_r12); FF_122: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, Q=>w_gcount_r13); FF_121: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, Q=>w_gcount_r14); FF_120: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, Q=>w_gcount_r15); FF_119: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); FF_118: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); FF_117: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); FF_116: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); FF_115: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); FF_114: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); FF_113: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); FF_112: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); FF_111: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); FF_110: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); FF_109: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); FF_108: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); FF_107: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); FF_106: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); FF_105: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); FF_104: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); FF_103: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); FF_102: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r20); FF_101: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r21); FF_100: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r22); FF_99: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r23); FF_98: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r24); FF_97: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r25); FF_96: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r26); FF_95: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r27); FF_94: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r28); FF_93: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r29); FF_92: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, Q=>w_gcount_r210); FF_91: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, Q=>w_gcount_r211); FF_90: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, Q=>w_gcount_r212); FF_89: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, Q=>w_gcount_r213); FF_88: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, Q=>w_gcount_r214); FF_87: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, Q=>w_gcount_r215); FF_86: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); FF_85: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); FF_84: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); FF_83: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); FF_82: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); FF_81: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); FF_80: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); FF_79: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); FF_78: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); FF_77: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); FF_76: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w210); FF_75: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w211); FF_74: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w212); FF_73: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w213); FF_72: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w214); FF_71: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w215); FF_70: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w216); FF_69: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_0, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_0); FF_68: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_1, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_1); FF_67: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_2, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_2); FF_66: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_3, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_3); FF_65: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_4, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_4); FF_64: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_5, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_5); FF_63: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_6, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_6); FF_62: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_7, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_7); FF_61: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_8, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_8); FF_60: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_9, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_9); FF_59: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_10, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_10); FF_58: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_11, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_11); FF_57: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_12, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_12); FF_56: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_13, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_13); FF_55: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_14, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_14); FF_54: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcnt_sub_15, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_15); FF_53: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0); FF_52: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1); FF_51: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2); FF_50: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3); FF_49: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4); FF_48: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5); FF_47: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_6, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_6); FF_46: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_7, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_7); FF_45: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_8, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_8); FF_44: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_9, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_9); FF_43: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_10, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_10); FF_42: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_11, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_11); FF_41: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_12, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_12); FF_40: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_13, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_13); FF_39: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_14, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_14); FF_38: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_15, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_15); FF_37: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcnt_sub_16, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_16); FF_36: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0)); FF_35: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1)); FF_34: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2)); FF_33: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3)); FF_32: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4)); FF_31: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5)); FF_30: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6)); FF_29: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7)); FF_28: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8)); FF_27: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9)); FF_26: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10)); FF_25: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11)); FF_24: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_12, CK=>WrClock, CD=>Reset, Q=>WCNT(12)); FF_23: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_13, CK=>WrClock, CD=>Reset, Q=>WCNT(13)); FF_22: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_14, CK=>WrClock, CD=>Reset, Q=>WCNT(14)); FF_21: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wfill_sub_15, CK=>WrClock, CD=>Reset, Q=>WCNT(15)); FF_20: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0)); FF_19: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1)); FF_18: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2)); FF_17: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3)); FF_16: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4)); FF_15: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5)); FF_14: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6)); FF_13: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7)); FF_12: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8)); FF_11: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9)); FF_10: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_10, CK=>RdClock, CD=>rRst, Q=>RCNT(10)); FF_9: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_11, CK=>RdClock, CD=>rRst, Q=>RCNT(11)); FF_8: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_12, CK=>RdClock, CD=>rRst, Q=>RCNT(12)); FF_7: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_13, CK=>RdClock, CD=>rRst, Q=>RCNT(13)); FF_6: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_14, CK=>RdClock, CD=>rRst, Q=>RCNT(14)); FF_5: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_15, CK=>RdClock, CD=>rRst, Q=>RCNT(15)); FF_4: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rfill_sub_16, CK=>RdClock, CD=>rRst, Q=>RCNT(16)); FF_3: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); FF_2: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); FF_1: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty); FF_0: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>AlmostFull); w_gctr_cia: FADD2B @@ -6807,26 +5198,26 @@ begin end Structure; -- synopsys translate_off -library ecp2m; +library ecp3; configuration Structure_CON of fifo_32kx16x8_mb2 is for Structure - for all:AGEB2 use entity ecp2m.AGEB2(V); end for; - for all:AND2 use entity ecp2m.AND2(V); end for; - for all:CU2 use entity ecp2m.CU2(V); end for; - for all:FADD2B use entity ecp2m.FADD2B(V); end for; - for all:FSUB2B use entity ecp2m.FSUB2B(V); end for; - for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; - for all:INV use entity ecp2m.INV(V); end for; - for all:MUX321 use entity ecp2m.MUX321(V); end for; - for all:OR2 use entity ecp2m.OR2(V); end for; - for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:XOR2 use entity ecp2m.XOR2(V); end for; - for all:DP16KB use entity ecp2m.DP16KB(V); end for; + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FSUB2B use entity ecp3.FSUB2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:MUX321 use entity ecp3.MUX321(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; end for; end Structure_CON; diff --git a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2_generate.log b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2_generate.log index 9e466d3..eceede3 100644 --- a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2_generate.log +++ b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2_generate.log @@ -1,17 +1,19 @@ +Starting process: module + Starting process: -SCUBA, Version ispLever_v8.0_PROD_Build (41) -Fri Jul 23 21:15:52 2010 +SCUBA, Version Diamond_1.3_Production (92) +Thu Sep 22 11:22:54 2011 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved. +Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. BEGIN SCUBA Module Synthesis - Issued command : /opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n fifo_32kx16x8_mb2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 15 -data_width 18 -num_words 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill -e + Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_32kx16x8_mb2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 15 -data_width 18 -num_words 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -rfill -fill -e Circuit name : fifo_32kx16x8_mb2 Module type : ebfifo Module Version : 5.4 diff --git a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2_tmpl.vhd b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2_tmpl.vhd index 0ff3433..041890c 100644 --- a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2_tmpl.vhd +++ b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb2_tmpl.vhd @@ -1,6 +1,6 @@ --- VHDL module instantiation generated by SCUBA ispLever_v8.0_PROD_Build (41) +-- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) -- Module Version: 5.4 --- Fri Jul 23 21:15:52 2010 +-- Thu Sep 22 11:22:54 2011 -- parameterized module component declaration component fifo_32kx16x8_mb2 diff --git a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb_tmpl.vhd b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb_tmpl.vhd index bc2e00d..a84a110 100755 --- a/gbe_ecp2m/ipcores/fifo_32kx16x8_mb_tmpl.vhd +++ b/gbe_ecp2m/ipcores/fifo_32kx16x8_mb_tmpl.vhd @@ -1,6 +1,6 @@ --- VHDL module instantiation generated by SCUBA ispLever_v8.0_PROD_Build (41) --- Module Version: 5.3 --- Fri Feb 05 16:48:13 2010 +-- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.4 +-- Thu Sep 22 11:22:35 2011 -- parameterized module component declaration component fifo_32kx16x8_mb diff --git a/gbe_ecp2m/ipcores/fifo_4096x32.lpc b/gbe_ecp2m/ipcores/fifo_4096x32.lpc index 3f5196b..39ae0d7 100755 --- a/gbe_ecp2m/ipcores/fifo_4096x32.lpc +++ b/gbe_ecp2m/ipcores/fifo_4096x32.lpc @@ -1,47 +1,47 @@ -[Device] -Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-5F900C -SpeedGrade=-5 -Package=FPBGA900 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.3 -ModuleName=fifo_4096x32 -SourceFormat=Schematic/VHDL -ParameterFileVersion=1.0 -Date=12/18/2009 -Time=03:02:30 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=4096 -Width=32 -RDepth=4096 -RWidth=32 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_4096x32 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/22/2011 +Time=11:24:15 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=4096 +Width=32 +RDepth=4096 +RWidth=32 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/gbe_ecp2m/ipcores/fifo_4096x32.vhd b/gbe_ecp2m/ipcores/fifo_4096x32.vhd index 51a2cd4..2f52ee4 100755 --- a/gbe_ecp2m/ipcores/fifo_4096x32.vhd +++ b/gbe_ecp2m/ipcores/fifo_4096x32.vhd @@ -1,2415 +1,1803 @@ --- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41) --- Module Version: 5.3 ---/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 4096 -width 32 -depth 4096 -rdata_width 32 -no_enable -pe -1 -pf -1 -e - --- Fri Dec 18 03:02:30 2009 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp2m; -use ecp2m.components.all; --- synopsys translate_on - -entity fifo_4096x32 is - port ( - Data: in std_logic_vector(31 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(31 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_4096x32; - -architecture Structure of fifo_4096x32 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal w_gdata_11: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal wptr_12: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal r_gdata_11: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_11: std_logic; - signal rptr_12: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal w_gcount_12: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal r_gcount_12: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal w_gcount_r212: std_logic; - signal w_gcount_r12: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal r_gcount_w212: std_logic; - signal r_gcount_w12: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co4: std_logic; - signal iwcount_12: std_logic; - signal co6: std_logic; - signal wcount_12: std_logic; - signal co5: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co4_1: std_logic; - signal ircount_12: std_logic; - signal co6_1: std_logic; - signal rcount_12: std_logic; - signal co5_1: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r8: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r10: std_logic; - signal wcount_r11: std_logic; - signal rcount_10: std_logic; - signal rcount_11: std_logic; - signal co5_2: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w6: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal rcount_w8: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w10: std_logic; - signal rcount_w11: std_logic; - signal wcount_10: std_logic; - signal wcount_11: std_logic; - signal co5_3: std_logic; - signal full_cmp_clr: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1 - -- synopsys translate_off - generic (initval : in String); - -- synopsys translate_on - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KB - -- synopsys translate_off - generic (GSR : in String; WRITEMODE_B : in String; - CSDECODE_B : in std_logic_vector(2 downto 0); - CSDECODE_A : in std_logic_vector(2 downto 0); - WRITEMODE_A : in String; RESETMODE : in String; - REGMODE_B : in String; REGMODE_A : in String; - DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); - -- synopsys translate_on - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; - CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; - CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute initval : string; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute CSDECODE_B : string; - attribute CSDECODE_A : string; - attribute WRITEMODE_B : string; - attribute WRITEMODE_A : string; - attribute RESETMODE : string; - attribute REGMODE_B : string; - attribute REGMODE_A : string; - attribute DATA_WIDTH_B : string; - attribute DATA_WIDTH_A : string; - attribute GSR : string; - attribute initval of LUT4_33 : label is "0x6996"; - attribute initval of LUT4_32 : label is "0x6996"; - attribute initval of LUT4_31 : label is "0x6996"; - attribute initval of LUT4_30 : label is "0x6996"; - attribute initval of LUT4_29 : label is "0x6996"; - attribute initval of LUT4_28 : label is "0x6996"; - attribute initval of LUT4_27 : label is "0x6996"; - attribute initval of LUT4_26 : label is "0x6996"; - attribute initval of LUT4_25 : label is "0x6996"; - attribute initval of LUT4_24 : label is "0x6996"; - attribute initval of LUT4_23 : label is "0x6996"; - attribute initval of LUT4_22 : label is "0x6996"; - attribute initval of LUT4_21 : label is "0x6996"; - attribute initval of LUT4_20 : label is "0x6996"; - attribute initval of LUT4_19 : label is "0x6996"; - attribute initval of LUT4_18 : label is "0x6996"; - attribute initval of LUT4_17 : label is "0x6996"; - attribute initval of LUT4_16 : label is "0x6996"; - attribute initval of LUT4_15 : label is "0x6996"; - attribute initval of LUT4_14 : label is "0x6996"; - attribute initval of LUT4_13 : label is "0x6996"; - attribute initval of LUT4_12 : label is "0x6996"; - attribute initval of LUT4_11 : label is "0x6996"; - attribute initval of LUT4_10 : label is "0x6996"; - attribute initval of LUT4_9 : label is "0x6996"; - attribute initval of LUT4_8 : label is "0x6996"; - attribute initval of LUT4_7 : label is "0x6996"; - attribute initval of LUT4_6 : label is "0x6996"; - attribute initval of LUT4_5 : label is "0x6996"; - attribute initval of LUT4_4 : label is "0x6996"; - attribute initval of LUT4_3 : label is "0x0410"; - attribute initval of LUT4_2 : label is "0x1004"; - attribute initval of LUT4_1 : label is "0x0140"; - attribute initval of LUT4_0 : label is "0x4001"; - attribute MEM_LPC_FILE of pdp_ram_0_0_7 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_7 : label is ""; - attribute CSDECODE_B of pdp_ram_0_0_7 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_0_7 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_0_7 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_0_7 : label is "NORMAL"; - attribute GSR of pdp_ram_0_0_7 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_0_7 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_0_7 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_0_7 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_0_7 : label is "4"; - attribute DATA_WIDTH_A of pdp_ram_0_0_7 : label is "4"; - attribute MEM_LPC_FILE of pdp_ram_0_1_6 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_1_6 : label is ""; - attribute CSDECODE_B of pdp_ram_0_1_6 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_1_6 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_1_6 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_1_6 : label is "NORMAL"; - attribute GSR of pdp_ram_0_1_6 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_1_6 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_1_6 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_1_6 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_1_6 : label is "4"; - attribute DATA_WIDTH_A of pdp_ram_0_1_6 : label is "4"; - attribute MEM_LPC_FILE of pdp_ram_0_2_5 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_2_5 : label is ""; - attribute CSDECODE_B of pdp_ram_0_2_5 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_2_5 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_2_5 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_2_5 : label is "NORMAL"; - attribute GSR of pdp_ram_0_2_5 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_2_5 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_2_5 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_2_5 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_2_5 : label is "4"; - attribute DATA_WIDTH_A of pdp_ram_0_2_5 : label is "4"; - attribute MEM_LPC_FILE of pdp_ram_0_3_4 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_3_4 : label is ""; - attribute CSDECODE_B of pdp_ram_0_3_4 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_3_4 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_3_4 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_3_4 : label is "NORMAL"; - attribute GSR of pdp_ram_0_3_4 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_3_4 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_3_4 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_3_4 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_3_4 : label is "4"; - attribute DATA_WIDTH_A of pdp_ram_0_3_4 : label is "4"; - attribute MEM_LPC_FILE of pdp_ram_0_4_3 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_4_3 : label is ""; - attribute CSDECODE_B of pdp_ram_0_4_3 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_4_3 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_4_3 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_4_3 : label is "NORMAL"; - attribute GSR of pdp_ram_0_4_3 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_4_3 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_4_3 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_4_3 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_4_3 : label is "4"; - attribute DATA_WIDTH_A of pdp_ram_0_4_3 : label is "4"; - attribute MEM_LPC_FILE of pdp_ram_0_5_2 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_5_2 : label is ""; - attribute CSDECODE_B of pdp_ram_0_5_2 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_5_2 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_5_2 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_5_2 : label is "NORMAL"; - attribute GSR of pdp_ram_0_5_2 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_5_2 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_5_2 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_5_2 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_5_2 : label is "4"; - attribute DATA_WIDTH_A of pdp_ram_0_5_2 : label is "4"; - attribute MEM_LPC_FILE of pdp_ram_0_6_1 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_6_1 : label is ""; - attribute CSDECODE_B of pdp_ram_0_6_1 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_6_1 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_6_1 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_6_1 : label is "NORMAL"; - attribute GSR of pdp_ram_0_6_1 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_6_1 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_6_1 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_6_1 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_6_1 : label is "4"; - attribute DATA_WIDTH_A of pdp_ram_0_6_1 : label is "4"; - attribute MEM_LPC_FILE of pdp_ram_0_7_0 : label is "fifo_4096x32.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_7_0 : label is ""; - attribute CSDECODE_B of pdp_ram_0_7_0 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_7_0 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_7_0 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_7_0 : label is "NORMAL"; - attribute GSR of pdp_ram_0_7_0 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_7_0 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_7_0 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_7_0 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_7_0 : label is "4"; - attribute DATA_WIDTH_A of pdp_ram_0_7_0 : label is "4"; - attribute GSR of FF_131 : label is "ENABLED"; - attribute GSR of FF_130 : label is "ENABLED"; - attribute GSR of FF_129 : label is "ENABLED"; - attribute GSR of FF_128 : label is "ENABLED"; - attribute GSR of FF_127 : label is "ENABLED"; - attribute GSR of FF_126 : label is "ENABLED"; - attribute GSR of FF_125 : label is "ENABLED"; - attribute GSR of FF_124 : label is "ENABLED"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t26: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t25: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t24: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t23: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t22: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t21: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t20: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t19: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t18: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t17: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t16: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t15: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t14: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t13: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t12: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t11: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t10: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t9: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t8: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t7: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t6: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t5: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t4: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t3: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t2: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t1: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t0: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - LUT4_33: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>w_gcount_r212, - DO0=>w_g2b_xor_cluster_0); - - LUT4_32: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_gcount_r28, - DO0=>w_g2b_xor_cluster_1); - - LUT4_31: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, - DO0=>w_g2b_xor_cluster_2); - - LUT4_30: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r11); - - LUT4_29: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10); - - LUT4_28: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8); - - LUT4_27: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); - - LUT4_26: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6); - - LUT4_25: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5); - - LUT4_24: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_23: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3); - - LUT4_22: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_21: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2); - - LUT4_20: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_19: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0); - - LUT4_18: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>r_gcount_w212, - DO0=>r_g2b_xor_cluster_0); - - LUT4_17: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, - DO0=>r_g2b_xor_cluster_1); - - LUT4_16: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, - DO0=>r_g2b_xor_cluster_2); - - LUT4_15: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w11); - - LUT4_14: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10); - - LUT4_13: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8); - - LUT4_12: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); - - LUT4_11: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6); - - LUT4_10: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5); - - LUT4_9: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4); - - LUT4_8: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3); - - LUT4_7: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_6: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2); - - LUT4_5: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0); - - LUT4_3: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0410") - -- synopsys translate_on - port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x1004") - -- synopsys translate_on - port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0140") - -- synopsys translate_on - port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4001") - -- synopsys translate_on - port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_7: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, - ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, - ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, - ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_1_6: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - -- synopsys translate_on - port map (DIA0=>Data(4), DIA1=>Data(5), DIA2=>Data(6), - DIA3=>Data(7), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, - ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, - ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, - ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(4), DOB1=>Q(5), DOB2=>Q(6), DOB3=>Q(7), - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_2_5: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - -- synopsys translate_on - port map (DIA0=>Data(8), DIA1=>Data(9), DIA2=>Data(10), - DIA3=>Data(11), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, - ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, - ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, - ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(8), DOB1=>Q(9), DOB2=>Q(10), - DOB3=>Q(11), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, - DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_3_4: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - -- synopsys translate_on - port map (DIA0=>Data(12), DIA1=>Data(13), DIA2=>Data(14), - DIA3=>Data(15), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, - ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, - ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, - ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(12), DOB1=>Q(13), DOB2=>Q(14), - DOB3=>Q(15), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, - DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_4_3: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - -- synopsys translate_on - port map (DIA0=>Data(16), DIA1=>Data(17), DIA2=>Data(18), - DIA3=>Data(19), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, - ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, - ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, - ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(16), DOB1=>Q(17), DOB2=>Q(18), - DOB3=>Q(19), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, - DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_5_2: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - -- synopsys translate_on - port map (DIA0=>Data(20), DIA1=>Data(21), DIA2=>Data(22), - DIA3=>Data(23), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, - ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, - ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, - ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(20), DOB1=>Q(21), DOB2=>Q(22), - DOB3=>Q(23), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, - DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_6_1: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - -- synopsys translate_on - port map (DIA0=>Data(24), DIA1=>Data(25), DIA2=>Data(26), - DIA3=>Data(27), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, - ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, - ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, - ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(24), DOB1=>Q(25), DOB2=>Q(26), - DOB3=>Q(27), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, - DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - pdp_ram_0_7_0: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, - DATA_WIDTH_A=> 4) - -- synopsys translate_on - port map (DIA0=>Data(28), DIA1=>Data(29), DIA2=>Data(30), - DIA3=>Data(31), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, - ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, ADB4=>rptr_2, - ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, ADB8=>rptr_6, - ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, ADB12=>rptr_10, - ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, - DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, - DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, - DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(28), DOB1=>Q(29), DOB2=>Q(30), - DOB3=>Q(31), DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, - DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, - DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); - - FF_131: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_130: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_129: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_128: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_127: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_126: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_125: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_124: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_123: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_122: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_121: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_120: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_119: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_118: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_117: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_116: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_115: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_114: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_113: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_112: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_111: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_110: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_109: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_108: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_107: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_106: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_105: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_104: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_103: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_102: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_101: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_100: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_99: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_98: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_97: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_96: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_95: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_94: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_93: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_92: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_91: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_90: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_89: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_88: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_87: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_86: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_85: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_84: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_83: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_82: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_81: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_80: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_79: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_78: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_77: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_76: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_75: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_74: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_73: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_72: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_71: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_70: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_69: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_68: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_67: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_66: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_65: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_64: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_63: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_62: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_61: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_60: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_59: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_58: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_57: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_56: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_55: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_54: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_53: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_52: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_51: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_50: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_49: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_48: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_47: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_46: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_45: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_44: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_43: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_42: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_41: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_40: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_39: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_38: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_37: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_36: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_35: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_34: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_33: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_32: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_31: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_30: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_29: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_28: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_27: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_26: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_25: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_24: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_23: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_22: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_21: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_20: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_19: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_18: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_17: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_16: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_15: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_14: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_13: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_12: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_11: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_10: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_9: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_8: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_7: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_6: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_5: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_4: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_3: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_2: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_1: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6, - NC0=>iwcount_12, NC1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_1, - NC0=>ircount_12, NC1=>open); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, - B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, - B1=>wcount_r11, CI=>co4_2, GE=>co5_2); - - empty_cmp_6: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, - B1=>r_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, - B1=>rcount_w11, CI=>co4_3, GE=>co5_3); - - full_cmp_6: AGEB2 - port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, - B1=>scuba_vlo, CI=>co5_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp2m; -configuration Structure_CON of fifo_4096x32 is - for Structure - for all:AGEB2 use entity ecp2m.AGEB2(V); end for; - for all:AND2 use entity ecp2m.AND2(V); end for; - for all:CU2 use entity ecp2m.CU2(V); end for; - for all:FADD2B use entity ecp2m.FADD2B(V); end for; - for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; - for all:INV use entity ecp2m.INV(V); end for; - for all:OR2 use entity ecp2m.OR2(V); end for; - for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:XOR2 use entity ecp2m.XOR2(V); end for; - for all:DP16KB use entity ecp2m.DP16KB(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.4 +--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4096 -width 32 -depth 4096 -rdata_width 32 -no_enable -pe -1 -pf -1 -e + +-- Thu Sep 22 11:24:15 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_4096x32 is + port ( + Data: in std_logic_vector(31 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(31 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_4096x32; + +architecture Structure of fifo_4096x32 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal w_gdata_11: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal wptr_12: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_11: std_logic; + signal rptr_12: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal w_gcount_12: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal w_gcount_r212: std_logic; + signal w_gcount_r12: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4: std_logic; + signal iwcount_12: std_logic; + signal co6: std_logic; + signal wcount_12: std_logic; + signal co5: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal co6_1: std_logic; + signal rcount_12: std_logic; + signal co5_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r6: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal wcount_r8: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal wcount_r10: std_logic; + signal wcount_r11: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal rcount_w6: std_logic; + signal rcount_w7: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal rcount_w8: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_3: std_logic; + signal rcount_w10: std_logic; + signal rcount_w11: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co5_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_7 : label is "fifo_4096x32.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_7 : label is ""; + attribute RESETMODE of pdp_ram_0_0_7 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_1_6 : label is "fifo_4096x32.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_6 : label is ""; + attribute RESETMODE of pdp_ram_0_1_6 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_2_5 : label is "fifo_4096x32.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_2_5 : label is ""; + attribute RESETMODE of pdp_ram_0_2_5 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_3_4 : label is "fifo_4096x32.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_3_4 : label is ""; + attribute RESETMODE of pdp_ram_0_3_4 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_4_3 : label is "fifo_4096x32.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_4_3 : label is ""; + attribute RESETMODE of pdp_ram_0_4_3 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_5_2 : label is "fifo_4096x32.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_5_2 : label is ""; + attribute RESETMODE of pdp_ram_0_5_2 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_6_1 : label is "fifo_4096x32.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_6_1 : label is ""; + attribute RESETMODE of pdp_ram_0_6_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_7_0 : label is "fifo_4096x32.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_7_0 : label is ""; + attribute RESETMODE of pdp_ram_0_7_0 : label is "SYNC"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t26: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t25: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t24: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t23: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t22: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t21: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t20: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t19: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t18: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t17: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t16: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t15: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t14: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t13: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t12: XOR2 + port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); + + XOR2_t11: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t10: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t9: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t8: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t7: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t6: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t5: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t4: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t3: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t2: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t1: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t0: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + LUT4_33: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>w_gcount_r212, + DO0=>w_g2b_xor_cluster_0); + + LUT4_32: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>w_gcount_r28, + DO0=>w_g2b_xor_cluster_1); + + LUT4_31: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, + DO0=>w_g2b_xor_cluster_2); + + LUT4_30: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r11); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, + AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>r_gcount_w212, + DO0=>r_g2b_xor_cluster_0); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, + DO0=>r_g2b_xor_cluster_1); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_2); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w11); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_7: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, + ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, + ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, + ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, + ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, + ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, + OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), + DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>open, DOB5=>open, + DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, + DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, + DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_0_1_6: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + port map (DIA0=>Data(4), DIA1=>Data(5), DIA2=>Data(6), + DIA3=>Data(7), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, + ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, + ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, + ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, + ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, + ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, + OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(4), + DOB1=>Q(5), DOB2=>Q(6), DOB3=>Q(7), DOB4=>open, DOB5=>open, + DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, + DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, + DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_0_2_5: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + port map (DIA0=>Data(8), DIA1=>Data(9), DIA2=>Data(10), + DIA3=>Data(11), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, + ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, + ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, + ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, + ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, + ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, + OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(8), + DOB1=>Q(9), DOB2=>Q(10), DOB3=>Q(11), DOB4=>open, DOB5=>open, + DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, + DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, + DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_0_3_4: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + port map (DIA0=>Data(12), DIA1=>Data(13), DIA2=>Data(14), + DIA3=>Data(15), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, + ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, + ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, + ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, + ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, + ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, + OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(12), + DOB1=>Q(13), DOB2=>Q(14), DOB3=>Q(15), DOB4=>open, + DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_0_4_3: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + port map (DIA0=>Data(16), DIA1=>Data(17), DIA2=>Data(18), + DIA3=>Data(19), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, + ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, + ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, + ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, + ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, + ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, + OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(16), + DOB1=>Q(17), DOB2=>Q(18), DOB3=>Q(19), DOB4=>open, + DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_0_5_2: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + port map (DIA0=>Data(20), DIA1=>Data(21), DIA2=>Data(22), + DIA3=>Data(23), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, + ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, + ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, + ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, + ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, + ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, + OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(20), + DOB1=>Q(21), DOB2=>Q(22), DOB3=>Q(23), DOB4=>open, + DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_0_6_1: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + port map (DIA0=>Data(24), DIA1=>Data(25), DIA2=>Data(26), + DIA3=>Data(27), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, + ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, + ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, + ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, + ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, + ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, + OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(24), + DOB1=>Q(25), DOB2=>Q(26), DOB3=>Q(27), DOB4=>open, + DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_0_7_0: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + port map (DIA0=>Data(28), DIA1=>Data(29), DIA2=>Data(30), + DIA3=>Data(31), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, + ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, + ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9, + ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, ADB3=>rptr_1, + ADB4=>rptr_2, ADB5=>rptr_3, ADB6=>rptr_4, ADB7=>rptr_5, + ADB8=>rptr_6, ADB9=>rptr_7, ADB10=>rptr_8, ADB11=>rptr_9, + ADB12=>rptr_10, ADB13=>rptr_11, CEB=>rden_i, CLKB=>RdClock, + OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(28), + DOB1=>Q(29), DOB2=>Q(30), DOB3=>Q(31), DOB4=>open, + DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + FF_131: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_130: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_129: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_128: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_127: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_126: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_125: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_124: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_123: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_122: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_121: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_120: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_119: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_12); + + FF_118: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_117: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_116: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_115: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_114: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_113: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_112: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_111: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_110: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_109: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_108: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_107: FD1P3DX + port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_106: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_12); + + FF_105: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_104: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_103: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_102: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_101: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_100: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_99: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_98: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_97: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_96: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_95: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_94: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_93: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_12); + + FF_92: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_91: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_90: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_89: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_88: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_87: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_86: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_85: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_84: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_83: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_82: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_81: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_80: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_79: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_78: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_77: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_76: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_75: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_74: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_73: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_72: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_71: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_70: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_69: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_68: FD1P3DX + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_67: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_66: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_65: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_64: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_63: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_62: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_61: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_60: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_59: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_58: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_57: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_56: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_55: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_54: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_53: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_52: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_51: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_50: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_49: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_48: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_47: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_46: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_45: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_44: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_43: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_42: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_41: FD1S3DX + port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r12); + + FF_40: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_39: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_38: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_37: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_36: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_35: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_34: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_33: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_32: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_31: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_30: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_29: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_28: FD1S3DX + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_27: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_26: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_25: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_24: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_23: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_22: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_21: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_20: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_19: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_18: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_17: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_16: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_15: FD1S3DX + port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r212); + + FF_14: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_13: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_12: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_11: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_10: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_9: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_8: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_7: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_6: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_5: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_4: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_3: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_2: FD1S3DX + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_gctr_6: CU2 + port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6, + NC0=>iwcount_12, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + r_gctr_6: CU2 + port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_1, + NC0=>ircount_12, NC1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, + B1=>wcount_r7, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, + B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, + B1=>wcount_r11, CI=>co4_2, GE=>co5_2); + + empty_cmp_6: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, + B1=>r_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, + B1=>rcount_w11, CI=>co4_3, GE=>co5_3); + + full_cmp_6: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co5_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_4096x32 is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/fifo_4096x32_tmpl.vhd b/gbe_ecp2m/ipcores/fifo_4096x32_tmpl.vhd index 745eb44..f26714f 100755 --- a/gbe_ecp2m/ipcores/fifo_4096x32_tmpl.vhd +++ b/gbe_ecp2m/ipcores/fifo_4096x32_tmpl.vhd @@ -1,18 +1,18 @@ --- VHDL module instantiation generated by SCUBA ispLever_v8.0_PROD_Build (41) --- Module Version: 5.3 --- Fri Dec 18 03:02:30 2009 - --- parameterized module component declaration -component fifo_4096x32 - port (Data: in std_logic_vector(31 downto 0); - WrClock: in std_logic; RdClock: in std_logic; - WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; - RPReset: in std_logic; Q: out std_logic_vector(31 downto 0); - Empty: out std_logic; Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_4096x32 - port map (Data(31 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(31 downto 0)=>__, Empty=>__, - Full=>__); +-- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.4 +-- Thu Sep 22 11:24:15 2011 + +-- parameterized module component declaration +component fifo_4096x32 + port (Data: in std_logic_vector(31 downto 0); + WrClock: in std_logic; RdClock: in std_logic; + WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + RPReset: in std_logic; Q: out std_logic_vector(31 downto 0); + Empty: out std_logic; Full: out std_logic); +end component; + +-- parameterized module component instance +__ : fifo_4096x32 + port map (Data(31 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, + RdEn=>__, Reset=>__, RPReset=>__, Q(31 downto 0)=>__, Empty=>__, + Full=>__); diff --git a/gbe_ecp2m/ipcores/fifo_4096x9.lpc b/gbe_ecp2m/ipcores/fifo_4096x9.lpc index 22cb7c6..6e382a8 100755 --- a/gbe_ecp2m/ipcores/fifo_4096x9.lpc +++ b/gbe_ecp2m/ipcores/fifo_4096x9.lpc @@ -1,47 +1,47 @@ -[Device] -Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-5F900C -SpeedGrade=-5 -Package=FPBGA900 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.2 -ModuleName=fifo_4096x9 -SourceFormat=Schematic/VHDL -ParameterFileVersion=1.0 -Date=01/05/2010 -Time=23:44:15 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=4096 -Width=9 -RDepth=4096 -RWidth=9 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_4096x9 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/22/2011 +Time=11:24:06 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=4096 +Width=9 +RDepth=4096 +RWidth=9 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/gbe_ecp2m/ipcores/fifo_4096x9.vhd b/gbe_ecp2m/ipcores/fifo_4096x9.vhd index ca644d2..75ae6c9 100755 --- a/gbe_ecp2m/ipcores/fifo_4096x9.vhd +++ b/gbe_ecp2m/ipcores/fifo_4096x9.vhd @@ -1,2171 +1,1624 @@ --- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) --- Module Version: 5.2 ---/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 4096 -width 9 -depth 4096 -rdata_width 9 -no_enable -pe -1 -pf -1 -e - --- Tue Jan 5 23:44:15 2010 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp2m; -use ecp2m.components.all; --- synopsys translate_on - -entity fifo_4096x9 is - port ( - Data: in std_logic_vector(8 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(8 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_4096x9; - -architecture Structure of fifo_4096x9 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal w_gdata_11: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal wptr_12: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal r_gdata_11: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_12: std_logic; - signal rptr_11: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal w_gcount_12: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal r_gcount_12: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal w_gcount_r212: std_logic; - signal w_gcount_r12: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal r_gcount_w212: std_logic; - signal r_gcount_w12: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co4: std_logic; - signal iwcount_12: std_logic; - signal co6: std_logic; - signal wcount_12: std_logic; - signal co5: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co4_1: std_logic; - signal ircount_12: std_logic; - signal co6_1: std_logic; - signal rcount_12: std_logic; - signal co5_1: std_logic; - signal mdout1_1_0: std_logic; - signal mdout1_0_0: std_logic; - signal mdout1_1_1: std_logic; - signal mdout1_0_1: std_logic; - signal mdout1_1_2: std_logic; - signal mdout1_0_2: std_logic; - signal mdout1_1_3: std_logic; - signal mdout1_0_3: std_logic; - signal mdout1_1_4: std_logic; - signal mdout1_0_4: std_logic; - signal mdout1_1_5: std_logic; - signal mdout1_0_5: std_logic; - signal mdout1_1_6: std_logic; - signal mdout1_0_6: std_logic; - signal mdout1_1_7: std_logic; - signal mdout1_0_7: std_logic; - signal rptr_11_ff: std_logic; - signal mdout1_1_8: std_logic; - signal mdout1_0_8: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r8: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r10: std_logic; - signal wcount_r11: std_logic; - signal rcount_10: std_logic; - signal rcount_11: std_logic; - signal co5_2: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w6: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal rcount_w8: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w10: std_logic; - signal rcount_w11: std_logic; - signal wcount_10: std_logic; - signal wcount_11: std_logic; - signal co5_3: std_logic; - signal full_cmp_clr: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component MUX21 - port (D0: in std_logic; D1: in std_logic; SD: in std_logic; - Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1 - -- synopsys translate_off - generic (initval : in String); - -- synopsys translate_on - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KB - -- synopsys translate_off - generic (GSR : in String; WRITEMODE_B : in String; - CSDECODE_B : in std_logic_vector(2 downto 0); - CSDECODE_A : in std_logic_vector(2 downto 0); - WRITEMODE_A : in String; RESETMODE : in String; - REGMODE_B : in String; REGMODE_A : in String; - DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); - -- synopsys translate_on - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; - CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; - CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute initval : string; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute CSDECODE_B : string; - attribute CSDECODE_A : string; - attribute WRITEMODE_B : string; - attribute WRITEMODE_A : string; - attribute RESETMODE : string; - attribute REGMODE_B : string; - attribute REGMODE_A : string; - attribute DATA_WIDTH_B : string; - attribute DATA_WIDTH_A : string; - attribute GSR : string; - attribute initval of LUT4_33 : label is "0x6996"; - attribute initval of LUT4_32 : label is "0x6996"; - attribute initval of LUT4_31 : label is "0x6996"; - attribute initval of LUT4_30 : label is "0x6996"; - attribute initval of LUT4_29 : label is "0x6996"; - attribute initval of LUT4_28 : label is "0x6996"; - attribute initval of LUT4_27 : label is "0x6996"; - attribute initval of LUT4_26 : label is "0x6996"; - attribute initval of LUT4_25 : label is "0x6996"; - attribute initval of LUT4_24 : label is "0x6996"; - attribute initval of LUT4_23 : label is "0x6996"; - attribute initval of LUT4_22 : label is "0x6996"; - attribute initval of LUT4_21 : label is "0x6996"; - attribute initval of LUT4_20 : label is "0x6996"; - attribute initval of LUT4_19 : label is "0x6996"; - attribute initval of LUT4_18 : label is "0x6996"; - attribute initval of LUT4_17 : label is "0x6996"; - attribute initval of LUT4_16 : label is "0x6996"; - attribute initval of LUT4_15 : label is "0x6996"; - attribute initval of LUT4_14 : label is "0x6996"; - attribute initval of LUT4_13 : label is "0x6996"; - attribute initval of LUT4_12 : label is "0x6996"; - attribute initval of LUT4_11 : label is "0x6996"; - attribute initval of LUT4_10 : label is "0x6996"; - attribute initval of LUT4_9 : label is "0x6996"; - attribute initval of LUT4_8 : label is "0x6996"; - attribute initval of LUT4_7 : label is "0x6996"; - attribute initval of LUT4_6 : label is "0x6996"; - attribute initval of LUT4_5 : label is "0x6996"; - attribute initval of LUT4_4 : label is "0x6996"; - attribute initval of LUT4_3 : label is "0x0410"; - attribute initval of LUT4_2 : label is "0x1004"; - attribute initval of LUT4_1 : label is "0x0140"; - attribute initval of LUT4_0 : label is "0x4001"; - attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_4096x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; - attribute CSDECODE_B of pdp_ram_0_0_1 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_0_1 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_0_1 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_0_1 : label is "NORMAL"; - attribute GSR of pdp_ram_0_0_1 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_0_1 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_0_1 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_0_1 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_0_1 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_0_0_1 : label is "9"; - attribute MEM_LPC_FILE of pdp_ram_1_0_0 : label is "fifo_4096x9.lpc"; - attribute MEM_INIT_FILE of pdp_ram_1_0_0 : label is ""; - attribute CSDECODE_B of pdp_ram_1_0_0 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_1_0_0 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_1_0_0 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_1_0_0 : label is "NORMAL"; - attribute GSR of pdp_ram_1_0_0 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_1_0_0 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_1_0_0 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_1_0_0 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_1_0_0 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_1_0_0 : label is "9"; - attribute GSR of FF_132 : label is "ENABLED"; - attribute GSR of FF_131 : label is "ENABLED"; - attribute GSR of FF_130 : label is "ENABLED"; - attribute GSR of FF_129 : label is "ENABLED"; - attribute GSR of FF_128 : label is "ENABLED"; - attribute GSR of FF_127 : label is "ENABLED"; - attribute GSR of FF_126 : label is "ENABLED"; - attribute GSR of FF_125 : label is "ENABLED"; - attribute GSR of FF_124 : label is "ENABLED"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t26: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t25: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t24: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t23: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t22: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t21: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t20: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t19: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t18: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t17: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t16: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t15: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t14: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t13: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t12: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t11: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t10: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t9: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t8: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t7: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t6: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t5: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t4: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t3: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t2: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t1: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t0: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - LUT4_33: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>w_gcount_r212, - DO0=>w_g2b_xor_cluster_0); - - LUT4_32: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_gcount_r28, - DO0=>w_g2b_xor_cluster_1); - - LUT4_31: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, - DO0=>w_g2b_xor_cluster_2); - - LUT4_30: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r11); - - LUT4_29: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10); - - LUT4_28: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8); - - LUT4_27: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, - AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); - - LUT4_26: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6); - - LUT4_25: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5); - - LUT4_24: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4); - - LUT4_23: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3); - - LUT4_22: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_21: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2); - - LUT4_20: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_19: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0); - - LUT4_18: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>r_gcount_w212, - DO0=>r_g2b_xor_cluster_0); - - LUT4_17: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, - DO0=>r_g2b_xor_cluster_1); - - LUT4_16: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, - DO0=>r_g2b_xor_cluster_2); - - LUT4_15: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w11); - - LUT4_14: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10); - - LUT4_13: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8); - - LUT4_12: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, - AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); - - LUT4_11: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6); - - LUT4_10: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5); - - LUT4_9: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4); - - LUT4_8: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3); - - LUT4_7: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_6: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2); - - LUT4_5: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1); - - LUT4_4: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0); - - LUT4_3: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0410") - -- synopsys translate_on - port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x1004") - -- synopsys translate_on - port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0140") - -- synopsys translate_on - port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4001") - -- synopsys translate_on - port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_1: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>wptr_11, CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>rptr_11, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, - DOB1=>mdout1_0_1, DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, - DOB4=>mdout1_0_4, DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, - DOB7=>mdout1_0_7, DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_1_0_0: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, - DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, - DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, - DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, - ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, - ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, - ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>wptr_11, CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, - ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, - ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, - CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>rptr_11, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, - DOB1=>mdout1_1_1, DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, - DOB4=>mdout1_1_4, DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, - DOB7=>mdout1_1_7, DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - FF_132: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_131: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_130: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_129: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_128: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_127: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_126: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_125: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_124: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_123: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_122: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_121: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_120: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_119: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_118: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_117: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_116: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_115: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_114: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_113: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_112: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_111: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_110: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_109: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_108: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_107: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_106: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_105: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_104: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_103: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_102: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_101: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_100: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_99: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_98: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_97: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_96: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_95: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_94: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_93: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_92: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_91: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_90: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_89: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_88: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_87: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_86: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_85: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_84: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_83: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_82: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_81: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_80: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_79: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_78: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_77: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_76: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_75: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_74: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_73: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_72: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_71: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_70: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_69: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_68: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_67: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_66: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_65: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_64: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_63: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_62: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_61: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_60: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_59: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_58: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_57: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_56: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_55: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_54: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_11_ff); - - FF_53: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_52: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_51: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_50: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_49: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_48: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_47: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_46: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_45: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_44: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_43: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_42: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_41: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_40: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_39: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_38: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_37: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_36: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_35: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_34: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_33: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_32: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_31: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_30: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_29: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_28: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_27: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_26: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_25: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_24: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_23: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_22: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_21: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_20: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_19: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_18: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_17: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_16: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_15: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_14: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_13: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_12: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_11: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_10: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_9: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_8: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_7: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_6: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_5: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_4: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_3: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_2: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_1: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6, - NC0=>iwcount_12, NC1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_1, - NC0=>ircount_12, NC1=>open); - - mux_8: MUX21 - port map (D0=>mdout1_0_0, D1=>mdout1_1_0, SD=>rptr_11_ff, - Z=>Q(0)); - - mux_7: MUX21 - port map (D0=>mdout1_0_1, D1=>mdout1_1_1, SD=>rptr_11_ff, - Z=>Q(1)); - - mux_6: MUX21 - port map (D0=>mdout1_0_2, D1=>mdout1_1_2, SD=>rptr_11_ff, - Z=>Q(2)); - - mux_5: MUX21 - port map (D0=>mdout1_0_3, D1=>mdout1_1_3, SD=>rptr_11_ff, - Z=>Q(3)); - - mux_4: MUX21 - port map (D0=>mdout1_0_4, D1=>mdout1_1_4, SD=>rptr_11_ff, - Z=>Q(4)); - - mux_3: MUX21 - port map (D0=>mdout1_0_5, D1=>mdout1_1_5, SD=>rptr_11_ff, - Z=>Q(5)); - - mux_2: MUX21 - port map (D0=>mdout1_0_6, D1=>mdout1_1_6, SD=>rptr_11_ff, - Z=>Q(6)); - - mux_1: MUX21 - port map (D0=>mdout1_0_7, D1=>mdout1_1_7, SD=>rptr_11_ff, - Z=>Q(7)); - - mux_0: MUX21 - port map (D0=>mdout1_0_8, D1=>mdout1_1_8, SD=>rptr_11_ff, - Z=>Q(8)); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, - B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, - B1=>wcount_r11, CI=>co4_2, GE=>co5_2); - - empty_cmp_6: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, - B1=>r_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, - B1=>rcount_w11, CI=>co4_3, GE=>co5_3); - - full_cmp_6: AGEB2 - port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, - B1=>scuba_vlo, CI=>co5_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp2m; -configuration Structure_CON of fifo_4096x9 is - for Structure - for all:AGEB2 use entity ecp2m.AGEB2(V); end for; - for all:AND2 use entity ecp2m.AND2(V); end for; - for all:CU2 use entity ecp2m.CU2(V); end for; - for all:FADD2B use entity ecp2m.FADD2B(V); end for; - for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; - for all:INV use entity ecp2m.INV(V); end for; - for all:MUX21 use entity ecp2m.MUX21(V); end for; - for all:OR2 use entity ecp2m.OR2(V); end for; - for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:XOR2 use entity ecp2m.XOR2(V); end for; - for all:DP16KB use entity ecp2m.DP16KB(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.4 +--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4096 -width 9 -depth 4096 -rdata_width 9 -no_enable -pe -1 -pf -1 -e + +-- Thu Sep 22 11:24:06 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_4096x9 is + port ( + Data: in std_logic_vector(8 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(8 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_4096x9; + +architecture Structure of fifo_4096x9 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal w_gdata_11: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal wptr_12: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_12: std_logic; + signal rptr_11: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal w_gcount_12: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal w_gcount_r212: std_logic; + signal w_gcount_r12: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4: std_logic; + signal iwcount_12: std_logic; + signal co6: std_logic; + signal wcount_12: std_logic; + signal co5: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal co6_1: std_logic; + signal rcount_12: std_logic; + signal co5_1: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal rptr_11_ff: std_logic; + signal mdout1_1_8: std_logic; + signal mdout1_0_8: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r6: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal wcount_r8: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal wcount_r10: std_logic; + signal wcount_r11: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal rcount_w6: std_logic; + signal rcount_w7: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal rcount_w8: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_3: std_logic; + signal rcount_w10: std_logic; + signal rcount_w11: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co5_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX21 + port (D0: in std_logic; D1: in std_logic; SD: in std_logic; + Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_4096x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; + attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_0_0 : label is "fifo_4096x9.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_0 : label is ""; + attribute RESETMODE of pdp_ram_1_0_0 : label is "SYNC"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t26: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t25: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t24: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t23: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t22: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t21: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t20: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t19: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t18: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t17: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t16: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t15: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t14: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t13: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t12: XOR2 + port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); + + XOR2_t11: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t10: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t9: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t8: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t7: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t6: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t5: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t4: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t3: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t2: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t1: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t0: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + LUT4_33: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>w_gcount_r212, + DO0=>w_g2b_xor_cluster_0); + + LUT4_32: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>w_gcount_r28, + DO0=>w_g2b_xor_cluster_1); + + LUT4_31: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, + DO0=>w_g2b_xor_cluster_2); + + LUT4_30: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r11); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, + AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>r_gcount_w212, + DO0=>r_g2b_xor_cluster_0); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, + DO0=>r_g2b_xor_cluster_1); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_2); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w11); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r212, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w212, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_1: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, + DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, + DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, + DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_0_0: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, + DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, + DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, + DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + FF_132: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_131: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_130: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_129: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_128: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_127: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_126: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_125: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_124: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_123: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_122: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_121: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_120: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_12); + + FF_119: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_118: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_117: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_116: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_115: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_114: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_113: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_112: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_111: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_110: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_109: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_108: FD1P3DX + port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_107: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_12); + + FF_106: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_105: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_104: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_103: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_102: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_101: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_100: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_99: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_98: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_97: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_96: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_95: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_94: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_12); + + FF_93: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_92: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_91: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_90: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_89: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_88: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_87: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_86: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_85: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_84: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_83: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_82: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_81: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_80: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_79: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_78: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_77: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_76: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_75: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_74: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_73: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_72: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_71: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_70: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_69: FD1P3DX + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_68: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_67: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_66: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_65: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_64: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_63: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_62: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_61: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_60: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_59: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_58: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_57: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_56: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_55: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_54: FD1P3DX + port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_11_ff); + + FF_53: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_52: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_51: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_50: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_49: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_48: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_47: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_46: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_45: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_44: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_43: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_42: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_41: FD1S3DX + port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r12); + + FF_40: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_39: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_38: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_37: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_36: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_35: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_34: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_33: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_32: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_31: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_30: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_29: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_28: FD1S3DX + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_27: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_26: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_25: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_24: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_23: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_22: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_21: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_20: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_19: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_18: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_17: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_16: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_15: FD1S3DX + port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r212); + + FF_14: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_13: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_12: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_11: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_10: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_9: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_8: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_7: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_6: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_5: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_4: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_3: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_2: FD1S3DX + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_gctr_6: CU2 + port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6, + NC0=>iwcount_12, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + r_gctr_6: CU2 + port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_1, + NC0=>ircount_12, NC1=>open); + + mux_8: MUX21 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, SD=>rptr_11_ff, + Z=>Q(0)); + + mux_7: MUX21 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, SD=>rptr_11_ff, + Z=>Q(1)); + + mux_6: MUX21 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, SD=>rptr_11_ff, + Z=>Q(2)); + + mux_5: MUX21 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, SD=>rptr_11_ff, + Z=>Q(3)); + + mux_4: MUX21 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, SD=>rptr_11_ff, + Z=>Q(4)); + + mux_3: MUX21 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, SD=>rptr_11_ff, + Z=>Q(5)); + + mux_2: MUX21 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, SD=>rptr_11_ff, + Z=>Q(6)); + + mux_1: MUX21 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, SD=>rptr_11_ff, + Z=>Q(7)); + + mux_0: MUX21 + port map (D0=>mdout1_0_8, D1=>mdout1_1_8, SD=>rptr_11_ff, + Z=>Q(8)); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, + B1=>wcount_r7, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, + B1=>w_g2b_xor_cluster_0, CI=>co3_2, GE=>co4_2); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, + B1=>wcount_r11, CI=>co4_2, GE=>co5_2); + + empty_cmp_6: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co5_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, + B1=>r_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, + B1=>rcount_w11, CI=>co4_3, GE=>co5_3); + + full_cmp_6: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co5_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_4096x9 is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:MUX21 use entity ecp3.MUX21(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/fifo_4096x9_tmpl.vhd b/gbe_ecp2m/ipcores/fifo_4096x9_tmpl.vhd index f754d74..8b69bd4 100755 --- a/gbe_ecp2m/ipcores/fifo_4096x9_tmpl.vhd +++ b/gbe_ecp2m/ipcores/fifo_4096x9_tmpl.vhd @@ -1,18 +1,18 @@ --- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) --- Module Version: 5.2 --- Tue Jan 5 23:44:15 2010 - --- parameterized module component declaration -component fifo_4096x9 - port (Data: in std_logic_vector(8 downto 0); WrClock: in std_logic; - RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; - Reset: in std_logic; RPReset: in std_logic; - Q: out std_logic_vector(8 downto 0); Empty: out std_logic; - Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_4096x9 - port map (Data(8 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(8 downto 0)=>__, Empty=>__, - Full=>__); +-- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.4 +-- Thu Sep 22 11:24:06 2011 + +-- parameterized module component declaration +component fifo_4096x9 + port (Data: in std_logic_vector(8 downto 0); WrClock: in std_logic; + RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; + Reset: in std_logic; RPReset: in std_logic; + Q: out std_logic_vector(8 downto 0); Empty: out std_logic; + Full: out std_logic); +end component; + +-- parameterized module component instance +__ : fifo_4096x9 + port map (Data(8 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, + RdEn=>__, Reset=>__, RPReset=>__, Q(8 downto 0)=>__, Empty=>__, + Full=>__); diff --git a/gbe_ecp2m/ipcores/fifo_64kx8.lpc b/gbe_ecp2m/ipcores/fifo_64kx8.lpc index 3d27821..badffb2 100755 --- a/gbe_ecp2m/ipcores/fifo_64kx8.lpc +++ b/gbe_ecp2m/ipcores/fifo_64kx8.lpc @@ -1,47 +1,47 @@ -[Device] -Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-5F900C -SpeedGrade=-5 -Package=FPBGA900 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO_DC -CoreRevision=5.2 -ModuleName=fifo_64kx8 -SourceFormat=Schematic/VHDL -ParameterFileVersion=1.0 -Date=12/26/2009 -Time=00:12:05 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=EBR Based -Depth=65536 -Width=8 -RDepth=65536 -RWidth=8 -regout=0 -CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=0 -PfMode=Static - Dual Threshold -PfAssert=508 -PfDeassert=506 -RDataCount=0 -WDataCount=0 -EnECC=0 +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_64kx8 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/22/2011 +Time=11:23:03 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=65536 +Width=8 +RDepth=65536 +RWidth=8 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/gbe_ecp2m/ipcores/fifo_64kx8.vhd b/gbe_ecp2m/ipcores/fifo_64kx8.vhd index ba79880..8d65547 100755 --- a/gbe_ecp2m/ipcores/fifo_64kx8.vhd +++ b/gbe_ecp2m/ipcores/fifo_64kx8.vhd @@ -1,4435 +1,3355 @@ --- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) --- Module Version: 5.2 ---/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 65536 -width 8 -depth 65536 -rdata_width 8 -no_enable -pe -1 -pf -1 -e - --- Sat Dec 26 00:12:05 2009 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp2m; -use ecp2m.components.all; --- synopsys translate_on - -entity fifo_64kx8 is - port ( - Data: in std_logic_vector(7 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(7 downto 0); - Empty: out std_logic; - Full: out std_logic); -end fifo_64kx8; - -architecture Structure of fifo_64kx8 is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal w_g2b_xor_cluster_2_1: std_logic; - signal w_g2b_xor_cluster_3_1: std_logic; - signal w_g2b_xor_cluster_3_2: std_logic; - signal w_g2b_xor_cluster_3: std_logic; - signal w_g2b_xor_cluster_2: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal func_xor_inet_3: std_logic; - signal func_xor_inet_2: std_logic; - signal func_xor_inet_1: std_logic; - signal func_xor_inet: std_logic; - signal func_xor_inet_4: std_logic; - signal func_xor_inet_5: std_logic; - signal r_g2b_xor_cluster_2_1: std_logic; - signal r_g2b_xor_cluster_3_1: std_logic; - signal r_g2b_xor_cluster_3_2: std_logic; - signal r_g2b_xor_cluster_3: std_logic; - signal r_g2b_xor_cluster_2: std_logic; - signal r_g2b_xor_cluster_1: std_logic; - signal func_xor_inet_9: std_logic; - signal func_xor_inet_8: std_logic; - signal func_xor_inet_7: std_logic; - signal func_xor_inet_6: std_logic; - signal func_xor_inet_10: std_logic; - signal func_xor_inet_11: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal w_gdata_8: std_logic; - signal w_gdata_9: std_logic; - signal w_gdata_10: std_logic; - signal w_gdata_11: std_logic; - signal w_gdata_12: std_logic; - signal w_gdata_13: std_logic; - signal w_gdata_14: std_logic; - signal w_gdata_15: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal wptr_9: std_logic; - signal wptr_10: std_logic; - signal wptr_11: std_logic; - signal wptr_12: std_logic; - signal wptr_13: std_logic; - signal wptr_14: std_logic; - signal wptr_15: std_logic; - signal wptr_16: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal r_gdata_6: std_logic; - signal r_gdata_7: std_logic; - signal r_gdata_8: std_logic; - signal r_gdata_9: std_logic; - signal r_gdata_10: std_logic; - signal r_gdata_11: std_logic; - signal r_gdata_12: std_logic; - signal r_gdata_13: std_logic; - signal r_gdata_14: std_logic; - signal r_gdata_15: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; - signal rptr_11: std_logic; - signal rptr_12: std_logic; - signal rptr_13: std_logic; - signal rptr_16: std_logic; - signal rptr_14: std_logic; - signal rptr_15: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal w_gcount_9: std_logic; - signal w_gcount_10: std_logic; - signal w_gcount_11: std_logic; - signal w_gcount_12: std_logic; - signal w_gcount_13: std_logic; - signal w_gcount_14: std_logic; - signal w_gcount_15: std_logic; - signal w_gcount_16: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal r_gcount_7: std_logic; - signal r_gcount_8: std_logic; - signal r_gcount_9: std_logic; - signal r_gcount_10: std_logic; - signal r_gcount_11: std_logic; - signal r_gcount_12: std_logic; - signal r_gcount_13: std_logic; - signal r_gcount_14: std_logic; - signal r_gcount_15: std_logic; - signal r_gcount_16: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal w_gcount_r29: std_logic; - signal w_gcount_r9: std_logic; - signal w_gcount_r210: std_logic; - signal w_gcount_r10: std_logic; - signal w_gcount_r211: std_logic; - signal w_gcount_r11: std_logic; - signal w_gcount_r212: std_logic; - signal w_gcount_r12: std_logic; - signal w_gcount_r213: std_logic; - signal w_gcount_r13: std_logic; - signal w_gcount_r214: std_logic; - signal w_gcount_r14: std_logic; - signal w_gcount_r215: std_logic; - signal w_gcount_r15: std_logic; - signal w_gcount_r216: std_logic; - signal w_gcount_r16: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal r_gcount_w27: std_logic; - signal r_gcount_w7: std_logic; - signal r_gcount_w28: std_logic; - signal r_gcount_w8: std_logic; - signal r_gcount_w29: std_logic; - signal r_gcount_w9: std_logic; - signal r_gcount_w210: std_logic; - signal r_gcount_w10: std_logic; - signal r_gcount_w211: std_logic; - signal r_gcount_w11: std_logic; - signal r_gcount_w212: std_logic; - signal r_gcount_w12: std_logic; - signal r_gcount_w213: std_logic; - signal r_gcount_w13: std_logic; - signal r_gcount_w214: std_logic; - signal r_gcount_w14: std_logic; - signal r_gcount_w215: std_logic; - signal r_gcount_w15: std_logic; - signal r_gcount_w216: std_logic; - signal r_gcount_w16: std_logic; - signal empty_i: std_logic; - signal rRst: std_logic; - signal full_i: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal iwcount_9: std_logic; - signal co3: std_logic; - signal iwcount_10: std_logic; - signal iwcount_11: std_logic; - signal co4: std_logic; - signal iwcount_12: std_logic; - signal iwcount_13: std_logic; - signal co5: std_logic; - signal iwcount_14: std_logic; - signal iwcount_15: std_logic; - signal co6: std_logic; - signal iwcount_16: std_logic; - signal co8: std_logic; - signal wcount_16: std_logic; - signal co7: std_logic; - signal scuba_vhi: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal ircount_7: std_logic; - signal co2_1: std_logic; - signal ircount_8: std_logic; - signal ircount_9: std_logic; - signal co3_1: std_logic; - signal ircount_10: std_logic; - signal ircount_11: std_logic; - signal co4_1: std_logic; - signal ircount_12: std_logic; - signal ircount_13: std_logic; - signal co5_1: std_logic; - signal ircount_14: std_logic; - signal ircount_15: std_logic; - signal co6_1: std_logic; - signal ircount_16: std_logic; - signal co8_1: std_logic; - signal rcount_16: std_logic; - signal co7_1: std_logic; - signal mdout1_3_0: std_logic; - signal mdout1_2_0: std_logic; - signal mdout1_1_0: std_logic; - signal mdout1_0_0: std_logic; - signal mdout1_3_1: std_logic; - signal mdout1_2_1: std_logic; - signal mdout1_1_1: std_logic; - signal mdout1_0_1: std_logic; - signal mdout1_3_2: std_logic; - signal mdout1_2_2: std_logic; - signal mdout1_1_2: std_logic; - signal mdout1_0_2: std_logic; - signal mdout1_3_3: std_logic; - signal mdout1_2_3: std_logic; - signal mdout1_1_3: std_logic; - signal mdout1_0_3: std_logic; - signal mdout1_3_4: std_logic; - signal mdout1_2_4: std_logic; - signal mdout1_1_4: std_logic; - signal mdout1_0_4: std_logic; - signal mdout1_3_5: std_logic; - signal mdout1_2_5: std_logic; - signal mdout1_1_5: std_logic; - signal mdout1_0_5: std_logic; - signal mdout1_3_6: std_logic; - signal mdout1_2_6: std_logic; - signal mdout1_1_6: std_logic; - signal mdout1_0_6: std_logic; - signal rptr_15_ff: std_logic; - signal rptr_14_ff: std_logic; - signal mdout1_3_7: std_logic; - signal mdout1_2_7: std_logic; - signal mdout1_1_7: std_logic; - signal mdout1_0_7: std_logic; - signal rden_i: std_logic; - signal cmp_ci: std_logic; - signal wcount_r0: std_logic; - signal wcount_r1: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_2: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_2: std_logic; - signal wcount_r4: std_logic; - signal wcount_r5: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_2: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; - signal rcount_6: std_logic; - signal rcount_7: std_logic; - signal co3_2: std_logic; - signal wcount_r8: std_logic; - signal wcount_r9: std_logic; - signal rcount_8: std_logic; - signal rcount_9: std_logic; - signal co4_2: std_logic; - signal wcount_r10: std_logic; - signal wcount_r11: std_logic; - signal rcount_10: std_logic; - signal rcount_11: std_logic; - signal co5_2: std_logic; - signal wcount_r12: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_12: std_logic; - signal rcount_13: std_logic; - signal co6_2: std_logic; - signal wcount_r14: std_logic; - signal wcount_r15: std_logic; - signal rcount_14: std_logic; - signal rcount_15: std_logic; - signal co7_2: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_3: std_logic; - signal rcount_w2: std_logic; - signal rcount_w3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_3: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_3: std_logic; - signal rcount_w6: std_logic; - signal rcount_w7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal rcount_w8: std_logic; - signal rcount_w9: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; - signal co4_3: std_logic; - signal rcount_w10: std_logic; - signal rcount_w11: std_logic; - signal wcount_10: std_logic; - signal wcount_11: std_logic; - signal co5_3: std_logic; - signal rcount_w12: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal wcount_12: std_logic; - signal wcount_13: std_logic; - signal co6_3: std_logic; - signal rcount_w14: std_logic; - signal rcount_w15: std_logic; - signal wcount_14: std_logic; - signal wcount_15: std_logic; - signal co7_3: std_logic; - signal full_cmp_clr: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component MUX41 - port (D0: in std_logic; D1: in std_logic; D2: in std_logic; - D3: in std_logic; SD1: in std_logic; SD2: in std_logic; - Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1 - -- synopsys translate_off - generic (initval : in String); - -- synopsys translate_on - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KB - -- synopsys translate_off - generic (GSR : in String; WRITEMODE_B : in String; - CSDECODE_B : in std_logic_vector(2 downto 0); - CSDECODE_A : in std_logic_vector(2 downto 0); - WRITEMODE_A : in String; RESETMODE : in String; - REGMODE_B : in String; REGMODE_A : in String; - DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); - -- synopsys translate_on - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; - CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; - CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute initval : string; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute CSDECODE_B : string; - attribute CSDECODE_A : string; - attribute WRITEMODE_B : string; - attribute WRITEMODE_A : string; - attribute RESETMODE : string; - attribute REGMODE_B : string; - attribute REGMODE_A : string; - attribute DATA_WIDTH_B : string; - attribute DATA_WIDTH_A : string; - attribute GSR : string; - attribute initval of LUT4_59 : label is "0x6996"; - attribute initval of LUT4_58 : label is "0x6996"; - attribute initval of LUT4_57 : label is "0x6996"; - attribute initval of LUT4_56 : label is "0x6996"; - attribute initval of LUT4_55 : label is "0x6996"; - attribute initval of LUT4_54 : label is "0x6996"; - attribute initval of LUT4_53 : label is "0x6996"; - attribute initval of LUT4_52 : label is "0x6996"; - attribute initval of LUT4_51 : label is "0x6996"; - attribute initval of LUT4_50 : label is "0x6996"; - attribute initval of LUT4_49 : label is "0x6996"; - attribute initval of LUT4_48 : label is "0x6996"; - attribute initval of LUT4_47 : label is "0x6996"; - attribute initval of LUT4_46 : label is "0x6996"; - attribute initval of LUT4_45 : label is "0x6996"; - attribute initval of LUT4_44 : label is "0x6996"; - attribute initval of LUT4_43 : label is "0x6996"; - attribute initval of LUT4_42 : label is "0x6996"; - attribute initval of LUT4_41 : label is "0x6996"; - attribute initval of LUT4_40 : label is "0x6996"; - attribute initval of LUT4_39 : label is "0x6996"; - attribute initval of LUT4_38 : label is "0x6996"; - attribute initval of LUT4_37 : label is "0x6996"; - attribute initval of LUT4_36 : label is "0x6996"; - attribute initval of LUT4_35 : label is "0x6996"; - attribute initval of LUT4_34 : label is "0x6996"; - attribute initval of LUT4_33 : label is "0x6996"; - attribute initval of LUT4_32 : label is "0x6996"; - attribute initval of LUT4_31 : label is "0x6996"; - attribute initval of LUT4_30 : label is "0x6996"; - attribute initval of LUT4_29 : label is "0x6996"; - attribute initval of LUT4_28 : label is "0x6996"; - attribute initval of LUT4_27 : label is "0x6996"; - attribute initval of LUT4_26 : label is "0x6996"; - attribute initval of LUT4_25 : label is "0x6996"; - attribute initval of LUT4_24 : label is "0x6996"; - attribute initval of LUT4_23 : label is "0x6996"; - attribute initval of LUT4_22 : label is "0x6996"; - attribute initval of LUT4_21 : label is "0x6996"; - attribute initval of LUT4_20 : label is "0x6996"; - attribute initval of LUT4_19 : label is "0x6996"; - attribute initval of LUT4_18 : label is "0x6996"; - attribute initval of LUT4_17 : label is "0x6996"; - attribute initval of LUT4_16 : label is "0x6996"; - attribute initval of LUT4_15 : label is "0x6996"; - attribute initval of LUT4_14 : label is "0x6996"; - attribute initval of LUT4_13 : label is "0x6996"; - attribute initval of LUT4_12 : label is "0x6996"; - attribute initval of LUT4_11 : label is "0x6996"; - attribute initval of LUT4_10 : label is "0x6996"; - attribute initval of LUT4_9 : label is "0x6996"; - attribute initval of LUT4_8 : label is "0x6996"; - attribute initval of LUT4_7 : label is "0x6996"; - attribute initval of LUT4_6 : label is "0x6996"; - attribute initval of LUT4_5 : label is "0x6996"; - attribute initval of LUT4_4 : label is "0x6996"; - attribute initval of LUT4_3 : label is "0x0410"; - attribute initval of LUT4_2 : label is "0x1004"; - attribute initval of LUT4_1 : label is "0x0140"; - attribute initval of LUT4_0 : label is "0x4001"; - attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_64kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; - attribute CSDECODE_B of pdp_ram_0_0_31 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_0_31 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_0_31 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_0_31 : label is "NORMAL"; - attribute GSR of pdp_ram_0_0_31 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_0_31 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_0_31 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_0_31 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_0_31 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_0_31 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_1_30 : label is "fifo_64kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_1_30 : label is ""; - attribute CSDECODE_B of pdp_ram_0_1_30 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_1_30 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_1_30 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_1_30 : label is "NORMAL"; - attribute GSR of pdp_ram_0_1_30 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_1_30 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_1_30 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_1_30 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_1_30 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_1_30 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_0_2_29 : label is "fifo_64kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_2_29 : label is ""; - attribute CSDECODE_B of pdp_ram_0_2_29 : label is "0b000"; - attribute CSDECODE_A of pdp_ram_0_2_29 : label is "0b000"; - attribute WRITEMODE_B of pdp_ram_0_2_29 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_2_29 : label is "NORMAL"; - attribute GSR of pdp_ram_0_2_29 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_2_29 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_2_29 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_2_29 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_2_29 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_0_2_29 : label is "1"; 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- attribute DATA_WIDTH_B of pdp_ram_2_6_9 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_2_6_9 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_2_7_8 : label is "fifo_64kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_2_7_8 : label is ""; - attribute CSDECODE_B of pdp_ram_2_7_8 : label is "0b010"; - attribute CSDECODE_A of pdp_ram_2_7_8 : label is "0b010"; - attribute WRITEMODE_B of pdp_ram_2_7_8 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_2_7_8 : label is "NORMAL"; - attribute GSR of pdp_ram_2_7_8 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_2_7_8 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_2_7_8 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_2_7_8 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_2_7_8 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_2_7_8 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_3_0_7 : label is "fifo_64kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_0_7 : label is ""; - attribute CSDECODE_B of pdp_ram_3_0_7 : label is "0b011"; - attribute CSDECODE_A of pdp_ram_3_0_7 : label is "0b011"; - attribute WRITEMODE_B of pdp_ram_3_0_7 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_3_0_7 : label is "NORMAL"; - attribute GSR of pdp_ram_3_0_7 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_3_0_7 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_3_0_7 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_3_0_7 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_3_0_7 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_3_0_7 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_3_1_6 : label is "fifo_64kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_1_6 : label is ""; - attribute CSDECODE_B of pdp_ram_3_1_6 : label is "0b011"; - attribute CSDECODE_A of pdp_ram_3_1_6 : label is "0b011"; - attribute WRITEMODE_B of pdp_ram_3_1_6 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_3_1_6 : label is "NORMAL"; - attribute GSR of pdp_ram_3_1_6 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_3_1_6 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_3_1_6 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_3_1_6 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_3_1_6 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_3_1_6 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_3_2_5 : label is "fifo_64kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_2_5 : label is ""; - attribute CSDECODE_B of pdp_ram_3_2_5 : label is "0b011"; - attribute CSDECODE_A of pdp_ram_3_2_5 : label is "0b011"; - attribute WRITEMODE_B of pdp_ram_3_2_5 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_3_2_5 : label is "NORMAL"; - attribute GSR of pdp_ram_3_2_5 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_3_2_5 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_3_2_5 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_3_2_5 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_3_2_5 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_3_2_5 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_3_3_4 : label is "fifo_64kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_3_4 : label is ""; - attribute CSDECODE_B of pdp_ram_3_3_4 : label is "0b011"; - attribute CSDECODE_A of pdp_ram_3_3_4 : label is "0b011"; - attribute WRITEMODE_B of pdp_ram_3_3_4 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_3_3_4 : label is "NORMAL"; - attribute GSR of pdp_ram_3_3_4 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_3_3_4 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_3_3_4 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_3_3_4 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_3_3_4 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_3_3_4 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_3_4_3 : label is "fifo_64kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_4_3 : label is ""; - attribute CSDECODE_B of pdp_ram_3_4_3 : label is "0b011"; - attribute CSDECODE_A of pdp_ram_3_4_3 : label is "0b011"; - attribute WRITEMODE_B of pdp_ram_3_4_3 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_3_4_3 : label is "NORMAL"; - attribute GSR of pdp_ram_3_4_3 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_3_4_3 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_3_4_3 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_3_4_3 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_3_4_3 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_3_4_3 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_3_5_2 : label is "fifo_64kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_5_2 : label is ""; - attribute CSDECODE_B of pdp_ram_3_5_2 : label is "0b011"; - attribute CSDECODE_A of pdp_ram_3_5_2 : label is "0b011"; - attribute WRITEMODE_B of pdp_ram_3_5_2 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_3_5_2 : label is "NORMAL"; - attribute GSR of pdp_ram_3_5_2 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_3_5_2 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_3_5_2 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_3_5_2 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_3_5_2 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_3_5_2 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_3_6_1 : label is "fifo_64kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_6_1 : label is ""; - attribute CSDECODE_B of pdp_ram_3_6_1 : label is "0b011"; - attribute CSDECODE_A of pdp_ram_3_6_1 : label is "0b011"; - attribute WRITEMODE_B of pdp_ram_3_6_1 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_3_6_1 : label is "NORMAL"; - attribute GSR of pdp_ram_3_6_1 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_3_6_1 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_3_6_1 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_3_6_1 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_3_6_1 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_3_6_1 : label is "1"; - attribute MEM_LPC_FILE of pdp_ram_3_7_0 : label is "fifo_64kx8.lpc"; - attribute MEM_INIT_FILE of pdp_ram_3_7_0 : label is ""; - attribute CSDECODE_B of pdp_ram_3_7_0 : label is "0b011"; - attribute CSDECODE_A of pdp_ram_3_7_0 : label is "0b011"; - attribute WRITEMODE_B of pdp_ram_3_7_0 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_3_7_0 : label is "NORMAL"; - attribute GSR of pdp_ram_3_7_0 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_3_7_0 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_3_7_0 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_3_7_0 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_3_7_0 : label is "1"; - attribute DATA_WIDTH_A of pdp_ram_3_7_0 : label is "1"; - attribute GSR of FF_173 : label is "ENABLED"; - attribute GSR of FF_172 : label is "ENABLED"; - attribute GSR of FF_171 : label is "ENABLED"; - attribute GSR of FF_170 : label is "ENABLED"; - attribute GSR of FF_169 : label is "ENABLED"; - attribute GSR of FF_168 : label is "ENABLED"; - attribute GSR of FF_167 : label is "ENABLED"; - attribute GSR of FF_166 : label is "ENABLED"; - attribute GSR of FF_165 : label is "ENABLED"; - attribute GSR of FF_164 : label is "ENABLED"; - attribute GSR of FF_163 : label is "ENABLED"; - attribute GSR of FF_162 : label is "ENABLED"; - attribute GSR of FF_161 : label is "ENABLED"; - attribute GSR of FF_160 : label is "ENABLED"; - attribute GSR of FF_159 : label is "ENABLED"; - attribute GSR of FF_158 : label is "ENABLED"; - attribute GSR of FF_157 : label is "ENABLED"; - attribute GSR of FF_156 : label is "ENABLED"; - attribute GSR of FF_155 : label is "ENABLED"; - attribute GSR of FF_154 : label is "ENABLED"; - attribute GSR of FF_153 : label is "ENABLED"; - attribute GSR of FF_152 : label is "ENABLED"; - attribute GSR of FF_151 : label is "ENABLED"; - attribute GSR of FF_150 : label is "ENABLED"; - attribute GSR of FF_149 : label is "ENABLED"; - attribute GSR of FF_148 : label is "ENABLED"; - attribute GSR of FF_147 : label is "ENABLED"; - attribute GSR of FF_146 : label is "ENABLED"; - attribute GSR of FF_145 : label is "ENABLED"; - attribute GSR of FF_144 : label is "ENABLED"; - attribute GSR of FF_143 : label is "ENABLED"; - attribute GSR of FF_142 : label is "ENABLED"; - attribute GSR of FF_141 : label is "ENABLED"; - attribute GSR of FF_140 : label is "ENABLED"; - attribute GSR of FF_139 : label is "ENABLED"; - attribute GSR of FF_138 : label is "ENABLED"; - attribute GSR of FF_137 : label is "ENABLED"; - attribute GSR of FF_136 : label is "ENABLED"; - attribute GSR of FF_135 : label is "ENABLED"; - attribute GSR of FF_134 : label is "ENABLED"; - attribute GSR of FF_133 : label is "ENABLED"; - attribute GSR of FF_132 : label is "ENABLED"; - attribute GSR of FF_131 : label is "ENABLED"; - attribute GSR of FF_130 : label is "ENABLED"; - attribute GSR of FF_129 : label is "ENABLED"; - attribute GSR of FF_128 : label is "ENABLED"; - attribute GSR of FF_127 : label is "ENABLED"; - attribute GSR of FF_126 : label is "ENABLED"; - attribute GSR of FF_125 : label is "ENABLED"; - attribute GSR of FF_124 : label is "ENABLED"; - attribute GSR of FF_123 : label is "ENABLED"; - attribute GSR of FF_122 : label is "ENABLED"; - attribute GSR of FF_121 : label is "ENABLED"; - attribute GSR of FF_120 : label is "ENABLED"; - attribute GSR of FF_119 : label is "ENABLED"; - attribute GSR of FF_118 : label is "ENABLED"; - attribute GSR of FF_117 : label is "ENABLED"; - attribute GSR of FF_116 : label is "ENABLED"; - attribute GSR of FF_115 : label is "ENABLED"; - attribute GSR of FF_114 : label is "ENABLED"; - attribute GSR of FF_113 : label is "ENABLED"; - attribute GSR of FF_112 : label is "ENABLED"; - attribute GSR of FF_111 : label is "ENABLED"; - attribute GSR of FF_110 : label is "ENABLED"; - attribute GSR of FF_109 : label is "ENABLED"; - attribute GSR of FF_108 : label is "ENABLED"; - attribute GSR of FF_107 : label is "ENABLED"; - attribute GSR of FF_106 : label is "ENABLED"; - attribute GSR of FF_105 : label is "ENABLED"; - attribute GSR of FF_104 : label is "ENABLED"; - attribute GSR of FF_103 : label is "ENABLED"; - attribute GSR of FF_102 : label is "ENABLED"; - attribute GSR of FF_101 : label is "ENABLED"; - attribute GSR of FF_100 : label is "ENABLED"; - attribute GSR of FF_99 : label is "ENABLED"; - attribute GSR of FF_98 : label is "ENABLED"; - attribute GSR of FF_97 : label is "ENABLED"; - attribute GSR of FF_96 : label is "ENABLED"; - attribute GSR of FF_95 : label is "ENABLED"; - attribute GSR of FF_94 : label is "ENABLED"; - attribute GSR of FF_93 : label is "ENABLED"; - attribute GSR of FF_92 : label is "ENABLED"; - attribute GSR of FF_91 : label is "ENABLED"; - attribute GSR of FF_90 : label is "ENABLED"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t34: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_1: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t33: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_0: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t32: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t31: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t30: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t29: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t28: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t27: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t26: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t25: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t24: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t23: XOR2 - port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); - - XOR2_t22: XOR2 - port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); - - XOR2_t21: XOR2 - port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); - - XOR2_t20: XOR2 - port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); - - XOR2_t19: XOR2 - port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); - - XOR2_t18: XOR2 - port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); - - XOR2_t17: XOR2 - port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); - - XOR2_t16: XOR2 - port map (A=>wcount_15, B=>wcount_16, Z=>w_gdata_15); - - XOR2_t15: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t14: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t13: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t12: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t11: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t10: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - XOR2_t9: XOR2 - port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); - - XOR2_t8: XOR2 - port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); - - XOR2_t7: XOR2 - port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); - - XOR2_t6: XOR2 - port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); - - XOR2_t5: XOR2 - port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); - - XOR2_t4: XOR2 - port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); - - XOR2_t3: XOR2 - port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); - - XOR2_t2: XOR2 - port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); - - XOR2_t1: XOR2 - port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); - - XOR2_t0: XOR2 - port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); - - LUT4_59: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, - AD1=>w_gcount_r215, AD0=>w_gcount_r216, - DO0=>w_g2b_xor_cluster_0); - - LUT4_58: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, - AD1=>w_gcount_r211, AD0=>w_gcount_r212, - DO0=>w_g2b_xor_cluster_1); - - LUT4_57: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_gcount_r28, - DO0=>w_g2b_xor_cluster_2); - - LUT4_56: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, - DO0=>w_g2b_xor_cluster_3); - - LUT4_55: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r215, AD2=>w_gcount_r216, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r15); - - LUT4_54: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, - AD1=>w_gcount_r216, AD0=>scuba_vlo, DO0=>wcount_r14); - - LUT4_53: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, - AD1=>w_gcount_r214, AD0=>wcount_r15, DO0=>wcount_r12); - - LUT4_52: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, - AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); - - LUT4_51: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, - AD1=>w_gcount_r212, AD0=>w_g2b_xor_cluster_0, - DO0=>wcount_r10); - - LUT4_50: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r9); - - LUT4_49: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r8); - - LUT4_48: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r27, AD0=>w_gcount_r28, DO0=>wcount_r7); - - LUT4_47: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_2_1); - - LUT4_46: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r6); - - LUT4_45: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r5); - - LUT4_44: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r24, DO0=>wcount_r4); - - LUT4_43: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); - - LUT4_42: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, - DO0=>wcount_r3); - - LUT4_41: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>scuba_vlo, - DO0=>w_g2b_xor_cluster_3_2); - - LUT4_40: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, - DO0=>wcount_r2); - - LUT4_39: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, - DO0=>wcount_r1); - - LUT4_38: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, - AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>func_xor_inet); - - LUT4_37: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>func_xor_inet_1); - - LUT4_36: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, - AD1=>w_gcount_r210, AD0=>w_gcount_r211, DO0=>func_xor_inet_2); - - LUT4_35: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, - AD1=>w_gcount_r214, AD0=>w_gcount_r215, DO0=>func_xor_inet_3); - - LUT4_34: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>w_gcount_r216, AD2=>scuba_vlo, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>func_xor_inet_4); - - LUT4_33: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, - AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, - DO0=>func_xor_inet_5); - - LUT4_32: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r0); - - LUT4_31: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, - AD1=>r_gcount_w215, AD0=>r_gcount_w216, - DO0=>r_g2b_xor_cluster_0); - - LUT4_30: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, - AD1=>r_gcount_w211, AD0=>r_gcount_w212, - DO0=>r_g2b_xor_cluster_1); - - LUT4_29: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, - DO0=>r_g2b_xor_cluster_2); - - LUT4_28: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>r_gcount_w24, - DO0=>r_g2b_xor_cluster_3); - - LUT4_27: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w15); - - LUT4_26: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, - AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); - - LUT4_25: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); - - LUT4_24: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, - AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); - - LUT4_23: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, - AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, - DO0=>rcount_w10); - - LUT4_22: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); - - LUT4_21: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); - - LUT4_20: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); - - LUT4_19: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, - AD1=>r_gcount_w28, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_2_1); - - LUT4_18: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); - - LUT4_17: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); - - LUT4_16: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); - - LUT4_15: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); - - LUT4_14: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, - DO0=>rcount_w3); - - LUT4_13: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>scuba_vlo, - DO0=>r_g2b_xor_cluster_3_2); - - LUT4_12: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, - DO0=>rcount_w2); - - LUT4_11: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, - AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, - DO0=>rcount_w1); - - LUT4_10: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet_6); - - LUT4_9: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_7); - - LUT4_8: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, - AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_8); - - LUT4_7: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, - AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_9); - - LUT4_6: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>func_xor_inet_10); - - LUT4_5: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>func_xor_inet_6, AD2=>func_xor_inet_7, - AD1=>func_xor_inet_8, AD0=>func_xor_inet_9, - DO0=>func_xor_inet_11); - - LUT4_4: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on - port map (AD3=>func_xor_inet_11, AD2=>func_xor_inet_10, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); - - LUT4_3: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0410") - -- synopsys translate_on - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x1004") - -- synopsys translate_on - port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0140") - -- synopsys translate_on - port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4001") - -- synopsys translate_on - port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - pdp_ram_0_0_31: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_0, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_1_30: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_1, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_2_29: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_2, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_3_28: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_3, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_4_27: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_4, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_5_26: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_5, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_6_25: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_6, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_0_7_24: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_0_7, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_0_23: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_0, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_1_22: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_1, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_2_21: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_2, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_3_20: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_3, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_4_19: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_4, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_5_18: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_5, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_6_17: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_6, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_1_7_16: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_1_7, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_0_15: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_0, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_1_14: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_1, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_2_13: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_2, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_3_12: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_3, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_4_11: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_4, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_5_10: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_5, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_6_9: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_6, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_2_7_8: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_2_7, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_0_7: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_0, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_1_6: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_1, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_2_5: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_2, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_3_4: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_3, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_4_3: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_4, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_5_2: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_5, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_6_1: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_6, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - pdp_ram_3_7_0: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, - DATA_WIDTH_A=> 1) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, - ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, - ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, - ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, - WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, - CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, - DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, - ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, - ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, - ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, - ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, - CSB0=>rptr_14, CSB1=>rptr_15, CSB2=>scuba_vlo, RSTB=>Reset, - DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, - DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>mdout1_3_7, DOB1=>open, DOB2=>open, DOB3=>open, - DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, - DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, - DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); - - FF_173: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_172: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_171: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_170: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_169: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_168: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_167: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_166: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_165: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_164: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_9); - - FF_163: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_10); - - FF_162: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_11); - - FF_161: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_12); - - FF_160: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_13); - - FF_159: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_14); - - FF_158: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_15); - - FF_157: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>iwcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_16); - - FF_156: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_155: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_154: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_153: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_152: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_151: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_150: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_149: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_148: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_147: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_9); - - FF_146: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_10); - - FF_145: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_11); - - FF_144: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_12); - - FF_143: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_13); - - FF_142: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_14); - - FF_141: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gdata_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_15); - - FF_140: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_16); - - FF_139: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_138: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_137: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_136: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_135: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_134: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_133: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_132: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_131: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_130: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_9); - - FF_129: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_10); - - FF_128: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_11); - - FF_127: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_12); - - FF_126: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_13); - - FF_125: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_14); - - FF_124: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_15); - - FF_123: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_16); - - FF_122: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_121: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_120: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_119: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_118: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_117: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_116: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_115: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_7); - - FF_114: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_8); - - FF_113: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_9); - - FF_112: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_10); - - FF_111: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_11); - - FF_110: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_12); - - FF_109: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_13); - - FF_108: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_14); - - FF_107: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_15); - - FF_106: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_16); - - FF_105: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_104: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_103: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_102: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_101: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_100: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_99: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_98: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_7); - - FF_97: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_8); - - FF_96: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_9); - - FF_95: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_10); - - FF_94: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_11); - - FF_93: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_12); - - FF_92: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_13); - - FF_91: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_14); - - FF_90: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_15); - - FF_89: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_16); - - FF_88: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_87: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_86: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_85: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_84: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_83: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_82: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_81: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_7); - - FF_80: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_8); - - FF_79: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_9); - - FF_78: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_10); - - FF_77: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_11); - - FF_76: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_12); - - FF_75: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_13); - - FF_74: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_14); - - FF_73: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_15); - - FF_72: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_16); - - FF_71: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_14_ff); - - FF_70: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, - Q=>rptr_15_ff); - - FF_69: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_68: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_67: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_66: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_65: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_64: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_63: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_62: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_61: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_60: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); - - FF_59: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r10); - - FF_58: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r11); - - FF_57: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r12); - - FF_56: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r13); - - FF_55: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r14); - - FF_54: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r15); - - FF_53: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_16, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r16); - - FF_52: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_51: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_50: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_49: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_48: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_47: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_46: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_45: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); - - FF_44: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); - - FF_43: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); - - FF_42: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); - - FF_41: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); - - FF_40: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); - - FF_39: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); - - FF_38: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); - - FF_37: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); - - FF_36: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); - - FF_35: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_34: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_33: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_32: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_31: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_30: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_29: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_28: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_27: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_26: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r29); - - FF_25: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r210); - - FF_24: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r211); - - FF_23: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r212); - - FF_22: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r213); - - FF_21: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r214); - - FF_20: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r215); - - FF_19: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>w_gcount_r16, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r216); - - FF_18: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_17: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_16: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_15: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_14: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_13: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_12: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_11: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); - - FF_10: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); - - FF_9: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); - - FF_8: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w210); - - FF_7: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w211); - - FF_6: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w212); - - FF_5: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w213); - - FF_4: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w214); - - FF_3: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w215); - - FF_2: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, - Q=>r_gcount_w216); - - FF_1: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_0: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, - NC0=>iwcount_8, NC1=>iwcount_9); - - w_gctr_5: CU2 - port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, - NC0=>iwcount_10, NC1=>iwcount_11); - - w_gctr_6: CU2 - port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, - NC0=>iwcount_12, NC1=>iwcount_13); - - w_gctr_7: CU2 - port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, - NC0=>iwcount_14, NC1=>iwcount_15); - - w_gctr_8: CU2 - port map (CI=>co7, PC0=>wcount_16, PC1=>scuba_vlo, CO=>co8, - NC0=>iwcount_16, NC1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, - NC0=>ircount_6, NC1=>ircount_7); - - r_gctr_4: CU2 - port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, - NC0=>ircount_8, NC1=>ircount_9); - - r_gctr_5: CU2 - port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, - NC0=>ircount_10, NC1=>ircount_11); - - r_gctr_6: CU2 - port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, - NC0=>ircount_12, NC1=>ircount_13); - - r_gctr_7: CU2 - port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, - NC0=>ircount_14, NC1=>ircount_15); - - r_gctr_8: CU2 - port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8_1, - NC0=>ircount_16, NC1=>open); - - mux_7: MUX41 - port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, - D3=>mdout1_3_0, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(0)); - - mux_6: MUX41 - port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, - D3=>mdout1_3_1, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(1)); - - mux_5: MUX41 - port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, - D3=>mdout1_3_2, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(2)); - - mux_4: MUX41 - port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, - D3=>mdout1_3_3, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(3)); - - mux_3: MUX41 - port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, - D3=>mdout1_3_4, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(4)); - - mux_2: MUX41 - port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, - D3=>mdout1_3_5, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(5)); - - mux_1: MUX41 - port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, - D3=>mdout1_3_6, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(6)); - - mux_0: MUX41 - port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, - D3=>mdout1_3_7, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(7)); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, - B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, - B1=>wcount_r3, CI=>co0_2, GE=>co1_2); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, - B1=>wcount_r5, CI=>co1_2, GE=>co2_2); - - empty_cmp_3: AGEB2 - port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, - B1=>wcount_r7, CI=>co2_2, GE=>co3_2); - - empty_cmp_4: AGEB2 - port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, - B1=>wcount_r9, CI=>co3_2, GE=>co4_2); - - empty_cmp_5: AGEB2 - port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, - B1=>wcount_r11, CI=>co4_2, GE=>co5_2); - - empty_cmp_6: AGEB2 - port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12, - B1=>w_g2b_xor_cluster_0, CI=>co5_2, GE=>co6_2); - - empty_cmp_7: AGEB2 - port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r14, - B1=>wcount_r15, CI=>co6_2, GE=>co7_2); - - empty_cmp_8: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co7_2, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, - B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, - B1=>rcount_w3, CI=>co0_3, GE=>co1_3); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, - B1=>rcount_w5, CI=>co1_3, GE=>co2_3); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, - B1=>rcount_w7, CI=>co2_3, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, - B1=>rcount_w9, CI=>co3_3, GE=>co4_3); - - full_cmp_5: AGEB2 - port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, - B1=>rcount_w11, CI=>co4_3, GE=>co5_3); - - full_cmp_6: AGEB2 - port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12, - B1=>r_g2b_xor_cluster_0, CI=>co5_3, GE=>co6_3); - - full_cmp_7: AGEB2 - port map (A0=>wcount_14, A1=>wcount_15, B0=>rcount_w14, - B1=>rcount_w15, CI=>co6_3, GE=>co7_3); - - full_cmp_8: AGEB2 - port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, - B1=>scuba_vlo, CI=>co7_3, GE=>full_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp2m; -configuration Structure_CON of fifo_64kx8 is - for Structure - for all:AGEB2 use entity ecp2m.AGEB2(V); end for; - for all:AND2 use entity ecp2m.AND2(V); end for; - for all:CU2 use entity ecp2m.CU2(V); end for; - for all:FADD2B use entity ecp2m.FADD2B(V); end for; - for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; - for all:INV use entity ecp2m.INV(V); end for; - for all:MUX41 use entity ecp2m.MUX41(V); end for; - for all:OR2 use entity ecp2m.OR2(V); end for; - for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:XOR2 use entity ecp2m.XOR2(V); end for; - for all:DP16KB use entity ecp2m.DP16KB(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.4 +--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 65536 -width 8 -depth 65536 -rdata_width 8 -no_enable -pe -1 -pf -1 -e + +-- Thu Sep 22 11:23:03 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_64kx8 is + port ( + Data: in std_logic_vector(7 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(7 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_64kx8; + +architecture Structure of fifo_64kx8 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_3_1: std_logic; + signal w_g2b_xor_cluster_3_2: std_logic; + signal w_g2b_xor_cluster_3: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal func_xor_inet_3: std_logic; + signal func_xor_inet_2: std_logic; + signal func_xor_inet_1: std_logic; + signal func_xor_inet: std_logic; + signal func_xor_inet_4: std_logic; + signal func_xor_inet_5: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_3_1: std_logic; + signal r_g2b_xor_cluster_3_2: std_logic; + signal r_g2b_xor_cluster_3: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal func_xor_inet_9: std_logic; + signal func_xor_inet_8: std_logic; + signal func_xor_inet_7: std_logic; + signal func_xor_inet_6: std_logic; + signal func_xor_inet_10: std_logic; + signal func_xor_inet_11: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal w_gdata_11: std_logic; + signal w_gdata_12: std_logic; + signal w_gdata_13: std_logic; + signal w_gdata_14: std_logic; + signal w_gdata_15: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal wptr_12: std_logic; + signal wptr_13: std_logic; + signal wptr_14: std_logic; + signal wptr_15: std_logic; + signal wptr_16: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal r_gdata_12: std_logic; + signal r_gdata_13: std_logic; + signal r_gdata_14: std_logic; + signal r_gdata_15: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_11: std_logic; + signal rptr_12: std_logic; + signal rptr_13: std_logic; + signal rptr_16: std_logic; + signal rptr_14: std_logic; + signal rptr_15: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal w_gcount_12: std_logic; + signal w_gcount_13: std_logic; + signal w_gcount_14: std_logic; + signal w_gcount_15: std_logic; + signal w_gcount_16: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal r_gcount_13: std_logic; + signal r_gcount_14: std_logic; + signal r_gcount_15: std_logic; + signal r_gcount_16: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal w_gcount_r212: std_logic; + signal w_gcount_r12: std_logic; + signal w_gcount_r213: std_logic; + signal w_gcount_r13: std_logic; + signal w_gcount_r214: std_logic; + signal w_gcount_r14: std_logic; + signal w_gcount_r215: std_logic; + signal w_gcount_r15: std_logic; + signal w_gcount_r216: std_logic; + signal w_gcount_r16: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal r_gcount_w213: std_logic; + signal r_gcount_w13: std_logic; + signal r_gcount_w214: std_logic; + signal r_gcount_w14: std_logic; + signal r_gcount_w215: std_logic; + signal r_gcount_w15: std_logic; + signal r_gcount_w216: std_logic; + signal r_gcount_w16: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4: std_logic; + signal iwcount_12: std_logic; + signal iwcount_13: std_logic; + signal co5: std_logic; + signal iwcount_14: std_logic; + signal iwcount_15: std_logic; + signal co6: std_logic; + signal iwcount_16: std_logic; + signal co8: std_logic; + signal wcount_16: std_logic; + signal co7: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal ircount_13: std_logic; + signal co5_1: std_logic; + signal ircount_14: std_logic; + signal ircount_15: std_logic; + signal co6_1: std_logic; + signal ircount_16: std_logic; + signal co8_1: std_logic; + signal rcount_16: std_logic; + signal co7_1: std_logic; + signal mdout1_3_0: std_logic; + signal mdout1_2_0: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_3_1: std_logic; + signal mdout1_2_1: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_3_2: std_logic; + signal mdout1_2_2: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_3_3: std_logic; + signal mdout1_2_3: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_3_4: std_logic; + signal mdout1_2_4: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_3_5: std_logic; + signal mdout1_2_5: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_3_6: std_logic; + signal mdout1_2_6: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal rptr_15_ff: std_logic; + signal rptr_14_ff: std_logic; + signal mdout1_3_7: std_logic; + signal mdout1_2_7: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r6: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal wcount_r8: std_logic; + signal wcount_r9: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal wcount_r10: std_logic; + signal wcount_r11: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_2: std_logic; + signal wcount_r12: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_12: std_logic; + signal rcount_13: std_logic; + signal co6_2: std_logic; + signal wcount_r14: std_logic; + signal wcount_r15: std_logic; + signal rcount_14: std_logic; + signal rcount_15: std_logic; + signal co7_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal rcount_w6: std_logic; + signal rcount_w7: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal rcount_w8: std_logic; + signal rcount_w9: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_3: std_logic; + signal rcount_w10: std_logic; + signal rcount_w11: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co5_3: std_logic; + signal rcount_w12: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal wcount_12: std_logic; + signal wcount_13: std_logic; + signal co6_3: std_logic; + signal rcount_w14: std_logic; + signal rcount_w15: std_logic; + signal wcount_14: std_logic; + signal wcount_15: std_logic; + signal co7_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX41 + port (D0: in std_logic; D1: in std_logic; D2: in std_logic; + D3: in std_logic; SD1: in std_logic; SD2: in std_logic; + Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; + attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_1_30 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_30 : label is ""; + attribute RESETMODE of pdp_ram_0_1_30 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_2_29 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_2_29 : label is ""; + attribute RESETMODE of pdp_ram_0_2_29 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_3_28 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_3_28 : label is ""; + attribute RESETMODE of pdp_ram_0_3_28 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_4_27 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_4_27 : label is ""; + attribute RESETMODE of pdp_ram_0_4_27 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_5_26 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_5_26 : label is ""; + attribute RESETMODE of pdp_ram_0_5_26 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_6_25 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_6_25 : label is ""; + attribute RESETMODE of pdp_ram_0_6_25 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_7_24 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_7_24 : label is ""; + attribute RESETMODE of pdp_ram_0_7_24 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_0_23 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_23 : label is ""; + attribute RESETMODE of pdp_ram_1_0_23 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_1_22 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_1_22 : label is ""; + attribute RESETMODE of pdp_ram_1_1_22 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_2_21 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_2_21 : label is ""; + attribute RESETMODE of pdp_ram_1_2_21 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_3_20 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_3_20 : label is ""; + attribute RESETMODE of pdp_ram_1_3_20 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_4_19 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_4_19 : label is ""; + attribute RESETMODE of pdp_ram_1_4_19 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_5_18 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_5_18 : label is ""; + attribute RESETMODE of pdp_ram_1_5_18 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_6_17 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_6_17 : label is ""; + attribute RESETMODE of pdp_ram_1_6_17 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_7_16 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_7_16 : label is ""; + attribute RESETMODE of pdp_ram_1_7_16 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_0_15 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_0_15 : label is ""; + attribute RESETMODE of pdp_ram_2_0_15 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_1_14 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_1_14 : label is ""; + attribute RESETMODE of pdp_ram_2_1_14 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_2_13 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_2_13 : label is ""; + attribute RESETMODE of pdp_ram_2_2_13 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_3_12 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_3_12 : label is ""; + attribute RESETMODE of pdp_ram_2_3_12 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_4_11 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_4_11 : label is ""; + attribute RESETMODE of pdp_ram_2_4_11 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_5_10 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_5_10 : label is ""; + attribute RESETMODE of pdp_ram_2_5_10 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_6_9 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_6_9 : label is ""; + attribute RESETMODE of pdp_ram_2_6_9 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_7_8 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_7_8 : label is ""; + attribute RESETMODE of pdp_ram_2_7_8 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_0_7 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_0_7 : label is ""; + attribute RESETMODE of pdp_ram_3_0_7 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_1_6 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_1_6 : label is ""; + attribute RESETMODE of pdp_ram_3_1_6 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_2_5 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_2_5 : label is ""; + attribute RESETMODE of pdp_ram_3_2_5 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_3_4 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_3_4 : label is ""; + attribute RESETMODE of pdp_ram_3_3_4 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_4_3 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_4_3 : label is ""; + attribute RESETMODE of pdp_ram_3_4_3 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_5_2 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_5_2 : label is ""; + attribute RESETMODE of pdp_ram_3_5_2 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_6_1 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_6_1 : label is ""; + attribute RESETMODE of pdp_ram_3_6_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_7_0 : label is "fifo_64kx8.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_7_0 : label is ""; + attribute RESETMODE of pdp_ram_3_7_0 : label is "SYNC"; + attribute GSR of FF_173 : label is "ENABLED"; + attribute GSR of FF_172 : label is "ENABLED"; + attribute GSR of FF_171 : label is "ENABLED"; + attribute GSR of FF_170 : label is "ENABLED"; + attribute GSR of FF_169 : label is "ENABLED"; + attribute GSR of FF_168 : label is "ENABLED"; + attribute GSR of FF_167 : label is "ENABLED"; + attribute GSR of FF_166 : label is "ENABLED"; + attribute GSR of FF_165 : label is "ENABLED"; + attribute GSR of FF_164 : label is "ENABLED"; + attribute GSR of FF_163 : label is "ENABLED"; + attribute GSR of FF_162 : label is "ENABLED"; + attribute GSR of FF_161 : label is "ENABLED"; + attribute GSR of FF_160 : label is "ENABLED"; + attribute GSR of FF_159 : label is "ENABLED"; + attribute GSR of FF_158 : label is "ENABLED"; + attribute GSR of FF_157 : label is "ENABLED"; + attribute GSR of FF_156 : label is "ENABLED"; + attribute GSR of FF_155 : label is "ENABLED"; + attribute GSR of FF_154 : label is "ENABLED"; + attribute GSR of FF_153 : label is "ENABLED"; + attribute GSR of FF_152 : label is "ENABLED"; + attribute GSR of FF_151 : label is "ENABLED"; + attribute GSR of FF_150 : label is "ENABLED"; + attribute GSR of FF_149 : label is "ENABLED"; + attribute GSR of FF_148 : label is "ENABLED"; + attribute GSR of FF_147 : label is "ENABLED"; + attribute GSR of FF_146 : label is "ENABLED"; + attribute GSR of FF_145 : label is "ENABLED"; + attribute GSR of FF_144 : label is "ENABLED"; + attribute GSR of FF_143 : label is "ENABLED"; + attribute GSR of FF_142 : label is "ENABLED"; + attribute GSR of FF_141 : label is "ENABLED"; + attribute GSR of FF_140 : label is "ENABLED"; + attribute GSR of FF_139 : label is "ENABLED"; + attribute GSR of FF_138 : label is "ENABLED"; + attribute GSR of FF_137 : label is "ENABLED"; + attribute GSR of FF_136 : label is "ENABLED"; + attribute GSR of FF_135 : label is "ENABLED"; + attribute GSR of FF_134 : label is "ENABLED"; + attribute GSR of FF_133 : label is "ENABLED"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t34: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t33: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t32: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t31: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t30: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t29: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t28: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t27: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t26: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t25: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t24: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t23: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t22: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t21: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t20: XOR2 + port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); + + XOR2_t19: XOR2 + port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); + + XOR2_t18: XOR2 + port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); + + XOR2_t17: XOR2 + port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); + + XOR2_t16: XOR2 + port map (A=>wcount_15, B=>wcount_16, Z=>w_gdata_15); + + XOR2_t15: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t14: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t13: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t12: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t11: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t10: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t9: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t8: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t7: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t6: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t5: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t4: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + XOR2_t3: XOR2 + port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); + + XOR2_t2: XOR2 + port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); + + XOR2_t1: XOR2 + port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); + + XOR2_t0: XOR2 + port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); + + LUT4_59: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, + AD1=>w_gcount_r215, AD0=>w_gcount_r216, + DO0=>w_g2b_xor_cluster_0); + + LUT4_58: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>w_gcount_r212, + DO0=>w_g2b_xor_cluster_1); + + LUT4_57: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>w_gcount_r28, + DO0=>w_g2b_xor_cluster_2); + + LUT4_56: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, + DO0=>w_g2b_xor_cluster_3); + + LUT4_55: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r215, AD2=>w_gcount_r216, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r15); + + LUT4_54: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, + AD1=>w_gcount_r216, AD0=>scuba_vlo, DO0=>wcount_r14); + + LUT4_53: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, + AD1=>w_gcount_r214, AD0=>wcount_r15, DO0=>wcount_r12); + + LUT4_52: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, + AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); + + LUT4_51: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, + AD1=>w_gcount_r212, AD0=>w_g2b_xor_cluster_0, + DO0=>wcount_r10); + + LUT4_50: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r9); + + LUT4_49: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r8); + + LUT4_48: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r27, AD0=>w_gcount_r28, DO0=>wcount_r7); + + LUT4_47: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_46: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r6); + + LUT4_45: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_44: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r24, DO0=>wcount_r4); + + LUT4_43: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); + + LUT4_42: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, + DO0=>wcount_r3); + + LUT4_41: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_3_2); + + LUT4_40: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, + DO0=>wcount_r2); + + LUT4_39: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, + DO0=>wcount_r1); + + LUT4_38: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>func_xor_inet); + + LUT4_37: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>func_xor_inet_1); + + LUT4_36: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>w_gcount_r211, DO0=>func_xor_inet_2); + + LUT4_35: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, + AD1=>w_gcount_r214, AD0=>w_gcount_r215, DO0=>func_xor_inet_3); + + LUT4_34: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r216, AD2=>scuba_vlo, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>func_xor_inet_4); + + LUT4_33: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, + AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, + DO0=>func_xor_inet_5); + + LUT4_32: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_31: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, + AD1=>r_gcount_w215, AD0=>r_gcount_w216, + DO0=>r_g2b_xor_cluster_0); + + LUT4_30: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>r_gcount_w212, + DO0=>r_g2b_xor_cluster_1); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, + DO0=>r_g2b_xor_cluster_2); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_3); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w15); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, + AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, + AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, + DO0=>rcount_w10); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, + DO0=>rcount_w3); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_3_2); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, + DO0=>rcount_w2); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, + DO0=>rcount_w1); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet_6); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_7); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_8); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_9); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>func_xor_inet_10); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet_6, AD2=>func_xor_inet_7, + AD1=>func_xor_inet_8, AD0=>func_xor_inet_9, + DO0=>func_xor_inet_11); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet_11, AD2=>func_xor_inet_10, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_31: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_1_30: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_1, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_2_29: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_2, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_3_28: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_3, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_4_27: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_4, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_5_26: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_5, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_6_25: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_6, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_7_24: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_7, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_0_23: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_1_22: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_1, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_2_21: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_2, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_3_20: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_3, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_4_19: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_4, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_5_18: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_5, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_6_17: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_6, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_7_16: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_7, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_0_15: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_1_14: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_1, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_2_13: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_2, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_3_12: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_3, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_4_11: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_4, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_5_10: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_5, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_6_9: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_6, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_7_8: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_7, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_0_7: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_1_6: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_1, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_2_5: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_2, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_3_4: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_3, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_4_3: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_4, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_5_2: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_5, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_6_1: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_6, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_7_0: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1, + DATA_WIDTH_A=> 1) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7), + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3, + ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7, + ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11, + ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock, + OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>wptr_14, CSA1=>wptr_15, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>rptr_0, + ADB1=>rptr_1, ADB2=>rptr_2, ADB3=>rptr_3, ADB4=>rptr_4, + ADB5=>rptr_5, ADB6=>rptr_6, ADB7=>rptr_7, ADB8=>rptr_8, + ADB9=>rptr_9, ADB10=>rptr_10, ADB11=>rptr_11, ADB12=>rptr_12, + ADB13=>rptr_13, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_14, CSB1=>rptr_15, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_7, DOB1=>open, + DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, + DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + FF_173: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_172: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_171: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_170: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_169: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_168: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_167: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_166: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_165: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_164: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_163: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_162: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_161: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_12); + + FF_160: FD1P3DX + port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_13); + + FF_159: FD1P3DX + port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_14); + + FF_158: FD1P3DX + port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_15); + + FF_157: FD1P3DX + port map (D=>iwcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_16); + + FF_156: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_155: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_154: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_153: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_152: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_151: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_150: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_149: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_148: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_147: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_146: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_145: FD1P3DX + port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_144: FD1P3DX + port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_12); + + FF_143: FD1P3DX + port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_13); + + FF_142: FD1P3DX + port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_14); + + FF_141: FD1P3DX + port map (D=>w_gdata_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_15); + + FF_140: FD1P3DX + port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_16); + + FF_139: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_138: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_137: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_136: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_135: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_134: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_133: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_132: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_131: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_130: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_129: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_128: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_127: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_12); + + FF_126: FD1P3DX + port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_13); + + FF_125: FD1P3DX + port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_14); + + FF_124: FD1P3DX + port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_15); + + FF_123: FD1P3DX + port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_16); + + FF_122: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_121: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_120: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_119: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_118: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_117: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_116: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_115: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_114: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_113: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_112: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_111: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_110: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_109: FD1P3DX + port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_13); + + FF_108: FD1P3DX + port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_14); + + FF_107: FD1P3DX + port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_15); + + FF_106: FD1P3DX + port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_16); + + FF_105: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_104: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_103: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_102: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_101: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_100: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_99: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_98: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_97: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_96: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_95: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_94: FD1P3DX + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_93: FD1P3DX + port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_92: FD1P3DX + port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_13); + + FF_91: FD1P3DX + port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_14); + + FF_90: FD1P3DX + port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_15); + + FF_89: FD1P3DX + port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_16); + + FF_88: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_87: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_86: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_85: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_84: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_83: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_82: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_81: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_80: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_79: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_78: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_77: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_76: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_75: FD1P3DX + port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_13); + + FF_74: FD1P3DX + port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_14); + + FF_73: FD1P3DX + port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_15); + + FF_72: FD1P3DX + port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_16); + + FF_71: FD1P3DX + port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_14_ff); + + FF_70: FD1P3DX + port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_15_ff); + + FF_69: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_68: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_67: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_66: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_65: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_64: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_63: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_62: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_61: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_60: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_59: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_58: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_57: FD1S3DX + port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r12); + + FF_56: FD1S3DX + port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r13); + + FF_55: FD1S3DX + port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r14); + + FF_54: FD1S3DX + port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r15); + + FF_53: FD1S3DX + port map (D=>w_gcount_16, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r16); + + FF_52: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_51: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_50: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_49: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_48: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_47: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_46: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_45: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_44: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_43: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_42: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_41: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_40: FD1S3DX + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_39: FD1S3DX + port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); + + FF_38: FD1S3DX + port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); + + FF_37: FD1S3DX + port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); + + FF_36: FD1S3DX + port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); + + FF_35: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_34: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_33: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_32: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_31: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_30: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_29: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_28: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_27: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_26: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_25: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_24: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_23: FD1S3DX + port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r212); + + FF_22: FD1S3DX + port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r213); + + FF_21: FD1S3DX + port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r214); + + FF_20: FD1S3DX + port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r215); + + FF_19: FD1S3DX + port map (D=>w_gcount_r16, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r216); + + FF_18: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_17: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_16: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_15: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_14: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_13: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_12: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_11: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_10: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_9: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_8: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_7: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_6: FD1S3DX + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_5: FD1S3DX + port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w213); + + FF_4: FD1S3DX + port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w214); + + FF_3: FD1S3DX + port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w215); + + FF_2: FD1S3DX + port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w216); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_gctr_6: CU2 + port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, + NC0=>iwcount_12, NC1=>iwcount_13); + + w_gctr_7: CU2 + port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, + NC0=>iwcount_14, NC1=>iwcount_15); + + w_gctr_8: CU2 + port map (CI=>co7, PC0=>wcount_16, PC1=>scuba_vlo, CO=>co8, + NC0=>iwcount_16, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + r_gctr_6: CU2 + port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, + NC0=>ircount_12, NC1=>ircount_13); + + r_gctr_7: CU2 + port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, + NC0=>ircount_14, NC1=>ircount_15); + + r_gctr_8: CU2 + port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8_1, + NC0=>ircount_16, NC1=>open); + + mux_7: MUX41 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, + D3=>mdout1_3_0, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(0)); + + mux_6: MUX41 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, + D3=>mdout1_3_1, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(1)); + + mux_5: MUX41 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, + D3=>mdout1_3_2, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(2)); + + mux_4: MUX41 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, + D3=>mdout1_3_3, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(3)); + + mux_3: MUX41 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, + D3=>mdout1_3_4, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(4)); + + mux_2: MUX41 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, + D3=>mdout1_3_5, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(5)); + + mux_1: MUX41 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, + D3=>mdout1_3_6, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(6)); + + mux_0: MUX41 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, + D3=>mdout1_3_7, SD1=>rptr_14_ff, SD2=>rptr_15_ff, Z=>Q(7)); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, + B1=>wcount_r7, CI=>co2_2, GE=>co3_2); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, + B1=>wcount_r9, CI=>co3_2, GE=>co4_2); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, + B1=>wcount_r11, CI=>co4_2, GE=>co5_2); + + empty_cmp_6: AGEB2 + port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12, + B1=>w_g2b_xor_cluster_0, CI=>co5_2, GE=>co6_2); + + empty_cmp_7: AGEB2 + port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r14, + B1=>wcount_r15, CI=>co6_2, GE=>co7_2); + + empty_cmp_8: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co7_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_3, GE=>co3_3); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, + B1=>rcount_w9, CI=>co3_3, GE=>co4_3); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, + B1=>rcount_w11, CI=>co4_3, GE=>co5_3); + + full_cmp_6: AGEB2 + port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12, + B1=>r_g2b_xor_cluster_0, CI=>co5_3, GE=>co6_3); + + full_cmp_7: AGEB2 + port map (A0=>wcount_14, A1=>wcount_15, B0=>rcount_w14, + B1=>rcount_w15, CI=>co6_3, GE=>co7_3); + + full_cmp_8: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co7_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_64kx8 is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:MUX41 use entity ecp3.MUX41(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/fifo_64kx8_tmpl.vhd b/gbe_ecp2m/ipcores/fifo_64kx8_tmpl.vhd index c0c7959..9aba2ac 100755 --- a/gbe_ecp2m/ipcores/fifo_64kx8_tmpl.vhd +++ b/gbe_ecp2m/ipcores/fifo_64kx8_tmpl.vhd @@ -1,18 +1,18 @@ --- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) --- Module Version: 5.2 --- Sat Dec 26 00:12:05 2009 - --- parameterized module component declaration -component fifo_64kx8 - port (Data: in std_logic_vector(7 downto 0); WrClock: in std_logic; - RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; - Reset: in std_logic; RPReset: in std_logic; - Q: out std_logic_vector(7 downto 0); Empty: out std_logic; - Full: out std_logic); -end component; - --- parameterized module component instance -__ : fifo_64kx8 - port map (Data(7 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, Q(7 downto 0)=>__, Empty=>__, - Full=>__); +-- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.4 +-- Thu Sep 22 11:23:03 2011 + +-- parameterized module component declaration +component fifo_64kx8 + port (Data: in std_logic_vector(7 downto 0); WrClock: in std_logic; + RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; + Reset: in std_logic; RPReset: in std_logic; + Q: out std_logic_vector(7 downto 0); Empty: out std_logic; + Full: out std_logic); +end component; + +-- parameterized module component instance +__ : fifo_64kx8 + port map (Data(7 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, + RdEn=>__, Reset=>__, RPReset=>__, Q(7 downto 0)=>__, Empty=>__, + Full=>__); diff --git a/gbe_ecp2m/ipcores/fifo_64kx9.lpc b/gbe_ecp2m/ipcores/fifo_64kx9.lpc index 73fde4a..a9ca96b 100644 --- a/gbe_ecp2m/ipcores/fifo_64kx9.lpc +++ b/gbe_ecp2m/ipcores/fifo_64kx9.lpc @@ -1,9 +1,9 @@ [Device] -Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-5F900C -SpeedGrade=-5 -Package=FPBGA900 +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 OperatingCondition=COM Status=P @@ -14,10 +14,10 @@ CoreStatus=Demo CoreName=FIFO_DC CoreRevision=5.4 ModuleName=fifo_64kx9 -SourceFormat=Schematic/VHDL +SourceFormat=VHDL ParameterFileVersion=1.0 -Date=07/26/2010 -Time=21:40:04 +Date=09/22/2011 +Time=11:23:21 [Parameters] Verilog=0 diff --git a/gbe_ecp2m/ipcores/fifo_64kx9.srp b/gbe_ecp2m/ipcores/fifo_64kx9.srp index 25e140d..3f23449 100644 --- a/gbe_ecp2m/ipcores/fifo_64kx9.srp +++ b/gbe_ecp2m/ipcores/fifo_64kx9.srp @@ -1,13 +1,13 @@ -SCUBA, Version ispLever_v8.0_PROD_Build (41) -Mon Jul 26 21:40:04 2010 +SCUBA, Version Diamond_1.3_Production (92) +Thu Sep 22 11:23:21 2011 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved. +Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - Issued command : /opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n fifo_64kx9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 16 -data_width 9 -num_words 65536 -rdata_width 9 -no_enable -pe -1 -pf -1 -e + Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_64kx9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 16 -data_width 9 -num_words 65536 -rdata_width 9 -no_enable -pe -1 -pf -1 -e Circuit name : fifo_64kx9 Module type : ebfifo Module Version : 5.4 @@ -34,9 +34,9 @@ Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved. INV : 12 MUX321 : 9 OR2 : 1 - ROM16X1 : 188 + ROM16X1A : 188 XOR2 : 32 - DP16KB : 32 + DP16KC : 32 Estimated Resource Usage: LUT : 379 EBR : 32 diff --git a/gbe_ecp2m/ipcores/fifo_64kx9.vhd b/gbe_ecp2m/ipcores/fifo_64kx9.vhd index bfd2745..9ad1f19 100644 --- a/gbe_ecp2m/ipcores/fifo_64kx9.vhd +++ b/gbe_ecp2m/ipcores/fifo_64kx9.vhd @@ -1,14 +1,14 @@ --- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41) +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) -- Module Version: 5.4 ---/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 65536 -width 9 -depth 65536 -rdata_width 9 -no_enable -pe -1 -pf -1 -e +--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 65536 -width 9 -depth 65536 -rdata_width 9 -no_enable -pe -1 -pf -1 -e --- Mon Jul 26 21:40:04 2010 +-- Thu Sep 22 11:23:21 2011 library IEEE; use IEEE.std_logic_1164.all; -- synopsys translate_off -library ecp2m; -use ecp2m.components.all; +library ecp3; +use ecp3.components.all; -- synopsys translate_on entity fifo_64kx9 is @@ -825,30 +825,18 @@ architecture Structure of fifo_64kx9 is S0: out std_logic; S1: out std_logic); end component; component FD1P3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on port (D: in std_logic; SP: in std_logic; CK: in std_logic; PD: in std_logic; Q: out std_logic); end component; component FD1P3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on port (D: in std_logic; SP: in std_logic; CK: in std_logic; CD: in std_logic; Q: out std_logic); end component; component FD1S3BX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on port (D: in std_logic; CK: in std_logic; PD: in std_logic; Q: out std_logic); end component; component FD1S3DX - -- synopsys translate_off - generic (GSR : in String); - -- synopsys translate_on port (D: in std_logic; CK: in std_logic; CD: in std_logic; Q: out std_logic); end component; @@ -873,10 +861,8 @@ architecture Structure of fifo_64kx9 is component OR2 port (A: in std_logic; B: in std_logic; Z: out std_logic); end component; - component ROM16X1 - -- synopsys translate_off - generic (initval : in String); - -- synopsys translate_on + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; AD0: in std_logic; DO0: out std_logic); end component; @@ -889,15 +875,12 @@ architecture Structure of fifo_64kx9 is component XOR2 port (A: in std_logic; B: in std_logic; Z: out std_logic); end component; - component DP16KB - -- synopsys translate_off + component DP16KC generic (GSR : in String; WRITEMODE_B : in String; - CSDECODE_B : in std_logic_vector(2 downto 0); - CSDECODE_A : in std_logic_vector(2 downto 0); - WRITEMODE_A : in String; RESETMODE : in String; - REGMODE_B : in String; REGMODE_A : in String; - DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); - -- synopsys translate_on + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); port (DIA0: in std_logic; DIA1: in std_logic; DIA2: in std_logic; DIA3: in std_logic; DIA4: in std_logic; DIA5: in std_logic; @@ -914,8 +897,8 @@ architecture Structure of fifo_64kx9 is ADA8: in std_logic; ADA9: in std_logic; ADA10: in std_logic; ADA11: in std_logic; ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; - CSA0: in std_logic; CSA1: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; CSA2: in std_logic; RSTA: in std_logic; DIB0: in std_logic; DIB1: in std_logic; DIB2: in std_logic; DIB3: in std_logic; @@ -933,8 +916,8 @@ architecture Structure of fifo_64kx9 is ADB8: in std_logic; ADB9: in std_logic; ADB10: in std_logic; ADB11: in std_logic; ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; - CSB0: in std_logic; CSB1: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; CSB2: in std_logic; RSTB: in std_logic; DOA0: out std_logic; DOA1: out std_logic; DOA2: out std_logic; DOA3: out std_logic; @@ -955,591 +938,106 @@ architecture Structure of fifo_64kx9 is DOB14: out std_logic; DOB15: out std_logic; DOB16: out std_logic; DOB17: out std_logic); end component; - attribute initval : string; attribute MEM_LPC_FILE : string; attribute MEM_INIT_FILE : string; - attribute CSDECODE_B : string; - attribute CSDECODE_A : string; - attribute WRITEMODE_B : string; - attribute WRITEMODE_A : string; attribute RESETMODE : string; - attribute REGMODE_B : string; - attribute REGMODE_A : string; - attribute DATA_WIDTH_B : string; - attribute DATA_WIDTH_A : string; attribute GSR : string; - attribute initval of LUT4_187 : label is "0x8000"; - attribute initval of LUT4_186 : label is "0x8000"; - attribute initval of LUT4_185 : label is "0x8000"; - attribute initval of LUT4_184 : label is "0x8000"; - attribute initval of LUT4_183 : label is "0x8000"; - attribute initval of LUT4_182 : label is "0x8000"; - attribute initval of LUT4_181 : label is "0x8000"; - attribute initval of LUT4_180 : label is "0x8000"; - attribute initval of LUT4_179 : label is "0x8000"; - attribute initval of LUT4_178 : label is "0x8000"; - attribute initval of LUT4_177 : label is "0x8000"; - attribute initval of LUT4_176 : label is "0x8000"; - attribute initval of LUT4_175 : label is "0x8000"; - attribute initval of LUT4_174 : label is "0x8000"; - attribute initval of LUT4_173 : label is "0x8000"; - attribute initval of LUT4_172 : label is "0x8000"; - attribute initval of LUT4_171 : label is "0x8000"; - attribute initval of LUT4_170 : label is "0x8000"; - attribute initval of LUT4_169 : label is "0x8000"; - attribute initval of LUT4_168 : label is "0x8000"; - attribute initval of LUT4_167 : label is "0x8000"; - attribute initval of LUT4_166 : label is "0x8000"; - attribute initval of LUT4_165 : label is "0x8000"; - attribute initval of LUT4_164 : label is "0x8000"; - attribute initval of LUT4_163 : label is "0x8000"; - attribute initval of LUT4_162 : label is "0x8000"; - attribute initval of LUT4_161 : label is "0x8000"; - attribute initval of LUT4_160 : label is "0x8000"; - attribute initval of LUT4_159 : label is "0x8000"; - attribute initval of LUT4_158 : label is "0x8000"; - attribute initval of LUT4_157 : label is "0x8000"; - attribute initval of LUT4_156 : label is "0x8000"; - attribute initval of LUT4_155 : label is "0x8000"; - attribute initval of LUT4_154 : label is "0x8000"; - attribute initval of LUT4_153 : label is "0x8000"; - attribute initval of LUT4_152 : label is "0x8000"; - attribute initval of LUT4_151 : label is "0x8000"; - attribute initval of LUT4_150 : label is "0x8000"; - attribute initval of LUT4_149 : label is "0x8000"; - attribute initval of LUT4_148 : label is "0x8000"; - attribute initval of LUT4_147 : label is "0x8000"; - attribute initval of LUT4_146 : label is "0x8000"; - attribute initval of LUT4_145 : label is "0x8000"; - attribute initval of LUT4_144 : label is "0x8000"; - attribute initval of LUT4_143 : label is "0x8000"; - attribute initval of LUT4_142 : label is "0x8000"; - attribute initval of LUT4_141 : label is "0x8000"; - attribute initval of LUT4_140 : label is "0x8000"; - attribute initval of LUT4_139 : label is "0x8000"; - attribute initval of LUT4_138 : label is "0x8000"; - attribute initval of LUT4_137 : label is "0x8000"; - attribute initval of LUT4_136 : label is "0x8000"; - attribute initval of LUT4_135 : label is "0x8000"; - attribute initval of LUT4_134 : label is "0x8000"; - attribute initval of LUT4_133 : label is "0x8000"; - attribute initval of LUT4_132 : label is "0x8000"; - attribute initval of LUT4_131 : label is "0x8000"; - attribute initval of LUT4_130 : label is "0x8000"; - attribute initval of LUT4_129 : label is "0x8000"; - attribute initval of LUT4_128 : label is "0x8000"; - attribute initval of LUT4_127 : label is "0x8000"; - attribute initval of LUT4_126 : label is "0x8000"; - attribute initval of LUT4_125 : label is "0x8000"; - attribute initval of LUT4_124 : label is "0x8000"; - attribute initval of LUT4_123 : label is "0x8000"; - attribute initval of LUT4_122 : label is "0x8000"; - attribute initval of LUT4_121 : label is "0x8000"; - attribute initval of LUT4_120 : label is "0x8000"; - attribute initval of LUT4_119 : label is "0x8000"; - attribute initval of LUT4_118 : label is "0x8000"; - attribute initval of LUT4_117 : label is "0x8000"; - attribute initval of LUT4_116 : label is "0x8000"; - attribute initval of LUT4_115 : label is "0x8000"; - attribute initval of LUT4_114 : label is "0x8000"; - attribute initval of LUT4_113 : label is "0x8000"; - attribute initval of LUT4_112 : label is "0x8000"; - attribute initval of LUT4_111 : label is "0x8000"; - attribute initval of LUT4_110 : label is "0x8000"; - attribute initval of LUT4_109 : label is "0x8000"; - attribute initval of LUT4_108 : label is "0x8000"; - attribute initval of LUT4_107 : label is "0x8000"; - attribute initval of LUT4_106 : label is "0x8000"; - attribute initval of LUT4_105 : label is "0x8000"; - attribute initval of LUT4_104 : label is "0x8000"; - attribute initval of LUT4_103 : label is "0x8000"; - attribute initval of LUT4_102 : label is "0x8000"; - attribute initval of LUT4_101 : label is "0x8000"; - attribute initval of LUT4_100 : label is "0x8000"; - attribute initval of LUT4_99 : label is "0x8000"; - attribute initval of LUT4_98 : label is "0x8000"; - attribute initval of LUT4_97 : label is "0x8000"; - attribute initval of LUT4_96 : label is "0x8000"; - attribute initval of LUT4_95 : label is "0x8000"; - attribute initval of LUT4_94 : label is "0x8000"; - attribute initval of LUT4_93 : label is "0x8000"; - attribute initval of LUT4_92 : label is "0x8000"; - attribute initval of LUT4_91 : label is "0x8000"; - attribute initval of LUT4_90 : label is "0x8000"; - attribute initval of LUT4_89 : label is "0x8000"; - attribute initval of LUT4_88 : label is "0x8000"; - attribute initval of LUT4_87 : label is "0x8000"; - attribute initval of LUT4_86 : label is "0x8000"; - attribute initval of LUT4_85 : label is "0x8000"; - attribute initval of LUT4_84 : label is "0x8000"; - attribute initval of LUT4_83 : label is "0x8000"; - attribute initval of LUT4_82 : label is "0x8000"; - attribute initval of LUT4_81 : label is "0x8000"; - attribute initval of LUT4_80 : label is "0x8000"; - attribute initval of LUT4_79 : label is "0x8000"; - attribute initval of LUT4_78 : label is "0x8000"; - attribute initval of LUT4_77 : label is "0x8000"; - attribute initval of LUT4_76 : label is "0x8000"; - attribute initval of LUT4_75 : label is "0x8000"; - attribute initval of LUT4_74 : label is "0x8000"; - attribute initval of LUT4_73 : label is "0x8000"; - attribute initval of LUT4_72 : label is "0x8000"; - attribute initval of LUT4_71 : label is "0x8000"; - attribute initval of LUT4_70 : label is "0x8000"; - attribute initval of LUT4_69 : label is "0x8000"; - attribute initval of LUT4_68 : label is "0x8000"; - attribute initval of LUT4_67 : label is "0x8000"; - attribute initval of LUT4_66 : label is "0x8000"; - attribute initval of LUT4_65 : label is "0x8000"; - attribute initval of LUT4_64 : label is "0x8000"; - attribute initval of LUT4_63 : label is "0x8000"; - attribute initval of LUT4_62 : label is "0x8000"; - attribute initval of LUT4_61 : label is "0x8000"; - attribute initval of LUT4_60 : label is "0x8000"; - attribute initval of LUT4_59 : label is "0x6996"; - attribute initval of LUT4_58 : label is "0x6996"; - attribute initval of LUT4_57 : label is "0x6996"; - attribute initval of LUT4_56 : label is "0x6996"; - attribute initval of LUT4_55 : label is "0x6996"; - attribute initval of LUT4_54 : label is "0x6996"; - attribute initval of LUT4_53 : label is "0x6996"; - attribute initval of LUT4_52 : label is "0x6996"; - attribute initval of LUT4_51 : label is "0x6996"; - attribute initval of LUT4_50 : label is "0x6996"; - attribute initval of LUT4_49 : label is "0x6996"; - attribute initval of LUT4_48 : label is "0x6996"; - attribute initval of LUT4_47 : label is "0x6996"; - attribute initval of LUT4_46 : label is "0x6996"; - attribute initval of LUT4_45 : label is "0x6996"; - attribute initval of LUT4_44 : label is "0x6996"; - attribute initval of LUT4_43 : label is "0x6996"; - attribute initval of LUT4_42 : label is "0x6996"; - attribute initval of LUT4_41 : label is "0x6996"; - attribute initval of LUT4_40 : label is "0x6996"; - attribute initval of LUT4_39 : label is "0x6996"; - attribute initval of LUT4_38 : label is "0x6996"; - attribute initval of LUT4_37 : label is "0x6996"; - attribute initval of LUT4_36 : label is "0x6996"; - attribute initval of LUT4_35 : label is "0x6996"; - attribute initval of LUT4_34 : label is "0x6996"; - attribute initval of LUT4_33 : label is "0x6996"; - attribute initval of LUT4_32 : label is "0x6996"; - attribute initval of LUT4_31 : label is "0x6996"; - attribute initval of LUT4_30 : label is "0x6996"; - attribute initval of LUT4_29 : label is "0x6996"; - attribute initval of LUT4_28 : label is "0x6996"; - attribute initval of LUT4_27 : label is "0x6996"; - attribute initval of LUT4_26 : label is "0x6996"; - attribute initval of LUT4_25 : label is "0x6996"; - attribute initval of LUT4_24 : label is "0x6996"; - attribute initval of LUT4_23 : label is "0x6996"; - attribute initval of LUT4_22 : label is "0x6996"; - attribute initval of LUT4_21 : label is "0x6996"; - attribute initval of LUT4_20 : label is "0x6996"; - attribute initval of LUT4_19 : label is "0x6996"; - attribute initval of LUT4_18 : label is "0x6996"; - attribute initval of LUT4_17 : label is "0x6996"; - attribute initval of LUT4_16 : label is "0x6996"; - attribute initval of LUT4_15 : label is "0x6996"; - attribute initval of LUT4_14 : label is "0x6996"; - attribute initval of LUT4_13 : label is "0x6996"; - attribute initval of LUT4_12 : label is "0x6996"; - attribute initval of LUT4_11 : label is "0x6996"; - attribute initval of LUT4_10 : label is "0x6996"; - attribute initval of LUT4_9 : label is "0x6996"; - attribute initval of LUT4_8 : label is "0x6996"; - attribute initval of LUT4_7 : label is "0x6996"; - attribute initval of LUT4_6 : label is "0x6996"; - attribute initval of LUT4_5 : label is "0x6996"; - attribute initval of LUT4_4 : label is "0x6996"; - attribute initval of LUT4_3 : label is "0x0410"; - attribute initval of LUT4_2 : label is "0x1004"; - attribute initval of LUT4_1 : label is "0x0140"; - attribute initval of LUT4_0 : label is "0x4001"; attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_64kx9.lpc"; attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; - attribute CSDECODE_B of pdp_ram_0_0_31 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_0_0_31 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_0_0_31 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_0_0_31 : label is "NORMAL"; - attribute GSR of pdp_ram_0_0_31 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_0_0_31 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_0_0_31 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_0_0_31 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_0_0_31 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_0_0_31 : label is "9"; + attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_1_0_30 : label is "fifo_64kx9.lpc"; attribute MEM_INIT_FILE of pdp_ram_1_0_30 : label is ""; - attribute CSDECODE_B of pdp_ram_1_0_30 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_1_0_30 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_1_0_30 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_1_0_30 : label is "NORMAL"; - attribute GSR of pdp_ram_1_0_30 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_1_0_30 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_1_0_30 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_1_0_30 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_1_0_30 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_1_0_30 : label is "9"; + attribute RESETMODE of pdp_ram_1_0_30 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_2_0_29 : label is "fifo_64kx9.lpc"; attribute MEM_INIT_FILE of pdp_ram_2_0_29 : label is ""; - attribute CSDECODE_B of pdp_ram_2_0_29 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_2_0_29 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_2_0_29 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_2_0_29 : label is "NORMAL"; - attribute GSR of pdp_ram_2_0_29 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_2_0_29 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_2_0_29 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_2_0_29 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_2_0_29 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_2_0_29 : label is "9"; + attribute RESETMODE of pdp_ram_2_0_29 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_3_0_28 : label is "fifo_64kx9.lpc"; attribute MEM_INIT_FILE of pdp_ram_3_0_28 : label is ""; - attribute CSDECODE_B of pdp_ram_3_0_28 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_3_0_28 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_3_0_28 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_3_0_28 : label is "NORMAL"; - attribute GSR of pdp_ram_3_0_28 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_3_0_28 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_3_0_28 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_3_0_28 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_3_0_28 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_3_0_28 : label is "9"; + attribute RESETMODE of pdp_ram_3_0_28 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_4_0_27 : label is "fifo_64kx9.lpc"; attribute MEM_INIT_FILE of pdp_ram_4_0_27 : label is ""; - attribute CSDECODE_B of pdp_ram_4_0_27 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_4_0_27 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_4_0_27 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_4_0_27 : label is "NORMAL"; - attribute GSR of pdp_ram_4_0_27 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_4_0_27 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_4_0_27 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_4_0_27 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_4_0_27 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_4_0_27 : label is "9"; + attribute RESETMODE of pdp_ram_4_0_27 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_5_0_26 : label is "fifo_64kx9.lpc"; attribute MEM_INIT_FILE of pdp_ram_5_0_26 : label is ""; - attribute CSDECODE_B of pdp_ram_5_0_26 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_5_0_26 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_5_0_26 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_5_0_26 : label is "NORMAL"; - attribute GSR of pdp_ram_5_0_26 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_5_0_26 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_5_0_26 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_5_0_26 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_5_0_26 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_5_0_26 : label is "9"; + attribute RESETMODE of pdp_ram_5_0_26 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_6_0_25 : label is "fifo_64kx9.lpc"; attribute MEM_INIT_FILE of pdp_ram_6_0_25 : label is ""; - attribute CSDECODE_B of pdp_ram_6_0_25 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_6_0_25 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_6_0_25 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_6_0_25 : label is "NORMAL"; - attribute GSR of pdp_ram_6_0_25 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_6_0_25 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_6_0_25 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_6_0_25 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_6_0_25 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_6_0_25 : label is "9"; + attribute RESETMODE of pdp_ram_6_0_25 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_7_0_24 : label is "fifo_64kx9.lpc"; attribute MEM_INIT_FILE of pdp_ram_7_0_24 : label is ""; - attribute CSDECODE_B of pdp_ram_7_0_24 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_7_0_24 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_7_0_24 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_7_0_24 : label is "NORMAL"; - attribute GSR of pdp_ram_7_0_24 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_7_0_24 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_7_0_24 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_7_0_24 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_7_0_24 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_7_0_24 : label is "9"; + attribute RESETMODE of pdp_ram_7_0_24 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_8_0_23 : label is "fifo_64kx9.lpc"; attribute MEM_INIT_FILE of pdp_ram_8_0_23 : label is ""; - attribute CSDECODE_B of pdp_ram_8_0_23 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_8_0_23 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_8_0_23 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_8_0_23 : label is "NORMAL"; - attribute GSR of pdp_ram_8_0_23 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_8_0_23 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_8_0_23 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_8_0_23 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_8_0_23 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_8_0_23 : label is "9"; + attribute RESETMODE of pdp_ram_8_0_23 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_9_0_22 : label is "fifo_64kx9.lpc"; attribute MEM_INIT_FILE of pdp_ram_9_0_22 : label is ""; - attribute CSDECODE_B of pdp_ram_9_0_22 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_9_0_22 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_9_0_22 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_9_0_22 : label is "NORMAL"; - attribute GSR of pdp_ram_9_0_22 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_9_0_22 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_9_0_22 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_9_0_22 : label is "NOREG"; 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- attribute WRITEMODE_A of pdp_ram_29_0_2 : label is "NORMAL"; - attribute GSR of pdp_ram_29_0_2 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_29_0_2 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_29_0_2 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_29_0_2 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_29_0_2 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_29_0_2 : label is "9"; + attribute RESETMODE of pdp_ram_29_0_2 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_30_0_1 : label is "fifo_64kx9.lpc"; attribute MEM_INIT_FILE of pdp_ram_30_0_1 : label is ""; - attribute CSDECODE_B of pdp_ram_30_0_1 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_30_0_1 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_30_0_1 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_30_0_1 : label is "NORMAL"; - attribute GSR of pdp_ram_30_0_1 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_30_0_1 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_30_0_1 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_30_0_1 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_30_0_1 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_30_0_1 : label is "9"; + attribute RESETMODE of pdp_ram_30_0_1 : label is "SYNC"; attribute MEM_LPC_FILE of pdp_ram_31_0_0 : label is "fifo_64kx9.lpc"; attribute MEM_INIT_FILE of pdp_ram_31_0_0 : label is ""; - attribute CSDECODE_B of pdp_ram_31_0_0 : label is "0b001"; - attribute CSDECODE_A of pdp_ram_31_0_0 : label is "0b001"; - attribute WRITEMODE_B of pdp_ram_31_0_0 : label is "NORMAL"; - attribute WRITEMODE_A of pdp_ram_31_0_0 : label is "NORMAL"; - attribute GSR of pdp_ram_31_0_0 : label is "DISABLED"; - attribute RESETMODE of pdp_ram_31_0_0 : label is "ASYNC"; - attribute REGMODE_B of pdp_ram_31_0_0 : label is "NOREG"; - attribute REGMODE_A of pdp_ram_31_0_0 : label is "NOREG"; - attribute DATA_WIDTH_B of pdp_ram_31_0_0 : label is "9"; - attribute DATA_WIDTH_A of pdp_ram_31_0_0 : label is "9"; + attribute RESETMODE of pdp_ram_31_0_0 : label is "SYNC"; attribute GSR of FF_176 : label is "ENABLED"; attribute GSR of FF_175 : label is "ENABLED"; attribute GSR of FF_174 : label is "ENABLED"; @@ -1847,17 +1345,13 @@ begin INV_5: INV port map (A=>wptr_15, Z=>wptr_15_inv); - LUT4_187: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_187: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, AD0=>wptr_14_inv, DO0=>func_and_inet); - LUT4_186: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_186: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet, AD2=>wptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec0_p00); @@ -1876,1337 +1370,963 @@ begin INV_0: INV port map (A=>rptr_15, Z=>rptr_15_inv); - LUT4_185: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_185: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, AD0=>rptr_14_inv, DO0=>func_and_inet_1); - LUT4_184: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_184: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_1, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec1_r10); - LUT4_183: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_183: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, AD0=>wptr_14_inv, DO0=>func_and_inet_2); - LUT4_182: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_182: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_2, AD2=>wptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec2_p01); - LUT4_181: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_181: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, AD0=>rptr_14_inv, DO0=>func_and_inet_3); - LUT4_180: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_180: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_3, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec3_r11); - LUT4_179: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_179: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, AD0=>wptr_14_inv, DO0=>func_and_inet_4); - LUT4_178: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_178: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_4, AD2=>wptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec4_p02); - LUT4_177: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_177: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, AD0=>rptr_14_inv, DO0=>func_and_inet_5); - LUT4_176: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_176: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_5, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec5_r12); - LUT4_175: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_175: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, AD0=>wptr_14_inv, DO0=>func_and_inet_6); - LUT4_174: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_174: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_6, AD2=>wptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec6_p03); - LUT4_173: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_173: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, AD0=>rptr_14_inv, DO0=>func_and_inet_7); - LUT4_172: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_172: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_7, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec7_r13); - LUT4_171: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_171: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, AD0=>wptr_14_inv, DO0=>func_and_inet_8); - LUT4_170: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_170: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_8, AD2=>wptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec8_p04); - LUT4_169: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_169: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, AD0=>rptr_14_inv, DO0=>func_and_inet_9); - LUT4_168: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_168: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_9, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec9_r14); - LUT4_167: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_167: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, AD0=>wptr_14_inv, DO0=>func_and_inet_10); - LUT4_166: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_166: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_10, AD2=>wptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec10_p05); - LUT4_165: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_165: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, AD0=>rptr_14_inv, DO0=>func_and_inet_11); - LUT4_164: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_164: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_11, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec11_r15); - LUT4_163: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_163: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14_inv, DO0=>func_and_inet_12); - LUT4_162: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_162: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_12, AD2=>wptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec12_p06); - LUT4_161: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_161: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14_inv, DO0=>func_and_inet_13); - LUT4_160: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_160: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_13, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec13_r16); - LUT4_159: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_159: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14_inv, DO0=>func_and_inet_14); - LUT4_158: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_158: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_14, AD2=>wptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec14_p07); - LUT4_157: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_157: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14_inv, DO0=>func_and_inet_15); - LUT4_156: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_156: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_15, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec15_r17); - LUT4_155: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_155: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, AD0=>wptr_14, DO0=>func_and_inet_16); - LUT4_154: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_154: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_16, AD2=>wptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec16_p08); - LUT4_153: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_153: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, AD0=>rptr_14, DO0=>func_and_inet_17); - LUT4_152: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_152: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_17, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec17_r18); - LUT4_151: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_151: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, AD0=>wptr_14, DO0=>func_and_inet_18); - LUT4_150: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_150: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_18, AD2=>wptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec18_p09); - LUT4_149: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_149: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, AD0=>rptr_14, DO0=>func_and_inet_19); - LUT4_148: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_148: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_19, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec19_r19); - LUT4_147: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_147: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, AD0=>wptr_14, DO0=>func_and_inet_20); - LUT4_146: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_146: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_20, AD2=>wptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec20_p010); - LUT4_145: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_145: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, AD0=>rptr_14, DO0=>func_and_inet_21); - LUT4_144: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_144: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_21, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec21_r110); - LUT4_143: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_143: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, AD0=>wptr_14, DO0=>func_and_inet_22); - LUT4_142: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_142: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_22, AD2=>wptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec22_p011); - LUT4_141: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_141: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, AD0=>rptr_14, DO0=>func_and_inet_23); - LUT4_140: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_140: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_23, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec23_r111); - LUT4_139: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_139: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, AD0=>wptr_14, DO0=>func_and_inet_24); - LUT4_138: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_138: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_24, AD2=>wptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec24_p012); - LUT4_137: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_137: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, AD0=>rptr_14, DO0=>func_and_inet_25); - LUT4_136: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_136: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_25, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec25_r112); - LUT4_135: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_135: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, AD0=>wptr_14, DO0=>func_and_inet_26); - LUT4_134: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_134: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_26, AD2=>wptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec26_p013); - LUT4_133: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_133: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, AD0=>rptr_14, DO0=>func_and_inet_27); - LUT4_132: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_132: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_27, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec27_r113); - LUT4_131: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_131: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, DO0=>func_and_inet_28); - LUT4_130: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_130: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_28, AD2=>wptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec28_p014); - LUT4_129: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_129: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, DO0=>func_and_inet_29); - LUT4_128: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_128: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_29, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec29_r114); - LUT4_127: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_127: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, DO0=>func_and_inet_30); - LUT4_126: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_126: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_30, AD2=>wptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec30_p015); - LUT4_125: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_125: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, DO0=>func_and_inet_31); - LUT4_124: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_124: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_31, AD2=>rptr_15_inv, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec31_r115); - LUT4_123: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_123: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, AD0=>wptr_14_inv, DO0=>func_and_inet_32); - LUT4_122: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_122: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_32, AD2=>wptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec32_p016); - LUT4_121: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_121: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, AD0=>rptr_14_inv, DO0=>func_and_inet_33); - LUT4_120: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_120: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_33, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec33_r116); - LUT4_119: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_119: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, AD0=>wptr_14_inv, DO0=>func_and_inet_34); - LUT4_118: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_118: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_34, AD2=>wptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec34_p017); - LUT4_117: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_117: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, AD0=>rptr_14_inv, DO0=>func_and_inet_35); - LUT4_116: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_116: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_35, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec35_r117); - LUT4_115: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_115: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, AD0=>wptr_14_inv, DO0=>func_and_inet_36); - LUT4_114: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_114: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_36, AD2=>wptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec36_p018); - LUT4_113: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_113: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, AD0=>rptr_14_inv, DO0=>func_and_inet_37); - LUT4_112: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_112: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_37, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec37_r118); - LUT4_111: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_111: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, AD0=>wptr_14_inv, DO0=>func_and_inet_38); - LUT4_110: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_110: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_38, AD2=>wptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec38_p019); - LUT4_109: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_109: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, AD0=>rptr_14_inv, DO0=>func_and_inet_39); - LUT4_108: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_108: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_39, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec39_r119); - LUT4_107: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_107: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, AD0=>wptr_14_inv, DO0=>func_and_inet_40); - LUT4_106: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_106: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_40, AD2=>wptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec40_p020); - LUT4_105: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_105: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, AD0=>rptr_14_inv, DO0=>func_and_inet_41); - LUT4_104: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_104: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_41, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec41_r120); - LUT4_103: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_103: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, AD0=>wptr_14_inv, DO0=>func_and_inet_42); - LUT4_102: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_102: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_42, AD2=>wptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec42_p021); - LUT4_101: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_101: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, AD0=>rptr_14_inv, DO0=>func_and_inet_43); - LUT4_100: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_100: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_43, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec43_r121); - LUT4_99: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_99: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14_inv, DO0=>func_and_inet_44); - LUT4_98: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_98: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_44, AD2=>wptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec44_p022); - LUT4_97: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_97: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14_inv, DO0=>func_and_inet_45); - LUT4_96: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_96: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_45, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec45_r122); - LUT4_95: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_95: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14_inv, DO0=>func_and_inet_46); - LUT4_94: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_94: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_46, AD2=>wptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec46_p023); - LUT4_93: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_93: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14_inv, DO0=>func_and_inet_47); - LUT4_92: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_92: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_47, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec47_r123); - LUT4_91: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_91: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, AD0=>wptr_14, DO0=>func_and_inet_48); - LUT4_90: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_90: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_48, AD2=>wptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec48_p024); - LUT4_89: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_89: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, AD0=>rptr_14, DO0=>func_and_inet_49); - LUT4_88: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_88: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_49, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec49_r124); - LUT4_87: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_87: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, AD0=>wptr_14, DO0=>func_and_inet_50); - LUT4_86: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_86: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_50, AD2=>wptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec50_p025); - LUT4_85: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_85: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, AD0=>rptr_14, DO0=>func_and_inet_51); - LUT4_84: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_84: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_51, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec51_r125); - LUT4_83: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_83: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, AD0=>wptr_14, DO0=>func_and_inet_52); - LUT4_82: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_82: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_52, AD2=>wptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec52_p026); - LUT4_81: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_81: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, AD0=>rptr_14, DO0=>func_and_inet_53); - LUT4_80: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_80: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_53, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec53_r126); - LUT4_79: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_79: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, AD0=>wptr_14, DO0=>func_and_inet_54); - LUT4_78: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_78: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_54, AD2=>wptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec54_p027); - LUT4_77: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_77: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, AD0=>rptr_14, DO0=>func_and_inet_55); - LUT4_76: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_76: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_55, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec55_r127); - LUT4_75: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_75: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, AD0=>wptr_14, DO0=>func_and_inet_56); - LUT4_74: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_74: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_56, AD2=>wptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec56_p028); - LUT4_73: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_73: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, AD0=>rptr_14, DO0=>func_and_inet_57); - LUT4_72: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_72: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_57, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec57_r128); - LUT4_71: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_71: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, AD0=>wptr_14, DO0=>func_and_inet_58); - LUT4_70: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_70: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_58, AD2=>wptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec58_p029); - LUT4_69: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_69: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, AD0=>rptr_14, DO0=>func_and_inet_59); - LUT4_68: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_68: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_59, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec59_r129); - LUT4_67: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_67: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, DO0=>func_and_inet_60); - LUT4_66: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_66: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_60, AD2=>wptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec60_p030); - LUT4_65: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_65: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, DO0=>func_and_inet_61); - LUT4_64: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_64: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_61, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec61_r130); - LUT4_63: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_63: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, DO0=>func_and_inet_62); - LUT4_62: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_62: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_62, AD2=>wptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec62_p031); - LUT4_61: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_61: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, DO0=>func_and_inet_63); - LUT4_60: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x8000") - -- synopsys translate_on + LUT4_60: ROM16X1A + generic map (initval=> X"8000") port map (AD3=>func_and_inet_63, AD2=>rptr_15, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec63_r131); - LUT4_59: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_59: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, AD1=>w_gcount_r215, AD0=>w_gcount_r216, DO0=>w_g2b_xor_cluster_0); - LUT4_58: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_58: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, AD1=>w_gcount_r211, AD0=>w_gcount_r212, DO0=>w_g2b_xor_cluster_1); - LUT4_57: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_57: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, AD1=>w_gcount_r27, AD0=>w_gcount_r28, DO0=>w_g2b_xor_cluster_2); - LUT4_56: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_56: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>w_g2b_xor_cluster_3); - LUT4_55: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_55: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r215, AD2=>w_gcount_r216, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r15); - LUT4_54: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_54: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>w_gcount_r216, AD0=>scuba_vlo, DO0=>wcount_r14); - LUT4_53: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_53: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, AD1=>w_gcount_r214, AD0=>wcount_r15, DO0=>wcount_r12); - LUT4_52: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_52: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); - LUT4_51: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_51: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>w_gcount_r212, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r10); - LUT4_50: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_50: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r9); - LUT4_49: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_49: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r8); - LUT4_48: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_48: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>w_gcount_r27, AD0=>w_gcount_r28, DO0=>wcount_r7); - LUT4_47: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_47: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_2_1); - LUT4_46: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_46: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r6); - LUT4_45: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_45: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r5); - LUT4_44: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_44: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r24, DO0=>wcount_r4); - LUT4_43: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_43: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); - LUT4_42: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_42: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, DO0=>wcount_r3); - LUT4_41: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_41: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_2); - LUT4_40: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_40: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, DO0=>wcount_r2); - LUT4_39: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_39: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, DO0=>wcount_r1); - LUT4_38: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_38: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>func_xor_inet); - LUT4_37: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_37: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>func_xor_inet_1); - LUT4_36: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_36: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>w_gcount_r210, AD0=>w_gcount_r211, DO0=>func_xor_inet_2); - LUT4_35: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_35: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, AD1=>w_gcount_r214, AD0=>w_gcount_r215, DO0=>func_xor_inet_3); - LUT4_34: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_34: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>w_gcount_r216, AD2=>scuba_vlo, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>func_xor_inet_4); - LUT4_33: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_33: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, DO0=>func_xor_inet_5); - LUT4_32: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_32: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r0); - LUT4_31: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_31: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, AD1=>r_gcount_w215, AD0=>r_gcount_w216, DO0=>r_g2b_xor_cluster_0); - LUT4_30: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_30: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, AD1=>r_gcount_w211, AD0=>r_gcount_w212, DO0=>r_g2b_xor_cluster_1); - LUT4_29: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_29: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>r_g2b_xor_cluster_2); - LUT4_28: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_28: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>r_g2b_xor_cluster_3); - LUT4_27: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_27: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w15); - LUT4_26: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_26: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); - LUT4_25: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_25: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); - LUT4_24: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_24: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); - LUT4_23: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_23: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w10); - LUT4_22: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_22: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); - LUT4_21: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_21: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); - LUT4_20: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_20: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); - LUT4_19: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_19: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_2_1); - LUT4_18: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_18: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); - LUT4_17: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_17: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); - LUT4_16: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_16: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); - LUT4_15: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_15: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); - LUT4_14: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_14: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, DO0=>rcount_w3); - LUT4_13: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_13: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_2); - LUT4_12: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_12: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, DO0=>rcount_w2); - LUT4_11: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_11: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, DO0=>rcount_w1); - LUT4_10: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_10: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet_6); - LUT4_9: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_9: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_7); - LUT4_8: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_8: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_8); - LUT4_7: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_7: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_9); - LUT4_6: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_6: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>func_xor_inet_10); - LUT4_5: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_5: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>func_xor_inet_6, AD2=>func_xor_inet_7, AD1=>func_xor_inet_8, AD0=>func_xor_inet_9, DO0=>func_xor_inet_11); - LUT4_4: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x6996") - -- synopsys translate_on + LUT4_4: ROM16X1A + generic map (initval=> X"6996") port map (AD3=>func_xor_inet_11, AD2=>func_xor_inet_10, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); - LUT4_3: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0410") - -- synopsys translate_on + LUT4_3: ROM16X1A + generic map (initval=> X"0410") port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, AD0=>scuba_vlo, DO0=>empty_cmp_set); - LUT4_2: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x1004") - -- synopsys translate_on + LUT4_2: ROM16X1A + generic map (initval=> X"1004") port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, AD0=>scuba_vlo, DO0=>empty_cmp_clr); - LUT4_1: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x0140") - -- synopsys translate_on + LUT4_1: ROM16X1A + generic map (initval=> X"0140") port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>full_cmp_set); - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4001") - -- synopsys translate_on + LUT4_0: ROM16X1A + generic map (initval=> X"4001") port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>full_cmp_clr); - pdp_ram_0_0_31: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + pdp_ram_0_0_31: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -3216,37 +2336,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec0_p00, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec1_r10, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, - DOB1=>mdout1_0_1, DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, - DOB4=>mdout1_0_4, DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, - DOB7=>mdout1_0_7, DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_1_0_30: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec0_p00, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec1_r10, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, + DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, + DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, + DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_0_30: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -3256,37 +2375,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec2_p01, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec3_r11, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, - DOB1=>mdout1_1_1, DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, - DOB4=>mdout1_1_4, DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, - DOB7=>mdout1_1_7, DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_2_0_29: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec2_p01, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec3_r11, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, + DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, + DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, + DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_0_29: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -3296,37 +2414,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec4_p02, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec5_r12, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, - DOB1=>mdout1_2_1, DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, - DOB4=>mdout1_2_4, DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, - DOB7=>mdout1_2_7, DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_3_0_28: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec4_p02, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec5_r12, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1, + DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4, + DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7, + DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_0_28: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -3336,37 +2453,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec6_p03, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec7_r13, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, - DOB1=>mdout1_3_1, DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, - DOB4=>mdout1_3_4, DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, - DOB7=>mdout1_3_7, DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_4_0_27: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec6_p03, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec7_r13, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1, + DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4, + DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7, + DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_4_0_27: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -3376,37 +2492,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec8_p04, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec9_r14, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_4_0, - DOB1=>mdout1_4_1, DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, - DOB4=>mdout1_4_4, DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, - DOB7=>mdout1_4_7, DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_5_0_26: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec8_p04, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec9_r14, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_4_0, DOB1=>mdout1_4_1, + DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, DOB4=>mdout1_4_4, + DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, DOB7=>mdout1_4_7, + DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_5_0_26: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -3416,37 +2531,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec10_p05, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec11_r15, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_5_0, - DOB1=>mdout1_5_1, DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, - DOB4=>mdout1_5_4, DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, - DOB7=>mdout1_5_7, DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_6_0_25: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec10_p05, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec11_r15, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_5_0, DOB1=>mdout1_5_1, + DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, DOB4=>mdout1_5_4, + DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, DOB7=>mdout1_5_7, + DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_6_0_25: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -3456,37 +2570,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec12_p06, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec13_r16, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_6_0, - DOB1=>mdout1_6_1, DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, - DOB4=>mdout1_6_4, DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, - DOB7=>mdout1_6_7, DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_7_0_24: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec12_p06, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec13_r16, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_6_0, DOB1=>mdout1_6_1, + DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, DOB4=>mdout1_6_4, + DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, DOB7=>mdout1_6_7, + DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_7_0_24: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -3496,37 +2609,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec14_p07, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec15_r17, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_7_0, - DOB1=>mdout1_7_1, DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, - DOB4=>mdout1_7_4, DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, - DOB7=>mdout1_7_7, DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_8_0_23: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec14_p07, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec15_r17, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_7_0, DOB1=>mdout1_7_1, + DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, DOB4=>mdout1_7_4, + DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, DOB7=>mdout1_7_7, + DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_8_0_23: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -3536,37 +2648,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec16_p08, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec17_r18, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_8_0, - DOB1=>mdout1_8_1, DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, - DOB4=>mdout1_8_4, DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, - DOB7=>mdout1_8_7, DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_9_0_22: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec16_p08, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec17_r18, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_8_0, DOB1=>mdout1_8_1, + DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, DOB4=>mdout1_8_4, + DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, DOB7=>mdout1_8_7, + DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_9_0_22: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -3576,37 +2687,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec18_p09, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec19_r19, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_9_0, - DOB1=>mdout1_9_1, DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, - DOB4=>mdout1_9_4, DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, - DOB7=>mdout1_9_7, DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - pdp_ram_10_0_21: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec18_p09, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec19_r19, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_9_0, DOB1=>mdout1_9_1, + DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, DOB4=>mdout1_9_4, + DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, DOB7=>mdout1_9_7, + DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_10_0_21: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -3616,37 +2726,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec20_p010, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec21_r110, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_10_0, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec20_p010, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec21_r110, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_10_0, DOB1=>mdout1_10_1, DOB2=>mdout1_10_2, DOB3=>mdout1_10_3, DOB4=>mdout1_10_4, DOB5=>mdout1_10_5, DOB6=>mdout1_10_6, DOB7=>mdout1_10_7, DOB8=>mdout1_10_8, DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - pdp_ram_11_0_20: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + pdp_ram_11_0_20: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -3656,37 +2765,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec22_p011, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec23_r111, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_11_0, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec22_p011, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec23_r111, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_11_0, DOB1=>mdout1_11_1, DOB2=>mdout1_11_2, DOB3=>mdout1_11_3, DOB4=>mdout1_11_4, DOB5=>mdout1_11_5, DOB6=>mdout1_11_6, DOB7=>mdout1_11_7, DOB8=>mdout1_11_8, DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - pdp_ram_12_0_19: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + pdp_ram_12_0_19: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -3696,37 +2804,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec24_p012, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec25_r112, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_12_0, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec24_p012, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec25_r112, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_12_0, DOB1=>mdout1_12_1, DOB2=>mdout1_12_2, DOB3=>mdout1_12_3, DOB4=>mdout1_12_4, DOB5=>mdout1_12_5, DOB6=>mdout1_12_6, DOB7=>mdout1_12_7, DOB8=>mdout1_12_8, DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - pdp_ram_13_0_18: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + pdp_ram_13_0_18: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -3736,37 +2843,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec26_p013, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec27_r113, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_13_0, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec26_p013, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec27_r113, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_13_0, DOB1=>mdout1_13_1, DOB2=>mdout1_13_2, DOB3=>mdout1_13_3, DOB4=>mdout1_13_4, DOB5=>mdout1_13_5, DOB6=>mdout1_13_6, DOB7=>mdout1_13_7, DOB8=>mdout1_13_8, DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - pdp_ram_14_0_17: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + pdp_ram_14_0_17: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -3776,37 +2882,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec28_p014, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec29_r114, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_14_0, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec28_p014, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec29_r114, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_14_0, DOB1=>mdout1_14_1, DOB2=>mdout1_14_2, DOB3=>mdout1_14_3, DOB4=>mdout1_14_4, DOB5=>mdout1_14_5, DOB6=>mdout1_14_6, DOB7=>mdout1_14_7, DOB8=>mdout1_14_8, DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - pdp_ram_15_0_16: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + pdp_ram_15_0_16: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -3816,37 +2921,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec30_p015, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec31_r115, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_15_0, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec30_p015, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec31_r115, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_15_0, DOB1=>mdout1_15_1, DOB2=>mdout1_15_2, DOB3=>mdout1_15_3, DOB4=>mdout1_15_4, DOB5=>mdout1_15_5, DOB6=>mdout1_15_6, DOB7=>mdout1_15_7, DOB8=>mdout1_15_8, DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - pdp_ram_16_0_15: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + pdp_ram_16_0_15: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -3856,37 +2960,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec32_p016, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec33_r116, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_16_0, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec32_p016, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec33_r116, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_16_0, DOB1=>mdout1_16_1, DOB2=>mdout1_16_2, DOB3=>mdout1_16_3, DOB4=>mdout1_16_4, DOB5=>mdout1_16_5, DOB6=>mdout1_16_6, DOB7=>mdout1_16_7, DOB8=>mdout1_16_8, DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - pdp_ram_17_0_14: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + pdp_ram_17_0_14: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -3896,37 +2999,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec34_p017, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec35_r117, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_17_0, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec34_p017, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec35_r117, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_17_0, DOB1=>mdout1_17_1, DOB2=>mdout1_17_2, DOB3=>mdout1_17_3, DOB4=>mdout1_17_4, DOB5=>mdout1_17_5, DOB6=>mdout1_17_6, DOB7=>mdout1_17_7, DOB8=>mdout1_17_8, DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - pdp_ram_18_0_13: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + pdp_ram_18_0_13: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -3936,37 +3038,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec36_p018, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec37_r118, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_18_0, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec36_p018, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec37_r118, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_18_0, DOB1=>mdout1_18_1, DOB2=>mdout1_18_2, DOB3=>mdout1_18_3, DOB4=>mdout1_18_4, DOB5=>mdout1_18_5, DOB6=>mdout1_18_6, DOB7=>mdout1_18_7, DOB8=>mdout1_18_8, DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - pdp_ram_19_0_12: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + pdp_ram_19_0_12: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -3976,37 +3077,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec38_p019, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec39_r119, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_19_0, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec38_p019, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec39_r119, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_19_0, DOB1=>mdout1_19_1, DOB2=>mdout1_19_2, DOB3=>mdout1_19_3, DOB4=>mdout1_19_4, DOB5=>mdout1_19_5, DOB6=>mdout1_19_6, DOB7=>mdout1_19_7, DOB8=>mdout1_19_8, DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - pdp_ram_20_0_11: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + pdp_ram_20_0_11: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -4016,37 +3116,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec40_p020, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec41_r120, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_20_0, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec40_p020, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec41_r120, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_20_0, DOB1=>mdout1_20_1, DOB2=>mdout1_20_2, DOB3=>mdout1_20_3, DOB4=>mdout1_20_4, DOB5=>mdout1_20_5, DOB6=>mdout1_20_6, DOB7=>mdout1_20_7, DOB8=>mdout1_20_8, DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - pdp_ram_21_0_10: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + pdp_ram_21_0_10: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -4056,37 +3155,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec42_p021, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec43_r121, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_21_0, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec42_p021, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec43_r121, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_21_0, DOB1=>mdout1_21_1, DOB2=>mdout1_21_2, DOB3=>mdout1_21_3, DOB4=>mdout1_21_4, DOB5=>mdout1_21_5, DOB6=>mdout1_21_6, DOB7=>mdout1_21_7, DOB8=>mdout1_21_8, DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - pdp_ram_22_0_9: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + pdp_ram_22_0_9: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -4096,37 +3194,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec44_p022, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec45_r122, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_22_0, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec44_p022, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec45_r122, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_22_0, DOB1=>mdout1_22_1, DOB2=>mdout1_22_2, DOB3=>mdout1_22_3, DOB4=>mdout1_22_4, DOB5=>mdout1_22_5, DOB6=>mdout1_22_6, DOB7=>mdout1_22_7, DOB8=>mdout1_22_8, DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - pdp_ram_23_0_8: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + pdp_ram_23_0_8: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -4136,37 +3233,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec46_p023, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec47_r123, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_23_0, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec46_p023, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec47_r123, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_23_0, DOB1=>mdout1_23_1, DOB2=>mdout1_23_2, DOB3=>mdout1_23_3, DOB4=>mdout1_23_4, DOB5=>mdout1_23_5, DOB6=>mdout1_23_6, DOB7=>mdout1_23_7, DOB8=>mdout1_23_8, DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - pdp_ram_24_0_7: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + pdp_ram_24_0_7: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -4176,37 +3272,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec48_p024, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec49_r124, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_24_0, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec48_p024, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec49_r124, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_24_0, DOB1=>mdout1_24_1, DOB2=>mdout1_24_2, DOB3=>mdout1_24_3, DOB4=>mdout1_24_4, DOB5=>mdout1_24_5, DOB6=>mdout1_24_6, DOB7=>mdout1_24_7, DOB8=>mdout1_24_8, DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - pdp_ram_25_0_6: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + pdp_ram_25_0_6: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -4216,37 +3311,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec50_p025, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec51_r125, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_25_0, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec50_p025, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec51_r125, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_25_0, DOB1=>mdout1_25_1, DOB2=>mdout1_25_2, DOB3=>mdout1_25_3, DOB4=>mdout1_25_4, DOB5=>mdout1_25_5, DOB6=>mdout1_25_6, DOB7=>mdout1_25_7, DOB8=>mdout1_25_8, DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - pdp_ram_26_0_5: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + pdp_ram_26_0_5: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -4256,37 +3350,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec52_p026, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec53_r126, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_26_0, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec52_p026, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec53_r126, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_26_0, DOB1=>mdout1_26_1, DOB2=>mdout1_26_2, DOB3=>mdout1_26_3, DOB4=>mdout1_26_4, DOB5=>mdout1_26_5, DOB6=>mdout1_26_6, DOB7=>mdout1_26_7, DOB8=>mdout1_26_8, DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - pdp_ram_27_0_4: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + pdp_ram_27_0_4: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -4296,37 +3389,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec54_p027, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec55_r127, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_27_0, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec54_p027, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec55_r127, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_27_0, DOB1=>mdout1_27_1, DOB2=>mdout1_27_2, DOB3=>mdout1_27_3, DOB4=>mdout1_27_4, DOB5=>mdout1_27_5, DOB6=>mdout1_27_6, DOB7=>mdout1_27_7, DOB8=>mdout1_27_8, DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - pdp_ram_28_0_3: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + pdp_ram_28_0_3: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -4336,37 +3428,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec56_p028, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec57_r128, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_28_0, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec56_p028, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec57_r128, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_28_0, DOB1=>mdout1_28_1, DOB2=>mdout1_28_2, DOB3=>mdout1_28_3, DOB4=>mdout1_28_4, DOB5=>mdout1_28_5, DOB6=>mdout1_28_6, DOB7=>mdout1_28_7, DOB8=>mdout1_28_8, DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - pdp_ram_29_0_2: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + pdp_ram_29_0_2: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -4376,37 +3467,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec58_p029, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec59_r129, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_29_0, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec58_p029, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec59_r129, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_29_0, DOB1=>mdout1_29_1, DOB2=>mdout1_29_2, DOB3=>mdout1_29_3, DOB4=>mdout1_29_4, DOB5=>mdout1_29_5, DOB6=>mdout1_29_6, DOB7=>mdout1_29_7, DOB8=>mdout1_29_8, DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - pdp_ram_30_0_1: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + pdp_ram_30_0_1: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -4416,37 +3506,36 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec60_p030, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec61_r130, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_30_0, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec60_p030, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec61_r130, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_30_0, DOB1=>mdout1_30_1, DOB2=>mdout1_30_2, DOB3=>mdout1_30_3, DOB4=>mdout1_30_4, DOB5=>mdout1_30_5, DOB6=>mdout1_30_6, DOB7=>mdout1_30_7, DOB8=>mdout1_30_8, DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - pdp_ram_31_0_0: DP16KB - -- synopsys translate_off - generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + pdp_ram_31_0_0: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) - -- synopsys translate_on port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, @@ -4456,24 +3545,25 @@ begin ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, - ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, - CSA0=>dec62_p031, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, - ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, - ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, - CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>dec63_r131, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_31_0, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec62_p031, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec63_r131, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_31_0, DOB1=>mdout1_31_1, DOB2=>mdout1_31_2, DOB3=>mdout1_31_3, DOB4=>mdout1_31_4, DOB5=>mdout1_31_5, DOB6=>mdout1_31_6, DOB7=>mdout1_31_7, DOB8=>mdout1_31_8, DOB9=>open, @@ -4481,1203 +3571,672 @@ begin DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); FF_176: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, Q=>wcount_0); FF_175: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_1); FF_174: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_2); FF_173: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_3); FF_172: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_4); FF_171: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_5); FF_170: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_6); FF_169: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_7); FF_168: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_8); FF_167: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_9); FF_166: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_10); FF_165: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_11); FF_164: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_12); FF_163: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_13); FF_162: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_14); FF_161: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_15); FF_160: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>iwcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_16); FF_159: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_0); FF_158: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_1); FF_157: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_2); FF_156: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_3); FF_155: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_4); FF_154: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_5); FF_153: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_6); FF_152: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_7); FF_151: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_8); FF_150: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_9); FF_149: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_10); FF_148: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_11); FF_147: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_12); FF_146: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_13); FF_145: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_14); FF_144: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gdata_15, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_15); FF_143: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_16); FF_142: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_0); FF_141: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_1); FF_140: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_2); FF_139: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_3); FF_138: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_4); FF_137: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_5); FF_136: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_6); FF_135: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_7); FF_134: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_8); FF_133: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_9); FF_132: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_10); FF_131: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_11); FF_130: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_12); FF_129: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_13); FF_128: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_14); FF_127: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_15); FF_126: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_16); FF_125: FD1P3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, Q=>rcount_0); FF_124: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_1); FF_123: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_2); FF_122: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_3); FF_121: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_4); FF_120: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_5); FF_119: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_6); FF_118: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_7); FF_117: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_8); FF_116: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_9); FF_115: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_10); FF_114: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_11); FF_113: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_12); FF_112: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_13); FF_111: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_14); FF_110: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_15); FF_109: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_16); FF_108: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_0); FF_107: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_1); FF_106: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_2); FF_105: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_3); FF_104: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_4); FF_103: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_5); FF_102: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_6); FF_101: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_7); FF_100: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_8); FF_99: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_9); FF_98: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_10); FF_97: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_11); FF_96: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_12); FF_95: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_13); FF_94: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_14); FF_93: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_15); FF_92: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_16); FF_91: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_0); FF_90: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_1); FF_89: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_2); FF_88: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_3); FF_87: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_4); FF_86: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_5); FF_85: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_6); FF_84: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_7); FF_83: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_8); FF_82: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_9); FF_81: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_10); FF_80: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_11); FF_79: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_12); FF_78: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_13); FF_77: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_14); FF_76: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_15); FF_75: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_16); FF_74: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, Q=>rptr_11_ff); FF_73: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, Q=>rptr_12_ff); FF_72: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, Q=>rptr_13_ff); FF_71: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, Q=>rptr_14_ff); FF_70: FD1P3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, Q=>rptr_15_ff); FF_69: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); FF_68: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); FF_67: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); FF_66: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); FF_65: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); FF_64: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); FF_63: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); FF_62: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); FF_61: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); FF_60: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); FF_59: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, Q=>w_gcount_r10); FF_58: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, Q=>w_gcount_r11); FF_57: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, Q=>w_gcount_r12); FF_56: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, Q=>w_gcount_r13); FF_55: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, Q=>w_gcount_r14); FF_54: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, Q=>w_gcount_r15); FF_53: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_16, CK=>RdClock, CD=>Reset, Q=>w_gcount_r16); FF_52: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); FF_51: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); FF_50: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); FF_49: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); FF_48: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); FF_47: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); FF_46: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); FF_45: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); FF_44: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); FF_43: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); FF_42: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); FF_41: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); FF_40: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); FF_39: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); FF_38: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); FF_37: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); FF_36: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); FF_35: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r20); FF_34: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r21); FF_33: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r22); FF_32: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r23); FF_31: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r24); FF_30: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r25); FF_29: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r26); FF_28: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r27); FF_27: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r28); FF_26: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r29); FF_25: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, Q=>w_gcount_r210); FF_24: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, Q=>w_gcount_r211); FF_23: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, Q=>w_gcount_r212); FF_22: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, Q=>w_gcount_r213); FF_21: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, Q=>w_gcount_r214); FF_20: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, Q=>w_gcount_r215); FF_19: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>w_gcount_r16, CK=>RdClock, CD=>Reset, Q=>w_gcount_r216); FF_18: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); FF_17: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); FF_16: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); FF_15: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); FF_14: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); FF_13: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); FF_12: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); FF_11: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); FF_10: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); FF_9: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); FF_8: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w210); FF_7: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w211); FF_6: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w212); FF_5: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w213); FF_4: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w214); FF_3: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w215); FF_2: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w216); FF_1: FD1S3BX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); FF_0: FD1S3DX - -- synopsys translate_off - generic map (GSR=> "ENABLED") - -- synopsys translate_on port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); w_gctr_cia: FADD2B @@ -5998,25 +4557,25 @@ begin end Structure; -- synopsys translate_off -library ecp2m; +library ecp3; configuration Structure_CON of fifo_64kx9 is for Structure - for all:AGEB2 use entity ecp2m.AGEB2(V); end for; - for all:AND2 use entity ecp2m.AND2(V); end for; - for all:CU2 use entity ecp2m.CU2(V); end for; - for all:FADD2B use entity ecp2m.FADD2B(V); end for; - for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; - for all:INV use entity ecp2m.INV(V); end for; - for all:MUX321 use entity ecp2m.MUX321(V); end for; - for all:OR2 use entity ecp2m.OR2(V); end for; - for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:XOR2 use entity ecp2m.XOR2(V); end for; - for all:DP16KB use entity ecp2m.DP16KB(V); end for; + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:MUX321 use entity ecp3.MUX321(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; end for; end Structure_CON; diff --git a/gbe_ecp2m/ipcores/fifo_64kx9_generate.log b/gbe_ecp2m/ipcores/fifo_64kx9_generate.log index 923ed74..6860ef8 100644 --- a/gbe_ecp2m/ipcores/fifo_64kx9_generate.log +++ b/gbe_ecp2m/ipcores/fifo_64kx9_generate.log @@ -1,17 +1,19 @@ +Starting process: module + Starting process: -SCUBA, Version ispLever_v8.0_PROD_Build (41) -Mon Jul 26 21:40:04 2010 +SCUBA, Version Diamond_1.3_Production (92) +Thu Sep 22 11:23:21 2011 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved. +Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. BEGIN SCUBA Module Synthesis - Issued command : /opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n fifo_64kx9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 16 -data_width 9 -num_words 65536 -rdata_width 9 -no_enable -pe -1 -pf -1 -e + Issued command : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo_64kx9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 16 -data_width 9 -num_words 65536 -rdata_width 9 -no_enable -pe -1 -pf -1 -e Circuit name : fifo_64kx9 Module type : ebfifo Module Version : 5.4 diff --git a/gbe_ecp2m/ipcores/fifo_64kx9_tmpl.vhd b/gbe_ecp2m/ipcores/fifo_64kx9_tmpl.vhd index 741989d..a9d000b 100644 --- a/gbe_ecp2m/ipcores/fifo_64kx9_tmpl.vhd +++ b/gbe_ecp2m/ipcores/fifo_64kx9_tmpl.vhd @@ -1,6 +1,6 @@ --- VHDL module instantiation generated by SCUBA ispLever_v8.0_PROD_Build (41) +-- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) -- Module Version: 5.4 --- Mon Jul 26 21:40:04 2010 +-- Thu Sep 22 11:23:21 2011 -- parameterized module component declaration component fifo_64kx9 diff --git a/gbe_ecp2m/ipcores/ip_mem.lpc b/gbe_ecp2m/ipcores/ip_mem.lpc index 8383be6..4c9ab25 100755 --- a/gbe_ecp2m/ipcores/ip_mem.lpc +++ b/gbe_ecp2m/ipcores/ip_mem.lpc @@ -1,9 +1,9 @@ [Device] -Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-5F900C -SpeedGrade=-5 -Package=FPBGA900 +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 OperatingCondition=COM Status=P @@ -14,10 +14,10 @@ CoreStatus=Demo CoreName=RAM_DP_TRUE CoreRevision=7.1 ModuleName=ip_mem -SourceFormat=Schematic/VHDL +SourceFormat=VHDL ParameterFileVersion=1.0 -Date=03/29/2010 -Time=21:52:48 +Date=09/22/2011 +Time=11:24:37 [Parameters] Verilog=0 @@ -45,7 +45,7 @@ AInData=Registered BInData=Registered AAdControl=Registered BAdControl=Registered -MemFile=/home/greg/projects/HubGen3/NewHub3/hub2/ipexpress/ip_mem/ip_mem.mem +MemFile=ip_mem.mem MemFormat=orca Reset=Sync GSR=Enabled @@ -55,3 +55,6 @@ Pad=0 EnECC=0 Optimization=Speed Pipeline=0 + +[FilesGenerated] +ip_mem.mem=mem diff --git a/gbe_ecp2m/ipcores/ip_mem.vhd b/gbe_ecp2m/ipcores/ip_mem.vhd index cfa2c6e..5b2e06e 100755 --- a/gbe_ecp2m/ipcores/ip_mem.vhd +++ b/gbe_ecp2m/ipcores/ip_mem.vhd @@ -1,14 +1,14 @@ --- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) -- Module Version: 7.1 ---/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type bram -wp 11 -rp 1010 -data_width 32 -rdata_width 32 -num_rows 256 -outdataB REGISTERED -writemodeA NORMAL -writemodeB NORMAL -resetmode SYNC -memfile /home/greg/projects/HubGen3/NewHub3/hub2/ipexpress/ip_mem/ip_mem.mem -memformat orca -cascade -1 -e +--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 11 -rp 1010 -data_width 32 -rdata_width 32 -num_rows 256 -outdataB REGISTERED -writemodeA NORMAL -writemodeB NORMAL -memfile ip_mem.mem -memformat orca -cascade -1 -e --- Mon Mar 29 21:52:49 2010 +-- Thu Sep 22 11:24:37 2011 library IEEE; use IEEE.std_logic_1164.all; -- synopsys translate_off -library ecp2m; -use ecp2m.components.all; +library ecp3; +use ecp3.components.all; -- synopsys translate_on entity ip_mem is @@ -42,8 +42,7 @@ architecture Structure of ip_mem is component VLO port (Z: out std_logic); end component; - component DP16KB - -- synopsys translate_off + component DP16KC generic (INITVAL_3F : in String; INITVAL_3E : in String; INITVAL_3D : in String; INITVAL_3C : in String; INITVAL_3B : in String; INITVAL_3A : in String; @@ -77,12 +76,10 @@ architecture Structure of ip_mem is INITVAL_03 : in String; INITVAL_02 : in String; INITVAL_01 : in String; INITVAL_00 : in String; GSR : in String; WRITEMODE_B : in String; - CSDECODE_B : in std_logic_vector(2 downto 0); - CSDECODE_A : in std_logic_vector(2 downto 0); - WRITEMODE_A : in String; RESETMODE : in String; - REGMODE_B : in String; REGMODE_A : in String; - DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); - -- synopsys translate_on + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); port (DIA0: in std_logic; DIA1: in std_logic; DIA2: in std_logic; DIA3: in std_logic; DIA4: in std_logic; DIA5: in std_logic; @@ -99,8 +96,8 @@ architecture Structure of ip_mem is ADA8: in std_logic; ADA9: in std_logic; ADA10: in std_logic; ADA11: in std_logic; ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; - CSA0: in std_logic; CSA1: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; CSA2: in std_logic; RSTA: in std_logic; DIB0: in std_logic; DIB1: in std_logic; DIB2: in std_logic; DIB3: in std_logic; @@ -118,8 +115,8 @@ architecture Structure of ip_mem is ADB8: in std_logic; ADB9: in std_logic; ADB10: in std_logic; ADB11: in std_logic; ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; - CSB0: in std_logic; CSB1: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; CSB2: in std_logic; RSTB: in std_logic; DOA0: out std_logic; DOA1: out std_logic; DOA2: out std_logic; DOA3: out std_logic; @@ -142,237 +139,17 @@ architecture Structure of ip_mem is end component; attribute MEM_LPC_FILE : string; attribute MEM_INIT_FILE : string; - attribute INITVAL_3F : string; - attribute INITVAL_3E : string; - attribute INITVAL_3D : string; - attribute INITVAL_3C : string; - attribute INITVAL_3B : string; - attribute INITVAL_3A : string; - attribute INITVAL_39 : string; - attribute INITVAL_38 : string; - attribute INITVAL_37 : string; - attribute INITVAL_36 : string; - attribute INITVAL_35 : string; - attribute INITVAL_34 : string; - attribute INITVAL_33 : string; - attribute INITVAL_32 : string; - attribute INITVAL_31 : string; - attribute INITVAL_30 : string; - attribute INITVAL_2F : string; - attribute INITVAL_2E : string; - attribute INITVAL_2D : string; - attribute INITVAL_2C : string; - attribute INITVAL_2B : string; - attribute INITVAL_2A : string; - attribute INITVAL_29 : string; - attribute INITVAL_28 : string; - attribute INITVAL_27 : string; - attribute INITVAL_26 : string; - attribute INITVAL_25 : string; - attribute INITVAL_24 : string; - attribute INITVAL_23 : string; - attribute INITVAL_22 : string; - attribute INITVAL_21 : string; - attribute INITVAL_20 : string; - attribute INITVAL_1F : string; - attribute INITVAL_1E : string; - attribute INITVAL_1D : string; - attribute INITVAL_1C : string; - attribute INITVAL_1B : string; - attribute INITVAL_1A : string; - attribute INITVAL_19 : string; - attribute INITVAL_18 : string; - attribute INITVAL_17 : string; - attribute INITVAL_16 : string; - attribute INITVAL_15 : string; - attribute INITVAL_14 : string; - attribute INITVAL_13 : string; - attribute INITVAL_12 : string; - attribute INITVAL_11 : string; - attribute INITVAL_10 : string; - attribute INITVAL_0F : string; - attribute INITVAL_0E : string; - attribute INITVAL_0D : string; - attribute INITVAL_0C : string; - attribute INITVAL_0B : string; - attribute INITVAL_0A : string; - attribute INITVAL_09 : string; - attribute INITVAL_08 : string; - attribute INITVAL_07 : string; - attribute INITVAL_06 : string; - attribute INITVAL_05 : string; - attribute INITVAL_04 : string; - attribute INITVAL_03 : string; - attribute INITVAL_02 : string; - attribute INITVAL_01 : string; - attribute INITVAL_00 : string; - attribute CSDECODE_B : string; - attribute CSDECODE_A : string; - attribute WRITEMODE_B : string; - attribute WRITEMODE_A : string; - attribute GSR : string; attribute RESETMODE : string; - attribute REGMODE_B : string; - attribute REGMODE_A : string; - attribute DATA_WIDTH_B : string; - attribute DATA_WIDTH_A : string; attribute MEM_LPC_FILE of ip_mem_0_0_1 : label is "ip_mem.lpc"; attribute MEM_INIT_FILE of ip_mem_0_0_1 : label is "ip_mem.mem"; - attribute INITVAL_3F of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3E of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3D of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3C of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3B of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3A of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_39 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_38 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_37 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_36 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_35 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_34 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_33 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_32 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_31 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_30 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2F of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2E of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2D of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2C of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2B of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2A of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_29 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_28 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_27 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_26 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_25 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_24 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_23 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_22 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_21 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_20 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1F of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1E of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1D of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1C of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1B of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1A of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_19 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_18 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_17 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_16 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_15 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_14 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_13 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_12 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_11 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_10 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_0F of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; - attribute INITVAL_0E of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; - attribute INITVAL_0D of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; - attribute INITVAL_0C of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; - attribute INITVAL_0B of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; - attribute INITVAL_0A of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; - attribute INITVAL_09 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; - attribute INITVAL_08 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; - attribute INITVAL_07 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; - attribute INITVAL_06 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; - attribute INITVAL_05 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; - attribute INITVAL_04 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000"; - attribute INITVAL_03 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780C35000008000133DC030C353000020001B397E9"; - attribute INITVAL_02 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780C35000007000133DC020C352000020001B397E9"; - attribute INITVAL_01 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780C35000006000133DC010C351000020001B397E9"; - attribute INITVAL_00 of ip_mem_0_0_1 : label is "0x00000000000000000000000000000000000005780C35000005000133DC000C350000020001B397E9"; - attribute CSDECODE_B of ip_mem_0_0_1 : label is "0b000"; - attribute CSDECODE_A of ip_mem_0_0_1 : label is "0b000"; - attribute WRITEMODE_B of ip_mem_0_0_1 : label is "NORMAL"; - attribute WRITEMODE_A of ip_mem_0_0_1 : label is "NORMAL"; - attribute GSR of ip_mem_0_0_1 : label is "DISABLED"; attribute RESETMODE of ip_mem_0_0_1 : label is "SYNC"; - attribute REGMODE_B of ip_mem_0_0_1 : label is "OUTREG"; - attribute REGMODE_A of ip_mem_0_0_1 : label is "NOREG"; - attribute DATA_WIDTH_B of ip_mem_0_0_1 : label is "18"; - attribute DATA_WIDTH_A of ip_mem_0_0_1 : label is "18"; attribute MEM_LPC_FILE of ip_mem_0_1_0 : label is "ip_mem.lpc"; attribute MEM_INIT_FILE of ip_mem_0_1_0 : label is "ip_mem.mem"; - attribute INITVAL_3F of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3E of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3D of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3C of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3B of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3A of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_39 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_38 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_37 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_36 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_35 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_34 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_33 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_32 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_31 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_30 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2F of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2E of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2D of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2C of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2B of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2A of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_29 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_28 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_27 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_26 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_25 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_24 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_23 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_22 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_21 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_20 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1F of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1E of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1D of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1C of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1B of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1A of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_19 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_18 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_17 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_16 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_15 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_14 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_13 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_12 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_11 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_10 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_0F of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_0E of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_0D of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_0C of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_0B of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_0A of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_09 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_08 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_07 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_06 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_05 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_04 of ip_mem_0_1_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_03 of ip_mem_0_1_0 : label is "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850"; - attribute INITVAL_02 of ip_mem_0_1_0 : label is "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850"; - attribute INITVAL_01 of ip_mem_0_1_0 : label is "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850"; - attribute INITVAL_00 of ip_mem_0_1_0 : label is "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850"; - attribute CSDECODE_B of ip_mem_0_1_0 : label is "0b000"; - attribute CSDECODE_A of ip_mem_0_1_0 : label is "0b000"; - attribute WRITEMODE_B of ip_mem_0_1_0 : label is "NORMAL"; - attribute WRITEMODE_A of ip_mem_0_1_0 : label is "NORMAL"; - attribute GSR of ip_mem_0_1_0 : label is "DISABLED"; attribute RESETMODE of ip_mem_0_1_0 : label is "SYNC"; - attribute REGMODE_B of ip_mem_0_1_0 : label is "OUTREG"; - attribute REGMODE_A of ip_mem_0_1_0 : label is "NOREG"; - attribute DATA_WIDTH_B of ip_mem_0_1_0 : label is "18"; - attribute DATA_WIDTH_A of ip_mem_0_1_0 : label is "18"; begin -- component instantiation statements - ip_mem_0_0_1: DP16KB - -- synopsys translate_off + ip_mem_0_0_1: DP16KC generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", @@ -437,11 +214,9 @@ begin INITVAL_02=> "0x00000000000000000000000000000000000005780C35000007000133DC020C352000020001B397E9", INITVAL_01=> "0x00000000000000000000000000000000000005780C35000006000133DC010C351000020001B397E9", INITVAL_00=> "0x00000000000000000000000000000000000005780C35000005000133DC000C350000020001B397E9", - CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", - REGMODE_B=> "OUTREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, - DATA_WIDTH_A=> 18) - -- synopsys translate_on + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "OUTREG", + REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18) port map (DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2), DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5), DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8), @@ -453,30 +228,30 @@ begin ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4), ADA9=>AddressA(5), ADA10=>AddressA(6), ADA11=>AddressA(7), ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>ClockEnA, - CLKA=>ClockA, WEA=>WrA, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>ResetA, DIB0=>DataInB(0), - DIB1=>DataInB(1), DIB2=>DataInB(2), DIB3=>DataInB(3), - DIB4=>DataInB(4), DIB5=>DataInB(5), DIB6=>DataInB(6), - DIB7=>DataInB(7), DIB8=>DataInB(8), DIB9=>DataInB(9), - DIB10=>DataInB(10), DIB11=>DataInB(11), DIB12=>DataInB(12), - DIB13=>DataInB(13), DIB14=>DataInB(14), DIB15=>DataInB(15), - DIB16=>DataInB(16), DIB17=>DataInB(17), ADB0=>scuba_vhi, - ADB1=>scuba_vhi, ADB2=>scuba_vlo, ADB3=>scuba_vlo, - ADB4=>AddressB(0), ADB5=>AddressB(1), ADB6=>AddressB(2), - ADB7=>AddressB(3), ADB8=>AddressB(4), ADB9=>AddressB(5), - ADB10=>AddressB(6), ADB11=>AddressB(7), ADB12=>scuba_vlo, - ADB13=>scuba_vlo, CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>ResetB, DOA0=>QA(0), DOA1=>QA(1), DOA2=>QA(2), - DOA3=>QA(3), DOA4=>QA(4), DOA5=>QA(5), DOA6=>QA(6), - DOA7=>QA(7), DOA8=>QA(8), DOA9=>QA(9), DOA10=>QA(10), - DOA11=>QA(11), DOA12=>QA(12), DOA13=>QA(13), DOA14=>QA(14), - DOA15=>QA(15), DOA16=>QA(16), DOA17=>QA(17), DOB0=>QB(0), - DOB1=>QB(1), DOB2=>QB(2), DOB3=>QB(3), DOB4=>QB(4), - DOB5=>QB(5), DOB6=>QB(6), DOB7=>QB(7), DOB8=>QB(8), - DOB9=>QB(9), DOB10=>QB(10), DOB11=>QB(11), DOB12=>QB(12), - DOB13=>QB(13), DOB14=>QB(14), DOB15=>QB(15), DOB16=>QB(16), - DOB17=>QB(17)); + CLKA=>ClockA, OCEA=>ClockEnA, WEA=>WrA, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>ResetA, + DIB0=>DataInB(0), DIB1=>DataInB(1), DIB2=>DataInB(2), + DIB3=>DataInB(3), DIB4=>DataInB(4), DIB5=>DataInB(5), + DIB6=>DataInB(6), DIB7=>DataInB(7), DIB8=>DataInB(8), + DIB9=>DataInB(9), DIB10=>DataInB(10), DIB11=>DataInB(11), + DIB12=>DataInB(12), DIB13=>DataInB(13), DIB14=>DataInB(14), + DIB15=>DataInB(15), DIB16=>DataInB(16), DIB17=>DataInB(17), + ADB0=>scuba_vhi, ADB1=>scuba_vhi, ADB2=>scuba_vlo, + ADB3=>scuba_vlo, ADB4=>AddressB(0), ADB5=>AddressB(1), + ADB6=>AddressB(2), ADB7=>AddressB(3), ADB8=>AddressB(4), + ADB9=>AddressB(5), ADB10=>AddressB(6), ADB11=>AddressB(7), + ADB12=>scuba_vlo, ADB13=>scuba_vlo, CEB=>ClockEnB, + CLKB=>ClockB, OCEB=>ClockEnB, WEB=>WrB, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>ResetB, DOA0=>QA(0), + DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>QA(4), + DOA5=>QA(5), DOA6=>QA(6), DOA7=>QA(7), DOA8=>QA(8), + DOA9=>QA(9), DOA10=>QA(10), DOA11=>QA(11), DOA12=>QA(12), + DOA13=>QA(13), DOA14=>QA(14), DOA15=>QA(15), DOA16=>QA(16), + DOA17=>QA(17), DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2), + DOB3=>QB(3), DOB4=>QB(4), DOB5=>QB(5), DOB6=>QB(6), + DOB7=>QB(7), DOB8=>QB(8), DOB9=>QB(9), DOB10=>QB(10), + DOB11=>QB(11), DOB12=>QB(12), DOB13=>QB(13), DOB14=>QB(14), + DOB15=>QB(15), DOB16=>QB(16), DOB17=>QB(17)); scuba_vhi_inst: VHI port map (Z=>scuba_vhi); @@ -484,8 +259,7 @@ begin scuba_vlo_inst: VLO port map (Z=>scuba_vlo); - ip_mem_0_1_0: DP16KB - -- synopsys translate_off + ip_mem_0_1_0: DP16KC generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", @@ -550,11 +324,9 @@ begin INITVAL_02=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", INITVAL_01=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", INITVAL_00=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", - CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", - REGMODE_B=> "OUTREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, - DATA_WIDTH_A=> 18) - -- synopsys translate_on + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "OUTREG", + REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18) port map (DIA0=>DataInA(18), DIA1=>DataInA(19), DIA2=>DataInA(20), DIA3=>DataInA(21), DIA4=>DataInA(22), DIA5=>DataInA(23), DIA6=>DataInA(24), DIA7=>DataInA(25), @@ -566,40 +338,41 @@ begin ADA5=>AddressA(1), ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4), ADA9=>AddressA(5), ADA10=>AddressA(6), ADA11=>AddressA(7), ADA12=>scuba_vlo, ADA13=>scuba_vlo, - CEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>ResetA, - DIB0=>DataInB(18), DIB1=>DataInB(19), DIB2=>DataInB(20), - DIB3=>DataInB(21), DIB4=>DataInB(22), DIB5=>DataInB(23), - DIB6=>DataInB(24), DIB7=>DataInB(25), DIB8=>DataInB(26), - DIB9=>DataInB(27), DIB10=>DataInB(28), DIB11=>DataInB(29), - DIB12=>DataInB(30), DIB13=>DataInB(31), DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vhi, ADB1=>scuba_vhi, ADB2=>scuba_vlo, - ADB3=>scuba_vlo, ADB4=>AddressB(0), ADB5=>AddressB(1), - ADB6=>AddressB(2), ADB7=>AddressB(3), ADB8=>AddressB(4), - ADB9=>AddressB(5), ADB10=>AddressB(6), ADB11=>AddressB(7), - ADB12=>scuba_vlo, ADB13=>scuba_vlo, CEB=>ClockEnB, - CLKB=>ClockB, WEB=>WrB, CSB0=>scuba_vlo, CSB1=>scuba_vlo, - CSB2=>scuba_vlo, RSTB=>ResetB, DOA0=>QA(18), DOA1=>QA(19), - DOA2=>QA(20), DOA3=>QA(21), DOA4=>QA(22), DOA5=>QA(23), - DOA6=>QA(24), DOA7=>QA(25), DOA8=>QA(26), DOA9=>QA(27), - DOA10=>QA(28), DOA11=>QA(29), DOA12=>QA(30), DOA13=>QA(31), - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>QB(18), DOB1=>QB(19), DOB2=>QB(20), DOB3=>QB(21), - DOB4=>QB(22), DOB5=>QB(23), DOB6=>QB(24), DOB7=>QB(25), - DOB8=>QB(26), DOB9=>QB(27), DOB10=>QB(28), DOB11=>QB(29), - DOB12=>QB(30), DOB13=>QB(31), DOB14=>open, DOB15=>open, - DOB16=>open, DOB17=>open); + CEA=>ClockEnA, CLKA=>ClockA, OCEA=>ClockEnA, WEA=>WrA, + CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>ResetA, DIB0=>DataInB(18), DIB1=>DataInB(19), + DIB2=>DataInB(20), DIB3=>DataInB(21), DIB4=>DataInB(22), + DIB5=>DataInB(23), DIB6=>DataInB(24), DIB7=>DataInB(25), + DIB8=>DataInB(26), DIB9=>DataInB(27), DIB10=>DataInB(28), + DIB11=>DataInB(29), DIB12=>DataInB(30), DIB13=>DataInB(31), + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vhi, ADB1=>scuba_vhi, + ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>AddressB(0), + ADB5=>AddressB(1), ADB6=>AddressB(2), ADB7=>AddressB(3), + ADB8=>AddressB(4), ADB9=>AddressB(5), ADB10=>AddressB(6), + ADB11=>AddressB(7), ADB12=>scuba_vlo, ADB13=>scuba_vlo, + CEB=>ClockEnB, CLKB=>ClockB, OCEB=>ClockEnB, WEB=>WrB, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>ResetB, DOA0=>QA(18), DOA1=>QA(19), DOA2=>QA(20), + DOA3=>QA(21), DOA4=>QA(22), DOA5=>QA(23), DOA6=>QA(24), + DOA7=>QA(25), DOA8=>QA(26), DOA9=>QA(27), DOA10=>QA(28), + DOA11=>QA(29), DOA12=>QA(30), DOA13=>QA(31), DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>QB(18), + DOB1=>QB(19), DOB2=>QB(20), DOB3=>QB(21), DOB4=>QB(22), + DOB5=>QB(23), DOB6=>QB(24), DOB7=>QB(25), DOB8=>QB(26), + DOB9=>QB(27), DOB10=>QB(28), DOB11=>QB(29), DOB12=>QB(30), + DOB13=>QB(31), DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); end Structure; -- synopsys translate_off -library ecp2m; +library ecp3; configuration Structure_CON of ip_mem is for Structure - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:DP16KB use entity ecp2m.DP16KB(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; end for; end Structure_CON; diff --git a/gbe_ecp2m/ipcores/ip_mem_tmpl.vhd b/gbe_ecp2m/ipcores/ip_mem_tmpl.vhd index 7d1cea6..d516b11 100755 --- a/gbe_ecp2m/ipcores/ip_mem_tmpl.vhd +++ b/gbe_ecp2m/ipcores/ip_mem_tmpl.vhd @@ -1,6 +1,6 @@ --- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) -- Module Version: 7.1 --- Mon Mar 29 21:52:49 2010 +-- Thu Sep 22 11:24:37 2011 -- parameterized module component declaration component ip_mem diff --git a/gbe_ecp2m/ipcores/mac_init_mem.lpc b/gbe_ecp2m/ipcores/mac_init_mem.lpc index 02c8376..42f57b0 100755 --- a/gbe_ecp2m/ipcores/mac_init_mem.lpc +++ b/gbe_ecp2m/ipcores/mac_init_mem.lpc @@ -1,45 +1,48 @@ -[Device] -Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-6F900C -SpeedGrade=-6 -Package=FPBGA900 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=ROM -CoreRevision=5.0 -ModuleName=mac_init_mem -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=08/20/2009 -Time=16:00:49 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -Address=54 -Data=8 -adPipeline=0 -inPipeline=0 -outPipeline=1 -MOR=0 -InData=Registered -AdControl=Registered -MemFile=/home/greg/NewHub2/hub2/ipexpress/mac_init_mem/macInitDataInvWithMac.mem -MemFormat=bin -Reset=Sync -Pad=0 -GSR=Enabled -EnECC=0 -Optimization=Speed -Pipeline=0 +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=ROM +CoreRevision=5.0 +ModuleName=mac_init_mem +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/22/2011 +Time=11:24:53 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Address=54 +Data=8 +adPipeline=0 +inPipeline=0 +outPipeline=1 +MOR=0 +InData=Registered +AdControl=Registered +MemFile=macInitDataInvWithMac.mem +MemFormat=bin +Reset=Sync +Pad=0 +GSR=Enabled +EnECC=0 +Optimization=Speed +Pipeline=0 + +[FilesGenerated] +macInitDataInvWithMac.mem=mem diff --git a/gbe_ecp2m/ipcores/mac_init_mem.vhd b/gbe_ecp2m/ipcores/mac_init_mem.vhd index c2c95e4..3934a61 100755 --- a/gbe_ecp2m/ipcores/mac_init_mem.vhd +++ b/gbe_ecp2m/ipcores/mac_init_mem.vhd @@ -1,413 +1,262 @@ --- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) --- Module Version: 5.0 ---/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type bram -wp 00 -rp 1100 -addr_width 6 -data_width 8 -num_rows 54 -outdata REGISTERED -resetmode SYNC -memfile /home/greg/NewHub2/hub2/ipexpress/mac_init_mem/macInitDataInvWithMac.mem -memformat bin -cascade -1 -e - --- Thu Aug 20 16:00:49 2009 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp2m; -use ecp2m.components.all; --- synopsys translate_on - -entity mac_init_mem is - port ( - Address: in std_logic_vector(5 downto 0); - OutClock: in std_logic; - OutClockEn: in std_logic; - Reset: in std_logic; - Q: out std_logic_vector(7 downto 0)); -end mac_init_mem; - -architecture Structure of mac_init_mem is - - -- internal signal declarations - signal scuba_vhi: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component DP16KB - -- synopsys translate_off - generic (INITVAL_3F : in String; INITVAL_3E : in String; - INITVAL_3D : in String; INITVAL_3C : in String; - INITVAL_3B : in String; INITVAL_3A : in String; - INITVAL_39 : in String; INITVAL_38 : in String; - INITVAL_37 : in String; INITVAL_36 : in String; - INITVAL_35 : in String; INITVAL_34 : in String; - INITVAL_33 : in String; INITVAL_32 : in String; - INITVAL_31 : in String; INITVAL_30 : in String; - INITVAL_2F : in String; INITVAL_2E : in String; - INITVAL_2D : in String; INITVAL_2C : in String; - INITVAL_2B : in String; INITVAL_2A : in String; - INITVAL_29 : in String; INITVAL_28 : in String; - INITVAL_27 : in String; INITVAL_26 : in String; - INITVAL_25 : in String; INITVAL_24 : in String; - INITVAL_23 : in String; INITVAL_22 : in String; - INITVAL_21 : in String; INITVAL_20 : in String; - INITVAL_1F : in String; INITVAL_1E : in String; - INITVAL_1D : in String; INITVAL_1C : in String; - INITVAL_1B : in String; INITVAL_1A : in String; - INITVAL_19 : in String; INITVAL_18 : in String; - INITVAL_17 : in String; INITVAL_16 : in String; - INITVAL_15 : in String; INITVAL_14 : in String; - INITVAL_13 : in String; INITVAL_12 : in String; - INITVAL_11 : in String; INITVAL_10 : in String; - INITVAL_0F : in String; INITVAL_0E : in String; - INITVAL_0D : in String; INITVAL_0C : in String; - INITVAL_0B : in String; INITVAL_0A : in String; - INITVAL_09 : in String; INITVAL_08 : in String; - INITVAL_07 : in String; INITVAL_06 : in String; - INITVAL_05 : in String; INITVAL_04 : in String; - INITVAL_03 : in String; INITVAL_02 : in String; - INITVAL_01 : in String; INITVAL_00 : in String; - GSR : in String; WRITEMODE_B : in String; - CSDECODE_B : in std_logic_vector(2 downto 0); - CSDECODE_A : in std_logic_vector(2 downto 0); - WRITEMODE_A : in String; RESETMODE : in String; - REGMODE_B : in String; REGMODE_A : in String; - DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); - -- synopsys translate_on - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; - CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; - CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute INITVAL_3F : string; - attribute INITVAL_3E : string; - attribute INITVAL_3D : string; - attribute INITVAL_3C : string; - attribute INITVAL_3B : string; - attribute INITVAL_3A : string; - attribute INITVAL_39 : string; - attribute INITVAL_38 : string; - attribute INITVAL_37 : string; - attribute INITVAL_36 : string; - attribute INITVAL_35 : string; - attribute INITVAL_34 : string; - attribute INITVAL_33 : string; - attribute INITVAL_32 : string; - attribute INITVAL_31 : string; - attribute INITVAL_30 : string; - attribute INITVAL_2F : string; - attribute INITVAL_2E : string; - attribute INITVAL_2D : string; - attribute INITVAL_2C : string; - attribute INITVAL_2B : string; - attribute INITVAL_2A : string; - attribute INITVAL_29 : string; - attribute INITVAL_28 : string; - attribute INITVAL_27 : string; - attribute INITVAL_26 : string; - attribute INITVAL_25 : string; - attribute INITVAL_24 : string; - attribute INITVAL_23 : string; - attribute INITVAL_22 : string; - attribute INITVAL_21 : string; - attribute INITVAL_20 : string; - attribute INITVAL_1F : string; - attribute INITVAL_1E : string; - attribute INITVAL_1D : string; - attribute INITVAL_1C : string; - attribute INITVAL_1B : string; - attribute INITVAL_1A : string; - attribute INITVAL_19 : string; - attribute INITVAL_18 : string; - attribute INITVAL_17 : string; - attribute INITVAL_16 : string; - attribute INITVAL_15 : string; - attribute INITVAL_14 : string; - attribute INITVAL_13 : string; - attribute INITVAL_12 : string; - attribute INITVAL_11 : string; - attribute INITVAL_10 : string; - attribute INITVAL_0F : string; - attribute INITVAL_0E : string; - attribute INITVAL_0D : string; - attribute INITVAL_0C : string; - attribute INITVAL_0B : string; - attribute INITVAL_0A : string; - attribute INITVAL_09 : string; - attribute INITVAL_08 : string; - attribute INITVAL_07 : string; - attribute INITVAL_06 : string; - attribute INITVAL_05 : string; - attribute INITVAL_04 : string; - attribute INITVAL_03 : string; - attribute INITVAL_02 : string; - attribute INITVAL_01 : string; - attribute INITVAL_00 : string; - attribute CSDECODE_B : string; - attribute CSDECODE_A : string; - attribute WRITEMODE_B : string; - attribute WRITEMODE_A : string; - attribute GSR : string; - attribute RESETMODE : string; - attribute REGMODE_B : string; - attribute REGMODE_A : string; - attribute DATA_WIDTH_B : string; - attribute DATA_WIDTH_A : string; - attribute MEM_LPC_FILE of mac_init_mem_0_0_0 : label is "mac_init_mem.lpc"; - attribute MEM_INIT_FILE of mac_init_mem_0_0_0 : label is "macInitDataInvWithMac.mem"; - attribute INITVAL_3F of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3E of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3D of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3C of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3B of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_3A of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_39 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_38 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_37 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_36 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_35 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_34 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_33 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_32 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_31 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_30 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2F of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2E of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2D of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2C of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2B of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_2A of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_29 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_28 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_27 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_26 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_25 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_24 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_23 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_22 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_21 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_20 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1F of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1E of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1D of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1C of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1B of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_1A of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_19 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_18 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_17 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_16 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_15 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_14 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_13 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_12 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_11 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_10 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_0F of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_0E of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_0D of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_0C of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_0B of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_0A of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_09 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_08 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_07 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_06 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_05 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_04 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_03 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_02 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - attribute INITVAL_01 of mac_init_mem_0_0_0 : label is "0x00000000000000000000000000008000000000000000000000000000000000000000000000000000"; - attribute INITVAL_00 of mac_init_mem_0_0_0 : label is "0x0000000000000000000000000000000000000000134BC0AC78024340000C0000000AEE0029901E0F"; - attribute CSDECODE_B of mac_init_mem_0_0_0 : label is "0b111"; - attribute CSDECODE_A of mac_init_mem_0_0_0 : label is "0b000"; - attribute WRITEMODE_B of mac_init_mem_0_0_0 : label is "NORMAL"; - attribute WRITEMODE_A of mac_init_mem_0_0_0 : label is "NORMAL"; - attribute GSR of mac_init_mem_0_0_0 : label is "DISABLED"; - attribute RESETMODE of mac_init_mem_0_0_0 : label is "SYNC"; - attribute REGMODE_B of mac_init_mem_0_0_0 : label is "NOREG"; - attribute REGMODE_A of mac_init_mem_0_0_0 : label is "OUTREG"; - attribute DATA_WIDTH_B of mac_init_mem_0_0_0 : label is "9"; - attribute DATA_WIDTH_A of mac_init_mem_0_0_0 : label is "9"; - -begin - -- component instantiation statements - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - mac_init_mem_0_0_0: DP16KB - -- synopsys translate_off - generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_03=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_02=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_01=> "0x00000000000000000000000000008000000000000000000000000000000000000000000000000000", - INITVAL_00=> "0x0000000000000000000000000000000000000000134BC0AC78024340000C0000000AEE0029901E0F", - CSDECODE_B=> "111", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - -- synopsys translate_on - port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, - ADA3=>Address(0), ADA4=>Address(1), ADA5=>Address(2), - ADA6=>Address(3), ADA7=>Address(4), ADA8=>Address(5), - ADA9=>scuba_vlo, ADA10=>scuba_vlo, ADA11=>scuba_vlo, - ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>OutClockEn, - CLKA=>OutClock, WEA=>scuba_vlo, CSA0=>scuba_vlo, - CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, - DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, - DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, - DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, - DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, - DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, - DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, - ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>scuba_vlo, ADB4=>scuba_vlo, ADB5=>scuba_vlo, - ADB6=>scuba_vlo, ADB7=>scuba_vlo, ADB8=>scuba_vlo, - ADB9=>scuba_vlo, ADB10=>scuba_vlo, ADB11=>scuba_vlo, - ADB12=>scuba_vlo, ADB13=>scuba_vlo, CEB=>scuba_vhi, - CLKB=>scuba_vlo, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>scuba_vlo, - DOA0=>Q(0), DOA1=>Q(1), DOA2=>Q(2), DOA3=>Q(3), DOA4=>Q(4), - DOA5=>Q(5), DOA6=>Q(6), DOA7=>Q(7), DOA8=>open, DOA9=>open, - DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, - DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open, - DOB0=>open, DOB1=>open, DOB2=>open, DOB3=>open, DOB4=>open, - DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, - DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - -end Structure; - --- synopsys translate_off -library ecp2m; -configuration Structure_CON of mac_init_mem is - for Structure - for all:VHI use entity ecp2m.VHI(V); end for; - for all:VLO use entity ecp2m.VLO(V); end for; - for all:DP16KB use entity ecp2m.DP16KB(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.0 +--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 00 -rp 1100 -addr_width 6 -data_width 8 -num_rows 54 -outdata REGISTERED -memfile macInitDataInvWithMac.mem -memformat bin -cascade -1 -e + +-- Thu Sep 22 11:24:53 2011 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity mac_init_mem is + port ( + Address: in std_logic_vector(5 downto 0); + OutClock: in std_logic; + OutClockEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(7 downto 0)); +end mac_init_mem; + +architecture Structure of mac_init_mem is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component DP16KC + generic (INITVAL_3F : in String; INITVAL_3E : in String; + INITVAL_3D : in String; INITVAL_3C : in String; + INITVAL_3B : in String; INITVAL_3A : in String; + INITVAL_39 : in String; INITVAL_38 : in String; + INITVAL_37 : in String; INITVAL_36 : in String; + INITVAL_35 : in String; INITVAL_34 : in String; + INITVAL_33 : in String; INITVAL_32 : in String; + INITVAL_31 : in String; INITVAL_30 : in String; + INITVAL_2F : in String; INITVAL_2E : in String; + INITVAL_2D : in String; INITVAL_2C : in String; + INITVAL_2B : in String; INITVAL_2A : in String; + INITVAL_29 : in String; INITVAL_28 : in String; + INITVAL_27 : in String; INITVAL_26 : in String; + INITVAL_25 : in String; INITVAL_24 : in String; + INITVAL_23 : in String; INITVAL_22 : in String; + INITVAL_21 : in String; INITVAL_20 : in String; + INITVAL_1F : in String; INITVAL_1E : in String; + INITVAL_1D : in String; INITVAL_1C : in String; + INITVAL_1B : in String; INITVAL_1A : in String; + INITVAL_19 : in String; INITVAL_18 : in String; + INITVAL_17 : in String; INITVAL_16 : in String; + INITVAL_15 : in String; INITVAL_14 : in String; + INITVAL_13 : in String; INITVAL_12 : in String; + INITVAL_11 : in String; INITVAL_10 : in String; + INITVAL_0F : in String; INITVAL_0E : in String; + INITVAL_0D : in String; INITVAL_0C : in String; + INITVAL_0B : in String; INITVAL_0A : in String; + INITVAL_09 : in String; INITVAL_08 : in String; + INITVAL_07 : in String; INITVAL_06 : in String; + INITVAL_05 : in String; INITVAL_04 : in String; + INITVAL_03 : in String; INITVAL_02 : in String; + INITVAL_01 : in String; INITVAL_00 : in String; + GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute MEM_LPC_FILE of mac_init_mem_0_0_0 : label is "mac_init_mem.lpc"; + attribute MEM_INIT_FILE of mac_init_mem_0_0_0 : label is "macInitDataInvWithMac.mem"; + attribute RESETMODE of mac_init_mem_0_0_0 : label is "SYNC"; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + mac_init_mem_0_0_0: DP16KC + generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_03=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_02=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_01=> "0x00000000000000000000000000008000000000000000000000000000000000000000000000000000", + INITVAL_00=> "0x0000000000000000000000000000000000000000134BC0AC78024340000C0000000AEE0029901E0F", + CSDECODE_B=> "0b111", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG", + REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, DATA_WIDTH_A=> 9) + port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo, + DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>Address(0), ADA4=>Address(1), ADA5=>Address(2), + ADA6=>Address(3), ADA7=>Address(4), ADA8=>Address(5), + ADA9=>scuba_vlo, ADA10=>scuba_vlo, ADA11=>scuba_vlo, + ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>OutClockEn, + CLKA=>OutClock, OCEA=>OutClockEn, WEA=>scuba_vlo, + CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>scuba_vlo, + ADB5=>scuba_vlo, ADB6=>scuba_vlo, ADB7=>scuba_vlo, + ADB8=>scuba_vlo, ADB9=>scuba_vlo, ADB10=>scuba_vlo, + ADB11=>scuba_vlo, ADB12=>scuba_vlo, ADB13=>scuba_vlo, + CEB=>scuba_vhi, CLKB=>scuba_vlo, OCEB=>scuba_vhi, + WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>scuba_vlo, DOA0=>Q(0), DOA1=>Q(1), + DOA2=>Q(2), DOA3=>Q(3), DOA4=>Q(4), DOA5=>Q(5), DOA6=>Q(6), + DOA7=>Q(7), DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>open, DOB1=>open, DOB2=>open, + DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, + DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of mac_init_mem is + for Structure + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_ecp2m/ipcores/mac_init_mem_tmpl.vhd b/gbe_ecp2m/ipcores/mac_init_mem_tmpl.vhd index 1aee5c2..853efd2 100755 --- a/gbe_ecp2m/ipcores/mac_init_mem_tmpl.vhd +++ b/gbe_ecp2m/ipcores/mac_init_mem_tmpl.vhd @@ -1,15 +1,15 @@ --- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) --- Module Version: 5.0 --- Thu Aug 20 16:00:49 2009 - --- parameterized module component declaration -component mac_init_mem - port (Address: in std_logic_vector(5 downto 0); - OutClock: in std_logic; OutClockEn: in std_logic; - Reset: in std_logic; Q: out std_logic_vector(7 downto 0)); -end component; - --- parameterized module component instance -__ : mac_init_mem - port map (Address(5 downto 0)=>__, OutClock=>__, OutClockEn=>__, - Reset=>__, Q(7 downto 0)=>__); +-- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) +-- Module Version: 5.0 +-- Thu Sep 22 11:24:53 2011 + +-- parameterized module component declaration +component mac_init_mem + port (Address: in std_logic_vector(5 downto 0); + OutClock: in std_logic; OutClockEn: in std_logic; + Reset: in std_logic; Q: out std_logic_vector(7 downto 0)); +end component; + +-- parameterized module component instance +__ : mac_init_mem + port map (Address(5 downto 0)=>__, OutClock=>__, OutClockEn=>__, + Reset=>__, Q(7 downto 0)=>__); diff --git a/gbe_ecp2m/ipcores/sgmii_gbe_pcs32/sgmii_gbe_pcs32.lpc b/gbe_ecp2m/ipcores/sgmii_gbe_pcs32/sgmii_gbe_pcs32.lpc index 6f17c6f..c91da93 100755 --- a/gbe_ecp2m/ipcores/sgmii_gbe_pcs32/sgmii_gbe_pcs32.lpc +++ b/gbe_ecp2m/ipcores/sgmii_gbe_pcs32/sgmii_gbe_pcs32.lpc @@ -1,26 +1,26 @@ -[Device] -Family=ep5m00 -PartType=LFE2M100E -PartName=LFE2M100E-5F900C -SpeedGrade=-5 -Package=FPBGA900 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=IPCFG -CoreStatus=Demo -CoreName=SGMII/Gb Ethernet PCS -CoreRevision=3.2 -ModuleName=sgmii_gbe_pcs32 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=12/10/2009 -Time=15:57:40 - -[Parameters] -RX_CTC=2 -RX_CTC_LOW=16 -RX_CTC_HIGH=32 -EasyConnect=1 +[Device] +Family=ep5m00 +PartType=LFE2M100E +PartName=LFE2M100E-5F900C +SpeedGrade=-5 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=IPCFG +CoreStatus=Demo +CoreName=SGMII/Gb Ethernet PCS +CoreRevision=3.2 +ModuleName=sgmii_gbe_pcs32 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=06/17/2011 +Time=11:34:20 + +[Parameters] +RX_CTC=2 +RX_CTC_LOW=16 +RX_CTC_HIGH=32 +EasyConnect=1 diff --git a/gbe_ecp2m/ipcores/tb_fifo_2048x8_tmpl.vhd b/gbe_ecp2m/ipcores/tb_fifo_2048x8_tmpl.vhd index 31ea3c3..343af71 100755 --- a/gbe_ecp2m/ipcores/tb_fifo_2048x8_tmpl.vhd +++ b/gbe_ecp2m/ipcores/tb_fifo_2048x8_tmpl.vhd @@ -1,102 +1,102 @@ --- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_2048x8 - port (Data : in std_logic_vector(7 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(7 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(7 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(7 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_2048x8 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 2051 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 2051 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 2051 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; +-- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component fifo_2048x8 + port (Data : in std_logic_vector(7 downto 0); + WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; + RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; + Q : out std_logic_vector(7 downto 0); Empty: out std_logic; + Full: out std_logic + ); + end component; + + signal Data : std_logic_vector(7 downto 0) := (others => '0'); + signal WrClock: std_logic := '0'; + signal RdClock: std_logic := '0'; + signal WrEn: std_logic := '0'; + signal RdEn: std_logic := '0'; + signal Reset: std_logic := '0'; + signal RPReset: std_logic := '0'; + signal Q : std_logic_vector(7 downto 0); + signal Empty: std_logic; + signal Full: std_logic; +begin + u1 : fifo_2048x8 + port map (Data => Data, WrClock => WrClock, RdClock => RdClock, + WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, + Q => Q, Empty => Empty, Full => Full + ); + + process + + begin + Data <= (others => '0') ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 2051 loop + wait until WrClock'event and WrClock = '1'; + Data <= Data + '1' after 1 ns; + end loop; + wait; + end process; + + WrClock <= not WrClock after 5.00 ns; + + RdClock <= not RdClock after 5.00 ns; + + process + + begin + WrEn <= '0' ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 2051 loop + wait until WrClock'event and WrClock = '1'; + WrEn <= '1' after 1 ns; + end loop; + WrEn <= '0' ; + wait; + end process; + + process + + begin + RdEn <= '0' ; + wait until Reset = '0'; + wait until WrEn = '1'; + wait until WrEn = '0'; + for i in 0 to 2051 loop + wait until RdClock'event and RdClock = '1'; + RdEn <= '1' after 1 ns; + end loop; + RdEn <= '0' ; + wait; + end process; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + + process + + begin + RPReset <= '1' ; + wait for 100 ns; + RPReset <= '0' ; + wait; + end process; + +end architecture test; diff --git a/gbe_ecp2m/ipcores/tb_fifo_32kx16x8_mb_tmpl.vhd b/gbe_ecp2m/ipcores/tb_fifo_32kx16x8_mb_tmpl.vhd index faff46a..1ad6e7d 100755 --- a/gbe_ecp2m/ipcores/tb_fifo_32kx16x8_mb_tmpl.vhd +++ b/gbe_ecp2m/ipcores/tb_fifo_32kx16x8_mb_tmpl.vhd @@ -1,4 +1,4 @@ --- VHDL testbench template generated by SCUBA ispLever_v8.0_PROD_Build (41) +-- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; diff --git a/gbe_ecp2m/ipcores/tb_fifo_4096x32_tmpl.vhd b/gbe_ecp2m/ipcores/tb_fifo_4096x32_tmpl.vhd index 69b93a2..0559dd7 100755 --- a/gbe_ecp2m/ipcores/tb_fifo_4096x32_tmpl.vhd +++ b/gbe_ecp2m/ipcores/tb_fifo_4096x32_tmpl.vhd @@ -1,102 +1,102 @@ --- VHDL testbench template generated by SCUBA ispLever_v8.0_PROD_Build (41) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_4096x32 - port (Data : in std_logic_vector(31 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(31 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(31 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(31 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_4096x32 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 4099 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 4099 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 4099 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; +-- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component fifo_4096x32 + port (Data : in std_logic_vector(31 downto 0); + WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; + RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; + Q : out std_logic_vector(31 downto 0); Empty: out std_logic; + Full: out std_logic + ); + end component; + + signal Data : std_logic_vector(31 downto 0) := (others => '0'); + signal WrClock: std_logic := '0'; + signal RdClock: std_logic := '0'; + signal WrEn: std_logic := '0'; + signal RdEn: std_logic := '0'; + signal Reset: std_logic := '0'; + signal RPReset: std_logic := '0'; + signal Q : std_logic_vector(31 downto 0); + signal Empty: std_logic; + signal Full: std_logic; +begin + u1 : fifo_4096x32 + port map (Data => Data, WrClock => WrClock, RdClock => RdClock, + WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, + Q => Q, Empty => Empty, Full => Full + ); + + process + + begin + Data <= (others => '0') ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 4099 loop + wait until WrClock'event and WrClock = '1'; + Data <= Data + '1' after 1 ns; + end loop; + wait; + end process; + + WrClock <= not WrClock after 5.00 ns; + + RdClock <= not RdClock after 5.00 ns; + + process + + begin + WrEn <= '0' ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 4099 loop + wait until WrClock'event and WrClock = '1'; + WrEn <= '1' after 1 ns; + end loop; + WrEn <= '0' ; + wait; + end process; + + process + + begin + RdEn <= '0' ; + wait until Reset = '0'; + wait until WrEn = '1'; + wait until WrEn = '0'; + for i in 0 to 4099 loop + wait until RdClock'event and RdClock = '1'; + RdEn <= '1' after 1 ns; + end loop; + RdEn <= '0' ; + wait; + end process; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + + process + + begin + RPReset <= '1' ; + wait for 100 ns; + RPReset <= '0' ; + wait; + end process; + +end architecture test; diff --git a/gbe_ecp2m/ipcores/tb_fifo_4096x9_tmpl.vhd b/gbe_ecp2m/ipcores/tb_fifo_4096x9_tmpl.vhd index a300fbe..9352be8 100755 --- a/gbe_ecp2m/ipcores/tb_fifo_4096x9_tmpl.vhd +++ b/gbe_ecp2m/ipcores/tb_fifo_4096x9_tmpl.vhd @@ -1,102 +1,102 @@ --- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_4096x9 - port (Data : in std_logic_vector(8 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(8 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(8 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(8 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_4096x9 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 4099 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 4099 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 4099 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; +-- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component fifo_4096x9 + port (Data : in std_logic_vector(8 downto 0); + WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; + RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; + Q : out std_logic_vector(8 downto 0); Empty: out std_logic; + Full: out std_logic + ); + end component; + + signal Data : std_logic_vector(8 downto 0) := (others => '0'); + signal WrClock: std_logic := '0'; + signal RdClock: std_logic := '0'; + signal WrEn: std_logic := '0'; + signal RdEn: std_logic := '0'; + signal Reset: std_logic := '0'; + signal RPReset: std_logic := '0'; + signal Q : std_logic_vector(8 downto 0); + signal Empty: std_logic; + signal Full: std_logic; +begin + u1 : fifo_4096x9 + port map (Data => Data, WrClock => WrClock, RdClock => RdClock, + WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, + Q => Q, Empty => Empty, Full => Full + ); + + process + + begin + Data <= (others => '0') ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 4099 loop + wait until WrClock'event and WrClock = '1'; + Data <= Data + '1' after 1 ns; + end loop; + wait; + end process; + + WrClock <= not WrClock after 5.00 ns; + + RdClock <= not RdClock after 5.00 ns; + + process + + begin + WrEn <= '0' ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 4099 loop + wait until WrClock'event and WrClock = '1'; + WrEn <= '1' after 1 ns; + end loop; + WrEn <= '0' ; + wait; + end process; + + process + + begin + RdEn <= '0' ; + wait until Reset = '0'; + wait until WrEn = '1'; + wait until WrEn = '0'; + for i in 0 to 4099 loop + wait until RdClock'event and RdClock = '1'; + RdEn <= '1' after 1 ns; + end loop; + RdEn <= '0' ; + wait; + end process; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + + process + + begin + RPReset <= '1' ; + wait for 100 ns; + RPReset <= '0' ; + wait; + end process; + +end architecture test; diff --git a/gbe_ecp2m/ipcores/tb_fifo_64kx8_tmpl.vhd b/gbe_ecp2m/ipcores/tb_fifo_64kx8_tmpl.vhd index b60730e..2096041 100755 --- a/gbe_ecp2m/ipcores/tb_fifo_64kx8_tmpl.vhd +++ b/gbe_ecp2m/ipcores/tb_fifo_64kx8_tmpl.vhd @@ -1,102 +1,102 @@ --- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component fifo_64kx8 - port (Data : in std_logic_vector(7 downto 0); - WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; - RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - Q : out std_logic_vector(7 downto 0); Empty: out std_logic; - Full: out std_logic - ); - end component; - - signal Data : std_logic_vector(7 downto 0) := (others => '0'); - signal WrClock: std_logic := '0'; - signal RdClock: std_logic := '0'; - signal WrEn: std_logic := '0'; - signal RdEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal RPReset: std_logic := '0'; - signal Q : std_logic_vector(7 downto 0); - signal Empty: std_logic; - signal Full: std_logic; -begin - u1 : fifo_64kx8 - port map (Data => Data, WrClock => WrClock, RdClock => RdClock, - WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - Q => Q, Empty => Empty, Full => Full - ); - - process - - begin - Data <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 65539 loop - wait until WrClock'event and WrClock = '1'; - Data <= Data + '1' after 1 ns; - end loop; - wait; - end process; - - WrClock <= not WrClock after 5.00 ns; - - RdClock <= not RdClock after 5.00 ns; - - process - - begin - WrEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 65539 loop - wait until WrClock'event and WrClock = '1'; - WrEn <= '1' after 1 ns; - end loop; - WrEn <= '0' ; - wait; - end process; - - process - - begin - RdEn <= '0' ; - wait until Reset = '0'; - wait until WrEn = '1'; - wait until WrEn = '0'; - for i in 0 to 65539 loop - wait until RdClock'event and RdClock = '1'; - RdEn <= '1' after 1 ns; - end loop; - RdEn <= '0' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - - process - - begin - RPReset <= '1' ; - wait for 100 ns; - RPReset <= '0' ; - wait; - end process; - -end architecture test; +-- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component fifo_64kx8 + port (Data : in std_logic_vector(7 downto 0); + WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; + RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; + Q : out std_logic_vector(7 downto 0); Empty: out std_logic; + Full: out std_logic + ); + end component; + + signal Data : std_logic_vector(7 downto 0) := (others => '0'); + signal WrClock: std_logic := '0'; + signal RdClock: std_logic := '0'; + signal WrEn: std_logic := '0'; + signal RdEn: std_logic := '0'; + signal Reset: std_logic := '0'; + signal RPReset: std_logic := '0'; + signal Q : std_logic_vector(7 downto 0); + signal Empty: std_logic; + signal Full: std_logic; +begin + u1 : fifo_64kx8 + port map (Data => Data, WrClock => WrClock, RdClock => RdClock, + WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, + Q => Q, Empty => Empty, Full => Full + ); + + process + + begin + Data <= (others => '0') ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 65539 loop + wait until WrClock'event and WrClock = '1'; + Data <= Data + '1' after 1 ns; + end loop; + wait; + end process; + + WrClock <= not WrClock after 5.00 ns; + + RdClock <= not RdClock after 5.00 ns; + + process + + begin + WrEn <= '0' ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 65539 loop + wait until WrClock'event and WrClock = '1'; + WrEn <= '1' after 1 ns; + end loop; + WrEn <= '0' ; + wait; + end process; + + process + + begin + RdEn <= '0' ; + wait until Reset = '0'; + wait until WrEn = '1'; + wait until WrEn = '0'; + for i in 0 to 65539 loop + wait until RdClock'event and RdClock = '1'; + RdEn <= '1' after 1 ns; + end loop; + RdEn <= '0' ; + wait; + end process; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + + process + + begin + RPReset <= '1' ; + wait for 100 ns; + RPReset <= '0' ; + wait; + end process; + +end architecture test; diff --git a/gbe_ecp2m/ipcores/tb_ip_mem_tmpl.vhd b/gbe_ecp2m/ipcores/tb_ip_mem_tmpl.vhd index 3b2d37f..862c84d 100755 --- a/gbe_ecp2m/ipcores/tb_ip_mem_tmpl.vhd +++ b/gbe_ecp2m/ipcores/tb_ip_mem_tmpl.vhd @@ -1,4 +1,4 @@ --- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) +-- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; diff --git a/gbe_ecp2m/ipcores/tb_mac_init_mem_tmpl.vhd b/gbe_ecp2m/ipcores/tb_mac_init_mem_tmpl.vhd index fd983a6..701eaf3 100755 --- a/gbe_ecp2m/ipcores/tb_mac_init_mem_tmpl.vhd +++ b/gbe_ecp2m/ipcores/tb_mac_init_mem_tmpl.vhd @@ -1,64 +1,64 @@ --- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -entity tb is -end entity tb; - - -architecture test of tb is - - component mac_init_mem - port (Address : in std_logic_vector(5 downto 0); - OutClock: in std_logic; OutClockEn: in std_logic; - Reset: in std_logic; Q : out std_logic_vector(7 downto 0) - ); - end component; - - signal Address : std_logic_vector(5 downto 0) := (others => '0'); - signal OutClock: std_logic := '0'; - signal OutClockEn: std_logic := '0'; - signal Reset: std_logic := '0'; - signal Q : std_logic_vector(7 downto 0); -begin - u1 : mac_init_mem - port map (Address => Address, OutClock => OutClock, OutClockEn => OutClockEn, - Reset => Reset, Q => Q - ); - - process - - begin - Address <= (others => '0') ; - wait for 100 ns; - wait until Reset = '0'; - for i in 0 to 57 loop - wait until OutClock'event and OutClock = '1'; - Address <= Address + '1' after 1 ns; - end loop; - wait; - end process; - - OutClock <= not OutClock after 5.00 ns; - - process - - begin - OutClockEn <= '0' ; - wait for 100 ns; - wait until Reset = '0'; - OutClockEn <= '1' ; - wait; - end process; - - process - - begin - Reset <= '1' ; - wait for 100 ns; - Reset <= '0' ; - wait; - end process; - -end architecture test; +-- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component mac_init_mem + port (Address : in std_logic_vector(5 downto 0); + OutClock: in std_logic; OutClockEn: in std_logic; + Reset: in std_logic; Q : out std_logic_vector(7 downto 0) + ); + end component; + + signal Address : std_logic_vector(5 downto 0) := (others => '0'); + signal OutClock: std_logic := '0'; + signal OutClockEn: std_logic := '0'; + signal Reset: std_logic := '0'; + signal Q : std_logic_vector(7 downto 0); +begin + u1 : mac_init_mem + port map (Address => Address, OutClock => OutClock, OutClockEn => OutClockEn, + Reset => Reset, Q => Q + ); + + process + + begin + Address <= (others => '0') ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 57 loop + wait until OutClock'event and OutClock = '1'; + Address <= Address + '1' after 1 ns; + end loop; + wait; + end process; + + OutClock <= not OutClock after 5.00 ns; + + process + + begin + OutClockEn <= '0' ; + wait for 100 ns; + wait until Reset = '0'; + OutClockEn <= '1' ; + wait; + end process; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + +end architecture test; -- 2.43.0