From 95e3d7ab9dabe75521d565a4314be298068a7211 Mon Sep 17 00:00:00 2001
From: Adrian Weber <adrian.a.weber@exp2.physik.uni-giessen.de>
Date: Mon, 20 Sep 2021 12:24:22 +0200
Subject: [PATCH] rename of dirich5s files for name appearance in bitfile

---
 dirich5s/config_compile_frankfurt.pl  | 2 +-
 dirich5s/config_compile_giessen.pl    | 2 +-
 dirich5s/config_compile_gsi.pl        | 2 +-
 dirich5s/{dirich.lpf => dirich5s.lpf} | 0
 dirich5s/{dirich.prj => dirich5s.prj} | 8 ++++----
 dirich5s/{dirich.vhd => dirich5s.vhd} | 4 ++--
 dirich5s/par.p2t                      | 2 +-
 7 files changed, 10 insertions(+), 10 deletions(-)
 rename dirich5s/{dirich.lpf => dirich5s.lpf} (100%)
 rename dirich5s/{dirich.prj => dirich5s.prj} (98%)
 rename dirich5s/{dirich.vhd => dirich5s.vhd} (99%)

diff --git a/dirich5s/config_compile_frankfurt.pl b/dirich5s/config_compile_frankfurt.pl
index 2dd81ea..e70af5f 100644
--- a/dirich5s/config_compile_frankfurt.pl
+++ b/dirich5s/config_compile_frankfurt.pl
@@ -4,7 +4,7 @@ Package     => 'CABGA381',
 Speedgrade  => '8',
 
 
-TOPNAME                      => "dirich",
+TOPNAME                      => "dirich5s",
 lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
 lm_license_file_for_par      => "1702\@jspc29",
 lattice_path                 => '/d/jspc29/lattice/diamond/3.10_x64',
diff --git a/dirich5s/config_compile_giessen.pl b/dirich5s/config_compile_giessen.pl
index f4f9196..2d99d8c 100644
--- a/dirich5s/config_compile_giessen.pl
+++ b/dirich5s/config_compile_giessen.pl
@@ -4,7 +4,7 @@ Package     => 'CABGA381',
 Speedgrade  => '8',
 
 
-TOPNAME                      => "dirich",
+TOPNAME                      => "dirich5s",
 lm_license_file_for_synplify => "7788\@fb07pc-u102325",
 lm_license_file_for_par      => "7788\@fb07pc-u102325",
 lattice_path                 => '/usr/local/diamond/3.11_x64/',
diff --git a/dirich5s/config_compile_gsi.pl b/dirich5s/config_compile_gsi.pl
index c5679b3..70ad53e 100644
--- a/dirich5s/config_compile_gsi.pl
+++ b/dirich5s/config_compile_gsi.pl
@@ -3,7 +3,7 @@ Devicename  => 'LFE5UM-85F',
 Package     => 'CABGA381',
 Speedgrade  => '8',
 
-TOPNAME                      => "dirich",
+TOPNAME                      => "dirich5s",
 lm_license_file_for_synplify => "27000\@lxcad01.gsi.de",
 lm_license_file_for_par      => "1702\@hadeb05.gsi.de",
 lattice_path                 => '/opt/lattice/diamond/3.8_x64',
diff --git a/dirich5s/dirich.lpf b/dirich5s/dirich5s.lpf
similarity index 100%
rename from dirich5s/dirich.lpf
rename to dirich5s/dirich5s.lpf
diff --git a/dirich5s/dirich.prj b/dirich5s/dirich5s.prj
similarity index 98%
rename from dirich5s/dirich.prj
rename to dirich5s/dirich5s.prj
index f4f4dfa..522af7e 100644
--- a/dirich5s/dirich.prj
+++ b/dirich5s/dirich5s.prj
@@ -12,7 +12,7 @@ set_option -part_companion ""
 # compilation/mapping options
 set_option -default_enum_encoding sequential
 set_option -symbolic_fsm_compiler 1
-set_option -top_module "dirich"
+set_option -top_module "dirich5s"
 set_option -resource_sharing false
 
 # map options
@@ -41,8 +41,8 @@ set_option -write_apr_constraint 0
 
 # set result format/file last
 project -result_format "edif"
-project -result_file "workdir/dirich.edf"
-set_option log_file "workdir/dirich_project.srf" 
+project -result_file "workdir/dirich5s.edf"
+set_option log_file "workdir/dirich5s_project.srf" 
 #implementation attributes
 
 set_option -vlog_std v2001
@@ -217,7 +217,7 @@ add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x32_OutReg/FIFO_
 add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd"
 
 
-add_file -vhdl -lib work "./dirich.vhd"
+add_file -vhdl -lib work "./dirich5s.vhd"
 #add_file -fpga_constraint "./synplify.fdc"
 
 
diff --git a/dirich5s/dirich.vhd b/dirich5s/dirich5s.vhd
similarity index 99%
rename from dirich5s/dirich.vhd
rename to dirich5s/dirich5s.vhd
index f40167d..3284b78 100644
--- a/dirich5s/dirich.vhd
+++ b/dirich5s/dirich5s.vhd
@@ -10,7 +10,7 @@ use work.trb_net_components.all;
 use work.trb3_components.all;
 use work.med_sync_define.all;
 
-entity dirich is
+entity dirich5s is
   port(
     CLOCK_CORE  : in std_logic;           --Main Oscillator
     CLOCK_IN    : in std_logic;           --external Clock
@@ -65,7 +65,7 @@ entity dirich is
 
 end entity;
 
-architecture dirich_arch of dirich is
+architecture dirich5s_arch of dirich5s is
   attribute syn_keep     : boolean;
   attribute syn_preserve : boolean;
 
diff --git a/dirich5s/par.p2t b/dirich5s/par.p2t
index 9750eae..bf72507 100644
--- a/dirich5s/par.p2t
+++ b/dirich5s/par.p2t
@@ -4,7 +4,7 @@
 #-m nodelist.txt	# Controlled by the compile.pl script.
 #-n 2  			# Controlled by the compile.pl script.
 -s 10
--t 89
+-t 93
 -c 2
 -e 2
 -i 10
-- 
2.43.0