From 96592fc556618f729036944fe076556c00dd24d4 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Sun, 20 Jan 2008 22:47:59 +0000 Subject: [PATCH] *** empty log message *** --- trb_net16_med_tlk.vhd | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/trb_net16_med_tlk.vhd b/trb_net16_med_tlk.vhd index 62672d4..523fd05 100644 --- a/trb_net16_med_tlk.vhd +++ b/trb_net16_med_tlk.vhd @@ -36,6 +36,7 @@ entity trb_net16_med_tlk is MED_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); MED_ERROR_OUT : out std_logic_vector (2 downto 0); STAT : out std_logic_vector (63 downto 0) + --connect STAT(0) to LED ); end trb_net16_med_tlk; @@ -158,7 +159,7 @@ begin end if; end process; - STAT(0) <= internal_reset; + STAT(0) <= counter(24) or tx_allow; STAT(1) <= rx_allow; STAT(2) <= tx_allow; STAT(3) <= fifo_wr_en_a; @@ -279,8 +280,6 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); ); fifo_rd_en_m <= tx_allow and not fifo_empty_m; - --fifo_wr_en_m <= MED_DATAREADY_IN and buf_MED_READ_OUT; - --fifo_din_m <= "00" & MED_DATA_IN; TLK_TX_ER <= '0'; TLK_TX_EN <= reg_TX_EN; @@ -355,13 +354,6 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); next_rx_allow <= '1'; next_state <= WAIT_FOR_TX_ALLOW; end if; --- when WAIT_FOR_RX_ALLOW => --- next_MED_ERROR_OUT <= ERROR_WAIT; --- if counter(22) = '1' then --22 --- next_rx_allow <= '1'; --- counter_reset <= '1'; --- next_state <= WAIT_FOR_TX_ALLOW; --- end if; when WAIT_FOR_TX_ALLOW => next_MED_ERROR_OUT <= ERROR_WAIT; if counter(27) = '1' then --20 @@ -384,7 +376,6 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); case current_state is when RESETTING => state_bits <= "000"; when WAIT_FOR_RX_LOCK => state_bits <= "001"; --- when WAIT_FOR_RX_ALLOW => state_bits <= "010"; when WAIT_FOR_TX_ALLOW => state_bits <= "011"; when WORKING => state_bits <= "100"; when others => state_bits <= "111"; -- 2.43.0