From 965988886f0a777c73a50d24df187360b6ce7b1d Mon Sep 17 00:00:00 2001 From: Cahit Date: Mon, 31 Mar 2014 12:06:17 +0200 Subject: [PATCH] Hit multiplexer is put in an entity for easier placement constraints. Epoch counter update logic in channel is changed for easier timing constraints. --- tdc_releases/tdc_v1.6/Channel.vhd | 30 +--------- tdc_releases/tdc_v1.6/Channel_200.vhd | 82 ++++++++++++++++++++------- tdc_releases/tdc_v1.6/Readout.vhd | 4 +- tdc_releases/tdc_v1.6/TDC.vhd | 77 ++++++++++++++++--------- 4 files changed, 118 insertions(+), 75 deletions(-) diff --git a/tdc_releases/tdc_v1.6/Channel.vhd b/tdc_releases/tdc_v1.6/Channel.vhd index c505f96..9da5fbc 100644 --- a/tdc_releases/tdc_v1.6/Channel.vhd +++ b/tdc_releases/tdc_v1.6/Channel.vhd @@ -57,15 +57,9 @@ architecture Channel of Channel is -- Signal Declarations ------------------------------------------------------------------------------- - -- hit signals - signal hit_in_i : std_logic; - signal hit_buf : std_logic; --- signal hit_inv : std_logic; - -- time stamp signal coarse_cntr_reg : std_logic_vector(10 downto 0); signal epoch_cntr_reg : std_logic_vector(27 downto 0); - signal epoch_cntr_2reg : std_logic_vector(27 downto 0); signal trig_win_end_tdc_i : std_logic; signal trig_win_end_rdo_i : std_logic; @@ -110,42 +104,25 @@ architecture Channel of Channel is -- other --- signal data_finished_i : std_logic; - ------------------------------------------------------------------------------- attribute syn_keep : boolean; - attribute syn_keep of hit_buf : signal is true; attribute syn_keep of trig_win_end_tdc_i : signal is true; attribute syn_keep of trig_win_end_rdo_i : signal is true; attribute syn_keep of epoch_cntr_reg : signal is true; --- attribute syn_keep of epoch_cntr_2reg : signal is true; attribute syn_preserve : boolean; attribute syn_preserve of coarse_cntr_reg : signal is true; - attribute syn_preserve of hit_buf : signal is true; attribute syn_preserve of trig_win_end_tdc_i : signal is true; attribute syn_preserve of epoch_cntr_reg : signal is true; --- attribute syn_preserve of epoch_cntr_2reg : signal is true; attribute nomerge : string; - attribute nomerge of hit_buf : signal is "true"; attribute nomerge of trig_win_end_tdc_i : signal is "true"; attribute nomerge of trig_win_end_rdo_i : signal is "true"; attribute nomerge of epoch_cntr_reg : signal is "true"; --- attribute nomerge of epoch_cntr_2reg : signal is "true"; - ------------------------------------------------------------------------------- begin - hit_in_i <= HIT_IN; - hit_buf <= not hit_in_i; - - --HitInvert: entity work.hit_inv - -- port map ( - -- PORT_IN => HIT_IN, - -- PORT_OUT => hit_inv); - Channel200 : Channel_200 generic map ( CHANNEL_ID => CHANNEL_ID, @@ -158,10 +135,10 @@ begin CLK_100 => CLK_100, RESET_100 => RESET_100, RESET_COUNTERS => RESET_COUNTERS, - HIT_IN => hit_buf, + HIT_IN => HIT_IN, TRIGGER_WIN_END_TDC => trig_win_end_tdc_i, TRIGGER_WIN_END_RDO => trig_win_end_rdo_i, - EPOCH_COUNTER_IN => epoch_cntr_reg, --epoch_cntr_2reg, + EPOCH_COUNTER_IN => epoch_cntr_reg, COARSE_COUNTER_IN => coarse_cntr_reg, READ_EN_IN => READ_EN_IN, FIFO_DATA_OUT => ch_data_i, @@ -195,7 +172,7 @@ begin FIFO_DATA_VALID_OUT <= buf_data_valid_i; FIFO_EMPTY_OUT <= buf_empty_i; FIFO_ALMOST_EMPTY_OUT <= buf_almost_empty_i; - trig_win_end_tdc_i <= TRIGGER_WIN_END_TDC;-- when rising_edge(CLK_200); + trig_win_end_tdc_i <= TRIGGER_WIN_END_TDC; trig_win_end_rdo_i <= TRIGGER_WIN_END_RDO when rising_edge(CLK_100); rd_en_reg <= READ_EN_IN when rising_edge(CLK_100); buf_empty_reg <= buf_empty_i when rising_edge(CLK_100); @@ -238,7 +215,6 @@ begin D_OUT => coarse_cntr_reg); epoch_cntr_reg <= EPOCH_COUNTER_IN when rising_edge(CLK_200); --- epoch_cntr_2reg <= epoch_cntr_reg when rising_edge(CLK_200); ------------------------------------------------------------------------------- -- DEBUG Counters diff --git a/tdc_releases/tdc_v1.6/Channel_200.vhd b/tdc_releases/tdc_v1.6/Channel_200.vhd index ce9028a..5dc78ff 100644 --- a/tdc_releases/tdc_v1.6/Channel_200.vhd +++ b/tdc_releases/tdc_v1.6/Channel_200.vhd @@ -5,7 +5,7 @@ -- File : Channel_200.vhd -- Author : c.ugur@gsi.de -- Created : 2012-08-28 --- Last update: 2014-03-07 +-- Last update: 2014-03-26 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -74,9 +74,25 @@ architecture Channel_200 of Channel_200 is signal hit_detect_2reg : std_logic; -- time stamp - signal time_stamp_i : std_logic_vector(10 downto 0); - signal coarse_cntr_reg : std_logic_vector(10 downto 0); - + signal time_stamp_i : std_logic_vector(10 downto 0); + signal time_stamp_reg : std_logic_vector(10 downto 0); + signal time_stamp_2reg : std_logic_vector(10 downto 0); + signal time_stamp_3reg : std_logic_vector(10 downto 0); + signal time_stamp_4reg : std_logic_vector(10 downto 0); + signal time_stamp_5reg : std_logic_vector(10 downto 0); + signal time_stamp_6reg : std_logic_vector(10 downto 0); + signal coarse_cntr_reg : std_logic_vector(10 downto 0); + signal coarse_cntr_overflow : std_logic; + signal coarse_cntr_overflow_reg : std_logic; + signal coarse_cntr_overflow_2reg : std_logic; + signal coarse_cntr_overflow_3reg : std_logic; + signal coarse_cntr_overflow_4reg : std_logic; + signal coarse_cntr_overflow_5reg : std_logic; + signal coarse_cntr_overflow_6reg : std_logic; + signal coarse_cntr_overflow_7reg : std_logic; + signal coarse_cntr_overflow_8reg : std_logic; + signal coarse_cntr_overflow_9reg : std_logic; + -- encoder signal encoder_start_i : std_logic; signal encoder_finished_i : std_logic; @@ -126,7 +142,7 @@ architecture Channel_200 of Channel_200 is signal fsm_wr_debug_fsm : std_logic_vector(3 downto 0); signal fsm_wr_debug_i : std_logic_vector(3 downto 0); - type FSM_RD is (IDLE, FLUSH_A, FLUSH_B, FLUSH_C, FLUSH_D, READOUT_EPOCH, READOUT_DATA_A, READOUT_DATA_B, READOUT_DATA_C); + type FSM_RD is (IDLE, FLUSH_A, FLUSH_B, FLUSH_C, FLUSH_D, READOUT_EPOCH, READOUT_DATA_A, READOUT_DATA_B, READOUT_DATA_C); signal FSM_RD_STATE : FSM_RD; signal trigger_win_end_rdo_flag_i : std_logic := '0'; signal fsm_rd_debug_i : std_logic_vector(3 downto 0); @@ -157,7 +173,7 @@ begin -- Channel_200 ClkEn => ff_array_en_i, Result => result_i); data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0000000FFFFFFF"&x"7FFFFFF"; - data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000"& not(HIT_IN) & x"000000"&"00" & HIT_IN; + data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000"& HIT_IN & x"000000"&"00" & not(HIT_IN); end generate SimAdderYes; SimAdderNo : if SIMULATION = c_NO generate --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) double transition @@ -170,7 +186,7 @@ begin -- Channel_200 ClkEn => ff_array_en_i, Result => result_i); data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"&x"7FFFFFF"; - data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000"& not(HIT_IN) & x"000000"&"00" & HIT_IN; + data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000"& HIT_IN & x"000000"&"00" & not(HIT_IN); end generate SimAdderNo; ff_array_en_i <= not(hit_detect_i or hit_detect_reg or hit_detect_2reg); @@ -191,16 +207,44 @@ begin -- Channel_200 if hit_detect_reg = '1' then time_stamp_i <= coarse_cntr_reg; end if; + time_stamp_reg <= time_stamp_i; + time_stamp_2reg <= time_stamp_reg; + time_stamp_3reg <= time_stamp_2reg; + time_stamp_4reg <= time_stamp_3reg; + time_stamp_5reg <= time_stamp_4reg; + time_stamp_6reg <= time_stamp_5reg; + --time_stamp_7reg <= time_stamp_6reg; + --time_stamp_8reg <= time_stamp_7reg; end if; end process TimeStampCapture; epoch_capture_time <= "00000001000"; + CoarseCounterOverflow: entity work.fallingEdgeDetect + port map ( + CLK => CLK_200, + SIGNAL_IN => coarse_cntr_reg(10), + PULSE_OUT => coarse_cntr_overflow); + + coarse_cntr_overflow_reg <= coarse_cntr_overflow when rising_edge(CLK_200); + coarse_cntr_overflow_2reg <= coarse_cntr_overflow_reg when rising_edge(CLK_200); + coarse_cntr_overflow_3reg <= coarse_cntr_overflow_2reg when rising_edge(CLK_200); + coarse_cntr_overflow_4reg <= coarse_cntr_overflow_3reg when rising_edge(CLK_200); + coarse_cntr_overflow_5reg <= coarse_cntr_overflow_4reg when rising_edge(CLK_200); + coarse_cntr_overflow_6reg <= coarse_cntr_overflow_5reg when rising_edge(CLK_200); + coarse_cntr_overflow_7reg <= coarse_cntr_overflow_6reg when rising_edge(CLK_200); + coarse_cntr_overflow_8reg <= coarse_cntr_overflow_7reg when rising_edge(CLK_200); + coarse_cntr_overflow_9reg <= coarse_cntr_overflow_8reg when rising_edge(CLK_200); + isChannelEpoch : if REFERENCE = c_NO generate EpochCounterCapture : process (CLK_200) begin if rising_edge(CLK_200) then - if coarse_cntr_reg = epoch_capture_time then +-- if coarse_cntr_reg = epoch_capture_time then + --if hit_detect_i = '1' then + -- epoch_cntr <= EPOCH_COUNTER_IN after 25 ns; + --end if; + if coarse_cntr_overflow_7reg = '1' then epoch_cntr <= EPOCH_COUNTER_IN; epoch_cntr_updated <= '1'; elsif write_epoch_i = '1' then @@ -550,7 +594,7 @@ begin -- Channel_200 fifo_data_in_i(28 downto 22) <= std_logic_vector(to_unsigned(CHANNEL_ID, 7)); -- channel number fifo_data_in_i(21 downto 12) <= encoder_data_out_i; -- fine time from the encoder fifo_data_in_i(11) <= '1'; --edge_type_i; -- rising '1' or falling '0' edge - fifo_data_in_i(10 downto 0) <= time_stamp_i; -- hit time stamp + fifo_data_in_i(10 downto 0) <= time_stamp_6reg; -- hit time stamp fifo_wr_en_i <= '1'; elsif write_stop_a_i = '1' then fifo_data_in_i(35 downto 32) <= x"f"; @@ -588,22 +632,22 @@ begin -- Channel_200 -- if the data readout is triggered by the end of the trigger window if TRIGGER_WIN_END_RDO = '1' then FSM_RD_STATE <= READOUT_DATA_A; - -- if the data readout is triggered by full fifo + -- if the data readout is triggered by full fifo elsif fifo_almost_full_flag = '1' then FSM_RD_STATE <= FLUSH_A; else FSM_RD_STATE <= IDLE; end if; --- + -- when FLUSH_A => FSM_RD_STATE <= FLUSH_B; --- + -- when FLUSH_B => FSM_RD_STATE <= FLUSH_C; --- + -- when FLUSH_C => FSM_RD_STATE <= FLUSH_D; --- + -- when FLUSH_D => -- wait until a readout request and register the last epoch word if TRIGGER_WIN_END_RDO = '1' or trigger_win_end_rdo_flag_i = '1' then @@ -611,17 +655,17 @@ begin -- Channel_200 else FSM_RD_STATE <= FLUSH_D; end if; --- + -- when READOUT_EPOCH => -- first epoch word should be readout FSM_RD_STATE <= READOUT_DATA_C; --- + -- when READOUT_DATA_A => FSM_RD_STATE <= READOUT_DATA_B; --- + -- when READOUT_DATA_B => FSM_RD_STATE <= READOUT_DATA_C; - + -- when READOUT_DATA_C => -- normal data readout until the end of the readout request if fifo_data_out_i(35 downto 32) = x"f" then @@ -629,7 +673,7 @@ begin -- Channel_200 else FSM_RD_STATE <= READOUT_DATA_C; end if; --- + -- when others => FSM_RD_STATE <= IDLE; end case; diff --git a/tdc_releases/tdc_v1.6/Readout.vhd b/tdc_releases/tdc_v1.6/Readout.vhd index 759e01d..6b615d6 100644 --- a/tdc_releases/tdc_v1.6/Readout.vhd +++ b/tdc_releases/tdc_v1.6/Readout.vhd @@ -5,7 +5,7 @@ -- File : Readout.vhd -- Author : cugur@gsi.de -- Created : 2012-10-25 --- Last update: 2014-03-13 +-- Last update: 2014-03-16 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -387,6 +387,7 @@ begin -- behavioral readout_fsm <= '0'; wait_fsm <= '0'; wr_status_fsm <= '0'; + buf_delay_fsm <= 0; fifo_nr_rd_fsm <= fifo_nr_rd; rd_fsm_debug_fsm <= x"0"; RD_NEXT <= RD_CURRENT; @@ -426,7 +427,6 @@ begin -- behavioral when WAIT_FOR_BUFFER_TRANSFER => -- the data from channel fifo is written to the buffer if buf_delay_i = 31 then RD_NEXT <= RD_CH; - buf_delay_fsm <= 0; else buf_delay_fsm <= buf_delay_i + 1; end if; diff --git a/tdc_releases/tdc_v1.6/TDC.vhd b/tdc_releases/tdc_v1.6/TDC.vhd index 241aaf0..d1246ba 100644 --- a/tdc_releases/tdc_v1.6/TDC.vhd +++ b/tdc_releases/tdc_v1.6/TDC.vhd @@ -175,10 +175,15 @@ architecture TDC of TDC is attribute syn_keep of coarse_cntr : signal is true; attribute syn_keep of coarse_cntr_reset_r : signal is true; attribute syn_keep of trig_win_end_tdc_i : signal is true; + attribute syn_keep of hit_in_i : signal is true; attribute syn_preserve : boolean; attribute syn_preserve of coarse_cntr : signal is true; attribute syn_preserve of coarse_cntr_reset_r : signal is true; attribute syn_preserve of trig_win_end_tdc_i : signal is true; + attribute syn_preserve of hit_in_i : signal is true; + attribute nomerge : string; + attribute nomerge of hit_in_i : signal is "true"; + begin @@ -227,31 +232,49 @@ begin hit_reg <= hit_latch when rising_edge(CLK_TDC); hit_2reg <= hit_reg when rising_edge(CLK_TDC); --- Channel and calibration enable signals - GEN_Channel_Enable : for i in 1 to CHANNEL_NUMBER-1 generate - process (ch_en_i, calibration_on, hit_calibration_i, hit_latch) - begin - if ch_en_i(i) = '1' then - if calibration_on = '1' then - hit_in_i(i) <= hit_calibration_i; - else - hit_in_i(i) <= hit_latch(i); - end if; - else - hit_in_i(i) <= '0'; - end if; - end process; - end generate GEN_Channel_Enable; - - -- purpose: Calibration trigger for the reference channel - process (calibration_on, hit_calibration_i, REFERENCE_TIME) is - begin -- process - if calibration_on = '1' then - hit_in_i(0) <= hit_calibration_i; - else - hit_in_i(0) <= REFERENCE_TIME; - end if; - end process; + GEN_hit_mux: for i in 1 to CHANNEL_NUMBER-1 generate + hit_mux_ch: hit_mux + port map ( + CH_EN_IN => ch_en_i(i), + CALIBRATION_EN_IN => calibration_on, + HIT_CALIBRATION_IN => hit_calibration_i, + HIT_PHYSICAL_IN => hit_latch(i), + HIT_OUT => hit_in_i(i)); + end generate GEN_hit_mux; + + hit_mux_ref: hit_mux + port map ( + CH_EN_IN => '1', + CALIBRATION_EN_IN => calibration_on, + HIT_CALIBRATION_IN => hit_calibration_i, + HIT_PHYSICAL_IN => REFERENCE_TIME, + HIT_OUT => hit_in_i(0)); + +---- Channel and calibration enable signals +-- GEN_Channel_Enable : for i in 1 to CHANNEL_NUMBER-1 generate +-- process (ch_en_i, calibration_on, hit_calibration_i, hit_latch) +-- begin +-- if ch_en_i(i) = '1' then +-- if calibration_on = '1' then +-- hit_in_i(i) <= hit_calibration_i; +-- else +-- hit_in_i(i) <= hit_latch(i); +-- end if; +-- else +-- hit_in_i(i) <= '0'; +-- end if; +-- end process; +-- end generate GEN_Channel_Enable; + + ---- purpose: Calibration trigger for the reference channel + --process (calibration_on, hit_calibration_i, REFERENCE_TIME) is + --begin -- process + -- if calibration_on = '1' then + -- hit_in_i(0) <= hit_calibration_i; + -- else + -- hit_in_i(0) <= REFERENCE_TIME; + -- end if; + --end process; CalibrationSwitch : process (CLK_READOUT) begin @@ -410,7 +433,7 @@ begin TRG_WIN_PRE => TRG_WIN_PRE, TRG_WIN_POST => TRG_WIN_POST, TRIGGER_WIN_EN_IN => trig_win_en_i, - TRIG_WIN_END_TDC_IN => trig_win_end_tdc_i(32), + TRIG_WIN_END_TDC_IN => trig_win_end_tdc_i(1), TRIG_WIN_END_RDO_IN => trig_win_end_rdo, COARSE_COUNTER_IN => coarse_cntr(0), EPOCH_COUNTER_IN => epoch_cntr, @@ -443,7 +466,7 @@ begin if reset_tdc = '1' then coarse_cntr_reset <= '1'; elsif run_mode_200 = '0' then - coarse_cntr_reset <= trig_win_end_tdc_i(32); + coarse_cntr_reset <= trig_win_end_tdc_i(1); elsif run_mode_edge_200 = '1' then coarse_cntr_reset <= '1'; elsif reset_coarse_cntr_flag = '1' and (VALID_TIMING_TRG_IN = '1' or VALID_NOTIMING_TRG_IN = '1') then -- 2.43.0