From 965a87e62f443aefb9d843458ec9d13250f0c56e Mon Sep 17 00:00:00 2001 From: Tobias Weber Date: Fri, 26 Sep 2014 16:57:22 +0200 Subject: [PATCH] Write complete Buffer content to TRB buffers if triggered --- mupix/sources/EventBuffer.vhd | 249 ++++++++++++++++++++++------------ 1 file changed, 161 insertions(+), 88 deletions(-) diff --git a/mupix/sources/EventBuffer.vhd b/mupix/sources/EventBuffer.vhd index be55002..6e023f9 100644 --- a/mupix/sources/EventBuffer.vhd +++ b/mupix/sources/EventBuffer.vhd @@ -1,6 +1,7 @@ ------------------------------------------------------------------------------- --Event Buffer FiFo for MuPix Readout --FiFo can be read via SlowControl Bus or transferred into FEE-FiFo on TRB +--T.Weber, University Mainz ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; @@ -9,37 +10,48 @@ use IEEE.numeric_std.all; use work.mupix_components.all; -entity EventBuffer is +entity eventbuffer is port ( - CLK : in std_logic; - Reset : in std_logic; - - --Data from MuPix Interface - MuPixData_in : in std_logic_vector(31 downto 0); - MuPixDataWr_in : in std_logic; - MuPixEndOfEvent_in : in std_logic; - - --Response from FEE (to TRB FiFo) - FEE_DATA_OUT : out std_logic_vector(31 downto 0); - FEE_DATA_WRITE_OUT : out std_logic; - FEE_DATA_FINISHED_OUT : out std_logic; - FEE_DATA_ALMOST_FULL_IN : in std_logic; - - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic); -end EventBuffer; - - -architecture Behavioral of EventBuffer is - - --FiFo Signals + clk : in std_logic; + reset : in std_logic; + + --data from mupix interface + mupixdata_in : in std_logic_vector(31 downto 0); + mupixdatawr_in : in std_logic; + mupixendofevent_in : in std_logic; + + --response from fee (to trb fifo) + fee_data_out : out std_logic_vector(31 downto 0); + fee_data_write_out : out std_logic; + fee_data_finished_out : out std_logic; + fee_data_almost_full_in : in std_logic; + + --trigger + valid_trigger_in : in std_logic; + + --clear buffer (in case of invalid trigger) + clear_buffer_in : in std_logic; + + -- slave bus + slv_read_in : in std_logic; + slv_write_in : in std_logic; + slv_data_in : in std_logic_vector(31 downto 0); + slv_addr_in : in std_logic_vector(15 downto 0); + slv_data_out : out std_logic_vector(31 downto 0); + slv_ack_out : out std_logic; + slv_no_more_data_out : out std_logic; + slv_unknown_addr_out : out std_logic); +end eventbuffer; + + +architecture behavioral of eventbuffer is + + --response to fee + signal fee_data_int : std_logic_vector(31 downto 0) := (others => '0'); + signal fee_data_write_int : std_logic := '0'; + signal fee_data_finished_int : std_logic := '0'; + + --fifo signals signal fifo_reset : std_logic; signal fifo_full : std_logic; signal fifo_empty : std_logic; @@ -50,100 +62,156 @@ architecture Behavioral of EventBuffer is signal fifo_data_out : std_logic_vector(31 downto 0); signal fifo_read_enable : std_logic; - --FiFo Readout via SLV_BUS - type FiFo_Read_S_States is (idle, wait1, wait2, done); - signal FiFo_Read_S_fsm : FiFo_Read_S_States := idle; - signal fifo_start_read : std_logic; - signal fifo_read_s : std_logic; + --fifo readout via slv_bus + type fifo_read_s_states is (idle, wait1, wait2, done); + signal fifo_read_s_fsm : fifo_read_s_states := idle; + signal fifo_start_read : std_logic := '0'; + signal fifo_read_s : std_logic := '0'; signal fifo_reading_s : std_logic := '0'; - signal fifo_read_done_s : std_logic; - signal fifo_read_busy_s : std_logic; + signal fifo_read_done_s : std_logic := '0'; + signal fifo_read_busy_s : std_logic := '0'; + + --fifo fast readout to trb data channel + type fifo_read_f_states is (idle, wait_for_data,flush_data, done); + signal fifo_read_f_fsm : fifo_read_f_states := idle; + signal fifo_read_f : std_logic := '0'; + signal fifo_read_busy_f : std_logic := '0'; + signal fifo_read_done_f : std_logic := '0'; -begin -- Behavioral +begin -- behavioral - -- Send data to FIFO (TODO: generate FiFo Core in Cores-Directory!!) + -- send data to fifo fifo_32_data_1 : fifo_32_data port map ( - Data => fifo_data_in, --Data In - Clock => CLK, - WrEn => fifo_write, - RdEn => fifo_read_enable, - Reset => fifo_reset, - Q => fifo_data_out, --Data Out - WCNT => fifo_write_ctr, - Empty => fifo_empty, - Full => fifo_full + data => fifo_data_in, --data in + clock => clk, + wren => fifo_write, + rden => fifo_read_enable, + reset => fifo_reset, + q => fifo_data_out, --data out + wcnt => fifo_write_ctr, + empty => fifo_empty, + full => fifo_full ); - fifo_read_enable <= fifo_read_s; + fifo_read_enable <= fifo_read_s or fifo_read_f; + fifo_reset <= clear_buffer_in; - FiFo_Write_Handler : process(clk) - begin -- process FiFo_Write_Handler + fifo_write_handler : process(clk) + begin -- process fifo_write_handler if rising_edge(clk) then fifo_write <= '0'; fifo_data_in <= (others => '0'); - if MuPixDataWr_in = '1' and fifo_full = '0' then + if mupixdatawr_in = '1' and fifo_full = '0' then fifo_write <= '1'; - fifo_data_in <= MuPixData_in; + fifo_data_in <= mupixdata_in; end if; end if; - end process FiFo_Write_Handler; - - --TODO: Transfer Data to TRB FiFo in case of valid trigger + end process fifo_write_handler; + ------------------------------------------------------------ + --fifo readout using trb slow control channel + ------------------------------------------------------------ + fifo_data_read_f: process is + begin -- process fifo_data_read_f + wait until rising_edge(clk); + fifo_read_f <= '0'; + fifo_read_busy_f <= '0'; + fifo_read_done_f <= '0'; + fee_data_int <= (others => '0'); + fee_data_write_int <= '0'; + fee_data_finished_int <= '0'; + if clear_buffer_in ='1' then + fifo_read_f_fsm <= idle; + end if; + case fifo_read_f_fsm is + when idle => + fifo_read_f_fsm <= idle; + if valid_trigger_in = '1' then + fifo_read_f <= '1'; + fifo_read_busy_f <= '1'; + fifo_read_f_fsm <= wait_for_data; + end if; + when wait_for_data => + fifo_read_f <= '1'; + fifo_read_busy_f <= '1'; + fifo_read_f_fsm <= flush_data; + when flush_data => + fifo_read_f <= '1'; + fifo_read_busy_f <= '1'; + fee_data_int <= fifo_data_out; + fee_data_write_int <= '1'; + if fifo_empty = '1' then + fifo_read_f <= '0'; + fifo_read_f_fsm <= done; + else + fifo_read_f_fsm <= flush_data; + end if; + when done => + fee_data_finished_int <= '1'; + fifo_read_f_fsm <= idle; + when others => null; + end case; + end process fifo_data_read_f; - FiFo_Data_Read : process(clk) + ------------------------------------------------------------ + --fifo readout using trb slow control channel + ------------------------------------------------------------ + fifo_data_read_s : process(clk) begin if rising_edge(clk) then fifo_read_done_s <= '0'; fifo_read_s <= '0'; fifo_read_busy_s <= '0'; - case FiFo_Read_S_fsm is + case fifo_read_s_fsm is when idle => if fifo_start_read = '1' then - if fifo_empty = '0' then + if fifo_read_busy_f = '1' then + fifo_read_done_s <= '1'; + fifo_read_s_fsm <= idle; + elsif fifo_empty = '0' then fifo_read_s <= '1'; fifo_read_busy_s <= '1'; - FiFo_Read_S_fsm <= wait1; + fifo_read_s_fsm <= wait1; else fifo_read_done_s <= '1'; - FiFo_Read_S_fsm <= idle; + fifo_read_s_fsm <= idle; end if; end if; when wait1 => fifo_read_busy_s <= '1'; - FiFo_Read_S_fsm <= wait2; + fifo_read_s_fsm <= wait2; when wait2 => fifo_read_busy_s <= '1'; - FiFo_Read_S_fsm <= done; + fifo_read_s_fsm <= done; when done => fifo_read_busy_s <= '0'; fifo_read_done_s <= '1'; - FiFo_Read_S_fsm <= idle; + fifo_read_s_fsm <= idle; end case; end if; - end process FiFo_Data_Read; + end process fifo_data_read_s; ----------------------------------------------------------------------------- - --TRB Slave Bus - --0x0300: Read FiFo Status - --0x0301: Read FiFo Write Counter - --0x0302: Read FiFo Data + --trb slave bus + --0x0300: read fifo status + --0x0301: read fifo write counter + --0x0302: read fifo data ----------------------------------------------------------------------------- fifo_status(1 downto 0) <= fifo_empty & fifo_full; fifo_status(12 downto 2) <= fifo_write_ctr; fifo_status(31 downto 13) <= (others => '0'); - SLV_BUS_HANDLER : process(clk) + slv_bus_handler : process(clk) begin if rising_edge(clk) then - SLV_DATA_OUT <= (others => '0'); - SLV_ACK_OUT <= '0'; - SLV_NO_MORE_DATA_OUT <= '0'; - SLV_UNKNOWN_ADDR_OUT <= '0'; + slv_data_out <= (others => '0'); + slv_ack_out <= '0'; + slv_no_more_data_out <= '0'; + slv_unknown_addr_out <= '0'; fifo_start_read <= '0'; if fifo_reading_s = '1' then @@ -152,34 +220,39 @@ begin -- Behavioral else if (fifo_empty = '0') then slv_data_out <= fifo_data_out; - SLV_ACK_OUT <= '1'; + slv_ack_out <= '1'; else - SLV_NO_MORE_DATA_OUT <= '1'; - SLV_ACK_OUT <= '0'; + slv_no_more_data_out <= '1'; + slv_ack_out <= '0'; end if; fifo_reading_s <= '0'; end if; - elsif SLV_WRITE_IN = '1' then - SLV_UNKNOWN_ADDR_OUT <= '1'; - elsif SLV_READ_IN = '1' then - case SLV_ADDR_IN is + elsif slv_write_in = '1' then + slv_unknown_addr_out <= '1'; + elsif slv_read_in = '1' then + case slv_addr_in is when x"0300" => - SLV_DATA_OUT <= fifo_status; - SLV_ACK_OUT <= '1'; + slv_data_out <= fifo_status; + slv_ack_out <= '1'; when x"0301" => - SLV_DATA_OUT(10 downto 0) <= fifo_write_ctr; - SLV_ACK_OUT <= '1'; + slv_data_out(10 downto 0) <= fifo_write_ctr; + slv_ack_out <= '1'; when x"0302" => fifo_start_read <= '1'; fifo_reading_s <= '1'; when others => - SLV_UNKNOWN_ADDR_OUT <= '1'; + slv_unknown_addr_out <= '1'; end case; end if; end if; - end process SLV_BUS_HANDLER; + end process slv_bus_handler; + + --map output signals + fee_data_out <= fee_data_int; + fee_data_write_out <= fee_data_write_int; + fee_data_finished_out <= fee_data_finished_int; -end Behavioral; +end behavioral; -- 2.43.0