From 969a6a4094674334b7d392f21fe8a22a3337a8f4 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 13 Feb 2015 15:12:57 +0100 Subject: [PATCH] updated central hub with new uart --- .gitignore | 1 + base/trb3_periph_mvdjtag.lpf | 6 +++++ trb3_gbe/compile_central_frankfurt.pl | 9 ++++--- trb3_gbe/trb3_central.vhd | 38 +++++++++------------------ 4 files changed, 25 insertions(+), 29 deletions(-) diff --git a/.gitignore b/.gitignore index 398ed0a..c221e1a 100644 --- a/.gitignore +++ b/.gitignore @@ -33,3 +33,4 @@ work *.wlf *stacktrace.txt *edn +licbug.txt diff --git a/base/trb3_periph_mvdjtag.lpf b/base/trb3_periph_mvdjtag.lpf index 5ffbe7b..2ede859 100644 --- a/base/trb3_periph_mvdjtag.lpf +++ b/base/trb3_periph_mvdjtag.lpf @@ -107,6 +107,12 @@ LOCATE COMP "CLK_GPLL_LEFT" SITE "U25"; DEFINE PORT GROUP "CLK_group" "CLK*" ; IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ; +LOCATE COMP "CLKRJ_0" SITE "U9"; +LOCATE COMP "CLKRJ_1" SITE "U8"; +LOCATE COMP "CLKRJ_2" SITE "Y34"; +LOCATE COMP "CLKRJ_3" SITE "Y33"; +DEFINE PORT GROUP "CLKRJ_group" "CLKRJ*" ; +IOBUF GROUP "CLKRJ_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4; ################################################################# # Trigger I/O diff --git a/trb3_gbe/compile_central_frankfurt.pl b/trb3_gbe/compile_central_frankfurt.pl index d5c93bc..20931ce 100755 --- a/trb3_gbe/compile_central_frankfurt.pl +++ b/trb3_gbe/compile_central_frankfurt.pl @@ -10,10 +10,10 @@ use strict; #Settings for this project my $TOPNAME = "trb3_central"; #Name of top-level entity #my $lattice_path = '/d/jspc29/lattice/diamond/2.01'; -my $lattice_path = '/d/jspc29/lattice/diamond/3.2_x64'; +my $lattice_path = '/d/jspc29/lattice/diamond/3.4_x64'; # my $synplify_path = '/d/jspc29/lattice/synplify/fpga_e201103/'; -my $synplify_path = '/d/jspc29/lattice/synplify/I-2013.09-SP1/'; -my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; +my $synplify_path = '/d/jspc29/lattice/synplify/J-2014.09-SP2/'; +my $lm_license_file_for_synplify = "1702\@hadeb05.gsi.de"; #"27000\@lxcad01.gsi.de"; my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; ################################################################################### @@ -71,7 +71,8 @@ $fh->close; system("env| grep LM_"); my $r = ""; -my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; +# my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; +my $c="$lattice_path/bin/lin64/synpwrap -fg -options -batch $TOPNAME.prj"; $r=execute($c, "do_not_exit" ); diff --git a/trb3_gbe/trb3_central.vhd b/trb3_gbe/trb3_central.vhd index 68ff2d7..eb9048a 100644 --- a/trb3_gbe/trb3_central.vhd +++ b/trb3_gbe/trb3_central.vhd @@ -280,14 +280,8 @@ signal stat_ack : std_logic := '0'; signal stat_nack : std_logic := '0'; signal stat_addr : std_logic_vector(15 downto 0) := (others => '0'); -signal uart_din : std_logic_vector(31 downto 0); -signal uart_dout : std_logic_vector(31 downto 0); -signal uart_write : std_logic := '0'; -signal uart_read : std_logic := '0'; -signal uart_ack : std_logic := '0'; -signal uart_nack : std_logic := '0'; -signal uart_empty : std_logic := '0'; -signal uart_addr : std_logic_vector(15 downto 0) := (others => '0'); +signal busuart_rx : CTRLBUS_RX; +signal busuart_tx : CTRLBUS_TX; signal uart_tx : std_logic_vector(4 downto 0); signal uart_rx : std_logic_vector(4 downto 0); @@ -909,16 +903,16 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler BUS_UNKNOWN_ADDR_IN(7) => stat_nack, --Uart - BUS_READ_ENABLE_OUT(8) => uart_read, - BUS_WRITE_ENABLE_OUT(8) => uart_write, - BUS_DATA_OUT(8*32+31 downto 8*32) => uart_din, - BUS_ADDR_OUT(8*16+15 downto 8*16) => uart_addr, + BUS_READ_ENABLE_OUT(8) => busuart_rx.read, + BUS_WRITE_ENABLE_OUT(8) => busuart_rx.write, + BUS_DATA_OUT(8*32+31 downto 8*32) => busuart_rx.data, + BUS_ADDR_OUT(8*16+15 downto 8*16) => busuart_rx.addr, BUS_TIMEOUT_OUT(8) => open, - BUS_DATA_IN(8*32+31 downto 8*32) => uart_dout, - BUS_DATAREADY_IN(8) => uart_ack, - BUS_WRITE_ACK_IN(8) => uart_ack, - BUS_NO_MORE_DATA_IN(8) => uart_empty, - BUS_UNKNOWN_ADDR_IN(8) => uart_nack, + BUS_DATA_IN(8*32+31 downto 8*32) => busuart_tx.data, + BUS_DATAREADY_IN(8) => busuart_tx.ack, + BUS_WRITE_ACK_IN(8) => busuart_tx.ack, + BUS_NO_MORE_DATA_IN(8) => busuart_tx.nack, + BUS_UNKNOWN_ADDR_IN(8) => busuart_tx.unknown, STAT_DEBUG => open ); @@ -1017,14 +1011,8 @@ gen_uart : if INCLUDE_UART = 1 generate RESET => reset_i, UART_RX => uart_rx, UART_TX => uart_tx, - DATA_OUT => uart_dout, - DATA_IN => uart_din, - ADDR_IN => uart_addr, - WRITE_IN => uart_write, - READ_IN => uart_read, - ACK_OUT => uart_ack, - EMPTY_OUT => uart_empty, - UNKWN_OUT => uart_nack + BUS_RX => busuart_rx, + BUS_TX => busuart_tx ); uart_rx(0) <= CLKRJ(0); -- 2.43.0