From 96f1e8b9dc737485ee9d81246bb6598012e213f7 Mon Sep 17 00:00:00 2001
From: hadaq <hadaq>
Date: Fri, 29 May 2009 14:43:28 +0000
Subject: [PATCH] *** empty log message ***

---
 compile_gsi.pl |  4 ++--
 mdc_oepb.vhd   | 18 ++++++++++++++----
 2 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/compile_gsi.pl b/compile_gsi.pl
index a993f77..a6c322f 100755
--- a/compile_gsi.pl
+++ b/compile_gsi.pl
@@ -32,8 +32,8 @@ my $PACKAGE="FPBGA256";
 my $SPEEDGRADE="5";
 
 #create full lpf file
-#system("cp ../trbnet/pinout/mdc_oep3.lpf workdir/mdc_oepb.lpf");
-#system("cat constraints.lpf >> workdir/mdc_oepb.lpf");
+system("cp ../trbnet/pinout/mdc_oep3.lpf workdir/mdc_oepb.lpf");
+system("cat constraints.lpf >> workdir/mdc_oepb.lpf");
 
 #generate timestamp
 my $t=time;
diff --git a/mdc_oepb.vhd b/mdc_oepb.vhd
index 1faca36..3fe2449 100644
--- a/mdc_oepb.vhd
+++ b/mdc_oepb.vhd
@@ -145,6 +145,7 @@ architecture mdc_oepb_arch of mdc_oepb is
   signal pseudo_timing_trigger : std_logic;
   signal cal_trigger_register_in_i : std_logic_vector(15 downto 0);
   signal direction_data_line_in_i : std_logic_vector(3 downto 0);
+  signal motherboard_type_in_i : std_logic_vector(3 downto 0);
 
 begin
 ---------------------------------------------------------------------
@@ -480,13 +481,22 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 )
   PROC_GEN_TIMING : process(CLK_100)
     begin
       if rising_edge(CLK_100) then
-        last_LVL1_TRG_RECEIVED_OUT <= REGIO_REGISTERS_OUT(0);
-        pseudo_timing_trigger <= REGIO_REGISTERS_OUT(0) and not last_LVL1_TRG_RECEIVED_OUT;
+      --  last_LVL1_TRG_RECEIVED_OUT <= REGIO_REGISTERS_OUT(0);
+      --  pseudo_timing_trigger <= REGIO_REGISTERS_OUT(0) and not last_LVL1_TRG_RECEIVED_OUT;
         cal_trigger_register_in_i <= x"000" & REGIO_REGISTERS_OUT(7 downto 4);
+        motherboard_type_in_i <= REGIO_REGISTERS_OUT(11 downto 8);
+        
       end if;
     end process;
 
- THE_TRIG_DISTR : trigger_distributor
+    PULSE_TRIGGER : edge_to_pulse
+      port map (
+        CLOCK         => CLK_100,
+        ENABLE_CLK_IN => '1',
+        SIGNAL_IN     => REGIO_REGISTERS_OUT(0),
+        PULSE_OUT     => pseudo_timing_trigger);
+
+    THE_TRIG_DISTR : trigger_distributor
     port map (
         CLK                => CLK_100,
         RESET              => reset,
@@ -544,7 +554,7 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 )
       ROC1_WRITTEN_OUT             => roc1_written_i,
      -- BUS_NUMBER_IN                => x"1",
       DIRECTION_DATA_LINE_IN       => direction_data_line_in_i,
-      BUS_CHAIN_IN                 => x"1",
+      MOTHERBOARD_TYPE_IN          => motherboard_type_in_i,
 
       ACKNOWLEDGE_TRB_INTERFACE_IN => x"1",
       INIT_TRB_INTERFACE_OUT       => open,
-- 
2.43.0