From 970b426eed83114decd7c8774e32f6374d7a48c7 Mon Sep 17 00:00:00 2001 From: Ludwig Maier Date: Mon, 15 Apr 2013 23:40:39 +0200 Subject: [PATCH] nxyter adc is delivering data so far --- nxyter/{source => cores}/fifo_32_data.vhd | 0 nxyter/cores/pll_adc_clk192.ipx | 8 + nxyter/cores/pll_adc_clk192.lpc | 66 + nxyter/cores/pll_adc_clk192.vhd | 97 ++ nxyter/cores/pll_adc_clk32.ipx | 8 + nxyter/cores/pll_adc_clk32.lpc | 66 + nxyter/cores/pll_adc_clk32.vhd | 97 ++ nxyter/cores/pll_nx_clk256.ipx | 8 + nxyter/cores/pll_nx_clk256.lpc | 66 + nxyter/{source => cores}/pll_nx_clk256.vhd | 2 +- nxyter/source/adc_receiver.vhd | 133 ++ nxyter/source/adcmv3_components.vhd | 148 -- nxyter/source/fifo_dc_9to36_dyn.vhd | 1245 ----------------- .../{nxyter.vhd => nxyter_fee_board.vhd} | 23 +- 14 files changed, 568 insertions(+), 1399 deletions(-) rename nxyter/{source => cores}/fifo_32_data.vhd (100%) create mode 100644 nxyter/cores/pll_adc_clk192.ipx create mode 100644 nxyter/cores/pll_adc_clk192.lpc create mode 100644 nxyter/cores/pll_adc_clk192.vhd create mode 100644 nxyter/cores/pll_adc_clk32.ipx create mode 100644 nxyter/cores/pll_adc_clk32.lpc create mode 100644 nxyter/cores/pll_adc_clk32.vhd create mode 100644 nxyter/cores/pll_nx_clk256.ipx create mode 100644 nxyter/cores/pll_nx_clk256.lpc rename nxyter/{source => cores}/pll_nx_clk256.vhd (99%) create mode 100644 nxyter/source/adc_receiver.vhd delete mode 100644 nxyter/source/adcmv3_components.vhd delete mode 100644 nxyter/source/fifo_dc_9to36_dyn.vhd rename nxyter/source/{nxyter.vhd => nxyter_fee_board.vhd} (97%) diff --git a/nxyter/source/fifo_32_data.vhd b/nxyter/cores/fifo_32_data.vhd similarity index 100% rename from nxyter/source/fifo_32_data.vhd rename to nxyter/cores/fifo_32_data.vhd diff --git a/nxyter/cores/pll_adc_clk192.ipx b/nxyter/cores/pll_adc_clk192.ipx new file mode 100644 index 0000000..1a132a6 --- /dev/null +++ b/nxyter/cores/pll_adc_clk192.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/nxyter/cores/pll_adc_clk192.lpc b/nxyter/cores/pll_adc_clk192.lpc new file mode 100644 index 0000000..244167c --- /dev/null +++ b/nxyter/cores/pll_adc_clk192.lpc @@ -0,0 +1,66 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.3 +ModuleName=pll_adc_clk192 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=04/15/2013 +Time=22:17:56 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=200 +Div=25 +ClkOPBp=0 +Post=4 +U_OFrq=192 +OP_Tol=0.0 +OFrq=192.000000 +DutyTrimP=Rising +DelayMultP=0 +fb_mode=CLKOP +Mult=24 +Phase=0.0 +Duty=8 +DelayMultS=0 +DPD=50% Duty +DutyTrimS=Rising +DelayMultD=0 +ClkOSDelay=0 +PhaseDuty=Static +CLKOK_INPUT=CLKOP +SecD=2 +U_KFrq=50 +OK_Tol=0.0 +KFrq= +ClkRst=0 +PCDR=0 +FINDELA=0 +VcoRate= +Bandwidth=1.141439 +;DelayControl=No +EnCLKOS=0 +ClkOSBp=0 +EnCLKOK=0 +ClkOKBp=0 +enClkOK2=0 diff --git a/nxyter/cores/pll_adc_clk192.vhd b/nxyter/cores/pll_adc_clk192.vhd new file mode 100644 index 0000000..bc30248 --- /dev/null +++ b/nxyter/cores/pll_adc_clk192.vhd @@ -0,0 +1,97 @@ +-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151) +-- Module Version: 5.3 +--/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -n pll_adc_clk192 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 192 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw -e + +-- Mon Apr 15 22:17:56 2013 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity pll_adc_clk192 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of pll_adc_clk192 : entity is true; +end pll_adc_clk192; + +architecture Structure of pll_adc_clk192 is + + -- internal signal declarations + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component EHXPLLF + generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; + DELAY_PWD : in String; DELAY_VAL : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + PHASE_DELAY_CNTL : in String; DUTY : in Integer; + PHASEADJ : in String; CLKOK_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; FIN : in String); + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; + FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "192.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLF + generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", + CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", + PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", + CLKOK_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 24, CLKI_DIV=> 25, + FIN=> "200.000000") + port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, + RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, + DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, + DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, + DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, + FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, + CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, + CLKINTFB=>open); + + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of pll_adc_clk192 is + for Structure + for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/nxyter/cores/pll_adc_clk32.ipx b/nxyter/cores/pll_adc_clk32.ipx new file mode 100644 index 0000000..890c7f3 --- /dev/null +++ b/nxyter/cores/pll_adc_clk32.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/nxyter/cores/pll_adc_clk32.lpc b/nxyter/cores/pll_adc_clk32.lpc new file mode 100644 index 0000000..2d97f85 --- /dev/null +++ b/nxyter/cores/pll_adc_clk32.lpc @@ -0,0 +1,66 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.3 +ModuleName=pll_adc_clk32 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=04/14/2013 +Time=23:13:35 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=200 +Div=25 +ClkOPBp=0 +Post=16 +U_OFrq=32 +OP_Tol=0.0 +OFrq=32.000000 +DutyTrimP=Rising +DelayMultP=0 +fb_mode=CLKOP +Mult=4 +Phase=0.0 +Duty=8 +DelayMultS=0 +DPD=50% Duty +DutyTrimS=Rising +DelayMultD=0 +ClkOSDelay=0 +PhaseDuty=Static +CLKOK_INPUT=CLKOP +SecD=2 +U_KFrq=50 +OK_Tol=0.0 +KFrq= +ClkRst=0 +PCDR=0 +FINDELA=0 +VcoRate= +Bandwidth=1.712159 +;DelayControl=No +EnCLKOS=0 +ClkOSBp=0 +EnCLKOK=0 +ClkOKBp=0 +enClkOK2=0 diff --git a/nxyter/cores/pll_adc_clk32.vhd b/nxyter/cores/pll_adc_clk32.vhd new file mode 100644 index 0000000..a293257 --- /dev/null +++ b/nxyter/cores/pll_adc_clk32.vhd @@ -0,0 +1,97 @@ +-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151) +-- Module Version: 5.3 +--/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -n pll_adc_clk32 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 32 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw -e + +-- Sun Apr 14 23:13:35 2013 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity pll_adc_clk32 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of pll_adc_clk32 : entity is true; +end pll_adc_clk32; + +architecture Structure of pll_adc_clk32 is + + -- internal signal declarations + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component EHXPLLF + generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; + DELAY_PWD : in String; DELAY_VAL : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + PHASE_DELAY_CNTL : in String; DUTY : in Integer; + PHASEADJ : in String; CLKOK_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; FIN : in String); + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; + FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "32.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLF + generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", + CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", + PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", + CLKOK_DIV=> 2, CLKOP_DIV=> 16, CLKFB_DIV=> 4, CLKI_DIV=> 25, + FIN=> "200.000000") + port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, + RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, + DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, + DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, + DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, + FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, + CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, + CLKINTFB=>open); + + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of pll_adc_clk32 is + for Structure + for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/nxyter/cores/pll_nx_clk256.ipx b/nxyter/cores/pll_nx_clk256.ipx new file mode 100644 index 0000000..e14fe9e --- /dev/null +++ b/nxyter/cores/pll_nx_clk256.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/nxyter/cores/pll_nx_clk256.lpc b/nxyter/cores/pll_nx_clk256.lpc new file mode 100644 index 0000000..61c089f --- /dev/null +++ b/nxyter/cores/pll_nx_clk256.lpc @@ -0,0 +1,66 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.3 +ModuleName=pll_nx_clk256 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=04/13/2013 +Time=17:24:24 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=100 +Div=25 +ClkOPBp=0 +Post=2 +U_OFrq=256 +OP_Tol=0.0 +OFrq=256.000000 +DutyTrimP=Rising +DelayMultP=0 +fb_mode=CLKOP +Mult=64 +Phase=0.0 +Duty=8 +DelayMultS=0 +DPD=50% Duty +DutyTrimS=Rising +DelayMultD=0 +ClkOSDelay=0 +PhaseDuty=Static +CLKOK_INPUT=CLKOP +SecD=2 +U_KFrq=50 +OK_Tol=0.0 +KFrq= +ClkRst=0 +PCDR=0 +FINDELA=0 +VcoRate= +Bandwidth=0.856080 +;DelayControl=No +EnCLKOS=0 +ClkOSBp=0 +EnCLKOK=0 +ClkOKBp=0 +enClkOK2=0 diff --git a/nxyter/source/pll_nx_clk256.vhd b/nxyter/cores/pll_nx_clk256.vhd similarity index 99% rename from nxyter/source/pll_nx_clk256.vhd rename to nxyter/cores/pll_nx_clk256.vhd index 02977d5..1299ae5 100644 --- a/nxyter/source/pll_nx_clk256.vhd +++ b/nxyter/cores/pll_nx_clk256.vhd @@ -2,7 +2,7 @@ -- Module Version: 5.3 --/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -n pll_nx_clk256 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 100 -phase_cntl STATIC -fclkop 256 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw -e --- Wed Oct 24 17:29:56 2012 +-- Sat Apr 13 17:24:24 2013 library IEEE; use IEEE.std_logic_1164.all; diff --git a/nxyter/source/adc_receiver.vhd b/nxyter/source/adc_receiver.vhd new file mode 100644 index 0000000..ccde877 --- /dev/null +++ b/nxyter/source/adc_receiver.vhd @@ -0,0 +1,133 @@ +---------------------------------------------------------------------------- +-- ADC Pulse height Handler +----------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.nxyter_components.all; + +entity adc_receiver is + + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + CLK_ADC_IN : in std_logic; + + ADC_FCLK_IN : in std_logic_vector(1 downto 0); + ADC_DCLK_IN : in std_logic_vector(1 downto 0); + ADC_SC_CLK32_OUT : out std_logic; + ADC_A_IN : in std_logic_vector(1 downto 0); + ADC_B_IN : in std_logic_vector(1 downto 0); + ADC_NX_IN : in std_logic_vector(1 downto 0); + ADC_D_IN : in std_logic_vector(1 downto 0); + + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end entity; + + +architecture Behavioral of adc_receiver is + + signal even_bit_reg : std_logic; + signal even_bit_ctr : unsigned(2 downto 0); + signal even_bits : std_logic_vector(5 downto 0); + signal even_word : std_logic_vector(5 downto 0); + signal new_even_word : std_logic; + + signal odd_bit_reg : std_logic; + signal odd_bit_ctr : unsigned(2 downto 0); + signal odd_bits : std_logic_vector(5 downto 0); + signal odd_word : std_logic_vector(5 downto 0); + signal new_odd_word : std_logic; + + signal adc_recv_clk : std_logic; + signal adc_recv_bits : std_logic_vector(3 downto 0); + + -- ADC PLLs + signal pll_32MHz : std_logic; + signal pll_lock_32MHz : std_logic; + + signal pll_192MHz : std_logic; + signal pll_lock_192MHz : std_logic; + +begin + + -- Debug + DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(1) <= pll_lock_32MHz; + DEBUG_OUT(2) <= pll_lock_192MHz; + -- DEBUG_OUT(3) <= '0';--pll_32MHz; + -- DEBUG_OUT(4) <= '0';--pll_192MHz; + -- + -- DEBUG_OUT(15 downto 5) <= (others => '0'); + + ----------------------------------------------------------------------------- + -- ADC PLLs + ----------------------------------------------------------------------------- + + pll_adc_clk192_1: pll_adc_clk192 + port map ( + CLK => CLK_ADC_IN, + CLKOP => pll_192MHz, + LOCK => pll_lock_192MHz + ); + + pll_adc_clk32_1: entity work.pll_adc_clk32 + port map ( + CLK => CLK_ADC_IN, + CLKOP => pll_32MHz, + LOCK => pll_lock_32MHz + ); + + ----------------------------------------------------------------------------- + -- ADC + ----------------------------------------------------------------------------- + + adc_ad9222_1: entity work.adc_ad9222 + generic map ( + CHANNELS => 4, + DEVICES => 2, + RESOLUTION => 12 + ) + port map ( + CLK => CLK_IN, + CLK_ADCREF => pll_32MHz, + CLK_ADCDAT => pll_192MHz, + RESTART_IN => '0', + ADCCLK_OUT => ADC_SC_CLK32_OUT, + + ADC_DATA(0) => ADC_NX_IN(0), + ADC_DATA(1) => ADC_A_IN(0), + ADC_DATA(2) => ADC_B_IN(0), + ADC_DATA(3) => ADC_D_IN(0), + + ADC_DATA(4) => ADC_NX_IN(1), + ADC_DATA(5) => ADC_A_IN(1), + ADC_DATA(6) => ADC_B_IN(1), + ADC_DATA(7) => ADC_D_IN(1), + + ADC_DCO => ADC_DCLK_IN, + ADC_FCO => ADC_FCLK_IN, + + DATA_OUT(11 downto 0) => DEBUG_OUT(15 downto 4), + DATA_OUT(95 downto 12) => open, + + FCO_OUT => open, + DATA_VALID_OUT(0) => DEBUG_OUT(3), + DATA_VALID_OUT(1) => open, + DEBUG => open + ); + + ----------------------------------------------------------------------------- + -- Output Signals + ----------------------------------------------------------------------------- + + ADC_SC_CLK32_OUT <= pll_32MHz; -- adc_sc_clk32_o; + + +end Behavioral; diff --git a/nxyter/source/adcmv3_components.vhd b/nxyter/source/adcmv3_components.vhd deleted file mode 100644 index 60fc111..0000000 --- a/nxyter/source/adcmv3_components.vhd +++ /dev/null @@ -1,148 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -package adcmv3_components is - -------------------------------------------------------------------------------- --- Components by Michael Boehmer -------------------------------------------------------------------------------- - - -------------------------------------------------------------------------------- --- TRBNet interfaces -------------------------------------------------------------------------------- - -component slv_register - generic ( - RESET_VALUE : std_logic_vector(31 downto 0)); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - BUSY_IN : in std_logic; - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - REG_DATA_IN : in std_logic_vector(31 downto 0); - REG_DATA_OUT : out std_logic_vector(31 downto 0); - STAT : out std_logic_vector(31 downto 0)); -end component slv_register; - -component slv_ped_thr_mem - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - SLV_ADDR_IN : in std_logic_vector(10 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - MEM_CLK_IN : in std_logic; - MEM_ADDR_IN : in std_logic_vector(6 downto 0); - MEM_0_D_OUT : out std_logic_vector(17 downto 0); - STAT : out std_logic_vector(31 downto 0)); -end component; - -component ped_thr_true - port ( - DataInA : in std_logic_vector(17 downto 0); - DataInB : in std_logic_vector(17 downto 0); - AddressA : in std_logic_vector(6 downto 0); - AddressB : in std_logic_vector(6 downto 0); - ClockA : in std_logic; - ClockB : in std_logic; - ClockEnA : in std_logic; - ClockEnB : in std_logic; - WrA : in std_logic; - WrB : in std_logic; - ResetA : in std_logic; - ResetB : in std_logic; - QA : out std_logic_vector(17 downto 0); - QB : out std_logic_vector(17 downto 0)); -end component; - -------------------------------------------------------------------------------- --- I2C INterfaces -------------------------------------------------------------------------------- - -component i2c_master - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SDA_IN : in std_logic; - SDA_OUT : out std_logic; - SCL_IN : in std_logic; - SCL_OUT : out std_logic; - STAT : out std_logic_vector(31 downto 0) - ); -end component i2c_master; - -component I2C_GSTART - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - START_IN : in std_logic; - DOSTART_IN : in std_logic; - I2C_SPEED_IN : in std_logic_vector(7 downto 0); - SDONE_OUT : out std_logic; - SOK_OUT : out std_logic; - SDA_IN : in std_logic; - SCL_IN : in std_logic; - R_SCL_OUT : out std_logic; - S_SCL_OUT : out std_logic; - R_SDA_OUT : out std_logic; - S_SDA_OUT : out std_logic; - BSM_OUT : out std_logic_vector(3 downto 0)); -end component I2C_GSTART; - - -component i2c_sendb - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - DOBYTE_IN : in std_logic; - I2C_SPEED_IN : in std_logic_vector(8 downto 0); - I2C_BYTE_IN : in std_logic_vector(8 downto 0); - I2C_BACK_OUT : out std_logic_vector(8 downto 0); - SDA_IN : in std_logic; - R_SDA_OUT : out std_logic; - S_SDA_OUT : out std_logic; - R_SCL_OUT : out std_logic; - S_SCL_OUT : out std_logic; - BDONE_OUT : out std_logic; - BOK_OUT : out std_logic; - BSM_OUT : out std_logic_vector(3 downto 0)); -end component i2c_sendb; - - -component i2c_slim - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - I2C_GO_IN : in std_logic; - ACTION_IN : in std_logic; - I2C_SPEED_IN : in std_logic_vector(8 downto 0); - I2C_ADR_IN : in std_logic_vector(7 downto 0); - I2C_CMD_IN : in std_logic_vector(7 downto 0); - I2C_DW_IN : in std_logic_vector(7 downto 0); - I2C_DR_OUT : out std_logic_vector(7 downto 0); - STATUS_OUT : out std_logic_vector(7 downto 0); - I2C_BUSY_OUT : out std_logic; - SDA_IN : in std_logic; - SDA_OUT : out std_logic; - SCL_IN : in std_logic; - SCL_OUT : out std_logic; - STAT : out std_logic_vector(31 downto 0)); -end component i2c_slim; - -end package; diff --git a/nxyter/source/fifo_dc_9to36_dyn.vhd b/nxyter/source/fifo_dc_9to36_dyn.vhd deleted file mode 100644 index 38dc35e..0000000 --- a/nxyter/source/fifo_dc_9to36_dyn.vhd +++ /dev/null @@ -1,1245 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_2.0_Production (151) --- Module Version: 5.4 ---/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 256 -width 9 -depth 256 -rdata_width 36 -regout -no_enable -pe 0 -pf -1 -e - --- Sun Mar 24 00:15:23 2013 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity fifo_dc_9to36_dyn is - port ( - Data: in std_logic_vector(8 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - AmEmptyThresh: in std_logic_vector(5 downto 0); - Q: out std_logic_vector(35 downto 0); - Empty: out std_logic; - Full: out std_logic; - AlmostEmpty: out std_logic); -end fifo_dc_9to36_dyn; - -architecture Structure of fifo_dc_9to36_dyn is - - -- internal signal declarations - signal invout_1: std_logic; - signal invout_0: std_logic; - signal wcount_r1: std_logic; - signal wcount_r0: std_logic; - signal w_g2b_xor_cluster_1: std_logic; - signal rcnt_reg_5_inv: std_logic; - signal w_gdata_0: std_logic; - signal w_gdata_1: std_logic; - signal w_gdata_2: std_logic; - signal w_gdata_3: std_logic; - signal w_gdata_4: std_logic; - signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; - signal wptr_0: std_logic; - signal wptr_1: std_logic; - signal wptr_2: std_logic; - signal wptr_3: std_logic; - signal wptr_4: std_logic; - signal wptr_5: std_logic; - signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; - signal r_gdata_0: std_logic; - signal r_gdata_1: std_logic; - signal r_gdata_2: std_logic; - signal r_gdata_3: std_logic; - signal r_gdata_4: std_logic; - signal r_gdata_5: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal w_gcount_0: std_logic; - signal w_gcount_1: std_logic; - signal w_gcount_2: std_logic; - signal w_gcount_3: std_logic; - signal w_gcount_4: std_logic; - signal w_gcount_5: std_logic; - signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; - signal r_gcount_0: std_logic; - signal r_gcount_1: std_logic; - signal r_gcount_2: std_logic; - signal r_gcount_3: std_logic; - signal r_gcount_4: std_logic; - signal r_gcount_5: std_logic; - signal r_gcount_6: std_logic; - signal w_gcount_r20: std_logic; - signal w_gcount_r0: std_logic; - signal w_gcount_r21: std_logic; - signal w_gcount_r1: std_logic; - signal w_gcount_r22: std_logic; - signal w_gcount_r2: std_logic; - signal w_gcount_r23: std_logic; - signal w_gcount_r3: std_logic; - signal w_gcount_r24: std_logic; - signal w_gcount_r4: std_logic; - signal w_gcount_r25: std_logic; - signal w_gcount_r5: std_logic; - signal w_gcount_r26: std_logic; - signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; - signal r_gcount_w20: std_logic; - signal r_gcount_w0: std_logic; - signal r_gcount_w21: std_logic; - signal r_gcount_w1: std_logic; - signal r_gcount_w22: std_logic; - signal r_gcount_w2: std_logic; - signal r_gcount_w23: std_logic; - signal r_gcount_w3: std_logic; - signal r_gcount_w24: std_logic; - signal r_gcount_w4: std_logic; - signal r_gcount_w25: std_logic; - signal r_gcount_w5: std_logic; - signal r_gcount_w26: std_logic; - signal r_gcount_w6: std_logic; - signal rcnt_reg_6: std_logic; - signal empty_i: std_logic; - signal full_i: std_logic; - signal rRst: std_logic; - signal iwcount_0: std_logic; - signal iwcount_1: std_logic; - signal w_gctr_ci: std_logic; - signal iwcount_2: std_logic; - signal iwcount_3: std_logic; - signal co0: std_logic; - signal iwcount_4: std_logic; - signal iwcount_5: std_logic; - signal co1: std_logic; - signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal co4: std_logic; - signal wcount_8: std_logic; - signal co3: std_logic; - signal ircount_0: std_logic; - signal ircount_1: std_logic; - signal r_gctr_ci: std_logic; - signal ircount_2: std_logic; - signal ircount_3: std_logic; - signal co0_1: std_logic; - signal ircount_4: std_logic; - signal ircount_5: std_logic; - signal co1_1: std_logic; - signal ircount_6: std_logic; - signal co3_1: std_logic; - signal rcount_6: std_logic; - signal co2_1: std_logic; - signal rcnt_sub_0: std_logic; - signal scuba_vhi: std_logic; - signal rcnt_sub_1: std_logic; - signal rcnt_sub_2: std_logic; - signal co0_2: std_logic; - signal rcnt_sub_3: std_logic; - signal rcnt_sub_4: std_logic; - signal co1_2: std_logic; - signal rcnt_sub_5: std_logic; - signal rcnt_sub_6: std_logic; - signal co2_2: std_logic; - signal rcnt_sub_msb: std_logic; - signal co3_2d: std_logic; - signal co3_2: std_logic; - signal cmp_ci: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; - signal rcount_0: std_logic; - signal rcount_1: std_logic; - signal co0_3: std_logic; - signal wcount_r4: std_logic; - signal w_g2b_xor_cluster_0: std_logic; - signal rcount_2: std_logic; - signal rcount_3: std_logic; - signal co1_3: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; - signal rcount_4: std_logic; - signal rcount_5: std_logic; - signal co2_3: std_logic; - signal empty_cmp_clr: std_logic; - signal empty_cmp_set: std_logic; - signal empty_d: std_logic; - signal empty_d_c: std_logic; - signal wren_i: std_logic; - signal cmp_ci_1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; - signal co0_4: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; - signal co1_4: std_logic; - signal rcount_w2: std_logic; - signal r_g2b_xor_cluster_0: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; - signal co2_4: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; - signal full_cmp_clr: std_logic; - signal full_cmp_set: std_logic; - signal full_d: std_logic; - signal full_d_c: std_logic; - signal rden_i: std_logic; - signal cmp_ci_2: std_logic; - signal rcnt_reg_0: std_logic; - signal rcnt_reg_1: std_logic; - signal co0_5: std_logic; - signal rcnt_reg_2: std_logic; - signal rcnt_reg_3: std_logic; - signal co1_5: std_logic; - signal rcnt_reg_4: std_logic; - signal rcnt_reg_5: std_logic; - signal co2_5: std_logic; - signal ae_clrsig: std_logic; - signal ae_setsig: std_logic; - signal ae_d: std_logic; - signal ae_d_c: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; GE: out std_logic); - end component; - component AND2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CO: out std_logic; NC0: out std_logic; NC1: out std_logic); - end component; - component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FSUB2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; BI: in std_logic; BOUT: out std_logic; - S0: out std_logic; S1: out std_logic); - end component; - component FD1P3BX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - PD: in std_logic; Q: out std_logic); - end component; - component FD1P3DX - port (D: in std_logic; SP: in std_logic; CK: in std_logic; - CD: in std_logic; Q: out std_logic); - end component; - component FD1S3BX - port (D: in std_logic; CK: in std_logic; PD: in std_logic; - Q: out std_logic); - end component; - component FD1S3DX - port (D: in std_logic; CK: in std_logic; CD: in std_logic; - Q: out std_logic); - end component; - component INV - port (A: in std_logic; Z: out std_logic); - end component; - component OR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component ROM16X1A - generic (INITVAL : in std_logic_vector(15 downto 0)); - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; - AD0: in std_logic; DO0: out std_logic); - end component; - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component XOR2 - port (A: in std_logic; B: in std_logic; Z: out std_logic); - end component; - component DP16KC - generic (GSR : in String; WRITEMODE_B : in String; - WRITEMODE_A : in String; CSDECODE_B : in String; - CSDECODE_A : in String; REGMODE_B : in String; - REGMODE_A : in String; DATA_WIDTH_B : in Integer; - DATA_WIDTH_A : in Integer); - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; - WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; - WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute RESETMODE : string; - attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_2 : label is "fifo_dc_9to36_dyn.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_2 : label is ""; - attribute RESETMODE of pdp_ram_0_0_2 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_1_1 : label is "fifo_dc_9to36_dyn.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_1_1 : label is ""; - attribute RESETMODE of pdp_ram_0_1_1 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_2_0 : label is "fifo_dc_9to36_dyn.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_2_0 : label is ""; - attribute RESETMODE of pdp_ram_0_2_0 : label is "SYNC"; - attribute GSR of FF_89 : label is "ENABLED"; - attribute GSR of FF_88 : label is "ENABLED"; - attribute GSR of FF_87 : label is "ENABLED"; - attribute GSR of FF_86 : label is "ENABLED"; - attribute GSR of FF_85 : label is "ENABLED"; - attribute GSR of FF_84 : label is "ENABLED"; - attribute GSR of FF_83 : label is "ENABLED"; - attribute GSR of FF_82 : label is "ENABLED"; - attribute GSR of FF_81 : label is "ENABLED"; - attribute GSR of FF_80 : label is "ENABLED"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; - attribute GSR of FF_31 : label is "ENABLED"; - attribute GSR of FF_30 : label is "ENABLED"; - attribute GSR of FF_29 : label is "ENABLED"; - attribute GSR of FF_28 : label is "ENABLED"; - attribute GSR of FF_27 : label is "ENABLED"; - attribute GSR of FF_26 : label is "ENABLED"; - attribute GSR of FF_25 : label is "ENABLED"; - attribute GSR of FF_24 : label is "ENABLED"; - attribute GSR of FF_23 : label is "ENABLED"; - attribute GSR of FF_22 : label is "ENABLED"; - attribute GSR of FF_21 : label is "ENABLED"; - attribute GSR of FF_20 : label is "ENABLED"; - attribute GSR of FF_19 : label is "ENABLED"; - attribute GSR of FF_18 : label is "ENABLED"; - attribute GSR of FF_17 : label is "ENABLED"; - attribute GSR of FF_16 : label is "ENABLED"; - attribute GSR of FF_15 : label is "ENABLED"; - attribute GSR of FF_14 : label is "ENABLED"; - attribute GSR of FF_13 : label is "ENABLED"; - attribute GSR of FF_12 : label is "ENABLED"; - attribute GSR of FF_11 : label is "ENABLED"; - attribute GSR of FF_10 : label is "ENABLED"; - attribute GSR of FF_9 : label is "ENABLED"; - attribute GSR of FF_8 : label is "ENABLED"; - attribute GSR of FF_7 : label is "ENABLED"; - attribute GSR of FF_6 : label is "ENABLED"; - attribute GSR of FF_5 : label is "ENABLED"; - attribute GSR of FF_4 : label is "ENABLED"; - attribute GSR of FF_3 : label is "ENABLED"; - attribute GSR of FF_2 : label is "ENABLED"; - attribute GSR of FF_1 : label is "ENABLED"; - attribute GSR of FF_0 : label is "ENABLED"; - attribute syn_keep : boolean; - -begin - -- component instantiation statements - AND2_t19: AND2 - port map (A=>WrEn, B=>invout_1, Z=>wren_i); - - INV_2: INV - port map (A=>full_i, Z=>invout_1); - - AND2_t18: AND2 - port map (A=>RdEn, B=>invout_0, Z=>rden_i); - - INV_1: INV - port map (A=>empty_i, Z=>invout_0); - - OR2_t17: OR2 - port map (A=>Reset, B=>RPReset, Z=>rRst); - - XOR2_t16: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t15: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - - XOR2_t14: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - - XOR2_t13: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - - XOR2_t12: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - - XOR2_t11: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - - XOR2_t10: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - - XOR2_t9: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); - - XOR2_t8: XOR2 - port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - - XOR2_t7: XOR2 - port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - - XOR2_t6: XOR2 - port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - - XOR2_t5: XOR2 - port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - - XOR2_t4: XOR2 - port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - - XOR2_t3: XOR2 - port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_gcount_r28, - DO0=>w_g2b_xor_cluster_0); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, - DO0=>w_g2b_xor_cluster_1); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r7); - - LUT4_15: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r6); - - LUT4_14: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4); - - LUT4_13: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, - AD1=>w_gcount_r25, AD0=>wcount_r6, DO0=>wcount_r3); - - LUT4_12: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r2); - - LUT4_11: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r1); - - LUT4_10: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r20, AD0=>scuba_vlo, DO0=>wcount_r0); - - LUT4_9: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, - AD1=>r_gcount_w25, AD0=>r_gcount_w26, - DO0=>r_g2b_xor_cluster_0); - - LUT4_8: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>rcount_w5); - - LUT4_7: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, - AD1=>r_gcount_w26, AD0=>scuba_vlo, DO0=>rcount_w4); - - LUT4_6: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, - AD1=>r_gcount_w24, AD0=>rcount_w5, DO0=>rcount_w2); - - LUT4_5: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, - AD1=>r_gcount_w23, AD0=>rcount_w4, DO0=>rcount_w1); - - LUT4_4: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, - AD1=>r_gcount_w22, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w0); - - XOR2_t2: XOR2 - port map (A=>w_gcount_r28, B=>rcount_6, Z=>rcnt_sub_msb); - - LUT4_3: ROM16X1A - generic map (initval=> X"0410") - port map (AD3=>rptr_6, AD2=>rcount_6, AD1=>w_gcount_r28, - AD0=>scuba_vlo, DO0=>empty_cmp_set); - - LUT4_2: ROM16X1A - generic map (initval=> X"1004") - port map (AD3=>rptr_6, AD2=>rcount_6, AD1=>w_gcount_r28, - AD0=>scuba_vlo, DO0=>empty_cmp_clr); - - LUT4_1: ROM16X1A - generic map (initval=> X"0140") - port map (AD3=>wptr_8, AD2=>wcount_8, AD1=>r_gcount_w26, - AD0=>scuba_vlo, DO0=>full_cmp_set); - - LUT4_0: ROM16X1A - generic map (initval=> X"4001") - port map (AD3=>wptr_8, AD2=>wcount_8, AD1=>r_gcount_w26, - AD0=>scuba_vlo, DO0=>full_cmp_clr); - - INV_0: INV - port map (A=>rcnt_reg_5, Z=>rcnt_reg_5_inv); - - AND2_t1: AND2 - port map (A=>rcnt_reg_6, B=>rcnt_reg_5_inv, Z=>ae_clrsig); - - AND2_t0: AND2 - port map (A=>rcnt_reg_6, B=>rcnt_reg_5, Z=>ae_setsig); - - pdp_ram_0_0_2: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18, - DATA_WIDTH_A=> 4) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>scuba_vlo, - ADA11=>scuba_vlo, ADA12=>scuba_vlo, ADA13=>scuba_vlo, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1, - ADB6=>rptr_2, ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5, - ADB10=>scuba_vlo, ADB11=>scuba_vlo, ADB12=>scuba_vlo, - ADB13=>scuba_vlo, CEB=>rden_i, CLKB=>RdClock, - OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), - DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(9), DOB5=>Q(10), - DOB6=>Q(11), DOB7=>Q(12), DOB8=>open, DOB9=>Q(18), - DOB10=>Q(19), DOB11=>Q(20), DOB12=>Q(21), DOB13=>Q(27), - DOB14=>Q(28), DOB15=>Q(29), DOB16=>Q(30), DOB17=>open); - - pdp_ram_0_1_1: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18, - DATA_WIDTH_A=> 4) - port map (DIA0=>Data(4), DIA1=>Data(5), DIA2=>Data(6), - DIA3=>Data(7), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>scuba_vlo, - ADA11=>scuba_vlo, ADA12=>scuba_vlo, ADA13=>scuba_vlo, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1, - ADB6=>rptr_2, ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5, - ADB10=>scuba_vlo, ADB11=>scuba_vlo, ADB12=>scuba_vlo, - ADB13=>scuba_vlo, CEB=>rden_i, CLKB=>RdClock, - OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(4), - DOB1=>Q(5), DOB2=>Q(6), DOB3=>Q(7), DOB4=>Q(13), DOB5=>Q(14), - DOB6=>Q(15), DOB7=>Q(16), DOB8=>open, DOB9=>Q(22), - DOB10=>Q(23), DOB11=>Q(24), DOB12=>Q(25), DOB13=>Q(31), - DOB14=>Q(32), DOB15=>Q(33), DOB16=>Q(34), DOB17=>open); - - pdp_ram_0_2_0: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18, - DATA_WIDTH_A=> 4) - port map (DIA0=>Data(8), DIA1=>scuba_vlo, DIA2=>scuba_vlo, - DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>scuba_vlo, - ADA11=>scuba_vlo, ADA12=>scuba_vlo, ADA13=>scuba_vlo, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1, - ADB6=>rptr_2, ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5, - ADB10=>scuba_vlo, ADB11=>scuba_vlo, ADB12=>scuba_vlo, - ADB13=>scuba_vlo, CEB=>rden_i, CLKB=>RdClock, - OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(8), - DOB1=>open, DOB2=>open, DOB3=>open, DOB4=>Q(17), DOB5=>open, - DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>Q(26), DOB10=>open, - DOB11=>open, DOB12=>open, DOB13=>Q(35), DOB14=>open, - DOB15=>open, DOB16=>open, DOB17=>open); - - FF_89: FD1P3BX - port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, - Q=>wcount_0); - - FF_88: FD1P3DX - port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_1); - - FF_87: FD1P3DX - port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_2); - - FF_86: FD1P3DX - port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_3); - - FF_85: FD1P3DX - port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_4); - - FF_84: FD1P3DX - port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_5); - - FF_83: FD1P3DX - port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_6); - - FF_82: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_81: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_80: FD1P3DX - port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_0); - - FF_79: FD1P3DX - port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_1); - - FF_78: FD1P3DX - port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_2); - - FF_77: FD1P3DX - port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_3); - - FF_76: FD1P3DX - port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_4); - - FF_75: FD1P3DX - port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_5); - - FF_74: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_6); - - FF_73: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_72: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_71: FD1P3DX - port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_0); - - FF_70: FD1P3DX - port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_1); - - FF_69: FD1P3DX - port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_2); - - FF_68: FD1P3DX - port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_3); - - FF_67: FD1P3DX - port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_4); - - FF_66: FD1P3DX - port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_5); - - FF_65: FD1P3DX - port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_6); - - FF_64: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_63: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_62: FD1P3BX - port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, - Q=>rcount_0); - - FF_61: FD1P3DX - port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_1); - - FF_60: FD1P3DX - port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_2); - - FF_59: FD1P3DX - port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_3); - - FF_58: FD1P3DX - port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_4); - - FF_57: FD1P3DX - port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_5); - - FF_56: FD1P3DX - port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rcount_6); - - FF_55: FD1P3DX - port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_0); - - FF_54: FD1P3DX - port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_1); - - FF_53: FD1P3DX - port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_2); - - FF_52: FD1P3DX - port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_3); - - FF_51: FD1P3DX - port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_4); - - FF_50: FD1P3DX - port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_5); - - FF_49: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>r_gcount_6); - - FF_48: FD1P3DX - port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_0); - - FF_47: FD1P3DX - port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_1); - - FF_46: FD1P3DX - port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_2); - - FF_45: FD1P3DX - port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_3); - - FF_44: FD1P3DX - port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_4); - - FF_43: FD1P3DX - port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_5); - - FF_42: FD1P3DX - port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, - Q=>rptr_6); - - FF_41: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); - - FF_40: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); - - FF_39: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); - - FF_38: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); - - FF_37: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); - - FF_36: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); - - FF_35: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); - - FF_34: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); - - FF_33: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); - - FF_32: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); - - FF_31: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); - - FF_30: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); - - FF_29: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); - - FF_28: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); - - FF_27: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); - - FF_26: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); - - FF_25: FD1S3DX - port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r20); - - FF_24: FD1S3DX - port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r21); - - FF_23: FD1S3DX - port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r22); - - FF_22: FD1S3DX - port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r23); - - FF_21: FD1S3DX - port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r24); - - FF_20: FD1S3DX - port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r25); - - FF_19: FD1S3DX - port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r26); - - FF_18: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_17: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - - FF_16: FD1S3DX - port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); - - FF_15: FD1S3DX - port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); - - FF_14: FD1S3DX - port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); - - FF_13: FD1S3DX - port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); - - FF_12: FD1S3DX - port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); - - FF_11: FD1S3DX - port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); - - FF_10: FD1S3DX - port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); - - FF_9: FD1S3DX - port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0); - - FF_8: FD1S3DX - port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1); - - FF_7: FD1S3DX - port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2); - - FF_6: FD1S3DX - port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3); - - FF_5: FD1S3DX - port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4); - - FF_4: FD1S3DX - port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5); - - FF_3: FD1S3DX - port map (D=>rcnt_sub_6, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_6); - - FF_2: FD1S3BX - port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); - - FF_1: FD1S3DX - port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - - FF_0: FD1S3BX - port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty); - - w_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, - S1=>open); - - w_gctr_0: CU2 - port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, - NC0=>iwcount_0, NC1=>iwcount_1); - - w_gctr_1: CU2 - port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, - NC0=>iwcount_2, NC1=>iwcount_3); - - w_gctr_2: CU2 - port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, - NC0=>iwcount_4, NC1=>iwcount_5); - - w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>scuba_vlo, CO=>co4, - NC0=>iwcount_8, NC1=>open); - - r_gctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, - S1=>open); - - r_gctr_0: CU2 - port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, - NC0=>ircount_0, NC1=>ircount_1); - - r_gctr_1: CU2 - port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, - NC0=>ircount_2, NC1=>ircount_3); - - r_gctr_2: CU2 - port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, - NC0=>ircount_4, NC1=>ircount_5); - - r_gctr_3: CU2 - port map (CI=>co2_1, PC0=>rcount_6, PC1=>scuba_vlo, CO=>co3_1, - NC0=>ircount_6, NC1=>open); - - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - rcnt_0: FSUB2B - port map (A0=>scuba_vhi, A1=>wcount_r2, B0=>scuba_vlo, - B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_2, S0=>open, - S1=>rcnt_sub_0); - - rcnt_1: FSUB2B - port map (A0=>wcount_r3, A1=>wcount_r4, B0=>rcount_1, - B1=>rcount_2, BI=>co0_2, BOUT=>co1_2, S0=>rcnt_sub_1, - S1=>rcnt_sub_2); - - rcnt_2: FSUB2B - port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r6, B0=>rcount_3, - B1=>rcount_4, BI=>co1_2, BOUT=>co2_2, S0=>rcnt_sub_3, - S1=>rcnt_sub_4); - - rcnt_3: FSUB2B - port map (A0=>wcount_r7, A1=>rcnt_sub_msb, B0=>rcount_5, - B1=>scuba_vlo, BI=>co2_2, BOUT=>co3_2, S0=>rcnt_sub_5, - S1=>rcnt_sub_6); - - rcntd: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>co3_2, COUT=>open, S0=>co3_2d, S1=>open); - - empty_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); - - empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r2, - B1=>wcount_r3, CI=>cmp_ci, GE=>co0_3); - - empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r4, - B1=>w_g2b_xor_cluster_0, CI=>co0_3, GE=>co1_3); - - empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r6, - B1=>wcount_r7, CI=>co1_3, GE=>co2_3); - - empty_cmp_3: AGEB2 - port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, - B1=>scuba_vlo, CI=>co2_3, GE=>empty_d_c); - - a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, - S1=>open); - - full_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, - CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); - - full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>cmp_ci_1, GE=>co0_4); - - full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w0, - B1=>rcount_w1, CI=>co0_4, GE=>co1_4); - - full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w2, - B1=>r_g2b_xor_cluster_0, CI=>co1_4, GE=>co2_4); - - full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w4, - B1=>rcount_w5, CI=>co2_4, GE=>co3_3); - - full_cmp_4: AGEB2 - port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, - B1=>scuba_vlo, CI=>co3_3, GE=>full_d_c); - - a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, - S1=>open); - - ae_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); - - ae_cmp_0: AGEB2 - port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1), - B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_5); - - ae_cmp_1: AGEB2 - port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3), - B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_5, GE=>co1_5); - - ae_cmp_2: AGEB2 - port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5), - B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_5, GE=>co2_5); - - ae_cmp_3: AGEB2 - port map (A0=>ae_setsig, A1=>scuba_vlo, B0=>ae_clrsig, - B1=>scuba_vlo, CI=>co2_5, GE=>ae_d_c); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - a2: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open); - - Empty <= empty_i; - Full <= full_i; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of fifo_dc_9to36_dyn is - for Structure - for all:AGEB2 use entity ecp3.AGEB2(V); end for; - for all:AND2 use entity ecp3.AND2(V); end for; - for all:CU2 use entity ecp3.CU2(V); end for; - for all:FADD2B use entity ecp3.FADD2B(V); end for; - for all:FSUB2B use entity ecp3.FSUB2B(V); end for; - for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; - for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; - for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; - for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; - for all:INV use entity ecp3.INV(V); end for; - for all:OR2 use entity ecp3.OR2(V); end for; - for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; - for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/nxyter/source/nxyter.vhd b/nxyter/source/nxyter_fee_board.vhd similarity index 97% rename from nxyter/source/nxyter.vhd rename to nxyter/source/nxyter_fee_board.vhd index f99ae31..f540b29 100644 --- a/nxyter/source/nxyter.vhd +++ b/nxyter/source/nxyter_fee_board.vhd @@ -197,7 +197,7 @@ begin -- DEBUG_LINE_OUT(7) <= '0'; -- -- --- DEBUG_gLINE_OUT(8) <= ADC_FCLK_IN; +-- DEBUG_LINE_OUT(8) <= ADC_FCLK_IN; -- DEBUG_LINE_OUT(9) <= ADC_DCLK_IN; -- DEBUG_LINE_OUT(10) <= ADC_SC_CLK32_OUT; -- DEBUG_LINE_OUT(11) <= ADC_A_IN; @@ -539,8 +539,8 @@ begin SLV_NO_MORE_DATA_OUT => slv_no_more_data(2), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2), - DEBUG_OUT => DEBUG_LINE_OUT - -- DEBUG_OUT => open + --DEBUG_OUT => DEBUG_LINE_OUT + DEBUG_OUT => open ); @@ -664,8 +664,21 @@ begin -- DEBUG => open -- ); - - ADC_SC_CLK32_OUT <= adc_clk_o; + + adc_ad9228_1: adc_ad9228 + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + ADC_FCLK_IN => ADC_FCLK_IN, + ADC_DCLK_IN => ADC_DCLK_IN, + ADC_SC_CLK32_OUT => ADC_SC_CLK32_OUT, + ADC_A_IN => ADC_A_IN, + ADC_B_IN => ADC_B_IN, + ADC_NX_IN => ADC_NX_IN, + ADC_D_IN => ADC_D_IN, + --DEBUG_OUT => open, + DEBUG_OUT => DEBUG_LINE_OUT + ); ------------------------------------------------------------------------------- -- nXyter Signals -- 2.43.0