From 9774e2de817c694e98518ef46b85b40e72e5bb6c Mon Sep 17 00:00:00 2001 From: Adrian Weber Date: Thu, 10 Jan 2019 00:06:26 +0100 Subject: [PATCH] mRICH Sensors with UID --- hub_cts/code/EnvBoardParserHandler.vhd | 20 +++---- hub_cts/code/trb3sc_tools_mRICH.vhd | 6 +-- hub_cts/trb3sc_hubcts.vhd | 73 +++++++++++++++++++++----- 3 files changed, 74 insertions(+), 25 deletions(-) diff --git a/hub_cts/code/EnvBoardParserHandler.vhd b/hub_cts/code/EnvBoardParserHandler.vhd index 41a71fa..2313002 100644 --- a/hub_cts/code/EnvBoardParserHandler.vhd +++ b/hub_cts/code/EnvBoardParserHandler.vhd @@ -28,20 +28,20 @@ architecture behavioral of envBoardParserHandler is signal serialNumber : std_logic_vector(6 downto 0) := "0000000"; signal sensorNumber : std_logic_vector(1 downto 0) := "00"; signal typ : std_logic_vector(1 downto 0) := "00"; - signal value : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_1111_1111"; + signal value : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; -- signals for output result from THE_MAGBOARD_PARSER -- sensor0 - signal value_M_T_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0001"; - signal value_M_X_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0010"; - signal value_M_Y_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0011"; - signal value_M_Z_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0100"; + signal value_M_T_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; + signal value_M_X_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; + signal value_M_Y_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; + signal value_M_Z_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; -- sensor1 - signal value_BME_T_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0101"; - signal value_BME_P_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0110"; - signal value_BME_H_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0111"; + signal value_BME_T_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; + signal value_BME_P_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; + signal value_BME_H_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; -- sensor2 - signal value_L_0_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_1000"; - signal value_L_1_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_1001"; + signal value_L_0_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; + signal value_L_1_i : unsigned(30 downto 0) := b"000_0000_0000_0000_0000_0000_0000_0000"; -- signals for PROC_CHECK_ERROR diff --git a/hub_cts/code/trb3sc_tools_mRICH.vhd b/hub_cts/code/trb3sc_tools_mRICH.vhd index b39d1f6..637177e 100644 --- a/hub_cts/code/trb3sc_tools_mRICH.vhd +++ b/hub_cts/code/trb3sc_tools_mRICH.vhd @@ -31,7 +31,7 @@ entity trb3sc_tools is LCD_DATA_IN : in std_logic_vector(511 downto 0) := (others => '0'); ADDITIONAL_REG : out std_logic_vector(31 downto 0); --HDR_IO - HEADER_IO : inout std_logic_vector(10 downto 1); + HEADER_IO : inout std_logic_vector(8 downto 1); --ADC ADC_CS : out std_logic := '0'; @@ -438,8 +438,8 @@ HEADER_IO(8) <= lcd_rst; debug_rx <= '0'; -debug_rx <= HEADER_IO(9); -HEADER_IO(10) <= debug_tx; +--debug_rx <= HEADER_IO(9); +--HEADER_IO(10) <= debug_tx; -- HEADER_IO( 9) : ONEWIRE-Temperature chain -- HEADER_IO(10): RX-UART from Sensorboard diff --git a/hub_cts/trb3sc_hubcts.vhd b/hub_cts/trb3sc_hubcts.vhd index 5622a87..c22e603 100644 --- a/hub_cts/trb3sc_hubcts.vhd +++ b/hub_cts/trb3sc_hubcts.vhd @@ -125,9 +125,9 @@ architecture trb3sc_arch of trb3sc_hubcts is signal int2med : int2med_array_t(0 to INTERFACE_NUM-1); signal ctrlbus_rx, bussci1_rx, bussci2_rx, bussci3_rx, bustools_rx, buscts_rx, - bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, handlerbus_rx, bustdc_rx,bustdccal_rx, bus_mbs_rx : CTRLBUS_RX; + bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, handlerbus_rx, bustdc_rx,bustdccal_rx, bus_mbs_rx, busonewire_rx, busparser_rx : CTRLBUS_RX; signal ctrlbus_tx, bussci1_tx, bussci2_tx, bussci3_tx, bustools_tx, buscts_tx, - bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in, bustdc_tx,bustdccal_tx, bus_mbs_tx : CTRLBUS_TX; + bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in, bustdc_tx,bustdccal_tx, bus_mbs_tx, busonewire_tx, busparser_tx : CTRLBUS_TX; signal sed_error_i : std_logic; signal bus_master_active : std_logic; @@ -236,7 +236,11 @@ architecture trb3sc_arch of trb3sc_hubcts is attribute syn_preserve of bustc_rx : signal is true; attribute syn_keep of bus_mbs_rx : signal is true; attribute syn_preserve of bus_mbs_rx : signal is true; - + attribute syn_keep of busonewire_rx : signal is true; + attribute syn_preserve of busonewire_rx : signal is true; + attribute syn_keep of busparser_rx : signal is true; + attribute syn_preserve of busparser_rx : signal is true; + begin @@ -846,9 +850,9 @@ end generate; --------------------------------------------------------------------------- THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( - PORT_NUMBER => 11, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"8100", 6 => x"8300", 7 => x"a000", 8 => x"c000", 9 => x"e000", 10 => x"e400", others => x"0000"), - PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 8, 6 => 8, 7 => 11, 8 => 12, 9 => 9 , 10 => 9, others => 0), + PORT_NUMBER => 13, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"8100", 6 => x"8300", 7 => x"a000", 8 => x"c000", 9 => x"e000", 10 => x"e400", 11 => x"e600",12 => x"e610", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 8, 6 => 8, 7 => 11, 8 => 12, 9 => 9 , 10 => 9 , 11 => 4 ,12 => 4 , others => 0), PORT_MASK_ENABLE => 1 ) port map( @@ -869,6 +873,8 @@ end generate; BUS_RX(8) => bustdc_rx, BUS_RX(9) => bustdccal_rx, BUS_RX(10)=> bus_mbs_rx, + BUS_RX(11)=> busonewire_rx, + BUS_RX(12)=> busparser_rx, BUS_TX(0) => bustools_tx, BUS_TX(1) => bustc_tx, BUS_TX(2) => bussci1_tx, @@ -880,6 +886,8 @@ end generate; BUS_TX(8) => bustdc_tx, BUS_TX(9) => bustdccal_tx, BUS_TX(10)=> bus_mbs_tx, + BUS_TX(11)=> busonewire_tx, + BUS_TX(12)=> busparser_tx, STAT_DEBUG => open ); @@ -906,7 +914,7 @@ end generate; SPI_MISO_IN => spi_miso, SPI_CLK_OUT => spi_clk, --Header - HEADER_IO => HDR_IO, + HEADER_IO => HDR_IO(8 downto 1), --LCD LCD_DATA_IN => open, --ADC @@ -1080,9 +1088,50 @@ end generate; hit_in_i(i*2+2) <= not INP(i+64); end generate Gen_Hit_In_Signals; end generate; - - -end architecture; - - + +--------------------------------------------------------------------------- +-- OneWire TempSensor DS18b20 +--------------------------------------------------------------------------- + THE_ONEWIRE : entity work.onewire_record + generic map( + N_SENSORS => 10, -- Number of connected sensors + ROM_ADDR_0 => x"2B0416524E83FF28", + ROM_ADDR_1 => x"F9041651C3F7FF28", + ROM_ADDR_2 => x"9E0000092C4AFD28", + ROM_ADDR_3 => x"F20000092C509F28", + ROM_ADDR_4 => x"D90000092C890E28", + ROM_ADDR_5 => x"A90000092C88F428", + ROM_ADDR_6 => x"EC0000092ACAE828", + ROM_ADDR_7 => x"430000092AC40728", + ROM_ADDR_8 => x"630000092ADF4428", + ROM_ADDR_9 => x"450000092C355A28" + ) + port map( + CLK => clk_sys, + RESET => reset_i, + READOUT_ENABLE_IN => '1', + --connection to 1-wire interface + ONEWIRE => HDR_IO(9), + --INTERLOCK + INTERLOCK_FLAG => open, + INTERLOCK_LIMIT => x"00000280",--interlock_limit_i, --40°C + -- SLOW CONTROL + BUS_RX => busonewire_rx, + BUS_TX => busonewire_tx + ); + THE_UART : entity work.uart_env + generic map( + OUTPUTS => 1, + BAUD => 9600 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + UART_RX(0)=> HDR_IO(10), + UART_TX(0)=> open, + BUS_RX => busparser_rx, + BUS_TX => busparser_tx + ); + +end architecture; -- 2.43.0