From 979c4e2d6e294670575a4ffd75f0e2cbe5daf94b Mon Sep 17 00:00:00 2001
From: Michael Boehmer <mboehmer@ph.tum.de>
Date: Wed, 26 Jan 2022 17:15:01 +0100
Subject: [PATCH] unknown

---
 special/phaser.vhd | 123 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 123 insertions(+)
 create mode 100644 special/phaser.vhd

diff --git a/special/phaser.vhd b/special/phaser.vhd
new file mode 100644
index 0000000..59f6e8d
--- /dev/null
+++ b/special/phaser.vhd
@@ -0,0 +1,123 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+
+entity phaser is
+  port( 
+    SAMPLE_CLK    : in  std_logic;
+    RESET         : in  std_logic;
+    SIGNAL_A_IN   : in  std_logic;
+    SIGNAL_B_IN   : in  std_logic;
+    LOW_CNT_OUT   : out std_logic_vector(15 downto 0);
+    HI_CNT_OUT    : out std_logic_vector(15 downto 0);
+    UPDATE_OUT    : out std_logic
+  );
+end entity phaser;
+
+architecture arch of phaser is
+
+-- Components
+
+-- state machine signals
+
+-- Signals
+  signal low_cnt      : unsigned(15 downto 0);
+  signal hi_cnt       : unsigned(15 downto 0);
+  signal cyc_cnt      : unsigned(15 downto 0);
+  signal update       : std_logic;
+  signal cycle_done_x : std_logic;
+  signal cycle_done   : std_logic;
+  signal phase_x      : std_logic;
+  signal phase        : std_logic;
+
+  signal low_cnt_int  : std_logic_vector(15 downto 0);
+  signal hi_cnt_int   : std_logic_vector(15 downto 0);
+
+--attribute HGROUP: string;
+--attribute BBOX: string;
+--attribute HGROUP of behavioural: architecture is "phaser";
+--attribute BBOX   of behavioural: architecture is "5,5";
+
+begin
+
+---------------------------------------------------------------------------
+-- Sync process
+---------------------------------------------------------------------------
+  THE_SYNC_PROCESS: process( SAMPLE_CLK ) 
+  begin
+    if( rising_edge(SAMPLE_CLK) ) then
+      cycle_done  <= cycle_done_x;
+      update      <= cycle_done;
+      phase       <= phase_x;
+    end if;
+  end process THE_SYNC_PROCESS;
+
+  phase_x <= SIGNAL_A_IN xor SIGNAL_B_IN;
+
+  -- Cycle counter
+  THE_CYC_CNT_PROC: process( SAMPLE_CLK, RESET )
+  begin
+    if( RESET = '1' ) then
+      cyc_cnt <= (others => '0');
+    elsif( rising_edge(SAMPLE_CLK) ) then
+      if( cycle_done = '1' ) then
+        cyc_cnt <= (others => '0');
+      else
+        cyc_cnt <= cyc_cnt + 1;
+      end if;
+    end if;
+  end process THE_CYC_CNT_PROC;
+
+  cycle_done_x <= '1' when (cyc_cnt = x"fffc") else '0';
+
+  -- low signal count
+  THE_LOW_CNT_PROC: process( SAMPLE_CLK, RESET )
+  begin
+    if( RESET = '1' ) then
+      low_cnt <= (others => '0');
+    elsif( rising_edge(SAMPLE_CLK) ) then
+      if( cycle_done = '1' ) then
+        low_cnt <= (others => '0');
+      elsif( phase = '0') then
+        low_cnt <= low_cnt + 1;
+      end if;
+    end if;
+  end process THE_LOW_CNT_PROC;
+
+  -- high signal count
+  THE_HI_CNT_PROC: process( SAMPLE_CLK, RESET )
+  begin
+    if( RESET = '1' ) then
+      hi_cnt <= (others => '0');
+    elsif( rising_edge(SAMPLE_CLK) ) then
+      if( cycle_done = '1' ) then
+        hi_cnt <= (others => '0');
+      elsif( phase = '1') then
+        hi_cnt <= hi_cnt + 1;
+      end if;
+    end if;
+  end process THE_HI_CNT_PROC;
+
+  THE_COUNTER_STORE_PROC: process( SAMPLE_CLK, RESET )
+  begin
+    if( RESET = '1' ) then
+      low_cnt_int <= (others => '0');
+      hi_cnt_int  <= (others => '0');
+    elsif( rising_edge(SAMPLE_CLK) ) then -- added
+      if( cycle_done = '1' ) then
+        low_cnt_int <= std_logic_vector(low_cnt);
+        hi_cnt_int  <= std_logic_vector(hi_cnt);
+      end if;
+    end if;
+  end process THE_COUNTER_STORE_PROC;
+
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+
+  LOW_CNT_OUT <= low_cnt_int;
+  HI_CNT_OUT  <= hi_cnt_int;
+  UPDATE_OUT  <= update;
+
+end architecture;
-- 
2.43.0