From 97d0e8f3e09d4ba7d6b0cf7625909a2827d5f7c6 Mon Sep 17 00:00:00 2001 From: Manuel Penschuck Date: Sun, 28 Sep 2014 20:38:54 +0200 Subject: [PATCH] CTS: Back-Up before migrating to CBMNet LPv3 --- cts/compile_central_frankfurt.pl | 16 ++++++++++------ cts/compile_constraints.pl | 9 +++++---- cts/config_default.vhd | 2 +- cts/trb3_central.prj | 14 +++++++------- cts/trb3_central.vhd | 7 +++---- cts/trb3_central_constraints.lpf | 2 +- 6 files changed, 27 insertions(+), 23 deletions(-) diff --git a/cts/compile_central_frankfurt.pl b/cts/compile_central_frankfurt.pl index ac56f69..f994e90 100755 --- a/cts/compile_central_frankfurt.pl +++ b/cts/compile_central_frankfurt.pl @@ -5,6 +5,7 @@ use strict; use Term::ANSIColor; use File::stat; use POSIX; +use Cwd 'abs_path'; ################################################################################### @@ -19,12 +20,15 @@ my $lattice_path = '/d/jspc29/lattice/diamond/3.2_x64'; my $synplify_path = '/d/jspc29/lattice/synplify/I-2013.09-SP1/'; ################################################################################### + system("./compile_constraints.pl"); symlink($CbmNetPath, '../cbmnet/cbmnet') unless (-e '../cbmnet/cbmnet'); use FileHandle; +my $absBasePath = abs_path($BasePath); + $ENV{'SYNPLIFY'}=$synplify_path; $ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; $ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; @@ -66,7 +70,6 @@ my $r = ""; my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; $r=execute($c, "do_not_exit" ); - chdir "workdir"; $fh = new FileHandle("<$TOPNAME".".srr"); @@ -113,17 +116,18 @@ execute($c); $c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); -$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; +$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; execute($c); -$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; +$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); + # TWR Timing Report -$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; +$c=qq|$lattice_path/ispfpga/bin/lin/trce -fullname -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); -$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; +$c=qq|$lattice_path/ispfpga/bin/lin/trce -fullname -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); @@ -138,7 +142,7 @@ sub execute { print color 'blue bold'; print "\n\ncommand to execute: $c \n"; print color 'reset'; - $r=system($c); + $r=system("$c | $absBasePath/pretty_syn.pl"); if($r) { print "$!"; if($op ne "do_not_exit") { diff --git a/cts/compile_constraints.pl b/cts/compile_constraints.pl index a45cb49..d7a9f8f 100755 --- a/cts/compile_constraints.pl +++ b/cts/compile_constraints.pl @@ -12,6 +12,7 @@ $workdir = $ARGV[0] if (@ARGV); # get activated modules +my %configSettings = (); open(CONFIG, 'config.vhd'); my $config = "#!!! This file was compiled using compile_contraints.pl.\n#!!! DO NOT EDIT AS ALL CHANGES WILL BE OVERRIDEN\n\n"; print "The following module configuration was derived from config.vhd:\n"; @@ -19,6 +20,7 @@ while(my $line = ) { if ($line =~ /(INCLUDE_\S+).*:=.*c_(yes|no)/i) { my $mod = uc $1; my $ena = (lc $2) eq 'yes' ? 1 : 0; + $configSettings{$mod} = $ena; my $conf = "set $mod $ena\n"; print ' ' . $conf; @@ -50,14 +52,13 @@ unless(-e $workdir) { chdir($workdir); system ("$back/../../base/linkdesignfiles.sh '$back'"); symlink "$back/../../base/cores/cbmnet_sfp1.txt", 'cbmnet_sfp1.txt'; +symlink "$back/../tdc_release/Adder_304.ngo", "Adder_304.ngo"; chdir($script_dir); -system ("ln -sfT $back/../tdc_release/Adder_304.ngo $workdir/Adder_304.ngo"); - system("cp ../base/trb3_central_cts.lpf $workdir/$TOPNAME.lpf"); -# system("cat tdc_release/tdc_constraints_4.lpf >> $workdir/$TOPNAME.lpf"); +system("cat tdc_release/tdc_constraints_4.lpf >> $workdir/$TOPNAME.lpf") if $configSettings{'INCLUDE_TDC'}; system("cat ".$TOPNAME."_constraints.lpf >> $workdir/$TOPNAME.lpf"); -system("sed -i 's#THE_TDC/#gen_TDC_THE_TDC/#g' $workdir/$TOPNAME.lpf"); +system("sed -i 's#THE_TDC/#gen_TDC.THE_TDC/#g' $workdir/$TOPNAME.lpf"); diff --git a/cts/config_default.vhd b/cts/config_default.vhd index 15a4e50..c13ca40 100644 --- a/cts/config_default.vhd +++ b/cts/config_default.vhd @@ -29,7 +29,7 @@ package config is constant USE_125_MHZ : integer range c_NO to c_YES := c_NO; --Run external 200 MHz clock source - constant USE_EXTERNAL_CLOCK : integer range c_NO to c_YES := c_NO; + constant USE_EXTERNAL_CLOCK : integer range c_NO to c_YES := c_YES; --Which external trigger module (ETM) to use? diff --git a/cts/trb3_central.prj b/cts/trb3_central.prj index 0213ef5..ec1bd5d 100644 --- a/cts/trb3_central.prj +++ b/cts/trb3_central.prj @@ -12,29 +12,29 @@ set_option -speed_grade -8 set_option -part_companion "" # compilation/mapping options -set_option -default_enum_encoding sequential +#set_option -default_enum_encoding sequential set_option -symbolic_fsm_compiler 1 set_option -top_module "trb3_central" -set_option -resource_sharing true +#set_option -resource_sharing true # Lattice XP set_option -maxfan 100 set_option -fix_gated_and_generated_clocks 1 -#set_option -RWCheckOnRam 1 -#set_option -update_models_cp 0 +set_option -RWCheckOnRam 1 +set_option -update_models_cp 0 set_option -syn_edif_array_rename 1 # map options set_option -frequency 200 -set_option -fanout_limit 100 +set_option -fanout_limit 1000 set_option -disable_io_insertion 0 set_option -force_gsr false -set_option -fixgatedclocks 3 -set_option -fixgeneratedclocks 3 set_option -compiler_compatible true +set_option -retiming 0 +set_option -pipe 1 set_option -max_parallel_jobs 3 #set_option -automatic_compile_point 1 diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd index 53a3c37..999ee51 100644 --- a/cts/trb3_central.vhd +++ b/cts/trb3_central.vhd @@ -1006,7 +1006,7 @@ begin ); -- TODO: just borrowed from CTS ... ! - JOUT2 <= "000" & cbm_dlm_ref_rec_va_i; + JOUT2 <= cbm_data2send_stop_i & cbm_link_active_i & cbm_clk_i & cbm_dlm_ref_rec_va_i; THE_CBMNET_READOUT: cbmnet_readout port map( @@ -2126,9 +2126,8 @@ LED_YELLOW <= link_ok when INCLUDE_CBMNET=c_NO else cbm_dlm_ref_rec_va_i; -- Test Connector --------------------------------------------------------------------------- - TEST_LINE(15 downto 0) <= tdc_debug; - TEST_LINE(16) <= CLK_EXT(3); --this prevents adding an input register in the CBM MBS input module - TEST_LINE(31 downto 17) <= (others => '0'); + TEST_LINE(17 downto 0) <= cbm_data_from_link_i; + TEST_LINE(31 downto 18) <= cbm_data2link_i(13 downto 0); end architecture; \ No newline at end of file diff --git a/cts/trb3_central_constraints.lpf b/cts/trb3_central_constraints.lpf index 0ad0e23..58cf0ec 120000 --- a/cts/trb3_central_constraints.lpf +++ b/cts/trb3_central_constraints.lpf @@ -1 +1 @@ -trb3_central_constraints_3.lpf \ No newline at end of file +trb3_central_constraints_2.lpf \ No newline at end of file -- 2.43.0