From 98ef9b931e10cf4c8e522a8a7a3a03d964900c09 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Thu, 18 Aug 2022 21:00:16 +0200 Subject: [PATCH] syntonous in operation --- gbe_hub/trb3sc_gbe_hub.vhd | 61 +++++++++++++++++++++++++++----------- 1 file changed, 43 insertions(+), 18 deletions(-) diff --git a/gbe_hub/trb3sc_gbe_hub.vhd b/gbe_hub/trb3sc_gbe_hub.vhd index dcaa3b2..4e13b27 100644 --- a/gbe_hub/trb3sc_gbe_hub.vhd +++ b/gbe_hub/trb3sc_gbe_hub.vhd @@ -208,7 +208,10 @@ architecture trb3sc_arch of trb3sc_gbe_hub is signal dlm_tag_ctr : unsigned(7 downto 0); signal inc_dlm_tag : std_logic; - + + signal master_clk : std_logic; + signal global_reset_i : std_logic; + begin -- SerDes usage: @@ -237,7 +240,7 @@ begin THE_CLOCK_RESET_HANDLER: entity clock_reset_handler port map( CLK_IN => CLK_SUPPL_PCLK, - GLOBAL_RESET_IN => '0', -- for sync operation + GLOBAL_RESET_IN => global_reset_i, --'0', -- for sync operation RESET_FROM_NET_IN => '0', -- unused -- CLK_OUT => clk_sys, @@ -253,16 +256,16 @@ begin LED_GREEN_OUT => LED_RJ_GREEN(1) ); - HDR_IO(1) <= clear_n_i; - HDR_IO(2) <= reset_n_i; - HDR_IO(3) <= tx_pll_lol_d_i; - HDR_IO(4) <= link_tx_ready_i; + HDR_IO(1) <= '0'; + HDR_IO(2) <= '0'; + HDR_IO(3) <= '0'; + HDR_IO(4) <= '0'; HDR_IO(5) <= '0'; HDR_IO(6) <= '0'; HDR_IO(7) <= '0'; HDR_IO(8) <= '0'; HDR_IO(9) <= '0'; - HDR_IO(10) <= clk_sys; + HDR_IO(10) <= '0'; --------------------------------------------------------------------------- -- DLM timing generator @@ -302,7 +305,7 @@ begin --------------------------------------------------------------------------- THE_SGL_CTRL: entity sgl_ctrl port map( - CLK => clk_sys, + CLK => master_clk, RESET => reset_i, -- UL port UL_FIFOFULL_IN => ul_tx_fifofull, -- UL TX FIFO is full @@ -334,7 +337,7 @@ begin -- Multiplexers for data streams --------------------------------------------------------------------------- THE_PIPELINING: for I in 0 to 9 generate - dl_rx_data_q(I) <= dl_rx_data(I) when rising_edge(clk_sys); + dl_rx_data_q(I) <= dl_rx_data(I) when rising_edge(master_clk); end generate THE_PIPELINING; THE_DL_RX_MUX: process( dl_rx_port_mux, dl_rx_data_q ) @@ -374,7 +377,7 @@ begin DBG(31 downto 0) <= debug(31 downto 0); DBG(32) <= '0'; - DBG(33) <= clk_sys; + DBG(33) <= master_clk; -- DBG(3 downto 0) <= dl_rx_port_mux; -- DBG(11 downto 4) <= ul_rx_data(7 downto 0); @@ -389,7 +392,7 @@ begin -- DBG(30) <= ul_rx_data(10); -- DBG(31) <= ul_rx_fifofull; -- DBG(32) <= dl_rx_data(0)(8); --- DBG(33) <= clk_sys; +-- DBG(33) <= master_clk; --------------------------------------------------------------------------- -- GbE wrapper without med interface @@ -403,7 +406,7 @@ begin LINK_HAS_FWD => '0' ) port map( - CLK_125_IN => clk_sys, + CLK_125_IN => master_clk, RESET => reset_i, GSR_N => reset_n_i, -- we connect to FIFO interface directly @@ -428,7 +431,7 @@ begin MY_TRBNET_ADDRESS_IN => timer.network_address, ISSUE_REBOOT_OUT => reboot_from_gbe, -- slow control by GbE - GSC_CLK_IN => clk_sys, + GSC_CLK_IN => master_clk, GSC_INIT_DATAREADY_OUT => gsc_init_dataready, GSC_INIT_DATA_OUT => gsc_init_data, GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num, @@ -462,7 +465,7 @@ begin ) port map( -- Misc - CLK => clk_sys, + CLK => master_clk, RESET => reset_i, CLK_EN => '1', --Port to GbE @@ -511,7 +514,7 @@ begin PORT_MASK_ENABLE => 1 ) port map( - CLK => clk_sys, + CLK => master_clk, RESET => reset_i, -- REGIO_RX => ctrlbus_rx, @@ -527,7 +530,7 @@ begin --------------------------------------------------------------------------- THE_TOOLS : entity work.tomcat_tools port map( - CLK => clk_sys, + CLK => master_clk, RESET => reset_i, --Flash & Reload FLASH_CS => flash_ncs_i, @@ -618,6 +621,11 @@ begin PCS_AN_READY_OUT(0) => open, -- for internal SCTRL LINK_ACTIVE_OUT(0) => open, -- for internal SCTRL TICK_MS_IN => tick_ms_int, + -- syntonous operation + MASTER_CLK_IN => master_clk, + MASTER_CLK_OUT => open, + TX_CLK_AVAIL_OUT => open, + SYNC_TX_PLL_IN => '0', -- DLM DLM_INJECT_IN(0) => dlm_inject_int, DLM_DATA_IN(7 downto 0) => dlm_tx_data_int, @@ -718,6 +726,11 @@ begin RX_LINK_READY_OUT => open, TX_LINK_READY_IN => link_tx_ready_i, TICK_MS_IN => tick_ms_int, + -- syntonous operation + MASTER_CLK_IN => master_clk, + MASTER_CLK_OUT => open, + TX_CLK_AVAIL_OUT => open, + SYNC_TX_PLL_IN => '0', -- DLM DLM_INJECT_IN(0) => dlm_inject_int, DLM_INJECT_IN(1) => dlm_inject_int, @@ -824,6 +837,11 @@ begin RX_LINK_READY_OUT => open, TX_LINK_READY_IN => link_tx_ready_i, TICK_MS_IN => tick_ms_int, + -- syntonous operation + MASTER_CLK_IN => master_clk, + MASTER_CLK_OUT => open, + TX_CLK_AVAIL_OUT => open, + SYNC_TX_PLL_IN => '0', -- DLM DLM_INJECT_IN(0) => dlm_inject_int, DLM_INJECT_IN(1) => dlm_inject_int, @@ -905,6 +923,11 @@ begin PCS_AN_READY_OUT(0) => open, -- for internal SCTRL LINK_ACTIVE_OUT(0) => link_active, -- for internal SCTRL TICK_MS_IN => tick_ms_int, + -- syntonous operation + MASTER_CLK_IN => master_clk, + MASTER_CLK_OUT => master_clk, + TX_CLK_AVAIL_OUT => tx_clk_avail_i, + SYNC_TX_PLL_IN => '0', -- DLM DLM_INJECT_IN => (others => '0'), DLM_DATA_IN => (others => '0'), @@ -924,7 +947,7 @@ begin CLEAR => clear_i, CLK_REF => clk_sys, TX_PLL_LOL_IN => tx_pll_lol_i, - TX_CLOCK_AVAIL_IN => '1', -- not needed here + TX_CLOCK_AVAIL_IN => tx_clk_avail_i, TX_PCS_RST_CH_C_OUT => tx_pcs_rst_i, SYNC_TX_QUAD_OUT => open, --not needed here LINK_TX_READY_OUT => link_tx_ready_i, @@ -933,12 +956,14 @@ begin tx_pll_lol_i <= tx_pll_lol_a_i or tx_pll_lol_b_i or tx_pll_lol_c_i or tx_pll_lol_d_i; + global_reset_i <= not tx_clk_avail_i; + --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- -- LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2) LED_GREEN <= not status(0); --'0'; - LED_ORANGE <= not '0'; + LED_ORANGE <= not tx_clk_avail_i; --'0'; LED_RED <= not '0'; LED_YELLOW <= not '0'; -- 2.43.0