From 992e8bfe4542b44a67a24c860407216d6b1c7116 Mon Sep 17 00:00:00 2001 From: Cahit Date: Mon, 6 May 2013 15:32:18 +0200 Subject: [PATCH] Edited for TDC v1.5 - cu --- trb3/TdcBuildingBlocks.tex | 89 +++++++++++++++++++++++++++++++++----- 1 file changed, 78 insertions(+), 11 deletions(-) diff --git a/trb3/TdcBuildingBlocks.tex b/trb3/TdcBuildingBlocks.tex index 6c68140..7c0d634 100644 --- a/trb3/TdcBuildingBlocks.tex +++ b/trb3/TdcBuildingBlocks.tex @@ -8,9 +8,19 @@ \label{fig:tdcChannelBlock} \end{wrapfigure} -The architecture of the TDC consists of a fine time measurement block, a coarse counter with granularity of 5~ns, an encoder for the conversion of the result to binary number and a First-In-First-Out (FIFO) memory block for data storage. A block diagram of the designed TDC is shown in Figure~\ref{fig:tdcChannelBlock}. +The architecture of the TDC consists of a fine time measurement block, a +coarse counter with granularity of 5~ns, an encoder for the conversion of the +result to binary number and a First-In-First-Out (FIFO) memory block for data +storage. A block diagram of the designed TDC is shown in +Figure~\ref{fig:tdcChannelBlock}. -In each TDC channel the measurement result of the fine time measurement block is converted to a binary number in the encoder and saved in the FIFO with a coarse time flag. The time interval between different signals measured at different channels can be calculated by simply taking the difference of the relevant measurement results. In Figure~\ref{fig:tdcDeltaTime} an example of two signals, their coarse and fine time values and the calculation of the time interval between these signals are shown. +In each TDC channel the measurement result of the fine time measurement block +is converted to a binary number in the encoder and saved in the FIFO with a +coarse time flag. The time interval between different signals measured at +different channels can be calculated by simply taking the difference of the +relevant measurement results. In Figure~\ref{fig:tdcDeltaTime} an example of +two signals, their coarse and fine time values and the calculation of the time +interval between these signals are shown. \begin{figure}[htb] %% LARGER SUBFIGURE @@ -40,9 +50,17 @@ In each TDC channel the measurement result of the fine time measurement block is \subsubsection{Fine Time Measurement} \label{sec:tdcFineTime} -For fine time measurements the Tapped Delay Line (TDL) method is used. This method is based on a delay path with delay elements, which have similar propagation delays. With the start signal the propagation along the delay line starts and with the stop signal the output of the each delay element is latched (Figure~\ref{fig:tdcTdl}). The location of the propagating signal along the delay line defines the fine time between start and stop signals. +For fine time measurements the Tapped Delay Line (TDL) method is used. This +method is based on a delay path with delay elements, which have similar +propagation delays. With the start signal the propagation along the delay line +starts and with the stop signal the output of the each delay element is +latched (Figure~\ref{fig:tdcTdl}). The location of the propagating signal +along the delay line defines the fine time between start and stop signals. -The delay line is realised on the dedicated carry chain structure of the Lattice FPGA using the 4-bit Look Up Tables (LUT) and the registers, as delay elements and as latches respectively. In Figure~\ref{fig:tdcSlice} the diagram of a slice with 2 LUTs and 2 registers is shown. +The delay line is realised on the dedicated carry chain structure of the +Lattice FPGA using the 4-bit Look Up Tables (LUT) and the registers, as delay +elements and as latches respectively. In Figure~\ref{fig:tdcSlice} the diagram +of a slice with 2 LUTs and 2 registers is shown. \begin{figure}[htb] %% SMALLER SUBFIGURES @@ -63,25 +81,59 @@ The delay line is realised on the dedicated carry chain structure of the Lattice \includegraphics[width=0.95\textwidth]{figures/slice.eps} \label{fig:tdcSlice}} \end{minipage} - \caption{Look Up Tables programmed as full adders along the carry chain are used as delay elements of Tapped Delay Line and their outputs are registered at the registers located at the same slice.} + \caption{Look Up Tables programmed as full adders along the carry chain are + used as delay elements of Tapped Delay Line and their outputs are + registered at the registers located at the same slice.} \label{fig:tdcTdlSlice} \end{figure} -In the designed TDC the stop signal is defined as the next rising edge of the system clock after the start signal. As the maximum time interval to be measured by the fine time counter is one clock cycle, the total propagation time of the carry signal, along the delay line, has to be longer than a clock period. Manual placement of the delay elements and the corresponding registers are done in order to achieve a uniform delay along the line. +In the designed TDC the stop signal is defined as the next rising edge of the +system clock after the start signal. As the maximum time interval to be +measured by the fine time counter is one clock cycle, the total propagation +time of the carry signal, along the delay line, has to be longer than a clock +period. Manual placement of the delay elements and the corresponding registers +are done in order to achieve a uniform delay along the line. -The propagation delay of a delay cell depends on temperature and the consistency of the power supply. This dependency effects the resolution of the TDC. In order to overcome this problem, the output data of the TDC has to be calibrated. +The propagation delay of a delay cell depends on temperature and the +consistency of the power supply. This dependency effects the resolution of the +TDC. In order to overcome this problem, the output data of the TDC has to be +calibrated. -For an FPGA TDC, digital calibration has to be applied to the raw data. Bin-by-bin calibration\cite{tdcBinCalibration} is suitable for this purpose. In this method a DNL histogram is created for a given number of hits. Assuming the hit signals are completely random and not correlated with the clock signal, the hits should be equally distributed over the time interval of the fine interpolator, which is the clock period. Then the bin width can be calculated from, +\subsubsection{Fine Time Calibration} + +For an FPGA TDC, digital calibration has to be applied to the raw +data. Bin-by-bin calibration\cite{tdcBinCalibration} is suitable for this +purpose. In this method a DNL histogram is created for a given number of +hits. Assuming the hit signals are completely random and not correlated with +the clock signal, the hits should be equally distributed over the time +interval of the fine interpolator, which is the clock period. Then the bin +width can be calculated from, \begin{equation} BW=n\times\frac{T_o}{N} \end{equation} -where $n$ is the actual number of hits of the bin and $N$ is the total number of hits. Using this calculation and the DNL histogram, which is already calculated, a \textit{Look-Up Table} (LUT)\footnote{A lookup table is used to display information, which is recorded previously, corresponding to an individual input.} is created to store the time values of each bin. The corresponding time value for each bin is the middle point of the bin width values. The time value of the first bin is the half of the bin width of the first bin. For the second bin, it is the summation of the bin width value of the first bin and half of the bin width value of the second bin, and so on. After creating the LUT this is used for subsequent measurements. An example of calibrated and uncalibrated time values are shown in \autoref{fig:calibration}. As may be seen from the graph, the quantisation levels of the calibrated data are distributed along the time more evenly than the uncalibrated data quantisation steps. As these quantisation -steps effect the non-linearities of the TDC, calibration has lowers the non-linearity values. +where $n$ is the actual number of hits of the bin and $N$ is the total number +of hits. Using this calculation and the DNL histogram, which is already +calculated, a \textit{Look-Up Table} (LUT)\footnote{A lookup table is used to + display information, which is recorded previously, corresponding to an + individual input.} is created to store the time values of each bin. The +corresponding time value for each bin is the middle point of the bin width +values. The time value of the first bin is the half of the bin width of the +first bin. For the second bin, it is the summation of the bin width value of +the first bin and half of the bin width value of the second bin, and so +on. After creating the LUT this is used for subsequent measurements. An +example of calibrated and un-calibrated time values are shown in +\autoref{fig:calibration}. As may be seen from the graph, the quantisation +levels of the calibrated data are distributed along the time more evenly than +the un-calibrated data quantisation steps. As these quantisation steps effect +the non-linearities of the TDC, calibration has lowers the non-linearity +values. \begin{figure}[htp] \centering \includegraphics[width=0.6\textwidth]{figures/Calibration_2.pdf} - \caption[An example of a LUT created by the bin-by-bin calibration method]{An example of a LUT created by the bin-by-bin calibration method (Adapted from \cite{tdcWuWaveunion})} + \caption[An example of a LUT created by the bin-by-bin calibration + method]{An example of a LUT created by the bin-by-bin calibration method + (Adapted from \cite{tdcWuWaveunion})} \label{fig:calibration} \end{figure} @@ -89,6 +141,21 @@ This calibration method is correct for a given temperature and supply voltage values, and the calibration LUT has to be updated regularly during the offline analysis. +For channels, which don't get enough signals - statistics - for proper +calibration, a calibration trigger functionality is implemented. The trigger +type 0xd sent from the CTS is used to shoot every channel with the signals +from the second oscillator on the board - uncorrelated with the oscillator +used for fine time measurements - in order to have sufficient statistics for +calibration. + +\begin{information} + It is advised to separate the calibration data taking and physical event + data taking, as the first event generated by the physical trigger after the + calibration trigger might still have calibration data. +\end{information} + + + %%% Local Variables: %%% mode: latex %%% TeX-master: "main" -- 2.43.0