From 993a8093cf2d848e89fe278b03afab38e10b0c83 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Tue, 11 Jan 2022 20:39:38 +0100 Subject: [PATCH] RX SerDes problem seems to be solved --- media_interfaces/med_ecp3_sfp_sync_all_RS.vhd | 15 ++++---- media_interfaces/sync/main_tx_reset_RS.vhd | 7 +--- media_interfaces/sync/med_sync_control_RS.vhd | 35 ++++--------------- media_interfaces/sync/med_sync_define_RS.vhd | 7 ---- media_interfaces/sync/rx_control_RS.vhd | 4 +-- media_interfaces/sync/tx_control_RS.vhd | 1 - 6 files changed, 17 insertions(+), 52 deletions(-) diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd index 401a94e..b1be58c 100644 --- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd @@ -11,7 +11,6 @@ use work.med_sync_define_RS.all; entity med_ecp3_sfp_sync_all_RS is generic( - SIM_MODE : integer := 0; IS_MODE : int_array_t(0 to 3) := (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED); IS_WAP_ZERO : integer := 1 ); @@ -278,7 +277,7 @@ begin txiclk_ch0 => clk_tx_full(0), -- drives TX FIFO bridge rx_full_clk_ch0 => clk_rx_full(0), -- recovered RX clock rx_half_clk_ch0 => clk_rx_half(0), - tx_full_clk_ch0 => clk_tx_full(0), -- TX clock from PLL + tx_full_clk_ch0 => open, --clk_tx_full(0), -- TX clock from PLL tx_half_clk_ch0 => clk_tx_half(0), fpga_rxrefclk_ch0 => CLK_REF_FULL, -- reference RX clock txdata_ch0 => tx_data(0*8+7 downto 0*8), @@ -309,7 +308,7 @@ begin txiclk_ch1 => clk_tx_full(1), rx_full_clk_ch1 => clk_rx_full(1), rx_half_clk_ch1 => clk_rx_half(1), - tx_full_clk_ch1 => clk_tx_full(1), + tx_full_clk_ch1 => open, --clk_tx_full(1), tx_half_clk_ch1 => clk_tx_half(1), fpga_rxrefclk_ch1 => CLK_REF_FULL, txdata_ch1 => tx_data(1*8+7 downto 1*8), @@ -340,7 +339,7 @@ begin txiclk_ch2 => clk_tx_full(2), rx_full_clk_ch2 => clk_rx_full(2), rx_half_clk_ch2 => clk_rx_half(2), - tx_full_clk_ch2 => clk_tx_full(2), + tx_full_clk_ch2 => open, --clk_tx_full(2), tx_half_clk_ch2 => clk_tx_half(2), fpga_rxrefclk_ch2 => CLK_REF_FULL, txdata_ch2 => tx_data(2*8+7 downto 2*8), @@ -371,7 +370,7 @@ begin txiclk_ch3 => clk_tx_full(3), rx_full_clk_ch3 => clk_rx_full(3), rx_half_clk_ch3 => clk_rx_half(3), - tx_full_clk_ch3 => clk_tx_full(3), + tx_full_clk_ch3 => open, --clk_tx_full(3), tx_half_clk_ch3 => clk_tx_half(3), fpga_rxrefclk_ch3 => CLK_REF_FULL, txdata_ch3 => tx_data(3*8+7 downto 3*8), @@ -414,11 +413,15 @@ begin tx_sync_qd_c => SYNC_TX_PLL_IN ); + clk_tx_full(0) <= MASTER_CLK_IN; + clk_tx_full(1) <= MASTER_CLK_IN; + clk_tx_full(2) <= MASTER_CLK_IN; + clk_tx_full(3) <= MASTER_CLK_IN; + gen_control : for i in 0 to 3 generate gen_used_control : if (IS_MODE(i) = c_IS_SLAVE) or (IS_MODE(i) = c_IS_MASTER) generate THE_MED_CONTROL : entity work.med_sync_control_RS generic map( - SIM_MODE => SIM_MODE, IS_WAP_ZERO => IS_WAP_ZERO, IS_MODE => IS_MODE(i) ) diff --git a/media_interfaces/sync/main_tx_reset_RS.vhd b/media_interfaces/sync/main_tx_reset_RS.vhd index 63652cd..d782390 100644 --- a/media_interfaces/sync/main_tx_reset_RS.vhd +++ b/media_interfaces/sync/main_tx_reset_RS.vhd @@ -5,9 +5,6 @@ USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.all; entity main_tx_reset_RS is - generic( - SIM_MODE : integer := 0 - ); port( CLEAR : in std_logic; -- async reset, active high CLK_REF : in std_logic; -- usually RX_REFCLK, not TX_REFCLK! @@ -26,9 +23,7 @@ end entity; architecture main_tx_reset_RS_arch of main_tx_reset_RS is - -- We use two different timing for simulation and real world. - -- Using SIM_MODE for implementation will most likely kill the link. - constant count_index : integer := 15 - (SIM_MODE * 9); -- end of timer + constant count_index : integer := 15; -- end of timer type statetype is ( IDLE, WAIT_FOR_TIMER, SYNC_ALL, SYNC_DONE, NORMAL ); diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd index 8da040a..dae365a 100644 --- a/media_interfaces/sync/med_sync_control_RS.vhd +++ b/media_interfaces/sync/med_sync_control_RS.vhd @@ -9,7 +9,6 @@ use work.med_sync_define_RS.all; entity med_sync_control_RS is generic( - SIM_MODE : integer := 0; -- 0 for simulation, 1 for implementation IS_WAP_ZERO : integer := 1; -- should be 1 for synchronous operation IS_MODE : integer := c_IS_UNUSED ); @@ -74,7 +73,6 @@ architecture med_sync_control_arch of med_sync_control_RS is signal led_rx, last_led_rx : std_logic; signal led_tx, last_led_tx : std_logic; signal timer : unsigned(20 downto 0); - signal sd_los_q : std_logic; signal reset_i : std_logic; signal link_tx_ready_i : std_logic; @@ -121,34 +119,16 @@ begin ------------------------------------------------- -- Reset signals ------------------------------------------------- --- synchronize SFP LOS signal - SYNC_SFP_SIGS : entity work.signal_sync - generic map( - WIDTH => 1, - DEPTH => 3 - ) - port map( - RESET => '0', - CLK0 => CLK_REF, - CLK1 => CLK_REF, - D_IN(0) => SFP_LOS_IN, - D_OUT(0) => sd_los_q - ); -- we use uplink signal detection as global reset (slave port) -- doesn't make sense to start while no link partner is available - GLOBAL_RESET_OUT <= sd_los_q; + GLOBAL_RESET_OUT <= SFP_LOS_IN; -- TX_CONTROL and RX_CONTROL reset --- reset_i <= (RESET or sd_los_q) when (IS_MODE = c_IS_SLAVE) --- else (RESET); reset_i <= RESET; - - -- We provide GLOBAL_RESET_OUT (in case of SLAVE port) to clock_reset_handler, - -- which turns it into global RESET signal. -- for syncing later - link_tx_ready_i <= LINK_TX_READY_IN; + link_tx_ready_i <= LINK_TX_READY_IN; -- usually CLK_REF based ------------------------------------------------- -- Reset RX FSM @@ -162,7 +142,7 @@ begin CV_IN => RX_CV_IN, LSM_IN => RX_LSM_IN, LOS_IN => RX_LOS_IN, - SD_LOS_IN => SFP_LOS_IN, -- could be "sd_los_q" (already sync'ed) + SD_LOS_IN => SFP_LOS_IN, WAP_ZERO_IN => is_wap_zero_i, -- outputs RX_SERDES_RST_OUT => rx_serdes_rst_i, -- CLK_REF based @@ -191,10 +171,7 @@ begin ------------------------------------------------- -- RX Data ------------------------------------------------- - THE_RX_CONTROL : rx_control_RS - generic map( - SIM_MODE => SIM_MODE - ) + THE_RX_CONTROL: rx_control_RS port map( CLK_RXI => CLK_RXI, CLK_SYS => CLK_SYS, @@ -234,7 +211,6 @@ begin ------------------------------------------------- THE_TX_CONTROL: tx_control_RS generic map( - SIM_MODE => SIM_MODE, IS_MODE => IS_MODE ) port map( @@ -281,7 +257,8 @@ begin ------------------------------------------------- led_ok <= link_full_done_i when rising_edge(CLK_SYS); led_rx <= (media_med2int_i.dataready or led_rx) and not timer(20) when rising_edge(CLK_SYS); - led_tx <= (MEDIA_INT2MED.dataready or led_tx or sd_los_q) and not timer(20) when rising_edge(CLK_SYS); +-- led_tx <= (MEDIA_INT2MED.dataready or led_tx or sd_los_q) and not timer(20) when rising_edge(CLK_SYS); + led_tx <= (MEDIA_INT2MED.dataready or led_tx or SFP_LOS_IN) and not timer(20) when rising_edge(CLK_SYS); ROC_TIMER_PROC: process( CLK_SYS, RESET ) begin diff --git a/media_interfaces/sync/med_sync_define_RS.vhd b/media_interfaces/sync/med_sync_define_RS.vhd index 3869f7c..0f8570b 100644 --- a/media_interfaces/sync/med_sync_define_RS.vhd +++ b/media_interfaces/sync/med_sync_define_RS.vhd @@ -75,9 +75,6 @@ component lattice_ecp3_fifo_18x16_dualport_oreg end component; component main_tx_reset_RS is - generic( - SIM_MODE : integer := 0 - ); port( CLEAR : in std_logic; -- async reset, active high CLK_REF : in std_logic; -- usually RX_REFCLK, not TX_REFCLK! @@ -95,9 +92,6 @@ component main_tx_reset_RS is end component; component rx_control_RS is - generic( - SIM_MODE : integer := 0 - ); port( CLK_RXI : in std_logic; CLK_SYS : in std_logic; @@ -127,7 +121,6 @@ end component; component tx_control_RS is generic( - SIM_MODE : integer := 0; IS_MODE : integer := c_IS_UNUSED ); port( diff --git a/media_interfaces/sync/rx_control_RS.vhd b/media_interfaces/sync/rx_control_RS.vhd index 74c3701..dde2604 100644 --- a/media_interfaces/sync/rx_control_RS.vhd +++ b/media_interfaces/sync/rx_control_RS.vhd @@ -8,9 +8,6 @@ use work.trb_net_std.all; use work.med_sync_define_RS.all; entity rx_control_RS is - generic( - SIM_MODE : integer := 0 - ); port( CLK_RXI : in std_logic; CLK_SYS : in std_logic; @@ -273,6 +270,7 @@ begin end case; + -- BUG: master ports don't reset correctly -- if( (RESET = '1') or (link_rx_ready_qrx = '0') ) then if( (RESET = '1') ) then rx_state <= SLEEP; diff --git a/media_interfaces/sync/tx_control_RS.vhd b/media_interfaces/sync/tx_control_RS.vhd index 6bf40e5..feaa457 100644 --- a/media_interfaces/sync/tx_control_RS.vhd +++ b/media_interfaces/sync/tx_control_RS.vhd @@ -11,7 +11,6 @@ use work.med_sync_define_RS.all; entity tx_control_RS is generic( - SIM_MODE : integer := 0; IS_MODE : integer := c_IS_UNUSED ); port( -- 2.43.0