From 99857c7a1ba4119001713a4513b07d79f3308869 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 24 Apr 2017 11:00:49 +0200 Subject: [PATCH] Update pinout files for all FPGA --- pinout/combiner.lpf | 18 ++++----- pinout/dirich.lpf | 18 +++++++++ pinout/thresholds.lpf | 90 +++++++++++++++++++++++++------------------ 3 files changed, 79 insertions(+), 47 deletions(-) diff --git a/pinout/combiner.lpf b/pinout/combiner.lpf index 4f433a2..67e221a 100644 --- a/pinout/combiner.lpf +++ b/pinout/combiner.lpf @@ -12,7 +12,7 @@ BANK 8 VCCIO 3.3 V; LOCATE COMP "CLOCK_PCLK" SITE "U9"; LOCATE COMP "CLOCK_PLL" SITE "U6"; DEFINE PORT GROUP "CLK_group" "CL*" ; -IOBUF GROUP "CLK_group" IO_TYPE=LVDS DIFFRESISTOR=100 BANK_VCCIO=2.5; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; LOCATE COMP "TRIGGER_OUT" SITE "F3"; LOCATE COMP "TRIGGER_TO_CTS" SITE "M8"; @@ -25,10 +25,10 @@ LOCATE COMP "ADC_CS" SITE "AA3"; LOCATE COMP "ADC_DIN" SITE "AB3"; LOCATE COMP "ADC_DOUT" SITE "AB4"; LOCATE COMP "ADC_CLK" SITE "AA4"; -IOBUF PORT "ADC_CS" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=2.5; -IOBUF PORT "ADC_DIN" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=2.5; -IOBUF PORT "ADC_DOUT" IO_TYPE=LVCMOS25 BANK_VCCIO=2.5; -IOBUF PORT "ADC_CLK" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=2.5; +IOBUF PORT "ADC_CS" IO_TYPE=LVCMOS25 DRIVE=8 ; +IOBUF PORT "ADC_DIN" IO_TYPE=LVCMOS25 DRIVE=8 ; +IOBUF PORT "ADC_DOUT" IO_TYPE=LVCMOS25 ; +IOBUF PORT "ADC_CLK" IO_TYPE=LVCMOS25 DRIVE=8 ; LOCATE COMP "POWER_BOARD_IO_1" SITE "AE3"; @@ -36,7 +36,7 @@ LOCATE COMP "POWER_BOARD_IO_2" SITE "AE4"; LOCATE COMP "POWER_BOARD_IO_3" SITE "AC8"; LOCATE COMP "POWER_BOARD_IO_4" SITE "AC9"; DEFINE PORT GROUP "POWER_group" "POWER*" ; -IOBUF GROUP "POWER_group" IO_TYPE=LVCMOS25 BANK_VCCIO=2.5; +IOBUF GROUP "POWER_group" IO_TYPE=LVCMOS25 ; LOCATE COMP "LED_RJ_GREEN_0" SITE "C25"; @@ -50,14 +50,14 @@ LOCATE COMP "LED_RJ_GREEN_1" SITE "G26"; LOCATE COMP "LED_RJ_RED_1" SITE "G25"; LOCATE COMP "LED_YELLOW" SITE "K24"; DEFINE PORT GROUP "LED_group" "LED*" ; -IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=3.3; +IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 DRIVE=8 ; LOCATE COMP "POWER_GOOD" SITE "C9"; IOBUF PORT "POWER_GOOD" IO_TYPE=LVTTL33; LOCATE COMP "CLOCK_SELECT_IN" SITE "M2"; -IOBUF PORT "CLOCK_SELECT_IN" IO_TYPE=LVCMOS25 BANK_VCCIO=2.5; +IOBUF PORT "CLOCK_SELECT_IN" IO_TYPE=LVCMOS25 ; LOCATE COMP "TEMPSENS" SITE "J13"; IOBUF PORT "TEMPSENS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ; @@ -86,7 +86,7 @@ LOCATE COMP "RJ45_SIG_3" SITE "G2"; LOCATE COMP "RJ45_SIG_4" SITE "K6"; LOCATE COMP "RJ45_SIG_5" SITE "K7"; DEFINE PORT GROUP "RJ45_SIG_group" "RJ45_SIG*" ; -IOBUF GROUP "RJ45_SIG_group" IO_TYPE=LVDS DIFFRESISTOR=100 BANK_VCCIO=2.5; +IOBUF GROUP "RJ45_SIG_group" IO_TYPE=LVDS25 DIFFRESISTOR=100 ; diff --git a/pinout/dirich.lpf b/pinout/dirich.lpf index e31383d..a786264 100644 --- a/pinout/dirich.lpf +++ b/pinout/dirich.lpf @@ -154,3 +154,21 @@ LOCATE COMP "TEST_LINE[13]" SITE "P4"; LOCATE COMP "TEST_LINE[14]" SITE "N1"; DEFINE PORT GROUP "TEST_group" "TEST*" ; IOBUF GROUP "TEST_group" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=2.5; + + +LOCATE COMP "MISO_IN_1" SITE "E7"; #DAC1_CTRL0 +LOCATE COMP "MISO_IN_2" SITE "A17"; #DAC2_CTRL0 +LOCATE COMP "MOSI_OUT_1" SITE "D7"; #DAC1_CTRL1 +LOCATE COMP "MOSI_OUT_2" SITE "A18"; #DAC2_CTRL1 +LOCATE COMP "SCLK_OUT_1" SITE "E6"; #DAC1_CTRL2 +LOCATE COMP "SCLK_OUT_2" SITE "B19"; #DAC2_CTRL2 +LOCATE COMP "CS_OUT_1" SITE "D6"; #DAC1_CTRL3 +LOCATE COMP "CS_OUT_2" SITE "B18"; #DAC2_CTRL3 +IOBUF PORT "MISO_IN_1 " IO_TYPE=LVCMOS25 PULLMODE=UP; +IOBUF PORT "MOSI_OUT_1" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW; +IOBUF PORT "SCLK_OUT_1" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW; +IOBUF PORT "CS_OUT_1" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW; +IOBUF PORT "MISO_IN_2 " IO_TYPE=LVCMOS25 PULLMODE=UP; +IOBUF PORT "MOSI_OUT_2" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW; +IOBUF PORT "SCLK_OUT_2" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW; +IOBUF PORT "CS_OUT_2" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW; diff --git a/pinout/thresholds.lpf b/pinout/thresholds.lpf index 8c6a5a2..f6f3b6c 100644 --- a/pinout/thresholds.lpf +++ b/pinout/thresholds.lpf @@ -1,42 +1,56 @@ +COMMERCIAL ; BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; -#LOCATE COMP "rstn" SITE "B3" ; -LOCATE COMP "LED[0]" SITE "H11" ; -LOCATE COMP "LED[1]" SITE "J13" ; -LOCATE COMP "LED[2]" SITE "J11" ; -LOCATE COMP "LED[3]" SITE "L12" ; -LOCATE COMP "LED[4]" SITE "K11" ; -LOCATE COMP "LED[5]" SITE "L13" ; -LOCATE COMP "LED[6]" SITE "N15" ; -LOCATE COMP "LED[7]" SITE "P16" ; -#LOCATE COMP "DIPSW[0]" SITE "N2" ; -#LOCATE COMP "DIPSW[1]" SITE "P1" ; -#LOCATE COMP "DIPSW[2]" SITE "M3" ; -#LOCATE COMP "DIPSW[3]" SITE "N1" ; -#LOCATE COMP "clk_x1" SITE "C8" ; -#FREQUENCY PORT "clk_x1" 12.000000 MHz ; -#IOBUF PORT "clk_x1" PULLMODE=NONE IO_TYPE=LVCMOS33 ; -#IOBUF PORT "DIPSW[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ; -#IOBUF PORT "DIPSW[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; -#IOBUF PORT "DIPSW[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; -#IOBUF PORT "DIPSW[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ; -#IOBUF PORT "rstn" PULLMODE=UP IO_TYPE=LVCMOS33 ; -IOBUF PORT "LED[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; -IOBUF PORT "LED[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; -IOBUF PORT "LED[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ; -IOBUF PORT "LED[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ; -IOBUF PORT "LED[4]" PULLMODE=UP IO_TYPE=LVCMOS33 ; -IOBUF PORT "LED[5]" PULLMODE=UP IO_TYPE=LVCMOS33 ; -IOBUF PORT "LED[6]" PULLMODE=UP IO_TYPE=LVCMOS33 ; -IOBUF PORT "LED[7]" PULLMODE=UP IO_TYPE=LVCMOS33 ; -SYSCONFIG MCCLK_FREQ=133 MASTER_SPI_PORT=DISABLE CONFIGURATION=CFG ; +SYSCONFIG MCCLK_FREQ=33 BACKGROUND_RECONFIG=ON ENABLE_TRANSFR=ENABLE MUX_CONFIGURATION_PORTS=ENABLE ; -LOCATE COMP "MISO_OUT" SITE "A4"; -LOCATE COMP "MOSI_IN" SITE "B4"; -LOCATE COMP "SCLK_IN" SITE "B5"; -LOCATE COMP "CS_IN" SITE "B6"; -IOBUF PORT "MISO_OUT" PULLMODE=UP IO_TYPE=LVCMOS33; -IOBUF PORT "MOSI_IN" PULLMODE=DOWN IO_TYPE=LVCMOS33; -IOBUF PORT "SCLK_IN" PULLMODE=DOWN IO_TYPE=LVCMOS33; -IOBUF PORT "CS_IN" PULLMODE=DOWN IO_TYPE=LVCMOS33; \ No newline at end of file +LOCATE COMP "MISO_OUT" SITE "E1"; #DAC1_CTRL0 +LOCATE COMP "MOSI_IN" SITE "F1"; #DAC1_CTRL1 +LOCATE COMP "SCLK_IN" SITE "D9"; #DAC1_CTRL2 +LOCATE COMP "CS_IN" SITE "G9"; #DAC1_CTRL3 +IOBUF PORT "MISO_OUT" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW; +IOBUF PORT "MOSI_IN" IO_TYPE=LVCMOS25 PULLMODE=UP; +IOBUF PORT "SCLK_IN" IO_TYPE=LVCMOS25 PULLMODE=UP; +IOBUF PORT "CS_IN" IO_TYPE=LVCMOS25 PULLMODE=UP; + + +LOCATE COMP "OUTPUT[1]" SITE "C1"; +LOCATE COMP "OUTPUT[2]" SITE "J3"; +LOCATE COMP "OUTPUT[3]" SITE "J7"; +LOCATE COMP "OUTPUT[4]" SITE "B1"; +LOCATE COMP "OUTPUT[5]" SITE "A2"; +LOCATE COMP "OUTPUT[6]" SITE "A8"; +LOCATE COMP "OUTPUT[7]" SITE "A3"; +LOCATE COMP "OUTPUT[8]" SITE "H9"; +LOCATE COMP "OUTPUT[9]" SITE "A5"; +LOCATE COMP "OUTPUT[10]" SITE "A6"; +LOCATE COMP "OUTPUT[11]" SITE "B9"; +LOCATE COMP "OUTPUT[12]" SITE "J8"; +LOCATE COMP "OUTPUT[13]" SITE "J6"; +LOCATE COMP "OUTPUT[14]" SITE "J5"; +LOCATE COMP "OUTPUT[15]" SITE "J2"; +LOCATE COMP "OUTPUT[16]" SITE "H1"; +DEFINE PORT GROUP "OUTPUT_group" "OUTPUT*" ; +IOBUF GROUP "OUTPUT_group" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW BANK_VCCIO=2.5 ; + +### +LOCATE COMP "DAC_FLAG" SITE "G1"; +IOBUF PORT "DAC_FLAG" IO_TYPE=LVCMOS25 PULLMODE=UP; + + +# LOCATE COMP "PWM_IN17" 1 SITE "A6"; +# LOCATE COMP "PWM_IN18" 2 SITE "A5"; +# LOCATE COMP "PWM_IN19" 3 SITE "A3"; +# LOCATE COMP "PWM_IN20" 4 SITE "A8"; +# LOCATE COMP "PWM_IN21" 5 SITE "B1"; +# LOCATE COMP "PWM_IN22" 6 SITE "H9"; +# LOCATE COMP "PWM_IN23" 7 SITE "B9"; +# LOCATE COMP "PWM_IN24" 8 SITE "J7"; +# LOCATE COMP "PWM_IN25" 9 SITE "J8"; +# LOCATE COMP "PWM_IN26" 10 SITE "J2"; +# LOCATE COMP "PWM_IN27" 11 SITE "H1"; +# LOCATE COMP "PWM_IN28" 12 SITE "J5"; +# LOCATE COMP "PWM_IN29" 13 SITE "J3"; +# LOCATE COMP "PWM_IN30" 14 SITE "J6"; +# LOCATE COMP "PWM_IN31" 15 SITE "C1"; +# LOCATE COMP "PWM_IN32" 16 SITE "A2"; -- 2.43.0