From 9a92755d674e20bc81c97e80c18aacfcd9fd9745 Mon Sep 17 00:00:00 2001
From: hadeshyp <hadeshyp>
Date: Thu, 18 Oct 2007 12:47:30 +0000
Subject: [PATCH] updated fifo, Jan

---
 trb_net_fifo.vhd             | 5 +++--
 xilinx/trb_net_fifo_arch.vhd | 4 ++--
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/trb_net_fifo.vhd b/trb_net_fifo.vhd
index bda4d5f..582182c 100644
--- a/trb_net_fifo.vhd
+++ b/trb_net_fifo.vhd
@@ -13,12 +13,13 @@ USE ieee.std_logic_arith.ALL;
 entity trb_net_fifo is
   
   generic (WIDTH : integer := 18;  	-- FIFO word width
-           DEPTH : integer := 3);     -- Depth of the FIFO, 2^(n+1)
+           DEPTH : integer := 3;     -- Depth of the FIFO, 2^(n+1)
+           FORCE_LUT : integer range 0 to 1 := 0): --don't allow use of BlockRAM
 
   port (CLK    : in std_logic;  		
         RESET  : in std_logic;  	
         CLK_EN : in std_logic;
-        
+
         DATA_IN         : in  std_logic_vector(WIDTH - 1 downto 0);  -- Input data
         WRITE_ENABLE_IN : in  std_logic;  		
         DATA_OUT        : out std_logic_vector(WIDTH - 1 downto 0);  -- Output data
diff --git a/xilinx/trb_net_fifo_arch.vhd b/xilinx/trb_net_fifo_arch.vhd
index 6535ba8..47a9b6b 100644
--- a/xilinx/trb_net_fifo_arch.vhd
+++ b/xilinx/trb_net_fifo_arch.vhd
@@ -50,7 +50,7 @@ architecture arch_trb_net_fifo of trb_net_fifo is
 
 begin
 
-  gen_shiftreg : if DEPTH /= 6 or WIDTH /= 18 generate
+  gen_shiftreg : if DEPTH /= 6 or WIDTH /= 18 or FORCE_LUT = 1 generate
   
     FULL_OUT  <= current_FULL;
     EMPTY_OUT <= current_EMPTY;
@@ -176,7 +176,7 @@ begin
 
 
 
-  gen_BRAM : if DEPTH = 6 and WIDTH = 18 generate
+  gen_BRAM : if (DEPTH = 6 and WIDTH = 18) and FORCE_LUT = 0 generate
    bram_fifo:trb_net16_bram_fifo
     port map (
       clock_in         => CLK,
-- 
2.43.0