From 9ad66d3e15deaf3787bfc3094478cb57e88406ae Mon Sep 17 00:00:00 2001 From: hadaq Date: Tue, 6 Nov 2012 15:19:37 +0000 Subject: [PATCH] typo fix - cu --- tdc_releases/tdc_v1.1/BusHandler.vhd | 6 ++-- tdc_releases/tdc_v1.1/Channel_200.vhd | 4 +-- .../tdc_v1.1/Reference_Channel_200.vhd | 4 +-- tdc_releases/tdc_v1.1/TDC.vhd | 2 +- tdc_releases/tdc_v1.1/trb3_periph.vhd | 34 +++++++++++++++++-- .../tdc_v1.1/trb3_periph_constraints.lpf | 1 + 6 files changed, 40 insertions(+), 11 deletions(-) diff --git a/tdc_releases/tdc_v1.1/BusHandler.vhd b/tdc_releases/tdc_v1.1/BusHandler.vhd index 7638702..1b4c3c7 100644 --- a/tdc_releases/tdc_v1.1/BusHandler.vhd +++ b/tdc_releases/tdc_v1.1/BusHandler.vhd @@ -10,12 +10,12 @@ use work.version.all; entity BusHandler is generic ( - CHANNEL_NUMBER : integer range 0 to 64 := 2); + BUS_LENGTH : integer range 0 to 64 := 2); port ( RESET : in std_logic; CLK : in std_logic; -- - DATA_IN : in std_logic_vector_array_32(0 to CHANNEL_NUMBER); + DATA_IN : in std_logic_vector_array_32(0 to BUS_LENGTH); READ_EN_IN : in std_logic; WRITE_EN_IN : in std_logic; ADDR_IN : in std_logic_vector(6 downto 0); @@ -48,7 +48,7 @@ begin data_ready_reg <= '0'; unknown_addr_reg <= '0'; elsif READ_EN_IN = '1' then - if to_integer(unsigned(ADDR_IN)) > CHANNEL_NUMBER then -- if bigger than 64 + if to_integer(unsigned(ADDR_IN)) > BUS_LENGTH then -- if bigger than 64 data_out_reg <= (others => '0'); data_ready_reg <= '0'; unknown_addr_reg <= '1'; diff --git a/tdc_releases/tdc_v1.1/Channel_200.vhd b/tdc_releases/tdc_v1.1/Channel_200.vhd index 157aa5d..9c28546 100644 --- a/tdc_releases/tdc_v1.1/Channel_200.vhd +++ b/tdc_releases/tdc_v1.1/Channel_200.vhd @@ -5,7 +5,7 @@ -- File : Channel_200.vhd -- Author : c.ugur@gsi.de -- Created : 2012-08-28 --- Last update: 2012-10-26 +-- Last update: 2012-11-06 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -134,7 +134,7 @@ begin -- Channel_200 DataB => data_b_i, ClkEn => ff_array_en_i, Result => result_i); - data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00000FFF" & x"7FFFFFF"; + data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" & x"7FFFFFF"; data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000" & not(HIT_IN) & x"000000" & "00" & HIT_IN; ff_array_en_i <= not(hit_detect_i or hit_detect_reg or hit_detect_2reg); diff --git a/tdc_releases/tdc_v1.1/Reference_Channel_200.vhd b/tdc_releases/tdc_v1.1/Reference_Channel_200.vhd index 8224a39..8b14169 100644 --- a/tdc_releases/tdc_v1.1/Reference_Channel_200.vhd +++ b/tdc_releases/tdc_v1.1/Reference_Channel_200.vhd @@ -5,7 +5,7 @@ -- File : Reference_channel_200.vhd -- Author : c.ugur@gsi.de -- Created : 2012-09-04 --- Last update: 2012-10-26 +-- Last update: 2012-11-06 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -135,7 +135,7 @@ begin -- Reference_Channel_200 DataB => data_b_i, ClkEn => ff_array_en_i, Result => result_i); - data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00000FF" & x"7FFFFFF"; + data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" & x"7FFFFFF"; data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000" & not(HIT_IN) & x"000000" & "00" & HIT_IN; ff_array_en_i <= not(hit_detect_i or hit_detect_reg or hit_detect_2reg); diff --git a/tdc_releases/tdc_v1.1/TDC.vhd b/tdc_releases/tdc_v1.1/TDC.vhd index 78d22b8..9fe00f1 100644 --- a/tdc_releases/tdc_v1.1/TDC.vhd +++ b/tdc_releases/tdc_v1.1/TDC.vhd @@ -237,7 +237,7 @@ begin -- Bus handler for the hit counter signals TheHitCounterBus : BusHandler generic map ( - CHANNEL_NUMBER => CHANNEL_NUMBER-1) + BUS_LENGTH => CHANNEL_NUMBER-1) port map ( RESET => RESET, CLK => CLK_READOUT, diff --git a/tdc_releases/tdc_v1.1/trb3_periph.vhd b/tdc_releases/tdc_v1.1/trb3_periph.vhd index 2f11460..a71d11b 100644 --- a/tdc_releases/tdc_v1.1/trb3_periph.vhd +++ b/tdc_releases/tdc_v1.1/trb3_periph.vhd @@ -195,6 +195,14 @@ architecture trb3_periph_arch of trb3_periph is signal dac_sck_i : std_logic; signal dac_sdi_i : std_logic; + signal hitreg_read_en : std_logic; + signal hitreg_write_en : std_logic; + signal hitreg_data_in : std_logic_vector(31 downto 0); + signal hitreg_addr : std_logic_vector(6 downto 0); + signal hitreg_data_out : std_logic_vector(31 downto 0); + signal hitreg_data_ready : std_logic; + signal hitreg_invalid : std_logic; + signal spi_bram_addr : std_logic_vector(7 downto 0); signal spi_bram_wr_d : std_logic_vector(7 downto 0); signal spi_bram_rd_d : std_logic_vector(7 downto 0); @@ -415,9 +423,9 @@ begin --------------------------------------------------------------------------- THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 3, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", others => x"0000"), - PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, others => 0) + PORT_NUMBER => 4, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", others => x"0000"), + PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, others => 0) ) port map( CLK => clk_100_i, @@ -470,6 +478,18 @@ begin BUS_WRITE_ACK_IN(2) => spidac_ack, BUS_NO_MORE_DATA_IN(2) => spidac_busy, BUS_UNKNOWN_ADDR_IN(2) => '0', + --HitRegisters + BUS_READ_ENABLE_OUT(3) => hitreg_read_en, + BUS_WRITE_ENABLE_OUT(3) => hitreg_write_en, + BUS_DATA_OUT(3*32+31 downto 3*32) => open, + BUS_ADDR_OUT(3*16+6 downto 3*16) => hitreg_addr, + BUS_ADDR_OUT(3*16+15 downto 3*16+7) => open, + BUS_TIMEOUT_OUT(3) => open, + BUS_DATA_IN(3*32+31 downto 3*32) => hitreg_data_out, + BUS_DATAREADY_IN(3) => hitreg_data_ready, + BUS_WRITE_ACK_IN(3) => '0', + BUS_NO_MORE_DATA_IN(3) => '0', + BUS_UNKNOWN_ADDR_IN(3) => hitreg_invalid, STAT_DEBUG => open ); @@ -614,6 +634,14 @@ begin DATA_WRITE_OUT => fee_data_write_i, -- data valid signal DATA_FINISHED_OUT => fee_data_finished_i, -- readout finished signal -- + --Hit Counter Bus + HCB_READ_EN_IN => hitreg_read_en, -- bus read en strobe + HCB_WRITE_EN_IN => hitreg_write_en, -- bus write en strobe + HCB_ADDR_IN => hitreg_addr, -- bus address + HCB_DATA_OUT => hitreg_data_out, -- bus data + HCB_DATAREADY_OUT => hitreg_data_ready, -- bus data ready strobe + HCB_UNKNOWN_ADDR_OUT => hitreg_invalid, -- bus invalid addr + -- SLOW_CONTROL_REG_OUT => stat_reg, LOGIC_ANALYSER_OUT => logic_analyser_i, CONTROL_REG_IN => ctrl_reg); diff --git a/tdc_releases/tdc_v1.1/trb3_periph_constraints.lpf b/tdc_releases/tdc_v1.1/trb3_periph_constraints.lpf index 6831ed4..7f411f7 100644 --- a/tdc_releases/tdc_v1.1/trb3_periph_constraints.lpf +++ b/tdc_releases/tdc_v1.1/trb3_periph_constraints.lpf @@ -49,6 +49,7 @@ LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_TH LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_TRBNET"; LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_TRBNET"; + ################################################################# # TDC Constraints ################################################################# -- 2.43.0