From 9bc0a360aa5c4c010ae7445ca1274d2bd443352b Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 20 Oct 2015 13:37:49 +0200 Subject: [PATCH] Adding design for ADC AddOn on TRB3sc --- adcaddon/compile.pl | 1 + adcaddon/config.vhd | 114 ++++ adcaddon/config_compile_frankfurt.pl | 21 + adcaddon/par.p2t | 21 + adcaddon/trb3_periph_adc_constraints.lpf | 51 ++ adcaddon/trb3sc_adc.prj | 186 +++++++ adcaddon/trb3sc_adc.sdc | 53 ++ adcaddon/trb3sc_adc.vhd | 522 +++++++++++++++++++ pinout/trb3sc_adc.lpf | 633 +++++++++++++++++++++++ 9 files changed, 1602 insertions(+) create mode 120000 adcaddon/compile.pl create mode 100644 adcaddon/config.vhd create mode 100644 adcaddon/config_compile_frankfurt.pl create mode 100644 adcaddon/par.p2t create mode 100644 adcaddon/trb3_periph_adc_constraints.lpf create mode 100644 adcaddon/trb3sc_adc.prj create mode 100644 adcaddon/trb3sc_adc.sdc create mode 100644 adcaddon/trb3sc_adc.vhd create mode 100644 pinout/trb3sc_adc.lpf diff --git a/adcaddon/compile.pl b/adcaddon/compile.pl new file mode 120000 index 0000000..4456748 --- /dev/null +++ b/adcaddon/compile.pl @@ -0,0 +1 @@ +../scripts/compile.pl \ No newline at end of file diff --git a/adcaddon/config.vhd b/adcaddon/config.vhd new file mode 100644 index 0000000..dc75654 --- /dev/null +++ b/adcaddon/config.vhd @@ -0,0 +1,114 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; + constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented. + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F3CC"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"60"; + +--set to 0 for backplane serdes, set to 3 for front SFP serdes + constant SERDES_NUM : integer := 0; + + constant INCLUDE_UART : integer := c_YES; + constant INCLUDE_SPI : integer := c_YES; + constant INCLUDE_LCD : integer := c_YES; + + + + constant USE_DUMMY_READOUT : integer := c_NO; --use slowcontrol for readout, no trigger logic + +--ADC sampling frequency (only 40 MHz supported a.t.m.) + constant ADC_SAMPLING_RATE : integer := 40; + +--These are currently used for the included features table only + constant ADC_PROCESSING_TYPE : integer := 0; + constant ADC_BASELINE_LOGIC : integer := c_YES; + constant ADC_TRIGGER_LOGIC : integer := c_YES; + constant ADC_CHANNELS : integer := 48; + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + type data_t is array (0 to 1023) of std_logic_vector(7 downto 0); + constant LCD_DATA : data_t := ( + x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00", --config don't touch + x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C", --config don't touch + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch + + x"54", x"72", x"62", x"33", x"73", x"63", x"0a", + x"0a", + x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"80", x"0a", + x"43", x"6f", x"6d", x"70", x"69", x"6c", x"65", x"54", x"69", x"6d", x"65", x"20", x"20", x"84", x"83", x"0a", + x"54", x"69", x"6d", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"82", x"81", x"0a", + others => x"00"); + + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"95009000"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( + HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + + + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); +begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(4,8)); --table version 4 + t(7 downto 0) := std_logic_vector(to_unsigned(ADC_SAMPLING_RATE,8)); + t(11 downto 8) := std_logic_vector(to_unsigned(ADC_PROCESSING_TYPE,4)); --processing type + t(14 downto 14) := std_logic_vector(to_unsigned(ADC_BASELINE_LOGIC,1)); + t(15 downto 15) := std_logic_vector(to_unsigned(ADC_TRIGGER_LOGIC,1)); + t(23 downto 16) := std_logic_vector(to_unsigned(ADC_CHANNELS,8)); + t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(51 downto 48) := x"0";--std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + return t; +end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; \ No newline at end of file diff --git a/adcaddon/config_compile_frankfurt.pl b/adcaddon/config_compile_frankfurt.pl new file mode 100644 index 0000000..c50e60e --- /dev/null +++ b/adcaddon/config_compile_frankfurt.pl @@ -0,0 +1,21 @@ +TOPNAME => "trb3sc_adc", +lm_license_file_for_synplify => "1702\@hadeb05.gsi.de", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1702\@hadeb05.gsi.de", +lattice_path => '/d/jspc29/lattice/diamond/3.5_x64', +# synplify_path => '/d/jspc29/lattice/synplify/J-2015.03-SP1/', +synplify_command => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options", +synplify_binary => "/d/jspc29/lattice/synplify/I-2013.09-SP1/bin/synplify_pro", +#synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", + +nodelist_file => 'nodelist_frankfurt.txt', + + +#Include only necessary lpf files +#pinout_file => '', #name of pin-out file, if not equal TOPNAME +include_TDC => 0, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, + diff --git a/adcaddon/par.p2t b/adcaddon/par.p2t new file mode 100644 index 0000000..e13de7d --- /dev/null +++ b/adcaddon/par.p2t @@ -0,0 +1,21 @@ +-w +-i 15 +-l 5 +-n 1 +-y +-s 12 +-t 25 +-c 1 +-e 2 +#-g guidefile.ncd +#-m nodelist.txt +# -w +# -i 6 +# -l 5 +# -n 1 +# -t 1 +# -s 1 +# -c 0 +# -e 0 +# +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1 diff --git a/adcaddon/trb3_periph_adc_constraints.lpf b/adcaddon/trb3_periph_adc_constraints.lpf new file mode 100644 index 0000000..dd0786b --- /dev/null +++ b/adcaddon/trb3_periph_adc_constraints.lpf @@ -0,0 +1,51 @@ + +################################################################# +# ADC Processor +################################################################# + +# UGROUP "Proc_0" BBOX 60 60 +# BLKNAME gen_reallogic_THE_ADC/gen_processors_0_THE_ADC_PROC; +# UGROUP "Proc_1" BBOX 60 60 +# BLKNAME gen_reallogic_THE_ADC/gen_processors_1_THE_ADC_PROC; +# UGROUP "Proc_2" BBOX 60 60 +# BLKNAME gen_reallogic_THE_ADC/gen_processors_2_THE_ADC_PROC; +# UGROUP "Proc_3" BBOX 60 60 +# BLKNAME gen_reallogic_THE_ADC/gen_processors_3_THE_ADC_PROC; +# UGROUP "Proc_4" BBOX 60 60 +# BLKNAME gen_reallogic_THE_ADC/gen_processors_4_THE_ADC_PROC; +# UGROUP "Proc_5" BBOX 60 60 +# BLKNAME gen_reallogic_THE_ADC/gen_processors_5_THE_ADC_PROC; +# UGROUP "Proc_6" BBOX 60 60 +# BLKNAME gen_reallogic_THE_ADC/gen_processors_6_THE_ADC_PROC; +# UGROUP "Proc_7" BBOX 60 60 +# BLKNAME gen_reallogic_THE_ADC/gen_processors_7_THE_ADC_PROC; +# UGROUP "Proc_8" BBOX 60 60 +# BLKNAME gen_reallogic_THE_ADC/gen_processors_8_THE_ADC_PROC; +# UGROUP "Proc_9" BBOX 60 60 +# BLKNAME gen_reallogic_THE_ADC/gen_processors_9_THE_ADC_PROC; +# UGROUP "Proc_10" BBOX 60 60 +# BLKNAME gen_reallogic_THE_ADC/gen_processors_10_THE_ADC_PROC; +# UGROUP "Proc_11" BBOX 60 60 +# BLKNAME gen_reallogic_THE_ADC/gen_processors_11_THE_ADC_PROC; + +INPUT_SETUP ALLPORTS 1.5 ns HOLD 1.5 ns CLKPORT ADC_DCO_1; +INPUT_SETUP ALLPORTS 1.5 ns HOLD 1.5 ns CLKPORT ADC_DCO_2; +INPUT_SETUP ALLPORTS 1.5 ns HOLD 1.5 ns CLKPORT ADC_DCO_3; +INPUT_SETUP ALLPORTS 1.5 ns HOLD 1.5 ns CLKPORT ADC_DCO_4; +INPUT_SETUP ALLPORTS 1.5 ns HOLD 1.5 ns CLKPORT ADC_DCO_5; +INPUT_SETUP ALLPORTS 1.5 ns HOLD 1.5 ns CLKPORT ADC_DCO_6; +INPUT_SETUP ALLPORTS 1.5 ns HOLD 1.5 ns CLKPORT ADC_DCO_7; +INPUT_SETUP ALLPORTS 1.5 ns HOLD 1.5 ns CLKPORT ADC_DCO_8; +INPUT_SETUP ALLPORTS 1.5 ns HOLD 1.5 ns CLKPORT ADC_DCO_9; +INPUT_SETUP ALLPORTS 1.5 ns HOLD 1.5 ns CLKPORT ADC_DCO_10; +INPUT_SETUP ALLPORTS 1.5 ns HOLD 1.5 ns CLKPORT ADC_DCO_11; +INPUT_SETUP ALLPORTS 1.5 ns HOLD 1.5 ns CLKPORT ADC_DCO_12; + +################################################################# +# Clocks +################################################################# +#USE PRIMARY NET "CLK_GPLL_RIGHT_c"; +#USE PRIMARY NET "CLK_PCLK_LEFT_c"; + +USE PRIMARY NET "CLK_CORE_PCLK"; +USE PRIMARY NET "CLK_EXT_PCLK"; \ No newline at end of file diff --git a/adcaddon/trb3sc_adc.prj b/adcaddon/trb3sc_adc.prj new file mode 100644 index 0000000..0939a95 --- /dev/null +++ b/adcaddon/trb3sc_adc.prj @@ -0,0 +1,186 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology LATTICE-ECP3 +set_option -part LFE3_150EA +set_option -package FN1156C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb3sc_adc" +set_option -resource_sharing true + +# map options +set_option -frequency 200 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 0 +set_option -pipe 0 +#set_option -force_gsr +set_option -force_gsr false +set_option -fixgatedclocks false #3 +set_option -fixgeneratedclocks false #3 +set_option -compiler_compatible true + + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb3sc_adc.edf" + +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + + + +#Packages +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" + +#Basic Infrastructure +add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd" +add_file -vhdl -lib work "../../trb3/base/cores/pll_in200_out40.vhd" +add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd" +add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd" + + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" + + +#Flash & Reload, Tools +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd" + +#TrbNet Endpoint +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + +add_file -vhdl -lib "work" "../../trb3/base/cores/pll_adc10bit.vhd" +add_file -vhdl -lib "work" "../../trb3/base/cores/dqsinput_7x5.vhd" +add_file -vhdl -lib "work" "../../trb3/base/cores/dqsinput_5x5.vhd" +add_file -vhdl -lib "work" "../../trb3/base/cores/fifo_cdt_200_50.vhd" +add_file -vhdl -lib "work" "../../trb3/ADC/cores/mulacc2.vhd" +add_file -vhdl -lib "work" "../../trb3/ADC/source/adc_package.vhd" +add_file -vhdl -lib "work" "../../trb3/ADC/source/adc_processor.vhd" +add_file -vhdl -lib "work" "../../trb3/ADC/source/adc_ad9219.vhd" +add_file -vhdl -lib "work" "../../trb3/ADC/source/adc_handler.vhd" +add_file -vhdl -lib "work" "../../trb3/ADC/source/adc_slowcontrol_data_buffer.vhd" + +add_file -vhdl -lib "work" "trb3sc_adc.vhd" +#add_file -constraint "trb3sc_adc.sdc" diff --git a/adcaddon/trb3sc_adc.sdc b/adcaddon/trb3sc_adc.sdc new file mode 100644 index 0000000..0909361 --- /dev/null +++ b/adcaddon/trb3sc_adc.sdc @@ -0,0 +1,53 @@ +# Synopsys, Inc. constraint file +# /d/jspc22/trb/git/trb3/ADC/trb3_periph_adc.sdc +# Written on Tue Aug 26 14:58:43 2014 +# by Synplify Pro, F-2012.03-SP1 Scope Editor + +# +# Collections +# + +# +# Clocks +# +define_clock {CLK_PCLK_RIGHT} -name {CLK_PCLK_RIGHT} -freq 200 -clockgroup default_clkgroup_0 +define_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1} -freq 100 -clockgroup default_clkgroup_1 +define_clock {TRIGGER_LEFT} -name {TRIGGER_LEFT} -freq 10 -clockgroup default_clkgroup_2 +define_clock {n:gen_reallogic\.THE_ADC.THE_ADC_LEFT.gen_7\.THE_7.sclk} -name {n:gen_reallogic\.THE_ADC.THE_ADC_LEFT.gen_7\.THE_7.sclk} -freq 100 -clockgroup default_clkgroup_3 +define_clock {n:gen_reallogic\.THE_ADC.THE_ADC_RIGHT.gen_5\.THE_5.sclk} -name {n:gen_reallogic\.THE_ADC.THE_ADC_RIGHT.gen_5\.THE_5.sclk} -freq 100 -clockgroup default_clkgroup_4 +define_clock {n:THE_MAIN_PLL.CLKOP} -name {n:THE_MAIN_PLL.CLKOP} -freq 100 -clockgroup default_clkgroup_5 +define_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1} -freq 100 -clockgroup default_clkgroup_6 +define_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.refclkdiv2_rx_ch1} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.refclkdiv2_rx_ch1} -freq 100 -clockgroup default_clkgroup_7 +define_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.refclkdiv2_tx_ch} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.refclkdiv2_tx_ch} -freq 100 -clockgroup default_clkgroup_8 + +# +# Clock to Clock +# + +# +# Inputs/Outputs +# + +# +# Registers +# + +# +# Delay Paths +# + +# +# Attributes +# + +# +# I/O Standards +# + +# +# Compile Points +# + +# +# Other +# diff --git a/adcaddon/trb3sc_adc.vhd b/adcaddon/trb3sc_adc.vhd new file mode 100644 index 0000000..0dac757 --- /dev/null +++ b/adcaddon/trb3sc_adc.vhd @@ -0,0 +1,522 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.config.all; +use work.version.all; +use work.adc_package.all; + +entity trb3sc_adc is + port( + --Clocks + CLK_SUPPL_PCLK : in std_logic; --125 MHz for GbE + CLK_CORE_PCLK : in std_logic; --Main Oscillator + CLK_EXT_PLL_LEFT : in std_logic; --External Clock + CLK_CORE_PLL_LEFT : in std_logic; --ADC Left + CLK_CORE_PLL_RIGHT : in std_logic; --ADC Right + --Trigger + TRIG_LEFT : in std_logic; --left side trigger input from fan-out + + --Connection to AddOn + ADC1_CH : in std_logic_vector(4 downto 0); + ADC2_CH : in std_logic_vector(4 downto 0); + ADC3_CH : in std_logic_vector(4 downto 0); + ADC4_CH : in std_logic_vector(4 downto 0); + ADC5_CH : in std_logic_vector(4 downto 0); + ADC6_CH : in std_logic_vector(4 downto 0); + ADC7_CH : in std_logic_vector(4 downto 0); + ADC8_CH : in std_logic_vector(4 downto 0); + ADC9_CH : in std_logic_vector(4 downto 0); + ADC10_CH : in std_logic_vector(4 downto 0); + ADC11_CH : in std_logic_vector(4 downto 0); + ADC12_CH : in std_logic_vector(4 downto 0); + ADC_DCO : in std_logic_vector(12 downto 1); + + SPI_ADC_SCK : out std_logic; + SPI_ADC_SDIO : inout std_logic; + + LMK_CLK : out std_logic; + LMK_DATA : out std_logic; + LMK_LE_1 : out std_logic; + LMK_LE_2 : out std_logic; + + P_CLOCK : out std_logic; + POWER_ENABLE : out std_logic; + + FPGA_CS : out std_logic_vector(1 downto 0); + FPGA_SCK : out std_logic_vector(1 downto 0); + FPGA_SDI : out std_logic_vector(1 downto 0); + FPGA_SDO : in std_logic_vector(1 downto 0); + + + --Additional IO + HDR_IO : inout std_logic_vector(10 downto 1); + RJ_IO : inout std_logic_vector( 3 downto 0); + SPARE_IN : in std_logic_vector( 1 downto 0); + BACK_GPIO : inout std_logic_vector( 3 downto 0); + --LED + LED_GREEN : out std_logic; + LED_YELLOW : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_RJ_GREEN : out std_logic_vector( 1 downto 0); + LED_RJ_RED : out std_logic_vector( 1 downto 0); + LED_WHITE : out std_logic_vector( 1 downto 0); + LED_SFP_GREEN : out std_logic_vector( 1 downto 0); + LED_SFP_RED : out std_logic_vector( 1 downto 0); + + --SFP + SFP_LOS : in std_logic_vector( 1 downto 0); + SFP_MOD0 : in std_logic_vector( 1 downto 0); + SFP_MOD1 : inout std_logic_vector( 1 downto 0) := (others => 'Z'); + SFP_MOD2 : inout std_logic_vector( 1 downto 0) := (others => 'Z'); + SFP_TX_DIS : out std_logic_vector( 1 downto 0) := (others => '0'); + + --Serdes switch + PCSSW_ENSMB : out std_logic; + PCSSW_EQ : out std_logic_vector( 3 downto 0); + PCSSW_PE : out std_logic_vector( 3 downto 0); + PCSSW : out std_logic_vector( 7 downto 0); + + --ADC + ADC_CLK : out std_logic; + ADC_CS : out std_logic; + ADC_DIN : out std_logic; + ADC_DOUT : in std_logic; + + --Flash, 1-wire, Reload + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_IN : out std_logic; + FLASH_OUT : in std_logic; + PROGRAMN : out std_logic; + ENPIRION_CLOCK : out std_logic; + TEMPSENS : inout std_logic; + + --Test Connectors + TEST_LINE : out std_logic_vector(15 downto 0) + ); + attribute syn_useioff : boolean; + --no IO-FF for LEDs relaxes timing constraints + attribute syn_useioff of LED_GREEN : signal is false; + attribute syn_useioff of LED_ORANGE : signal is false; + attribute syn_useioff of LED_RED : signal is false; + attribute syn_useioff of LED_YELLOW : signal is false; + attribute syn_useioff of TEMPSENS : signal is false; + attribute syn_useioff of PROGRAMN : signal is false; + attribute syn_useioff of TRIG_LEFT : signal is false; + + attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_IN : signal is true; + attribute syn_useioff of FLASH_OUT : signal is true; + attribute syn_useioff of TEST_LINE : signal is false; + + + +end entity; + + +architecture trb3sc_adc_arch of trb3sc_adc is + + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys, clk_full, clk_full_osc : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + + signal time_counter : unsigned(31 downto 0) := (others => '0'); + signal led : std_logic_vector(1 downto 0); + signal debug_clock_reset : std_logic_vector(31 downto 0); + + --Media Interface + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + + --READOUT + signal readout_rx : READOUT_RX; + signal readout_tx : readout_tx_array_t(0 to 11); + + signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, busadc_rx, bus_master_out, handlerbus_rx : CTRLBUS_RX; + signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, busadc_tx, bus_master_in : CTRLBUS_TX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal sed_error_i : std_logic; + signal clock_select : std_logic; + signal bus_master_active : std_logic; + + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); + + signal timer : TIMERS; + signal lcd_data : std_logic_vector(511 downto 0); + + signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic; + + + signal adcspi_ctrl : std_logic_vector(7 downto 0); + + + +begin +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- +THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + INT_CLK_IN => CLK_CORE_PCLK, + EXT_CLK_IN => CLK_EXT_PLL_LEFT, + NET_CLK_FULL_IN => med2int(0).clk_full, + NET_CLK_HALF_IN => med2int(0).clk_half, + RESET_FROM_NET => med2int(0).stat_op(13), + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + FULL_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + REF_CLK_OUT => clk_full_osc, + + ENPIRION_CLOCK => ENPIRION_CLOCK, + LED_RED_OUT => LED_RJ_RED, + LED_GREEN_OUT => LED_RJ_GREEN, + DEBUG_OUT => debug_clock_reset + ); + + +--------------------------------------------------------------------------- +-- TrbNet Uplink +--------------------------------------------------------------------------- + + THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync + generic map( + SERDES_NUM => SERDES_NUM, + IS_SYNC_SLAVE => c_YES + ) + port map( + CLK_REF_FULL => med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_REFCLK_P_IN => '0', + SD_REFCLK_N_IN => '0', + SD_PRSNT_N_IN => sfp_prsnt_i, + SD_LOS_IN => sfp_los_i, + SD_TXDIS_OUT => sfp_txdis_i, + --Control Interface + BUS_RX => bussci_rx, + BUS_TX => bussci_tx, + -- Status and control port + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + + SFP_TX_DIS(0) <= '1'; + gen_sfp_con : if SERDES_NUM = 3 generate + sfp_los_i <= SFP_LOS(1); + sfp_prsnt_i <= SFP_MOD0(1); + SFP_TX_DIS(1) <= sfp_txdis_i; + end generate; + gen_bpl_con : if SERDES_NUM = 0 generate + sfp_los_i <= BACK_GPIO(1); + sfp_prsnt_i <= BACK_GPIO(1); + BACK_GPIO(0) <= sfp_txdis_i; + end generate; + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- +THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record + generic map ( + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + REGIO_INIT_ENDPOINT_ID => x"0001", + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 12, + DATA_BUFFER_DEPTH => 10, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**10-511, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + -- Media direction port + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => TRIG_LEFT, + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + + --Slow Control Port + REGIO_COMMON_STAT_REG_IN => (others => '0'), --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + + ONEWIRE_INOUT => TEMPSENS, + --Timing registers + TIMERS_OUT => timer + + ); + +--------------------------------------------------------------------------- +-- AddOn +--------------------------------------------------------------------------- +gen_reallogic : if USE_DUMMY_READOUT = 0 generate + THE_ADC : entity work.adc_handler + port map( + CLK => clk_sys, + CLK_ADCRAW => clk_full_osc, + + ADCCLK_OUT => P_CLOCK, + ADC_DATA( 4 downto 0) => ADC1_CH, + ADC_DATA( 9 downto 5) => ADC2_CH, + ADC_DATA(14 downto 10) => ADC3_CH, + ADC_DATA(19 downto 15) => ADC4_CH, + ADC_DATA(24 downto 20) => ADC5_CH, + ADC_DATA(29 downto 25) => ADC6_CH, + ADC_DATA(34 downto 30) => ADC7_CH, + ADC_DATA(39 downto 35) => ADC8_CH, + ADC_DATA(44 downto 40) => ADC9_CH, + ADC_DATA(49 downto 45) => ADC10_CH, + ADC_DATA(54 downto 50) => ADC11_CH, + ADC_DATA(59 downto 55) => ADC12_CH, + ADC_DCO => ADC_DCO, + TRIGGER_FLAG_OUT => open, + + TRIGGER_IN => TRIG_LEFT, + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + BUS_RX => busadc_rx, + BUS_TX => busadc_tx, + + ADCSPI_CTRL => adcspi_ctrl + ); +end generate; + +gen_dummyreadout : if USE_DUMMY_READOUT = 1 generate + THE_ADC : entity work.adc_slowcontrol_data_buffer + port map( + CLK => clk_sys, + CLK_ADCRAW => clk_full_osc, + + ADCCLK_OUT => P_CLOCK, + ADC_DATA( 4 downto 0) => ADC1_CH, + ADC_DATA( 9 downto 5) => ADC2_CH, + ADC_DATA(14 downto 10) => ADC3_CH, + ADC_DATA(19 downto 15) => ADC4_CH, + ADC_DATA(24 downto 20) => ADC5_CH, + ADC_DATA(29 downto 25) => ADC6_CH, + ADC_DATA(34 downto 30) => ADC7_CH, + ADC_DATA(39 downto 35) => ADC8_CH, + ADC_DATA(44 downto 40) => ADC9_CH, + ADC_DATA(49 downto 45) => ADC10_CH, + ADC_DATA(54 downto 50) => ADC11_CH, + ADC_DATA(59 downto 55) => ADC12_CH, + ADC_DCO => ADC_DCO, + + ADC_CONTROL_OUT => adcspi_ctrl, + + BUS_RX => busadc_rx, + BUS_TX => busadc_tx + ); +end generate; + + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + + handlerbus_rx <= ctrlbus_rx when bus_master_active = '0' else bus_master_out; + + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 4, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => handlerbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(2) => bustc_rx, --Clock switch + BUS_RX(3) => busadc_rx, + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bussci_tx, + BUS_TX(2) => bustc_tx, + BUS_TX(3) => busadc_tx, + + STAT_DEBUG => open + ); + + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS: entity work.trb3sc_tools + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => FLASH_CS, + FLASH_CLK => FLASH_CLK, + FLASH_IN => FLASH_OUT, + FLASH_OUT => FLASH_IN, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15), + --SPI + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT=> spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, + --Header + HEADER_IO => HDR_IO, + --LCD + LCD_DATA_IN => lcd_data, + --ADC + ADC_CS => ADC_CS, + ADC_MOSI => ADC_DIN, + ADC_MISO => ADC_DOUT, + ADC_CLK => ADC_CLK, + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => ctrlbus_tx, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => open + ); + + -- the bits spi_CS (chip select) determines which SPI device is to be programmed + -- it is already inverted, such that spi_CS=0xffff when nothing is to be programmed + -- since the CS of the ADCs can only be controlled via the FPGA, + -- we multiplex the SDI/O and SCK lines according to CS. This way we can control + -- when which SPI device should be addressed via software + + FPGA_CS_mux: process (spi_cs(2 downto 0)) is + begin -- process FPGA_CS_mux + case spi_cs(2 downto 0) is + when b"110" => + FPGA_CS <= b"00"; + when b"101" => + FPGA_CS <= b"01"; + when b"011" => + FPGA_CS <= b"10"; + when others => + FPGA_CS <= b"11"; + end case; + end process FPGA_CS_mux; + + FPGA_SCK(0) <= spi_clk(0) when spi_cs(2 downto 0) /= b"111" else '1'; + FPGA_SDI(0) <= spi_mosi(0) when spi_cs(2 downto 0) /= b"111" else '0'; + spi_miso(0) <= FPGA_SDO(0) when spi_cs(2 downto 0) /= b"111" else '0'; + spi_miso(1) <= FPGA_SDO(0) when spi_cs(2 downto 0) /= b"111" else '0'; + spi_miso(2) <= FPGA_SDO(0) when spi_cs(2 downto 0) /= b"111" else '0'; + + SPI_ADC_SCK <= spi_clk(3) when spi_cs(3) = '0' else adcspi_ctrl(4); + SPI_ADC_SDIO <= spi_mosi(3) when spi_cs(3) = '0' else adcspi_ctrl(5); + FPGA_SCK(1) <= '0' when spi_cs(3) = '0' else adcspi_ctrl(6); --CSB + + LMK_CLK <= spi_clk(4) when spi_cs(5 downto 4) /= b"11" else '1' ; + LMK_DATA <= spi_mosi(4) when spi_cs(5 downto 4) /= b"11" else '0' ; + LMK_LE_1 <= spi_cs(4); -- active low + LMK_LE_2 <= spi_cs(5); -- active low + + POWER_ENABLE <= adcspi_ctrl(0); + + +--------------------------------------------------------------------------- +-- Switches +--------------------------------------------------------------------------- +--Serdes Select + PCSSW_ENSMB <= '0'; + PCSSW_EQ <= x"0"; + PCSSW_PE <= x"F"; + PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1 + +--------------------------------------------------------------------------- +-- I/O +--------------------------------------------------------------------------- + + RJ_IO <= "0000"; + + BACK_GPIO <= (others => 'Z'); +-- BACK_LVDS <= (others => '0'); +-- BACK_3V3 <= (others => 'Z'); + + +--------------------------------------------------------------------------- +-- LCD Data to display +--------------------------------------------------------------------------- + lcd_data(15 downto 0) <= timer.network_address; + lcd_data(47 downto 16) <= timer.microsecond; + lcd_data(79 downto 48) <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)); + lcd_data(511 downto 80) <= (others => '0'); + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + --LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2) + LED_GREEN <= debug_clock_reset(0); + LED_ORANGE <= debug_clock_reset(1); + LED_RED <= not sed_error_i; + LED_YELLOW <= debug_clock_reset(2); + LED_WHITE(0) <= time_counter(26) and time_counter(19); + LED_WHITE(1) <= time_counter(20); + LED_SFP_GREEN <= not med2int(0).stat_op(9) & '1'; --SFP Link Status + LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) & '1'; --SFP RX/TX + +--------------------------------------------------------------------------- +-- Test Circuits +--------------------------------------------------------------------------- + process begin + wait until rising_edge(clk_sys); + time_counter <= time_counter + 1; + if reset_i = '1' then + time_counter <= (others => '0'); + end if; + end process; + + + +end architecture; diff --git a/pinout/trb3sc_adc.lpf b/pinout/trb3sc_adc.lpf new file mode 100644 index 0000000..bbf675d --- /dev/null +++ b/pinout/trb3sc_adc.lpf @@ -0,0 +1,633 @@ +################################################################# +# Clock I/O +################################################################# +LOCATE COMP "CLK_SUPPL_PLL_RIGHT" SITE "Y28"; #was SUPPL_CLOCK1_P +LOCATE COMP "CLK_SUPPL_PLL_LEFT" SITE "Y9"; #was SUPPL_CLOCK2_P +LOCATE COMP "CLK_SUPPL_PCLK" SITE "V9"; #was SUPPL_CLOCK3_P +LOCATE COMP "CLK_CORE_PCLK" SITE "U9"; #was "CORE_CLOCK0_P" +LOCATE COMP "CLK_CORE_PLL_LEFT" SITE "U6"; #was "CORE_CLOCK1_P" +LOCATE COMP "CLK_CORE_PLL_RIGHT" SITE "V34"; #was "CORE_CLOCK2_P" +LOCATE COMP "CLK_EXT_PCLK" SITE "U28"; #was "EXT_CLOCK0_P" +LOCATE COMP "CLK_EXT_PLL_RIGHT" SITE "P30"; #was "EXT_CLOCK1_P" +LOCATE COMP "CLK_EXT_PLL_LEFT" SITE "N7"; #was "EXT_CLOCK2_P" +DEFINE PORT GROUP "CLK_group" "CLK*" ; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + + +LOCATE COMP "TRIG_PLL" SITE "AJ34"; +LOCATE COMP "TRIG_RIGHT" SITE "P34"; +LOCATE COMP "TRIG_LEFT" SITE "T6"; +DEFINE PORT GROUP "TRIG_group" "TRIG*" ; +IOBUF GROUP "TRIG_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + + + + +################################################################# +# Backplane I/O +################################################################# +LOCATE COMP "BACK_GPIO_0" SITE "C26"; +LOCATE COMP "BACK_GPIO_1" SITE "D26"; +LOCATE COMP "BACK_GPIO_2" SITE "B27"; +LOCATE COMP "BACK_GPIO_3" SITE "C27"; +# LOCATE COMP "BACK_GPIO_4" SITE "D27"; +# LOCATE COMP "BACK_GPIO_5" SITE "E27"; +# LOCATE COMP "BACK_GPIO_6" SITE "B28"; +# LOCATE COMP "BACK_GPIO_7" SITE "A28"; +# LOCATE COMP "BACK_GPIO_8" SITE "A26"; +# LOCATE COMP "BACK_GPIO_9" SITE "A27"; +# LOCATE COMP "BACK_GPIO_10" SITE "A29"; +# LOCATE COMP "BACK_GPIO_11" SITE "A30"; +# LOCATE COMP "BACK_GPIO_12" SITE "H26"; +# LOCATE COMP "BACK_GPIO_13" SITE "H25"; +# LOCATE COMP "BACK_GPIO_14" SITE "A31"; +# LOCATE COMP "BACK_GPIO_15" SITE "B31"; +DEFINE PORT GROUP "BACK_GPIO_group" "BACK_GPIO*" ; +IOBUF GROUP "BACK_GPIO_group" IO_TYPE=LVCMOS25 PULLMODE=UP; + +# LOCATE COMP "BACK_LVDS_0" SITE "V2"; +# LOCATE COMP "BACK_LVDS_1" SITE "T4"; +# # LOCATE COMP "BACK_LVDS_0_N" SITE "V1"; +# # LOCATE COMP "BACK_LVDS_1_N" SITE "T3"; +# DEFINE PORT GROUP "BACK_LVDS_group" "BACK_LVDS*" ; +# IOBUF GROUP "BACK_LVDS_group" IO_TYPE=LVDS25; +# +# LOCATE COMP "BACK_3V3_0" SITE "E11"; +# LOCATE COMP "BACK_3V3_1" SITE "F12"; +# LOCATE COMP "BACK_3V3_2" SITE "F10"; +# LOCATE COMP "BACK_3V3_3" SITE "E10"; +# DEFINE PORT GROUP "BACK_3V3_group" "BACK_3V3*" ; +# IOBUF GROUP "BACK_3V3_group" IO_TYPE=LVTTL33 PULLMODE=DOWN; + +################################################################# +# AddOn Connector +################################################################# +# # LOCATE COMP "DQLL0_0_N" SITE "AA1"; +# # LOCATE COMP "DQLL0_1_N" SITE "AB1"; +# # LOCATE COMP "DQLL0_2_N" SITE "AA3"; +# # LOCATE COMP "DQLL0_3_N" SITE "AB5"; +# # LOCATE COMP "DQLL0_4_N" SITE "AA7"; +# # LOCATE COMP "DQLL1_0_N" SITE "Y1"; +# # LOCATE COMP "DQLL1_1_N" SITE "W3"; +# # LOCATE COMP "DQLL1_2_N" SITE "W1"; +# # LOCATE COMP "DQLL1_3_N" SITE "W9"; +# # LOCATE COMP "DQLL1_4_N" SITE "AA8"; +# # LOCATE COMP "DQLL2_0_N" SITE "AC4"; +# # LOCATE COMP "DQLL2_1_N" SITE "AC1"; +# # LOCATE COMP "DQLL2_2_N" SITE "AB3"; +# # LOCATE COMP "DQLL2_3_N" SITE "AB8"; +# # LOCATE COMP "DQLL2_4_N" SITE "AB6"; +# # LOCATE COMP "DQLL3_0_N" SITE "AE3"; +# # LOCATE COMP "DQLL3_1_N" SITE "AC10" +# # LOCATE COMP "DQLL3_2_N" SITE "AE1"; +# # LOCATE COMP "DQLL3_3_N" SITE "AD3"; +# # LOCATE COMP "DQLL3_4_N" SITE "AC8"; +# # LOCATE COMP "DQLR0_0_N" SITE "AB33" +# # LOCATE COMP "DQLR0_1_N" SITE "AA26" +# # LOCATE COMP "DQLR0_2_N" SITE "AC33" +# # LOCATE COMP "DQLR0_3_N" SITE "AA30" +# # LOCATE COMP "DQLR0_4_N" SITE "AA27" +# # LOCATE COMP "DQLR1_0_N" SITE "AD30" +# # LOCATE COMP "DQLR1_1_N" SITE "AB31" +# # LOCATE COMP "DQLR1_2_N" SITE "AE33" +# # LOCATE COMP "DQLR1_3_N" SITE "AD34" +# # LOCATE COMP "DQLR1_4_N" SITE "AG34" +# # LOCATE COMP "DQLR2_0_N" SITE "W29"; +# # LOCATE COMP "DQLR2_1_N" SITE "W26"; +# # LOCATE COMP "DQLR2_2_N" SITE "W33";; +# # LOCATE COMP "DQLR2_3_N" SITE "Y33";; +# # LOCATE COMP "DQLR2_4_N" SITE "Y25"; +# # LOCATE COMP "DQSLL0_C" SITE "AB9"; +# # LOCATE COMP "DQSLL1_C" SITE "Y6"; +# # LOCATE COMP "DQSLL2_C" SITE "AE5"; +# # LOCATE COMP "DQSLL3_C" SITE "AK1"; +# # LOCATE COMP "DQSLR0_C" SITE "AC30" +# # LOCATE COMP "DQSLR1_C" SITE "AB25"; +# # LOCATE COMP "DQSLR2_C" SITE "AA29"; +# # LOCATE COMP "DQSUL0_C" SITE "M9";; +# # LOCATE COMP "DQSUL1_C" SITE "L9";; +# # LOCATE COMP "DQSUL2_C" SITE "H3";; +# # LOCATE COMP "DQSUL3_C" SITE "N10";; +# # LOCATE COMP "DQSUR0_C" SITE "M27";; +# # LOCATE COMP "DQSUR1_C" SITE "N28";; +# # LOCATE COMP "DQSUR2_C" SITE "U30";; +# # LOCATE COMP "DQUL0_0_N" SITE "L4";; +# # LOCATE COMP "DQUL0_1_N" SITE "M3";; +# # LOCATE COMP "DQUL0_2_N" SITE "K5";; +# # LOCATE COMP "DQUL0_3_N" SITE "M1";; +# # LOCATE COMP "DQUL0_4_N" SITE "L6";; +# # LOCATE COMP "DQUL1_0_N" SITE "L1";; +# # LOCATE COMP "DQUL1_1_N" SITE "K1";; +# # LOCATE COMP "DQUL1_2_N" SITE "K3";; +# # LOCATE COMP "DQUL1_3_N" SITE "L7";; +# # LOCATE COMP "DQUL1_4_N" SITE "J6";; +# # LOCATE COMP "DQUL2_0_N" SITE "F1";; +# # LOCATE COMP "DQUL2_1_N" SITE "E3"; +# # LOCATE COMP "DQUL2_2_N" SITE "G1"; +# # LOCATE COMP "DQUL2_3_N" SITE "J1"; +# # LOCATE COMP "DQUL2_4_N" SITE "H2"; +# # LOCATE COMP "DQUL3_0_N" SITE "N3"; +# # LOCATE COMP "DQUL3_1_N" SITE "N1"; +# # LOCATE COMP "DQUL3_2_N" SITE "N5"; +# # LOCATE COMP "DQUL3_3_N" SITE "P4"; +# # LOCATE COMP "DQUL3_4_N" SITE "P8"; +# # LOCATE COMP "DQUR0_0_N" SITE "M25"; +# # LOCATE COMP "DQUR0_1_N" SITE "L31"; +# # LOCATE COMP "DQUR0_2_N" SITE "L33";; +# # LOCATE COMP "DQUR0_3_N" SITE "K30"; +# # LOCATE COMP "DQUR0_4_N" SITE "K33"; +# # LOCATE COMP "DQUR1_0_N" SITE "N29"; +# # LOCATE COMP "DQUR1_1_N" SITE "P26"; +# # LOCATE COMP "DQUR1_2_N" SITE "N31"; +# # LOCATE COMP "DQUR1_3_N" SITE "N33"; +# # LOCATE COMP "DQUR1_4_N" SITE "P27";; +# # LOCATE COMP "DQUR2_0_N" SITE "T31";; +# # LOCATE COMP "DQUR2_1_N" SITE "T27";; +# # LOCATE COMP "DQUR2_2_N" SITE "U31";; +# # LOCATE COMP "DQUR2_3_N" SITE "T33";; +# # LOCATE COMP "DQUR2_4_N" SITE "U27"; +# +# LOCATE COMP "DQLL0_0" SITE "AA2"; #was "DQLL0_0_P" 1 +# LOCATE COMP "DQLL0_1" SITE "AB2"; #was "DQLL0_1_P" 5 +# LOCATE COMP "DQLL0_2" SITE "AA4"; #was "DQLL0_2_P" 9 +# LOCATE COMP "DQSLL0" SITE "AA10"; #was "DQSLL0_T" 13 +# LOCATE COMP "DQLL0_3" SITE "AA5"; #was "DQLL0_3_P" 17 +# LOCATE COMP "DQLL0_4" SITE "Y7"; #was "DQLL0_4_P" 21 +# LOCATE COMP "DQLL2_0" SITE "AC5"; #was "DQLL2_0_P" 25 +# LOCATE COMP "DQLL2_1" SITE "AC2"; #was "DQLL2_1_P" 29 +# LOCATE COMP "DQLL2_2" SITE "AB4"; #was "DQLL2_2_P" 33 +# LOCATE COMP "DQSLL2" SITE "AD5"; #was "DQSLL2_T" 37 +# LOCATE COMP "DQLL2_3" SITE "AA9"; #was "DQLL2_3_P" 41 +# LOCATE COMP "DQLL2_4" SITE "AB7"; #was "DQLL2_4_P" 45 +# LOCATE COMP "DQUL3_0" SITE "N4"; #was "DQUL3_0_P" 49 +# LOCATE COMP "DQUL3_1" SITE "N2"; #was "DQUL3_1_P" 53 +# LOCATE COMP "DQUL3_2" SITE "M5"; #was "DQUL3_2_P" 57 +# LOCATE COMP "DQSUL3" SITE "M10"; #was "DQSUL3_T" 61 +# LOCATE COMP "DQUL3_3" SITE "P5"; #was "DQUL3_3_P" 65 +# LOCATE COMP "DQUL3_4" SITE "N8"; #was "DQUL3_4_P" 69 +# LOCATE COMP "DQUL1_0" SITE "L2"; #was "DQUL1_0_P" 73 +# LOCATE COMP "DQUL1_1" SITE "K2"; #was "DQUL1_1_P" 77 +# LOCATE COMP "DQUL1_2" SITE "K4"; #was "DQUL1_2_P" 81 +# LOCATE COMP "DQSUL1" SITE "L10"; #was "DQSUL1_T" 85 +# LOCATE COMP "DQUL1_3" SITE "M8"; #was "DQUL1_3_P" 89 +# LOCATE COMP "DQUL1_4" SITE "K7"; #was "DQUL1_4_P" 93 +# +# LOCATE COMP "DQUR0_0" SITE "L26"; #was "DQUR0_0_P" 105 +# LOCATE COMP "DQUR0_1" SITE "L32"; #was "DQUR0_1_P" 109 +# LOCATE COMP "DQSUR0" SITE "M26"; #was "DQSUR0_T" 113 +# LOCATE COMP "DQUR0_2" SITE "L34"; #was "DQUR0_2_P" 117 +# LOCATE COMP "DQUR0_3" SITE "K29"; #was "DQUR0_3_P" 121 +# LOCATE COMP "DQUR0_4" SITE "K34"; #was "DQUR0_4_P" 125 +# LOCATE COMP "DQLR0_0" SITE "AB34"; #was "DQLR0_0_P" 129 +# LOCATE COMP "DQLR0_1" SITE "AA25"; #was "DQLR0_1_P" 133 +# LOCATE COMP "DQLR0_2" SITE "AC34"; #was "DQLR0_2_P" 137 +# LOCATE COMP "DQSLR0" SITE "AB30"; #was "DQSLR0_T" 141 +# LOCATE COMP "DQLR0_3" SITE "AA31"; #was "DQLR0_3_P" 145 +# LOCATE COMP "DQLR0_4" SITE "AA28"; #was "DQLR0_4_P" 149 +# +# LOCATE COMP "DQLR1_0" SITE "AD31"; #was "DQLR1_0_P" 169 +# LOCATE COMP "DQLR1_1" SITE "AB32"; #was "DQLR1_1_P" 173 +# LOCATE COMP "DQLR1_2" SITE "AE34"; #was "DQLR1_2_P" 177 +# LOCATE COMP "DQSLR1" SITE "AB26"; #was "DQSLR1_T" 181 +# LOCATE COMP "DQLR1_3" SITE "AD33"; #was "DQLR1_3_P" 185 +# LOCATE COMP "DQLR1_4" SITE "AF34"; #was "DQLR1_4_P" 189 +# +# +# LOCATE COMP "DQLL3_0" SITE "AE4"; #was "DQLL3_0_P" 2 +# LOCATE COMP "DQLL3_1" SITE "AB10"; #was "DQLL3_1_P" 6 +# LOCATE COMP "DQLL3_2" SITE "AE2"; #was "DQLL3_2_P" 10 +# LOCATE COMP "DQSLL3" SITE "AJ1"; #was "DQSLL3_T" 14 +# LOCATE COMP "DQLL3_3" SITE "AD4"; #was "DQLL3_3_P" 18 +# LOCATE COMP "DQLL3_4" SITE "AC9"; #was "DQLL3_4_P" 22 +# LOCATE COMP "DQLL1_0" SITE "Y2"; #was "DQLL1_0_P" 26 +# LOCATE COMP "DQLL1_1" SITE "W4"; #was "DQLL1_1_P" 30 +# LOCATE COMP "DQLL1_2" SITE "W2"; #was "DQLL1_2_P" 34 +# LOCATE COMP "DQSLL1" SITE "W6"; #was "DQSLL1_T" 38 +# LOCATE COMP "DQLL1_3" SITE "W8"; #was "DQLL1_3_P" 42 +# LOCATE COMP "DQLL1_4" SITE "Y8"; #was "DQLL1_4_P" 46 +# LOCATE COMP "DQUL2_0" SITE "F2"; #was "DQUL2_0_P" 50 +# LOCATE COMP "DQUL2_1" SITE "F3"; #was "DQUL2_1_P" 54 +# LOCATE COMP "DQUL2_2" SITE "G2"; #was "DQUL2_2_P" 58 +# LOCATE COMP "DQSUL2" SITE "G3"; #was "DQSUL2_T" 62 +# LOCATE COMP "DQUL2_3" SITE "H1"; #was "DQUL2_3_P" 66 +# LOCATE COMP "DQUL2_4" SITE "J3"; #was "DQUL2_4_P" 70 +# LOCATE COMP "DQUL0_0" SITE "L5"; #was "DQUL0_0_P" 74 +# LOCATE COMP "DQUL0_1" SITE "M4"; #was "DQUL0_1_P" 78 +# LOCATE COMP "DQUL0_2" SITE "K6"; #was "DQUL0_2_P" 82 +# LOCATE COMP "DQSUL0" SITE "N9"; #was "DQSUL0_T" 86 +# LOCATE COMP "DQUL0_3" SITE "M2"; #was "DQUL0_3_P" 90 +# LOCATE COMP "DQUL0_4" SITE "M7"; #was "DQUL0_4_P" 94 +# +# LOCATE COMP "DQUR1_0" SITE "N30"; #was "DQUR1_0_P" 106 +# LOCATE COMP "DQUR1_1" SITE "N26"; #was "DQUR1_1_P" 110 +# LOCATE COMP "DQUR1_2" SITE "N32"; #was "DQUR1_2_P" 114 +# LOCATE COMP "DQSUR1" SITE "N27"; #was "DQSUR1_T" 118 +# LOCATE COMP "DQUR1_3" SITE "N34"; #was "DQUR1_3_P" 122 +# LOCATE COMP "DQUR1_4" SITE "P28"; #was "DQUR1_4_P" 126 +# LOCATE COMP "DQUR2_0" SITE "T32"; #was "DQUR2_0_P" 130 +# LOCATE COMP "DQUR2_1" SITE "T26"; #was "DQUR2_1_P" 134 +# LOCATE COMP "DQUR2_2" SITE "U32"; #was "DQUR2_2_P" 138 +# LOCATE COMP "DQSUR2" SITE "T30"; #was "DQSUR2_T" 142 +# LOCATE COMP "DQUR2_3" SITE "T34"; #was "DQUR2_3_P" 146 +# LOCATE COMP "DQUR2_4" SITE "U26"; #was "DQUR2_4_P" 150 +# +# LOCATE COMP "DQLR2_0" SITE "W30"; #was "DQLR2_0_P" 170 +# LOCATE COMP "DQLR2_1" SITE "W27"; #was "DQLR2_1_P" 174 +# LOCATE COMP "DQLR2_2" SITE "W34"; #was "DQLR2_2_P" 178 +# LOCATE COMP "DQSLR2" SITE "Y30"; #was "DQSLR2_T" 182 +# LOCATE COMP "DQLR2_3" SITE "Y34"; #was "DQLR2_3_P" 186 +# LOCATE COMP "DQLR2_4" SITE "Y26"; #was "DQLR2_4_P" 190 +# +# DEFINE PORT GROUP "DQ_group" "DQ*" ; +# IOBUF GROUP "DQ_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + + + +################################################################# +# ADC INPUTS +################################################################# + +LOCATE COMP "ADC1_CH_0" SITE "AA2"; +LOCATE COMP "ADC1_CH_1" SITE "AB2"; +LOCATE COMP "ADC1_CH_2" SITE "AA4"; +LOCATE COMP "ADC_DCO_1" SITE "AA10"; +LOCATE COMP "ADC1_CH_3" SITE "AA5"; +LOCATE COMP "ADC1_CH_4" SITE "Y7"; + +LOCATE COMP "ADC2_CH_0" SITE "AE4"; +LOCATE COMP "ADC2_CH_1" SITE "AB10"; +LOCATE COMP "ADC2_CH_2" SITE "AE2"; +LOCATE COMP "ADC_DCO_2" SITE "AJ1"; +LOCATE COMP "ADC2_CH_3" SITE "AD4"; +LOCATE COMP "ADC2_CH_4" SITE "AC9"; + +LOCATE COMP "ADC3_CH_0" SITE "AC5"; +LOCATE COMP "ADC3_CH_1" SITE "AC2"; +LOCATE COMP "ADC3_CH_2" SITE "AB4"; +LOCATE COMP "ADC_DCO_3" SITE "AD5"; +LOCATE COMP "ADC3_CH_3" SITE "AA9"; +LOCATE COMP "ADC3_CH_4" SITE "AB7"; + +LOCATE COMP "ADC4_CH_0" SITE "Y2"; +LOCATE COMP "ADC4_CH_1" SITE "W4"; +LOCATE COMP "ADC4_CH_2" SITE "W2"; +LOCATE COMP "ADC_DCO_4" SITE "W6"; +LOCATE COMP "ADC4_CH_3" SITE "W8"; +LOCATE COMP "ADC4_CH_4" SITE "Y8"; + +LOCATE COMP "ADC5_CH_0" SITE "F2"; +LOCATE COMP "ADC5_CH_1" SITE "F3"; +LOCATE COMP "ADC5_CH_2" SITE "G2"; +LOCATE COMP "ADC_DCO_5" SITE "G3"; +LOCATE COMP "ADC5_CH_3" SITE "H1"; +LOCATE COMP "ADC5_CH_4" SITE "J3"; + +LOCATE COMP "ADC6_CH_0" SITE "L5"; +LOCATE COMP "ADC6_CH_1" SITE "M4"; +LOCATE COMP "ADC6_CH_2" SITE "K6"; +LOCATE COMP "ADC_DCO_6" SITE "N9"; +LOCATE COMP "ADC6_CH_3" SITE "M2"; +LOCATE COMP "ADC6_CH_4" SITE "M7"; + +LOCATE COMP "ADC7_CH_0" SITE "L26"; +LOCATE COMP "ADC7_CH_1" SITE "L32"; +LOCATE COMP "ADC_DCO_7" SITE "M26"; +LOCATE COMP "ADC7_CH_2" SITE "L34"; +LOCATE COMP "ADC7_CH_3" SITE "K29"; +LOCATE COMP "ADC7_CH_4" SITE "K34"; + +LOCATE COMP "ADC8_CH_0" SITE "L2"; +LOCATE COMP "ADC8_CH_1" SITE "K2"; +LOCATE COMP "ADC8_CH_2" SITE "K4"; +LOCATE COMP "ADC_DCO_8" SITE "L10"; +LOCATE COMP "ADC8_CH_3" SITE "M8"; +LOCATE COMP "ADC8_CH_4" SITE "K7"; + +LOCATE COMP "ADC9_CH_0" SITE "AB34"; +LOCATE COMP "ADC9_CH_1" SITE "AA25"; +LOCATE COMP "ADC9_CH_2" SITE "AC34"; +LOCATE COMP "ADC_DCO_9" SITE "AB30"; +LOCATE COMP "ADC9_CH_3" SITE "AA31"; +LOCATE COMP "ADC9_CH_4" SITE "AA28"; + +LOCATE COMP "ADC10_CH_0" SITE "N30"; +LOCATE COMP "ADC10_CH_1" SITE "N26"; +LOCATE COMP "ADC10_CH_2" SITE "N32"; +LOCATE COMP "ADC_DCO_10" SITE "N27"; +LOCATE COMP "ADC10_CH_3" SITE "N34"; +LOCATE COMP "ADC10_CH_4" SITE "P28"; + +LOCATE COMP "ADC11_CH_0" SITE "T32"; +LOCATE COMP "ADC11_CH_1" SITE "T26"; +LOCATE COMP "ADC11_CH_2" SITE "U32"; +LOCATE COMP "ADC_DCO_11" SITE "T30"; +LOCATE COMP "ADC11_CH_3" SITE "T34"; +LOCATE COMP "ADC11_CH_4" SITE "U26"; + +LOCATE COMP "ADC12_CH_0" SITE "AD31"; +LOCATE COMP "ADC12_CH_1" SITE "AB32"; +LOCATE COMP "ADC12_CH_2" SITE "AE34"; +LOCATE COMP "ADC_DCO_12" SITE "AB26"; +LOCATE COMP "ADC12_CH_3" SITE "AD33"; +LOCATE COMP "ADC12_CH_4" SITE "AF34"; + +DEFINE PORT GROUP "ADC_group" "ADC*" ; +IOBUF GROUP "ADC_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + + +LOCATE COMP "SPI_ADC_SCK" SITE "AA29"; +LOCATE COMP "SPI_ADC_SDIO" SITE "Y30"; +DEFINE PORT GROUP "SPI_ADC_group" "SPI_ADC*" ; +IOBUF GROUP "SPI_ADC_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8; + + +LOCATE COMP "LMK_CLK" SITE "M10"; +LOCATE COMP "LMK_DATA" SITE "W34"; +LOCATE COMP "LMK_LE_1" SITE "N10"; +LOCATE COMP "LMK_LE_2" SITE "P5"; +DEFINE PORT GROUP "LMK_group" "LMK*" ; +IOBUF GROUP "LMK_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8; + +LOCATE COMP "POWER_ENABLE" SITE "P4"; +IOBUF PORT "POWER_ENABLE" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8 ; + +LOCATE COMP "P_CLOCK" SITE "N2"; +IOBUF PORT "P_CLOCK" IO_TYPE=LVDS25 ; + +LOCATE COMP "FPGA_CS_0" SITE "Y26"; +LOCATE COMP "FPGA_CS_1" SITE "Y25"; +LOCATE COMP "FPGA_SCK_0" SITE "Y34"; +LOCATE COMP "FPGA_SCK_1" SITE "Y33"; +LOCATE COMP "FPGA_SDI_0" SITE "N4"; +LOCATE COMP "FPGA_SDI_1" SITE "N3"; +LOCATE COMP "FPGA_SDO_0" SITE "W27"; +LOCATE COMP "FPGA_SDO_1" SITE "W26"; +DEFINE PORT GROUP "FPGA_group" "FPGA_*" ; +IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP; + + +################################################################# +# Pin-header IO +################################################################# +LOCATE COMP "HDR_IO_1" SITE "AP28"; +LOCATE COMP "HDR_IO_2" SITE "AN28"; +LOCATE COMP "HDR_IO_3" SITE "AP27"; +LOCATE COMP "HDR_IO_4" SITE "AN27"; +LOCATE COMP "HDR_IO_5" SITE "AM27"; +LOCATE COMP "HDR_IO_6" SITE "AL27"; +LOCATE COMP "HDR_IO_7" SITE "AH26"; +LOCATE COMP "HDR_IO_8" SITE "AG26"; +LOCATE COMP "HDR_IO_9" SITE "AM28"; +LOCATE COMP "HDR_IO_10" SITE "AL28"; +DEFINE PORT GROUP "HDR_group" "HDR*" ; +IOBUF GROUP "HDR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ; + +################################################################# +# KEL Connector +################################################################# +# # LOCATE COMP "KEL1_N" SITE "AP6"; +# # LOCATE COMP "KEL2_N" SITE "AP3"; +# # LOCATE COMP "KEL3_N" SITE "AN2"; +# # LOCATE COMP "KEL4_N" SITE "AM3"; +# # LOCATE COMP "KEL5_N" SITE "AM5"; +# # LOCATE COMP "KEL6_N" SITE "AN6"; +# # LOCATE COMP "KEL7_N" SITE "AM4"; +# # LOCATE COMP "KEL8_N" SITE "AJ6"; +# # LOCATE COMP "KEL9_N" SITE "AJ3"; +# # LOCATE COMP "KEL10_N" SITE "AK3"; +# # LOCATE COMP "KEL11_N" SITE "AD8"; +# # LOCATE COMP "KEL12_N" SITE "AK4"; +# # LOCATE COMP "KEL13_N" SITE "V3"; +# # LOCATE COMP "KEL14_N" SITE "W5"; +# # LOCATE COMP "KEL15_N" SITE "T8"; +# # LOCATE COMP "KEL16_N" SITE "T1"; +# # LOCATE COMP "KEL17_N" SITE "P6"; +# # LOCATE COMP "KEL18_N" SITE "T7"; +# # LOCATE COMP "KEL19_N" SITE "R1"; +# # LOCATE COMP "KEL20_N" SITE "P10"; +# # LOCATE COMP "KEL21_N" SITE "AP30"; +# # LOCATE COMP "KEL22_N" SITE "AP32"; +# # LOCATE COMP "KEL23_N" SITE "AN33"; +# # LOCATE COMP "KEL24_N" SITE "AN31"; +# # LOCATE COMP "KEL25_N" SITE "AM32"; +# # LOCATE COMP "KEL26_N" SITE "AN29"; +# # LOCATE COMP "KEL27_N" SITE "AM31"; +# # LOCATE COMP "KEL28_N" SITE "AM30"; +# # LOCATE COMP "KEL29_N" SITE "AL33"; +# # LOCATE COMP "KEL30_N" SITE "AK31"; +# # LOCATE COMP "KEL31_N" SITE "AJ33"; +# # LOCATE COMP "KEL32_N" SITE "AK32"; +# # LOCATE COMP "KEL33_N" SITE "AF31"; +# # LOCATE COMP "KEL34_N" SITE "AE31"; +# # LOCATE COMP "KEL35_N" SITE "AE29"; +# # LOCATE COMP "KEL36_N" SITE "AD25"; +# # LOCATE COMP "KEL37_N" SITE "L30"; +# # LOCATE COMP "KEL38_N" SITE "AB27"; +# # LOCATE COMP "KEL39_N" SITE "M33"; +# # LOCATE COMP "KEL40_N" SITE "M28"; +# LOCATE COMP "KEL_1" SITE "AP5"; +# LOCATE COMP "KEL_2" SITE "AP2"; +# LOCATE COMP "KEL_3" SITE "AN1"; +# LOCATE COMP "KEL_4" SITE "AN3"; +# LOCATE COMP "KEL_5" SITE "AL5"; +# LOCATE COMP "KEL_6" SITE "AM6"; +# LOCATE COMP "KEL_7" SITE "AL4"; +# LOCATE COMP "KEL_8" SITE "AJ5"; +# LOCATE COMP "KEL_9" SITE "AJ2"; +# LOCATE COMP "KEL_10" SITE "AL3"; +# LOCATE COMP "KEL_11" SITE "AD9"; +# LOCATE COMP "KEL_12" SITE "AJ4"; +# LOCATE COMP "KEL_13" SITE "V4"; +# LOCATE COMP "KEL_14" SITE "V5"; +# LOCATE COMP "KEL_15" SITE "T9"; +# LOCATE COMP "KEL_16" SITE "T2"; +# LOCATE COMP "KEL_17" SITE "P7"; +# LOCATE COMP "KEL_18" SITE "R8"; +# LOCATE COMP "KEL_19" SITE "R2"; +# LOCATE COMP "KEL_20" SITE "P9"; +# LOCATE COMP "KEL_21" SITE "AP29"; +# LOCATE COMP "KEL_22" SITE "AP33"; +# LOCATE COMP "KEL_23" SITE "AN34"; +# LOCATE COMP "KEL_24" SITE "AP31"; +# LOCATE COMP "KEL_25" SITE "AN32"; +# LOCATE COMP "KEL_26" SITE "AM29"; +# LOCATE COMP "KEL_27" SITE "AL31"; +# LOCATE COMP "KEL_28" SITE "AL30"; +# LOCATE COMP "KEL_29" SITE "AL34"; +# LOCATE COMP "KEL_30" SITE "AJ31"; +# LOCATE COMP "KEL_31" SITE "AH33"; +# LOCATE COMP "KEL_32" SITE "AL32"; +# LOCATE COMP "KEL_33" SITE "AF32"; +# LOCATE COMP "KEL_34" SITE "AE32"; +# LOCATE COMP "KEL_35" SITE "AE30"; +# LOCATE COMP "KEL_36" SITE "AD26"; +# LOCATE COMP "KEL_37" SITE "M29"; +# LOCATE COMP "KEL_38" SITE "AC28"; +# LOCATE COMP "KEL_39" SITE "M34"; +# LOCATE COMP "KEL_40" SITE "L28"; +# DEFINE PORT GROUP "KEL_group" "KEL*" ; +# IOBUF GROUP "KEL_group" IO_TYPE=LVDS25 ; + +################################################################# +# Many LED +################################################################# +LOCATE COMP "LED_RJ_GREEN_0" SITE "C25"; +LOCATE COMP "LED_RJ_RED_0" SITE "D25"; +LOCATE COMP "LED_GREEN" SITE "D24"; +LOCATE COMP "LED_ORANGE" SITE "E24"; +LOCATE COMP "LED_RED" SITE "K23"; +LOCATE COMP "LED_RJ_GREEN_1" SITE "G26"; +LOCATE COMP "LED_RJ_RED_1" SITE "G25"; +LOCATE COMP "LED_YELLOW" SITE "K24"; +IOBUF PORT "LED_RJ_GREEN_0" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RJ_RED_0" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_GREEN" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_ORANGE" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RED" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RJ_GREEN_1" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RJ_RED_1" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_YELLOW" IO_TYPE=LVCMOS25 ; + +LOCATE COMP "LED_SFP_GREEN_0" SITE "B4"; +LOCATE COMP "LED_SFP_GREEN_1" SITE "A6"; +LOCATE COMP "LED_SFP_RED_0" SITE "A3"; +LOCATE COMP "LED_SFP_RED_1" SITE "A8"; +DEFINE PORT GROUP "LED_SFP_group" "LED_SFP*" ; +IOBUF GROUP "LED_SFP_group" IO_TYPE=LVTTL33 ; + +LOCATE COMP "LED_WHITE_0" SITE "A32"; +LOCATE COMP "LED_WHITE_1" SITE "A33"; +DEFINE PORT GROUP "LED_WHITE_group" "LED_WHITE*" ; +IOBUF GROUP "LED_WHITE_group" IO_TYPE=LVTTL33 ; + +################################################################# +# SFP Control Signals +################################################################# +LOCATE COMP "SFP_LOS_0" SITE "B6"; +LOCATE COMP "SFP_LOS_1" SITE "C9"; +LOCATE COMP "SFP_MOD0_0" SITE "A5"; +LOCATE COMP "SFP_MOD0_1" SITE "K11"; +LOCATE COMP "SFP_MOD1_0" SITE "B7"; +LOCATE COMP "SFP_MOD1_1" SITE "J11"; +LOCATE COMP "SFP_MOD2_0" SITE "A7"; +LOCATE COMP "SFP_MOD2_1" SITE "D9"; +# LOCATE COMP "SFP_RATE_SEL_0" SITE "A4"; +# LOCATE COMP "SFP_RATE_SEL_1" SITE "C8"; +LOCATE COMP "SFP_TX_DIS_0" SITE "D6"; +LOCATE COMP "SFP_TX_DIS_1" SITE "A9"; +# LOCATE COMP "SFP_TX_FAULT_0" SITE "C5"; +# LOCATE COMP "SFP_TX_FAULT_1" SITE "B8"; +DEFINE PORT GROUP "SFP_group" "SFP*" ; +IOBUF GROUP "SFP_group" IO_TYPE=LVTTL33 ; + + + +################################################################# +# Serdes Output Switch +################################################################# +LOCATE COMP "PCSSW_ENSMB" SITE "B3"; +LOCATE COMP "PCSSW_EQ_0" SITE "B1"; +LOCATE COMP "PCSSW_EQ_1" SITE "B2"; +LOCATE COMP "PCSSW_EQ_2" SITE "E4"; +LOCATE COMP "PCSSW_EQ_3" SITE "D4"; +LOCATE COMP "PCSSW_PE_0" SITE "C3"; +LOCATE COMP "PCSSW_PE_1" SITE "C4"; +LOCATE COMP "PCSSW_PE_2" SITE "D3"; +LOCATE COMP "PCSSW_PE_3" SITE "C2"; +LOCATE COMP "PCSSW_1" SITE "D5"; +LOCATE COMP "PCSSW_0" SITE "A2"; +LOCATE COMP "PCSSW_2" SITE "E13"; +LOCATE COMP "PCSSW_3" SITE "F13"; +LOCATE COMP "PCSSW_4" SITE "G13"; +LOCATE COMP "PCSSW_5" SITE "H14"; +LOCATE COMP "PCSSW_6" SITE "A13"; +LOCATE COMP "PCSSW_7" SITE "B13"; +DEFINE PORT GROUP "PCSSW_group" "PCSSW*" ; +IOBUF GROUP "PCSSW_group" IO_TYPE=LVTTL33 PULLMODE=DOWN ; + + +################################################################# +# ADC +################################################################# +LOCATE COMP "ADC_CLK" SITE "A14"; +LOCATE COMP "ADC_CS" SITE "B14"; +LOCATE COMP "ADC_DIN" SITE "G17"; +LOCATE COMP "ADC_DOUT" SITE "G16"; +IOBUF PORT "ADC_CLK" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_CS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_DIN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_DOUT" IO_TYPE=LVTTL33 PULLMODE=UP ; + + + +################################################################# +# RJ-45 connectors +################################################################# +LOCATE COMP "RJ_IO_1" SITE "R28"; +LOCATE COMP "RJ_IO_2" SITE "R31"; +LOCATE COMP "RJ_IO_3" SITE "R26"; +LOCATE COMP "RJ_IO_4" SITE "R34"; +#LOCATE COMP "RJ_IO_1_N" SITE "R27"; +#LOCATE COMP "RJ_IO_2_N" SITE "R30"; +#LOCATE COMP "RJ_IO_3_N" SITE "R25"; +#LOCATE COMP "RJ_IO_4_N" SITE "R33"; +IOBUF PORT "RJ_IO_1" IO_TYPE=LVDS25 ; +IOBUF PORT "RJ_IO_2" IO_TYPE=LVDS25 ; +IOBUF PORT "RJ_IO_3" IO_TYPE=LVDS25E ; +IOBUF PORT "RJ_IO_4" IO_TYPE=LVDS25E ; + + +LOCATE COMP "SPARE_IN_0" SITE "K31"; +LOCATE COMP "SPARE_IN_1" SITE "R4"; +#LOCATE COMP "SPARE_IN0_N" SITE "K32"; +#LOCATE COMP "SPARE_IN1_N" SITE "R3"; +IOBUF PORT "SPARE_IN_1" IO_TYPE=LVDS25 DIFFRESISTOR=100 ; +IOBUF PORT "SPARE_IN_2" IO_TYPE=LVDS25 DIFFRESISTOR=100 ; + + + +################################################################# +# Flash ROM and Reboot +################################################################# +LOCATE COMP "FLASH_CLK" SITE "F34"; #was "SPI_CLK" +LOCATE COMP "FLASH_CS" SITE "D34"; #was "SPI_CS" +LOCATE COMP "FLASH_IN" SITE "F33"; #was "SPI_IN" +LOCATE COMP "FLASH_OUT" SITE "F32"; #was "SPI_OUT" +LOCATE COMP "PROGRAMN" SITE "C31"; + +DEFINE PORT GROUP "FLASH_group" "FLASH*" ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVTTL33 PULLMODE=NONE; +IOBUF PORT "PROGRAMN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ; + +LOCATE COMP "ENPIRION_CLOCK" SITE "H23"; +IOBUF PORT "ENPIRION_CLOCK" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; + + +################################################################# +# Misc +################################################################# +LOCATE COMP "TEMPSENS" SITE "J13"; #was TEMP_OWB +IOBUF PORT "TEMPSENS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ; + + +################################################################# +# Trigger I/O +################################################################# +LOCATE COMP "TEST_LINE_0" SITE "A19"; +LOCATE COMP "TEST_LINE_1" SITE "B19"; +LOCATE COMP "TEST_LINE_2" SITE "K20"; +LOCATE COMP "TEST_LINE_3" SITE "L19"; +LOCATE COMP "TEST_LINE_4" SITE "C19"; +LOCATE COMP "TEST_LINE_5" SITE "D19"; +LOCATE COMP "TEST_LINE_6" SITE "J19"; +LOCATE COMP "TEST_LINE_7" SITE "K19"; +LOCATE COMP "TEST_LINE_8" SITE "A20"; +LOCATE COMP "TEST_LINE_9" SITE "B20"; +LOCATE COMP "TEST_LINE_10" SITE "G20"; +LOCATE COMP "TEST_LINE_11" SITE "G21"; +LOCATE COMP "TEST_LINE_12" SITE "C20"; +LOCATE COMP "TEST_LINE_13" SITE "D20"; +LOCATE COMP "TEST_LINE_14" SITE "F21"; +LOCATE COMP "TEST_LINE_15" SITE "F22"; +DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8; \ No newline at end of file -- 2.43.0