From 9c5ab38dce486b32d919a5aa7aef0e39c7504a77 Mon Sep 17 00:00:00 2001 From: Rene Hagdorn Date: Fri, 27 Apr 2018 14:24:20 +0200 Subject: [PATCH] Some minor changes of FrameGen. Should work now... --- mupix/Mupix8/sources/FrameGenMux2.vhd | 6 +++--- mupix/Mupix8/trb3_periph.prj | 3 +++ 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/mupix/Mupix8/sources/FrameGenMux2.vhd b/mupix/Mupix8/sources/FrameGenMux2.vhd index d636176..d9f5d13 100644 --- a/mupix/Mupix8/sources/FrameGenMux2.vhd +++ b/mupix/Mupix8/sources/FrameGenMux2.vhd @@ -121,7 +121,7 @@ signal gen_start : std_logic := '0'; signal gen_num : std_logic_vector(31 downto 0) := (others => '0'); signal gen_pause : std_logic_vector(31 downto 0) := (others => '0'); signal gen_down : std_logic_vector(31 downto 0) := (others => '0'); -signal gen_wren : std_logic := '0'; +signal gen_wren : std_logic_vector(3 downto 0) := (others => '0'); signal gen_chansel : chan_type := ("00", "01", "10", "11"); signal gen_data : data_type; @@ -149,7 +149,7 @@ begin -- Behavioral data_pause => gen_pause, data_down => gen_down, chan_sel => gen_chansel(J), - writeEn => gen_wren, + writeEn => gen_wren(J), data_out => gen_data(J) ); @@ -161,7 +161,7 @@ begin -- Behavioral port map( CLK => clk, RST => reset, - WriteEn => gen_wren, + WriteEn => gen_wren(J), ReadEn => fifo_rden(J), DataIn => gen_data(J), DataOut => fifo_data(J), diff --git a/mupix/Mupix8/trb3_periph.prj b/mupix/Mupix8/trb3_periph.prj index 5f0ff94..834d673 100644 --- a/mupix/Mupix8/trb3_periph.prj +++ b/mupix/Mupix8/trb3_periph.prj @@ -174,3 +174,6 @@ add_file -vhdl -lib "work" "sources/DataMux.vhd" add_file -vhdl -lib "work" "sources/MupixDataLink.vhd" add_file -vhdl -lib "work" "sources/TriggerHandler.vhd" add_file -vhdl -lib "work" "sources/Arbiter.vhd" +add_file -vhdl -lib "work" "sources/DatasourceSelector.vhd" +add_file -vhdl -lib "work" "sources/FrameGenMux2.vhd" +add_file -vhdl -lib "work" "sources/Generator3.vhd" -- 2.43.0