From 9c7ef81f41e702c5e50e5b47b9d74ed19058927e Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 11 Aug 2022 10:07:38 +0200 Subject: [PATCH] update mimosis design with own GbE link on AddOn --- mimosis/config.vhd | 4 +- mimosis/par.p2t | 2 +- mimosis/trb5sc_mimosis.prj | 7 +- mimosis/trb5sc_mimosis.vhd | 191 ++++++++++++++++++++++++++++++++----- 4 files changed, 177 insertions(+), 27 deletions(-) diff --git a/mimosis/config.vhd b/mimosis/config.vhd index 27af7ac..b2db444 100644 --- a/mimosis/config.vhd +++ b/mimosis/config.vhd @@ -37,6 +37,7 @@ package config is constant EVENT_BUFFER_SIZE : integer range 9 to 15 := 15; -- size of the event buffer, 2**N constant EVENT_MAX_SIZE : integer := 15000; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 + constant USE_GBE : integer := c_YES; --Runs with 120 MHz instead of 100 MHz constant USE_120_MHZ : integer := c_NO; @@ -83,7 +84,7 @@ package config is constant CLOCK_FREQUENCY : integer; constant MEDIA_FREQUENCY : integer; constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); - + constant BROADCAST_BITMASK : std_logic_vector(7 downto 0) := (7 => (not std_logic_vector(to_unsigned(USE_GBE,1))(0)), others => '1'); end; @@ -105,6 +106,7 @@ function generateIncludedFeatures return std_logic_vector is -- t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); -- t(15) := '1'; --TDC -- t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2)); + t(16 downto 16) := std_logic_vector(to_unsigned(USE_GBE,1)); t(28 downto 28) := std_logic_vector(to_unsigned(1-SERDES_NUM,1)); t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); diff --git a/mimosis/par.p2t b/mimosis/par.p2t index cd64b6a..2c43fcd 100644 --- a/mimosis/par.p2t +++ b/mimosis/par.p2t @@ -4,7 +4,7 @@ #-m nodelist.txt # Controlled by the compile.pl script. #-n 1 # Controlled by the compile.pl script. -s 10 --t 3 +-t 4 -c 2 -e 2 -i 10 diff --git a/mimosis/trb5sc_mimosis.prj b/mimosis/trb5sc_mimosis.prj index 0f12a46..79f9de9 100644 --- a/mimosis/trb5sc_mimosis.prj +++ b/mimosis/trb5sc_mimosis.prj @@ -178,6 +178,7 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" @@ -248,15 +249,15 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch0/serdes_gbe. #add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4096x9.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32x8.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32x8.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x72.vhd" #add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9.vhd" #add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af.vhd" #add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx16x8_mb2.vhd" #add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2048x8x16.vhd" #add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_65536x18x9.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/slv_mac_memory.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ip_mem.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ip_mem.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx18x9_wcnt.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af_cnt.vhd" diff --git a/mimosis/trb5sc_mimosis.vhd b/mimosis/trb5sc_mimosis.vhd index 98bca21..c38e979 100644 --- a/mimosis/trb5sc_mimosis.vhd +++ b/mimosis/trb5sc_mimosis.vhd @@ -120,8 +120,8 @@ architecture arch of trb5sc_mimosis is signal readout_rx : READOUT_RX; signal readout_tx : readout_tx_array_t(0 to 0); - signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in, busmimosis_tx, busi2c_tx : CTRLBUS_TX; - signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busmimosis_rx, busi2c_rx : CTRLBUS_RX; + signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in, busmimosis_tx, busi2c_tx, busgbeip_tx, busgbereg_tx, busfwd_tx : CTRLBUS_TX; + signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busmimosis_rx, busi2c_rx, busgbeip_rx, busgbereg_rx, busfwd_rx : CTRLBUS_RX; signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); @@ -139,7 +139,6 @@ architecture arch of trb5sc_mimosis is signal out_data : std_logic_vector(15 downto 0); signal out_i : std_logic_vector( 7 downto 0); signal inp_i : std_logic_vector( 7 downto 0); - signal dummy : std_logic_vector( 1 downto 0); signal i2c_reg_0, i2c_reg_1 : std_logic_vector(31 downto 0); @@ -148,6 +147,18 @@ architecture arch of trb5sc_mimosis is signal mimosis_scl_drv, mimosis_sda_drv : std_logic; signal i2c_go_100, i2c_go : std_logic; signal i2c_reg_5_40 : std_logic_vector(31 downto 0); + + --signal fwd_dst_mac : std_logic_vector(47 downto 0); + --signal fwd_dst_ip : std_logic_vector(31 downto 0); + --signal fwd_dst_port : std_logic_vector(15 downto 0); + --signal fwd_data : std_logic_vector(7 downto 0); + --signal fwd_datavalid : std_logic; + --signal fwd_sop : std_logic; + --signal fwd_eop : std_logic; + --signal fwd_ready : std_logic; + --signal fwd_full : std_logic; + --signal fwd_length : std_logic_vector(15 downto 0); + --signal fwd_do_send : std_logic; begin @@ -246,7 +257,7 @@ RJ(0) <= clk_40; THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record generic map ( ADDRESS_MASK => x"FFFF", - BROADCAST_BITMASK => x"FF", + BROADCAST_BITMASK => BROADCAST_BITMASK, REGIO_INIT_ENDPOINT_ID => x"0001", REGIO_USE_1WIRE_INTERFACE => c_I2C, TIMING_TRIGGER_RAW => c_YES, @@ -257,14 +268,16 @@ RJ(0) <= clk_40; DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, TRG_RELEASE_AFTER_DATA => c_YES, HEADER_BUFFER_DEPTH => 9, - HEADER_BUFFER_FULL_THRESH => 2**9-16 + HEADER_BUFFER_FULL_THRESH => 2**9-16, + USE_GBE => USE_GBE ) port map( -- Misc - CLK => clk_sys, - RESET => reset_i, - CLK_EN => '1', + CLK => clk_sys, + RESET => reset_i, + CLK_125 => CLK_125, + CLEAR_N => GSR_N, -- Media direction port MEDIA_MED2INT => med2int(0), @@ -299,8 +312,8 @@ RJ(0) <= clk_40; THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( PORT_NUMBER => 5, - PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"de00", others => x"0000"), - PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 5, others => 0), + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"de00", 5 => x"8100", 6 => x"8300", 7 => x"8400", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 5, 5 => 8, 6 => 8, 7 => 8, others => 0), PORT_MASK_ENABLE => 1 ) port map( @@ -315,11 +328,17 @@ RJ(0) <= clk_40; BUS_RX(2) => bustc_rx, --Clock switch BUS_RX(3) => busmimosis_rx, BUS_RX(4) => busi2c_rx, + --BUS_RX(5) => busgbeip_rx, + --BUS_RX(6) => busgbereg_rx, + --BUS_RX(7) => busfwd_rx, BUS_TX(0) => bustools_tx, BUS_TX(1) => bussci_tx, BUS_TX(2) => bustc_tx, BUS_TX(3) => busmimosis_tx, BUS_TX(4) => busi2c_tx, + --BUS_TX(5) => busgbeip_tx, + --BUS_TX(6) => busgbereg_tx, + --BUS_TX(7) => busfwd_tx, STAT_DEBUG => open ); @@ -498,6 +517,143 @@ end process; TEST(14) <= flash_ncs_i; FLASH_NCS <= flash_ncs_i; + +----------------------------------------------------------------------------- +---- GbE +----------------------------------------------------------------------------- + --GBE : entity work.gbe_wrapper + --generic map( + --DO_SIMULATION => 0, + --INCLUDE_DEBUG => 0, + --USE_INTERNAL_TRBNET_DUMMY => 0, + --USE_EXTERNAL_TRBNET_DUMMY => 0, + --RX_PATH_ENABLE => 1, + --FIXED_SIZE_MODE => 1, + --INCREMENTAL_MODE => 1, + --FIXED_SIZE => 100, + --FIXED_DELAY_MODE => 1, + --UP_DOWN_MODE => 0, + --UP_DOWN_LIMIT => 100, + --FIXED_DELAY => 100, + + --NUMBER_OF_GBE_LINKS => 1, + --LINKS_ACTIVE => "0001", + + --LINK_HAS_READOUT => "0000", + --LINK_HAS_SLOWCTRL => "0000", + --LINK_HAS_DHCP => "0001", + --LINK_HAS_ARP => "0001", + --LINK_HAS_PING => "0001", + --LINK_HAS_FWD => "0001" + --) + --port map( + --CLK_SYS_IN => clk_sys, + --CLK_125_IN => CLK_125, + --RESET => reset_i, + --GSR_N => GSR_N, + ---- Trigger + --TRIGGER_IN => '0', + ---- SFP + --SD_PRSNT_N_IN(0) => SFP_MOD_0, + --SD_LOS_IN(0) => SFP_LOS, + --SD_TXDIS_OUT(0) => SFP_TX_DIS, + ---- trigger channel + ---- only for LINK_HAS_READOUT + --CTS_NUMBER_IN => (others => '0'), + --CTS_CODE_IN => (others => '0'), + --CTS_INFORMATION_IN => (others => '0'), + --CTS_READOUT_TYPE_IN => (others => '0'), + --CTS_START_READOUT_IN => '0', + --CTS_DATA_OUT => open, + --CTS_DATAREADY_OUT => open, + --CTS_READOUT_FINISHED_OUT => open, + --CTS_READ_IN => '1', + --CTS_LENGTH_OUT => open, + --CTS_ERROR_PATTERN_OUT => open, + ---- data channel + ---- only for LINK_HAS_READOUT + --FEE_DATA_IN => (others => '0'), + --FEE_DATAREADY_IN => '0', + --FEE_READ_OUT => open, + --FEE_STATUS_BITS_IN => (others => '0'), + --FEE_BUSY_IN => '0', + ---- unique adresses + --MC_UNIQUE_ID_IN => timer.uid, + --MY_TRBNET_ADDRESS_IN => timer.network_address, + --ISSUE_REBOOT_OUT => open, --BUG: needs to be connected + ---- slow control by GbE + --GSC_CLK_IN => open, + --GSC_INIT_DATAREADY_OUT => open, + --GSC_INIT_DATA_OUT => open, + --GSC_INIT_PACKET_NUM_OUT => open, + --GSC_INIT_READ_IN => '1', + --GSC_REPLY_DATAREADY_IN => '0', + --GSC_REPLY_DATA_IN => (others => '0'), + --GSC_REPLY_PACKET_NUM_IN => (others => '0'), + --GSC_REPLY_READ_OUT => open, + --GSC_BUSY_IN => '0', + ---- readout + --BUS_IP_RX => busgbeip_rx, -- registers inside GbE + --BUS_IP_TX => busgbeip_tx, -- registers inside GbE + --BUS_REG_RX => busgbereg_rx, -- registers inside GbE + --BUS_REG_TX => busgbereg_tx, -- registers inside GbE + ---- Forwarder + --FWD_DST_MAC_IN(47 downto 0) => fwd_dst_mac, + --FWD_DST_IP_IN(31 downto 0) => fwd_dst_ip, + --FWD_DST_UDP_IN(15 downto 0) => fwd_dst_port, + --FWD_DATA_IN(7 downto 0) => fwd_data, + --FWD_DATA_VALID_IN(0) => fwd_datavalid, + --FWD_SOP_IN(0) => fwd_sop, + --FWD_EOP_IN(0) => fwd_eop, + --FWD_READY_OUT(0) => fwd_ready, + --FWD_FULL_OUT(0) => fwd_full, + ---- reset + --MAKE_RESET_OUT => open, -- reset by GbE --BUG: needs to be connected + ---- debug and status + --STATUS_OUT => open, + --DEBUG_OUT => open + --); + + + +----------------------------------------------------------------------------- +---- Test registers +----------------------------------------------------------------------------- +--THE_REGS : process begin + --wait until rising_edge(clk_sys); + --busfwd_tx.ack <= '0'; + --busfwd_tx.nack <= '0'; + --busfwd_tx.unknown <= '0'; + + --if busfwd_rx.write = '1' then + --busfwd_tx.ack <= '1'; + --case busfwd_rx.addr(7 downto 0) is + --when x"00" => fwd_dst_ip <= busfwd_rx.data; + --when x"01" => fwd_dst_port <= busfwd_rx.data(15 downto 0); + --when x"02" => fwd_dst_mac(31 downto 0) <= busfwd_rx.data; + --when x"03" => fwd_dst_mac(47 downto 32) <= busfwd_rx.data(15 downto 0); + --when x"04" => fwd_length <= busfwd_rx.data(15 downto 0); + --when x"05" => fwd_do_send <= busfwd_rx.data(0); + --when others => busfwd_tx.ack <= '0'; busfwd_tx.unknown <= '1'; + --end case; + --elsif busfwd_rx.read = '1' then + --busfwd_tx.ack <= '1'; + --case busfwd_rx.addr(7 downto 0) is + --when x"00" => busfwd_tx.data <= fwd_dst_ip; + --when x"01" => busfwd_tx.data <= x"0000" & fwd_dst_port; + --when x"02" => busfwd_tx.data <= fwd_dst_mac(31 downto 0); + --when x"03" => busfwd_tx.data <= x"0000" & fwd_dst_mac(47 downto 32); + --when x"04" => busfwd_tx.data <= x"0000" & fwd_length; + --when x"05" => busfwd_tx.data <= x"0000000" & fwd_full & fwd_ready & "0" & fwd_do_send; + --when others => busfwd_tx.ack <= '0'; busfwd_tx.unknown <= '1'; + --end case; + --end if; + --if reset_i = '1' then + --fwd_do_send <= '0'; + --end if; +--end process; + + --------------------------------------------------------------------------- -- Output stage --------------------------------------------------------------------------- @@ -526,8 +682,8 @@ end process; when 3 => out_data <= x"0000"; when 4 => out_data <= x"5555"; when 5 => out_data <= x"5555"; - when 6 => out_data <= x"5555";--dummy & dummy & dummy & dummy & dummy & dummy & dummy & dummy; - when 7 => out_data <= x"5555";--dummy & dummy & dummy & dummy & dummy & dummy & dummy & dummy; + when 6 => out_data <= x"5555"; + when 7 => out_data <= x"5555"; end case; end process; @@ -535,15 +691,6 @@ end process; H4(3 downto 0) <= out_i(7 downto 4); - process begin - wait until rising_edge(clk_160); - if add_reg(31) = '0' then - dummy <= "01"; - else - dummy <= not dummy; - end if; - end process; - --------------------------------------------------------------------------- -- Input stage --------------------------------------------------------------------------- @@ -571,7 +718,7 @@ end process; -- readout_tx(0).data_write <= '0'; -- readout_tx(0).busy_release <= '1'; - +SFP_ADDON_TX_DIS <= (others => '0'); end architecture; -- 2.43.0