From 9eccc1677d37468dc37062ed391df7ad149a0ae4 Mon Sep 17 00:00:00 2001 From: Cahit Date: Mon, 22 Aug 2016 21:41:51 +0200 Subject: [PATCH] corrected databuffer threshold calculation for the endpoint --- dirich/config.vhd | 6 +- dirich/dirich.vhd | 462 +++++++++++++++++++++++----------------------- 2 files changed, 236 insertions(+), 232 deletions(-) diff --git a/dirich/config.vhd b/dirich/config.vhd index 110aef8..222661e 100644 --- a/dirich/config.vhd +++ b/dirich/config.vhd @@ -11,17 +11,17 @@ package config is ------------------------------------------------------------------------------ --TDC settings constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement - constant NUM_TDC_CHANNELS : integer range 1 to 65 := 2; -- number of tdc channels per module + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 3; -- number of tdc channels per module constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 -- 0: single edge only, -- 1: same channel, -- 2: alternating channels, -- 3: same channel with stretcher - constant RING_BUFFER_SIZE : integer range 0 to 7 := 0; --ring buffer size + constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size -- mode: 0, 1, 2, 3, 7 -- size: 32, 64, 96, 128, dyn - constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC + constant TDC_DATA_FORMAT : integer range 0 to 3 := 15; --type of data format for the TDC -- 0: Single fine time as the sum of the two transitions -- 1: Double fine time, individual transitions -- 14: Debug - single fine time and the ROM addresses for the two transitions diff --git a/dirich/dirich.vhd b/dirich/dirich.vhd index 2be182b..2b603d5 100644 --- a/dirich/dirich.vhd +++ b/dirich/dirich.vhd @@ -12,83 +12,83 @@ use work.med_sync_define.all; entity dirich is port( - CLOCK_IN : in std_logic; --Main Oscillator - TRIG_IN : in std_logic; --Reference Time - CLOCK_CAL : in std_logic; --on-board calibration oscillator - - INPUT : in std_logic_vector(32 downto 1); - PWM : out std_logic_vector(32 downto 1); - + CLOCK_IN : in std_logic; --Main Oscillator + TRIG_IN : in std_logic; --Reference Time + CLOCK_CAL : in std_logic; --on-board calibration oscillator + + INPUT : in std_logic_vector(32 downto 1); + PWM : out std_logic_vector(32 downto 1); + --Additional IO - SIG : inout std_logic_vector( 4 downto 1); + SIG : inout std_logic_vector(4 downto 1); --1:master ready, 2: slave ready, 3-4 trigger, 5 reset --LED - LED_GREEN : out std_logic; - LED_YELLOW : out std_logic; - LED_ORANGE : out std_logic; - LED_RED : out std_logic; + LED_GREEN : out std_logic; + LED_YELLOW : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; --ADC - ADC_SCLK : out std_logic; - ADC_CS : out std_logic; - ADC_DIN : out std_logic; - ADC_DOUT : in std_logic; + ADC_SCLK : out std_logic; + ADC_CS : out std_logic; + ADC_DIN : out std_logic; + ADC_DOUT : in std_logic; --Flash, 1-wire, Reload - FLASH_CLK : out std_logic; - FLASH_CS : out std_logic; - FLASH_IN : out std_logic; - FLASH_OUT : in std_logic; - FLASH_HOLD : out std_logic; - FLASH_WP : out std_logic; - PROGRAMN : out std_logic; - TEMP_LINE : inout std_logic; - + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_IN : out std_logic; + FLASH_OUT : in std_logic; + FLASH_HOLD : out std_logic; + FLASH_WP : out std_logic; + PROGRAMN : out std_logic; + TEMP_LINE : inout std_logic; + --Test Connectors - TEST_LINE : inout std_logic_vector(14 downto 1) + TEST_LINE : inout std_logic_vector(14 downto 1) ); - attribute syn_useioff : boolean; + attribute syn_useioff : boolean; -- attribute syn_useioff of FLASH_CLK : signal is true; - attribute syn_useioff of FLASH_CS : signal is true; - attribute syn_useioff of FLASH_IN : signal is true; - attribute syn_useioff of FLASH_OUT : signal is true; - attribute syn_useioff of INPUT : signal is false; - + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_IN : signal is true; + attribute syn_useioff of FLASH_OUT : signal is true; + attribute syn_useioff of INPUT : signal is false; + end entity; architecture dirich_arch of dirich is attribute syn_keep : boolean; attribute syn_preserve : boolean; - - signal clk_sys, clk_full, clk_full_osc : std_logic; - signal GSR_N : std_logic; - signal reset_i : std_logic; - signal clear_i : std_logic; - + + signal clk_sys, clk_full, clk_full_osc : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + signal time_counter : unsigned(31 downto 0) := (others => '0'); signal debug_clock_reset : std_logic_vector(31 downto 0); signal debug_tools : std_logic_vector(31 downto 0); --Media Interface - signal med2int : med2int_array_t(0 to 0); - signal int2med : int2med_array_t(0 to 0); - signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); signal link_stat_in, link_stat_out : std_logic; --READOUT - signal readout_rx : READOUT_RX; - signal readout_tx : readout_tx_array_t(0 to 0); - - signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in : CTRLBUS_TX; - signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out : CTRLBUS_RX; - - signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); - signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); - + signal readout_rx : READOUT_RX; + signal readout_tx : readout_tx_array_t(0 to 0); + + signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in : CTRLBUS_TX; + signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out : CTRLBUS_RX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + signal sed_error_i : std_logic; signal clock_select : std_logic; signal bus_master_active : std_logic; signal flash_clk_i : std_logic; - + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); signal pwm_i : std_logic_vector(31 downto 0); @@ -101,59 +101,60 @@ architecture dirich_arch of dirich is signal logic_analyser_i : std_logic_vector(16 downto 1); signal led_los_lock : std_logic; - signal los_count : unsigned(23 downto 0); - + signal los_count : unsigned(23 downto 0); + attribute syn_keep of GSR_N : signal is true; - attribute syn_preserve of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; component usrmclk port( - USRMCLKI : in std_ulogic; + USRMCLKI : in std_ulogic; USRMCLKTS : in std_ulogic ); end component; -attribute syn_noprune: boolean ; -attribute syn_noprune of USRMCLK: component is true; - - + attribute syn_noprune : boolean; + attribute syn_noprune of USRMCLK : component is true; + + begin --------------------------------------------------------------------------- -- Clock & Reset Handling --------------------------------------------------------------------------- -THE_CLOCK_RESET : entity work.clock_reset_handler - port map( - CLOCK_IN => CLOCK_IN, - RESET_FROM_NET => med2int(0).stat_op(13), - - BUS_RX => bustc_rx, - BUS_TX => bustc_tx, - - RESET_OUT => reset_i, - CLEAR_OUT => clear_i, - GSR_OUT => GSR_N, - - REF_CLK_OUT => clk_full, - SYS_CLK_OUT => clk_sys, - RAW_CLK_OUT => clk_full_osc, - - DEBUG_OUT => debug_clock_reset - ); + THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + CLOCK_IN => CLOCK_IN, + RESET_FROM_NET => med2int(0).stat_op(13), + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + REF_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + RAW_CLK_OUT => clk_full_osc, + + DEBUG_OUT => debug_clock_reset + ); + + process + begin + wait until rising_edge(CLOCK_CAL); + if debug_clock_reset(0) = '0' then + led_los_lock <= '0'; + los_count <= (others => '0'); + elsif los_count(23) = '0' then + los_count <= los_count + 1; + else + led_los_lock <= '1'; + end if; + end process; + -process begin - wait until rising_edge(CLOCK_CAL); - if debug_clock_reset(0) = '0' then - led_los_lock <= '0'; - los_count <= (others => '0'); - elsif los_count(23) = '0' then - los_count <= los_count + 1; - else - led_los_lock <= '1'; - end if; -end process; - - --------------------------------------------------------------------------- -- TrbNet Uplink --------------------------------------------------------------------------- @@ -164,14 +165,14 @@ end process; IS_SYNC_SLAVE => c_YES ) port map( - CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, - CLK_INTERNAL_FULL => clk_full_osc, - SYSCLK => clk_sys, - RESET => reset_i, - CLEAR => clear_i, + CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, --Internal Connection - MEDIA_MED2INT => med2int(0), - MEDIA_INT2MED => int2med(0), + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), --Sync operation RX_DLM => open, @@ -180,68 +181,68 @@ end process; TX_DLM_WORD => open, --SFP Connection - SD_PRSNT_N_IN => link_stat_in, - SD_LOS_IN => link_stat_in, - SD_TXDIS_OUT => link_stat_out, + SD_PRSNT_N_IN => link_stat_in, + SD_LOS_IN => link_stat_in, + SD_TXDIS_OUT => link_stat_out, --Control Interface - BUS_RX => bussci_rx, - BUS_TX => bussci_tx, + BUS_RX => bussci_rx, + BUS_TX => bussci_tx, -- Status and control port - STAT_DEBUG => med_stat_debug(63 downto 0), - CTRL_DEBUG => open + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => open ); -SIG(2) <= '1' when link_stat_out = '1' else '0'; -link_stat_in <= SIG(1); - + SIG(2) <= '1' when link_stat_out = '1' else '0'; + link_stat_in <= SIG(1); + --------------------------------------------------------------------------- -- Endpoint --------------------------------------------------------------------------- -THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record - generic map ( - ADDRESS_MASK => x"FFFF", - BROADCAST_BITMASK => x"FF", - REGIO_INIT_ENDPOINT_ID => x"0001", - TIMING_TRIGGER_RAW => c_YES, - --Configure data handler - DATA_INTERFACE_NUMBER => 1, - DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, - DATA_BUFFER_WIDTH => 32, - DATA_BUFFER_FULL_THRESH => EVENT_BUFFER_SIZE/2, - TRG_RELEASE_AFTER_DATA => c_YES, - HEADER_BUFFER_DEPTH => 9, - HEADER_BUFFER_FULL_THRESH => 2**8 - ) - - port map( - -- Misc - CLK => clk_sys, - RESET => reset_i, - CLK_EN => '1', - - -- Media direction port - MEDIA_MED2INT => med2int(0), - MEDIA_INT2MED => int2med(0), - - --Timing trigger in - TRG_TIMING_TRG_RECEIVED_IN => TRIG_IN, - - READOUT_RX => readout_rx, - READOUT_TX => readout_tx, - - --Slow Control Port - REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 - REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 - BUS_RX => ctrlbus_rx, - BUS_TX => ctrlbus_tx, - BUS_MASTER_IN => bus_master_in, - BUS_MASTER_OUT => bus_master_out, - BUS_MASTER_ACTIVE => bus_master_active, - - ONEWIRE_INOUT => TEMP_LINE, - --Timing registers - TIMERS_OUT => timer - ); + THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record + generic map ( + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + REGIO_INIT_ENDPOINT_ID => x"0001", + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**8 + ) + + port map( + -- Misc + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + + -- Media direction port + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => TRIG_IN, + + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + + --Slow Control Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + + ONEWIRE_INOUT => TEMP_LINE, + --Timing registers + TIMERS_OUT => timer + ); --------------------------------------------------------------------------- -- Bus Handler @@ -252,19 +253,19 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record generic map( PORT_NUMBER => 5, PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"c000", others => x"0000"), - PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 8, 4 => 12, others => 0), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 8, 4 => 12, others => 0), PORT_MASK_ENABLE => 1 ) port map( CLK => clk_sys, RESET => reset_i, - REGIO_RX => ctrlbus_rx, - REGIO_TX => ctrlbus_tx, - - BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED - BUS_RX(1) => bussci_rx, --SCI Serdes - BUS_RX(2) => bustc_rx, --Clock switch + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(2) => bustc_rx, --Clock switch BUS_RX(3) => busthresh_rx, BUS_RX(4) => bustdc_rx, BUS_TX(0) => bustools_tx, @@ -272,23 +273,23 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record BUS_TX(2) => bustc_tx, BUS_TX(3) => busthresh_tx, BUS_TX(4) => bustdc_tx, - + STAT_DEBUG => open ); --------------------------------------------------------------------------- -- Control Tools --------------------------------------------------------------------------- - THE_TOOLS: entity work.trb3sc_tools + THE_TOOLS : entity work.trb3sc_tools port map( - CLK => clk_sys, - RESET => reset_i, - + CLK => clk_sys, + RESET => reset_i, + --Flash & Reload - FLASH_CS => FLASH_CS, --FLASH_CS, + FLASH_CS => FLASH_CS, --FLASH_CS, FLASH_CLK => FLASH_CLK, - FLASH_IN => FLASH_OUT, --FLASH_OUT, - FLASH_OUT => FLASH_IN,--FLASH_IN, + FLASH_IN => FLASH_OUT, --FLASH_OUT, + FLASH_OUT => FLASH_IN, --FLASH_IN, PROGRAMN => PROGRAMN, REBOOT_IN => common_ctrl_reg(15), --SPI @@ -322,109 +323,112 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record DEBUG_OUT => debug_tools ); - -FLASH_HOLD <= '1'; -FLASH_WP <= '1'; + + FLASH_HOLD <= '1'; + FLASH_WP <= '1'; --------------------------------------------------------------------------- -- PWM / Thresh --------------------------------------------------------------------------- -THE_PWM_GEN : entity work.pwm_generator - port map( - CLK => clk_sys, - CLK_FAST => CLOCK_IN, - BUS_RX => busthresh_rx, - BUS_TX => busthresh_tx, - TEMP_IN => timer.temperature, - PWM => pwm_i - ); - -PWM <= pwm_i; + THE_PWM_GEN : entity work.pwm_generator + port map( + CLK => clk_sys, + CLK_FAST => CLOCK_IN, + BUS_RX => busthresh_rx, + BUS_TX => busthresh_tx, + TEMP_IN => timer.temperature, + PWM => pwm_i + ); + + PWM <= pwm_i; --------------------------------------------------------------------------- -- I/O --------------------------------------------------------------------------- - + TEST_LINE(8 downto 1) <= hdr_io(7 downto 0); hdr_io(8) <= TEST_LINE(9); TEST_LINE(10) <= hdr_io(9); TEST_LINE(14 downto 11) <= time_counter(31 downto 28); - + --------------------------------------------------------------------------- -- LCD Data to display --------------------------------------------------------------------------- lcd_data(15 downto 0) <= timer.network_address; lcd_data(47 downto 16) <= timer.microsecond; - lcd_data(79 downto 48) <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)); + lcd_data(79 downto 48) <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)); lcd_data(91 downto 80) <= timer.temperature; lcd_data(95 downto 92) <= x"0"; lcd_data(159 downto 96) <= timer.uid; lcd_data(191 downto 160) <= debug_tools; - lcd_data(511 downto 192) <= (others => '0'); - + lcd_data(511 downto 192) <= (others => '0'); + --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- - LED_GREEN <= not med2int(0).stat_op(9) or led_off; - LED_ORANGE <= debug_clock_reset(0) or led_off; - LED_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) or led_off; - LED_YELLOW <= led_los_lock or led_off; + LED_GREEN <= not med2int(0).stat_op(9) or led_off; + LED_ORANGE <= debug_clock_reset(0) or led_off; + LED_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) or led_off; + LED_YELLOW <= led_los_lock or led_off; --------------------------------------------------------------------------- -- Test Circuits --------------------------------------------------------------------------- - process begin + process + begin wait until rising_edge(clk_sys); - time_counter <= time_counter + 1; + time_counter <= time_counter + 1; if reset_i = '1' then time_counter <= (others => '0'); end if; - end process; + end process; ------------------------------------------------------------------------------- -- TDC ------------------------------------------------------------------------------- --- THE_TDC : entity work.TDC_record --- generic map ( --- CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module --- STATUS_REG_NR => 21, -- Number of status regs --- DEBUG => c_YES, --- SIMULATION => c_NO) --- port map ( --- RESET => reset_i, --- CLK_TDC => CLOCK_IN, --- CLK_READOUT => clk_sys, -- Clock for the readout --- REFERENCE_TIME => TRIG_IN, -- Reference time input --- HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals --- HIT_CAL_IN => CLOCK_CAL, -- Hits for calibrating the TDC --- -- Trigger signals from handler --- BUSRDO_RX => readout_rx, --- BUSRDO_TX => readout_tx(0), --- -- Slow control bus --- BUS_RX => bustdc_rx, --- BUS_TX => bustdc_tx, --- -- Dubug signals --- INFO_IN => timer, --- LOGIC_ANALYSER_OUT => logic_analyser_i --- ); --- --- -- For single edge measurements --- gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate --- hit_in_i <= INPUT; --- end generate; --- --- -- For ToT Measurements --- gen_double : if DOUBLE_EDGE_TYPE = 2 generate --- Gen_Hit_In_Signals : for i in 1 to 16 generate --- hit_in_i(i*2-1) <= INPUT(i); --- hit_in_i(i*2) <= not INPUT(i); --- end generate Gen_Hit_In_Signals; --- end generate; + THE_TDC : entity work.TDC_record + generic map ( + CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module + STATUS_REG_NR => 21, -- Number of status regs + DEBUG => c_YES, + SIMULATION => c_NO) + port map ( + RESET => reset_i, + CLK_TDC => CLOCK_IN, + CLK_READOUT => clk_sys, -- Clock for the readout + REFERENCE_TIME => TRIG_IN, -- Reference time input + HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals + HIT_CAL_IN => CLOCK_CAL, -- Hits for calibrating the TDC + -- Trigger signals from handler + BUSRDO_RX => readout_rx, + BUSRDO_TX => readout_tx(0), + -- Slow control bus + BUS_RX => bustdc_rx, + BUS_TX => bustdc_tx, + -- Dubug signals + INFO_IN => timer, + LOGIC_ANALYSER_OUT => logic_analyser_i + ); + +-- For single edge measurements + --gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate + -- hit_in_i <= INPUT; + --end generate; + hit_in_i(1) <= INPUT(31); + hit_in_i(2) <= INPUT(32); + +-- For ToT Measurements + gen_double : if DOUBLE_EDGE_TYPE = 2 generate + Gen_Hit_In_Signals : for i in 1 to 16 generate + hit_in_i(i*2-1) <= INPUT(i); + hit_in_i(i*2) <= not INPUT(i); + end generate Gen_Hit_In_Signals; + end generate; end architecture; -- 2.43.0