From c5c5814382b011bc78605013ca18328d1bcf5507 Mon Sep 17 00:00:00 2001 From: "P. Schakel" Date: Thu, 13 Apr 2017 11:36:22 +0200 Subject: [PATCH] Latest version of SODA. Panda Data Concentrator on TRB3 and on Xilinx KC705 board running at 2Gb/s Feature Extraction at Kintex 7 Front End ADC board Feature Extraction on Virtex 6 (old version) SODA source and SODA hub on TRB3 board --- .../ADC32dualgain.xdc | 944 ++++ .../ADC32dualgain_debug.xdc | 0 .../FEE_Kintex_ADCboard.vhd | 2383 ++++++++++ .../FEE_Kintex_ADCboard_Vivado.xpr | 1826 +++++++ .../sources/FEE_startup.vhd | 428 ++ .../sources/LMK04806.vhd | 414 ++ .../sources/adc/ADC_SLOW_CTRL.vhd | 155 + .../sources/adc}/AdcClock.vhd | 1006 ++-- .../sources/adc/AdcData.vhd | 350 ++ .../sources/adc/AdcFrame.vhd | 182 + .../sources/adc/AdcSerialProg.vhd | 320 ++ .../sources/adc/AdcToplevel.vhd | 492 ++ .../sources/adc}/FEE_ADCinput_module.vhd | 564 ++- .../sources/adc/FEE_Kintex_ADCboard.ucf | 1153 +++++ .../sources/gtx/FEE_SODAfrequencydiv5.vhd | 190 + .../sources/gtx/FEE_data16to8.vhd | 109 + .../sources/gtx/FEE_data8to16.vhd | 100 + .../sources/gtx/FEE_gtxModule.vhd | 413 ++ .../sources/gtx/FEE_gtxWrapper_Kintex7.vhd | 549 +++ .../sources/gtx/gtx_common.vhd | 251 + .../sources/gtx/ip/gtxkintex7fee80.vhd | 584 +++ .../ip/gtxkintex7fee80_auto_phase_align.vhd | 202 + .../gtx/ip/gtxkintex7fee80_clock_module.vhd} | 475 +- .../sources/gtx/ip/gtxkintex7fee80_gt.vhd | 816 ++++ .../gtxkintex7fee80_rx_manual_phase_align.vhd | 286 ++ .../gtx/ip/gtxkintex7fee80_rx_startup_fsm.vhd | 738 +++ .../gtx/ip/gtxkintex7fee80_sync_block.vhd | 144 + .../gtx/ip/gtxkintex7fee80_sync_pulse.vhd | 157 + .../sources/gtx/ip/gtxkintex7fee80_top.vhd | 929 ++++ .../gtxkintex7fee80_tx_manual_phase_align.vhd | 380 ++ .../gtx/ip/gtxkintex7fee80_tx_startup_fsm.vhd | 562 +++ .../ip_vivado/IPsources/gtxkintex7fee80.vhd | 403 ++ .../gtxkintex7fee80_auto_phase_align.vhd | 198 + .../gtxkintex7fee80_cpll_railing.vhd | 144 + .../IPsources/gtxkintex7fee80_gt.vhd | 834 ++++ .../IPsources/gtxkintex7fee80_init.vhd | 885 ++++ .../IPsources/gtxkintex7fee80_multi_gt.vhd | 509 ++ .../gtxkintex7fee80_rx_startup_fsm.vhd | 788 ++++ .../IPsources/gtxkintex7fee80_sync_block.vhd | 194 + .../gtxkintex7fee80_tx_startup_fsm.vhd | 609 +++ .../gtxKintex7FEE80/gtxKintex7FEE80.xci | 1239 +++++ .../gtx/ip_vivado/gtxKintex7FEE80_exdes.xdc} | 200 +- .../gtxkintex7fee80_clock_module.vhd} | 444 +- .../gtx/ip_vivado/gtxkintex7fee80_common.vhd | 247 + .../gtxkintex7fee80_common_reset.vhd | 154 + .../gtxkintex7fee80_gt_usrclk_source.vhd | 206 + .../gtx/ip_vivado/gtxkintex7fee80_support.vhd | 663 +++ .../SystemMonitorKintex.xci | 284 ++ .../ip/async_fifo_16x9/async_fifo_16x9.xci | 423 ++ .../async_fifo_256x32/async_fifo_256x32.xci | 425 ++ .../async_fifo_512x32/async_fifo_512x32.xci | 423 ++ ...c_progfull448_progempty128_fifo_512x34.xci | 429 ++ .../sources/ip/aurora_dual/aurora_dual.xci | 243 + .../aurora_dual_aurora_pkg.vhd} | 109 +- .../aurora_dual_axi_to_ll_exdes.vhd | 183 + .../aurora_dual_cdc_sync_exdes.vhd | 741 +++ .../aurora_dual_clock_module.vhd | 148 + .../aurora_dual_gt_common_wrapper.vhd | 229 + .../aurora_dual_ll_to_axi_exdes.vhd | 140 + .../aurora_dual_module.vhd | 877 ++++ .../aurora_dual_support.vhd | 587 +++ .../aurora_dual_support_reset_logic.vhd | 220 + .../blockmem1x18_xilinx.xci | 200 + .../blockmem1x96_xilinx.xci | 199 + .../blockmem2x18_xilinx.xci | 199 + .../blockmem2x96_xilinx.xci | 199 + .../blockmem3x18_xilinx.xci | 199 + .../blockmem3x96_xilinx.xci | 199 + .../blockmem4x18_xilinx.xci | 199 + .../blockmem5x18_xilinx.xci | 199 + .../ip/blockmem_xilinx/blockmem_xilinx.xci | 199 + .../ip/clock100to200/clock100to200.xci | 517 ++ .../clockmodule100to80M.xci | 549 +++ .../clockmodule40Mto80M.xci | 524 +++ .../gtxKintex7FEE80_clockmodule.xci | 521 ++ .../sources/ip/sem.xcix | Bin 0 -> 898467 bytes .../sources/ip/sem_sem_vio.xcix | Bin 0 -> 14365798 bytes .../sources/ip/sem_support/sem_sem_cfg.vhd | 250 + .../ip/sem_support/sem_sem_example.vhd | 603 +++ .../sources/ip/sem_support/sem_sem_hid.vhd | 413 ++ .../sources/ip/sem_support/sem_sem_mon.vhd | 321 ++ .../ip/sem_support/sem_sem_mon_fifo.vhd | 293 ++ .../ip/sem_support/sem_sem_mon_piso.vhd | 309 ++ .../ip/sem_support/sem_sem_mon_sipo.vhd | 243 + .../sync_fifo_512x111/sync_fifo_512x111.xci | 422 ++ .../ip/sync_fifo_512x41/sync_fifo_512x41.xci | 424 ++ .../sync_fifo_FWFT_512x36.xci | 428 ++ .../sync_fifo_progempty32_FWFT_512x104.xci | 427 ++ ...c_fifo_progfull364_progempty128_512x36.xci | 428 ++ ...c_fifo_progfull504_progempty128_512x36.xci | 424 ++ ...nc_fifo_progfull504_progempty32_512x36.xci | 426 ++ .../sources/ip/vio36/vio36.xci | 822 ++++ .../sources/reboot.vhd | 119 + .../sources/sem_module.vhd | 359 ++ .../sources/sensors}/SystemMonitorModule.vhd | 342 +- .../sources/sensors/TMP104module.vhd | 296 ++ .../FEE_modules/FEE_MWDfilter_unsigned.vhd | 283 ++ .../FEE_modules/FEE_SODAfrequencydiv5.vhd | 4 +- .../FEE_modules/FEE_adc32_module.vhd | 558 ++- .../FEE_baselinefollower_eventdetector.vhd | 212 +- .../FEE_modules/FEE_board_slowcontrol.vhd | 32 +- .../FEE_modules/FEE_collect_pileup_pulses.vhd | 310 ++ .../FEE_modules/FEE_combine_data.vhd | 329 +- .../FEE_modules/FEE_dual_pulse_waveform.vhd | 1957 +++++--- .../FEE_modules/FEE_eventdetector.vhd | 18 +- .../FEE_modules/FEE_extract_pulse.vhd | 190 +- .../FEE_modules/FEE_fifo32to8_SODA.vhd | 140 +- .../FEE_modules/FEE_fiforead2write.vhd | 138 + .../FEE_modules/FEE_gtxWrapper_Virtex6.vhd | 9 +- .../FEE_modules/FEE_measure_frequency.vhd | 6 +- FEE_ADC32board/FEE_modules/FEE_mux2to1.vhd | 484 +- .../FEE_modules/FEE_mux_readfifo.vhd | 10 +- .../FEE_modules/FEE_pileup_check.vhd | 310 +- .../FEE_modules/FEE_pulse2to1_pulse.vhd | 8 + .../FEE_pulse_and_pileup_waveforms.vhd | 658 ++- .../FEE_modules/FEE_pulse_detect.vhd | 158 + .../FEE_modules/FEE_pulsewaveform_buffer.vhd | 75 +- .../FEE_modules/FEE_receive_split.vhd | 347 ++ .../FEE_slowcontrol_packet_receiver.vhd | 38 +- .../FEE_slowcontrol_receive_from_cpu.vhd | 71 +- .../FEE_modules/FEE_sorting_mux.vhd | 653 +-- .../FEE_modules/FEE_sorting_wavemux.vhd | 704 +-- .../FEE_modules/FEE_transmit_combine.vhd | 577 +++ .../FEE_modules/FEE_waveform_to_36bits.vhd | 518 +- .../FEE_modules/FEE_wavemux2to1.vhd | 484 +- .../FEE_modules/FEE_wavemux_readfifo.vhd | 8 +- FEE_ADC32board/FEE_modules/GrayCounter.vhd | 46 + FEE_ADC32board/FEE_modules/Panda_package.vhd | 140 +- FEE_ADC32board/FEE_modules/asyncfifo.vhd | 174 + .../FEE_modules/iirfilter_1order_selectBW.vhd | 28 +- .../FEE_modules/posedge_async_to_pulse.vhd | 64 + FEE_ADC32board/FEE_modules/shift_register.vhd | 6 +- .../FEE_modules/shift_register_small.vhd | 226 + .../modules/ADCrefdesign/AdcData.vhd | 775 --- .../modules/ADCrefdesign/AdcFrame.vhd | 859 ---- .../modules/ADCrefdesign/AdcToplevel.vhd | 739 --- .../ADCrefdesign/DoubleNibbleDetect.vhd | 293 -- .../modules/ADCrefdesign/GenPulse.vhd | 132 - FEE_ADC32board/modules/LMK03806.vhd | 564 --- FEE_ADC32board/project/FEE_ADC32board.gise | 33 - FEE_ADC32board/project/FEE_ADC32board.ucf | 1009 ---- FEE_ADC32board/project/FEE_ADC32board.xise | 669 --- FEE_ADC32board/project/FEE_ADC32board_top.vhd | 2184 --------- .../project/ipcore_dir/FEE_clockbuf80MHz.asy | 17 - .../project/ipcore_dir/FEE_clockbuf80MHz.gise | 52 - .../project/ipcore_dir/FEE_clockbuf80MHz.ucf | 58 - .../project/ipcore_dir/FEE_clockbuf80MHz.vho | 89 - .../project/ipcore_dir/FEE_clockbuf80MHz.xco | 269 -- .../project/ipcore_dir/FEE_clockbuf80MHz.xise | 75 - .../ipcore_dir/SystemMonitorVirtex.asy | 89 - .../ipcore_dir/SystemMonitorVirtex.gise | 53 - .../ipcore_dir/SystemMonitorVirtex.vhd | 192 - .../ipcore_dir/SystemMonitorVirtex.vho | 112 - .../ipcore_dir/SystemMonitorVirtex.xco | 163 - .../ipcore_dir/SystemMonitorVirtex.xise | 68 - .../project/ipcore_dir/_xmsgs/pn_parser.xmsgs | 15 - .../project/ipcore_dir/async_fifo_16x9.asy | 41 - .../project/ipcore_dir/async_fifo_16x9.gise | 53 - .../project/ipcore_dir/async_fifo_16x9.ngc | 3 - .../project/ipcore_dir/async_fifo_16x9.vhd | 283 -- .../project/ipcore_dir/async_fifo_16x9.vho | 95 - .../project/ipcore_dir/async_fifo_16x9.xco | 213 - .../project/ipcore_dir/async_fifo_16x9.xise | 74 - .../project/ipcore_dir/async_fifo_512x32.asy | 41 - .../project/ipcore_dir/async_fifo_512x32.gise | 54 - .../project/ipcore_dir/async_fifo_512x32.ngc | 3 - .../project/ipcore_dir/async_fifo_512x32.vhd | 282 -- .../project/ipcore_dir/async_fifo_512x32.vho | 92 - .../project/ipcore_dir/async_fifo_512x32.xco | 217 - .../project/ipcore_dir/async_fifo_512x32.xise | 72 - .../ipcore_dir/clockmodule40switch.asy | 33 - .../ipcore_dir/clockmodule40switch.gise | 52 - .../ipcore_dir/clockmodule40switch.ucf | 61 - .../ipcore_dir/clockmodule40switch.vho | 100 - .../ipcore_dir/clockmodule40switch.xco | 269 -- .../ipcore_dir/clockmodule40switch.xise | 75 - .../project/ipcore_dir/clockmodule80M.asy | 17 - .../project/ipcore_dir/clockmodule80M.gise | 52 - .../project/ipcore_dir/clockmodule80M.ucf | 58 - .../project/ipcore_dir/clockmodule80M.vho | 90 - .../project/ipcore_dir/clockmodule80M.xco | 269 -- .../project/ipcore_dir/clockmodule80M.xise | 75 - .../project/ipcore_dir/clockmodule80to80M.asy | 33 - .../ipcore_dir/clockmodule80to80M.gise | 52 - .../project/ipcore_dir/clockmodule80to80M.ucf | 59 - .../project/ipcore_dir/clockmodule80to80M.vho | 101 - .../project/ipcore_dir/clockmodule80to80M.xco | 269 -- .../ipcore_dir/clockmodule80to80M.xise | 75 - FEE_ADC32board/project/ipcore_dir/coregen.cgp | 9 - .../project/ipcore_dir/data_vio.ngc | 3 - .../project/ipcore_dir/double_reset.vhd | 140 - .../ipcore_dir/fifo_generator_v8_3_readme.txt | 197 - .../project/ipcore_dir/frame_check.vhd | 702 --- .../project/ipcore_dir/frame_gen.vhd | 329 -- .../project/ipcore_dir/gtxVirtex6FEE80.gise | 51 - .../project/ipcore_dir/gtxVirtex6FEE80.vho | 270 -- .../project/ipcore_dir/gtxVirtex6FEE80.xco | 411 -- .../project/ipcore_dir/gtxVirtex6FEE80.xise | 143 - .../doc/ug516_v6_gtxwizard.pdf | Bin 3376991 -> 0 bytes .../example_design/double_reset.vhd | 140 - .../example_design/frame_check.vhd | 702 --- .../example_design/frame_gen.vhd | 329 -- .../example_design/gtxVirtex6FEE80_top.sdc | 72 - .../example_design/gtxVirtex6FEE80_top.ucf | 96 - .../example_design/gtxVirtex6FEE80_top.xcf | 74 - .../example_design/gtx_attributes.ucf | 280 -- .../gtxvirtex6fee80_rx_sync.vhd | 244 - .../example_design/gtxvirtex6fee80_top.vhd | 1373 ------ .../gtxvirtex6fee80_tx_sync.vhd | 226 - .../example_design/mgt_usrclk_source_mmcm.vhd | 218 - .../gtxVirtex6FEE80/gtxvirtex6fee80.pf | 221 - .../implement/chipscope_project.cpj | 3760 --------------- .../gtxVirtex6FEE80/implement/data_vio.ngc | 3 - .../gtxVirtex6FEE80/implement/icon.ngc | 3 - .../gtxVirtex6FEE80/implement/ila.ngc | 3 - .../gtxVirtex6FEE80/implement/implement.bat | 122 - .../gtxVirtex6FEE80/implement/implement.sh | 123 - .../implement/implement_synplify.bat | 120 - .../implement/implement_synplify.sh | 122 - .../implement/planAhead_ise.bat | 71 - .../implement/planAhead_ise.sh | 71 - .../implement/planAhead_ise.tcl | 127 - .../implement/rx_phase_align_fifo.ngc | 3 - .../gtxVirtex6FEE80/implement/synplify.prj | 101 - .../implement/tx_phase_align_fifo.ngc | 3 - .../gtxVirtex6FEE80/implement/xst.prj | 72 - .../gtxVirtex6FEE80/implement/xst.scr | 99 - .../gtxVirtex6FEE80/simulation/demo_tb.vhd | 266 -- .../simulation/demo_tb_imp.vhd | 251 - .../simulation/functional/simulate_isim.bat | 92 - .../simulation/functional/simulate_isim.sh | 94 - .../simulation/functional/simulate_mti.do | 119 - .../simulation/functional/simulate_ncsim.bat | 98 - .../simulation/functional/simulate_ncsim.sh | 99 - .../simulation/functional/simulate_vcs.sh | 86 - .../simulation/functional/ucli_commands.key | 66 - .../simulation/functional/vcs_session.tcl | 136 - .../simulation/functional/wave_isim.tcl | 120 - .../simulation/functional/wave_mti.do | 132 - .../simulation/functional/wave_ncsim.sv | 120 - .../simulation/netlist/simulate_mti.do | 97 - .../v6_gtxwizard_v1_12_readme.txt | 153 - .../project/ipcore_dir/gtx_attributes.ucf | 280 -- .../project/ipcore_dir/gtxvirtex6fee80.vhd | 377 -- .../ipcore_dir/gtxvirtex6fee80_gtx.vhd | 639 --- .../ipcore_dir/gtxvirtex6fee80_rx_sync.vhd | 244 - .../ipcore_dir/gtxvirtex6fee80_top.vhd | 1373 ------ .../ipcore_dir/gtxvirtex6fee80_tx_sync.vhd | 226 - FEE_ADC32board/project/ipcore_dir/icon.ngc | 3 - FEE_ADC32board/project/ipcore_dir/icon0.asy | 25 - FEE_ADC32board/project/ipcore_dir/icon0.gise | 32 - FEE_ADC32board/project/ipcore_dir/icon0.ngc | 3 - FEE_ADC32board/project/ipcore_dir/icon0.ucf | 9 - FEE_ADC32board/project/ipcore_dir/icon0.vhd | 33 - FEE_ADC32board/project/ipcore_dir/icon0.vho | 44 - FEE_ADC32board/project/ipcore_dir/icon0.xco | 56 - FEE_ADC32board/project/ipcore_dir/icon0.xise | 79 - .../project/ipcore_dir/icon0_readme.txt | 57 - FEE_ADC32board/project/ipcore_dir/ila.ngc | 3 - FEE_ADC32board/project/ipcore_dir/ila128.asy | 17 - FEE_ADC32board/project/ipcore_dir/ila128.gise | 53 - FEE_ADC32board/project/ipcore_dir/ila128.ngc | 3 - FEE_ADC32board/project/ipcore_dir/ila128.vhd | 31 - FEE_ADC32board/project/ipcore_dir/ila128.vho | 40 - FEE_ADC32board/project/ipcore_dir/ila128.xco | 138 - FEE_ADC32board/project/ipcore_dir/ila128.xise | 72 - .../project/ipcore_dir/ila128_readme.txt | 57 - FEE_ADC32board/project/ipcore_dir/ila36.asy | 17 - FEE_ADC32board/project/ipcore_dir/ila36.gise | 53 - FEE_ADC32board/project/ipcore_dir/ila36.ngc | 3 - FEE_ADC32board/project/ipcore_dir/ila36.vhd | 31 - FEE_ADC32board/project/ipcore_dir/ila36.vho | 40 - FEE_ADC32board/project/ipcore_dir/ila36.xco | 138 - FEE_ADC32board/project/ipcore_dir/ila36.xise | 72 - .../project/ipcore_dir/ila36_readme.txt | 57 - .../ipcore_dir/mgt_usrclk_source_mmcm.vhd | 218 - .../project/ipcore_dir/sync_fifo_512x41.asy | 37 - .../project/ipcore_dir/sync_fifo_512x41.gise | 53 - .../project/ipcore_dir/sync_fifo_512x41.ngc | 3 - .../project/ipcore_dir/sync_fifo_512x41.vhd | 280 -- .../project/ipcore_dir/sync_fifo_512x41.vho | 93 - .../project/ipcore_dir/sync_fifo_512x41.xco | 213 - .../project/ipcore_dir/sync_fifo_512x41.xise | 74 - .../ipcore_dir/sync_fifo_FWFT_512x36.asy | 37 - .../ipcore_dir/sync_fifo_FWFT_512x36.gise | 53 - .../ipcore_dir/sync_fifo_FWFT_512x36.ngc | 3 - .../ipcore_dir/sync_fifo_FWFT_512x36.vhd | 280 -- .../ipcore_dir/sync_fifo_FWFT_512x36.vho | 93 - .../ipcore_dir/sync_fifo_FWFT_512x36.xco | 213 - .../ipcore_dir/sync_fifo_FWFT_512x36.xise | 74 - ...c_fifo_progfull364_progempty128_512x36.asy | 45 - ..._fifo_progfull364_progempty128_512x36.gise | 53 - ...c_fifo_progfull364_progempty128_512x36.ngc | 3 - ...c_fifo_progfull364_progempty128_512x36.vhd | 286 -- ...c_fifo_progfull364_progempty128_512x36.vho | 97 - ...c_fifo_progfull364_progempty128_512x36.xco | 213 - ..._fifo_progfull364_progempty128_512x36.xise | 74 - ...c_fifo_progfull504_progempty128_512x36.asy | 45 - ..._fifo_progfull504_progempty128_512x36.gise | 53 - ...c_fifo_progfull504_progempty128_512x36.ngc | 3 - ...c_fifo_progfull504_progempty128_512x36.vhd | 286 -- ...c_fifo_progfull504_progempty128_512x36.vho | 97 - ...c_fifo_progfull504_progempty128_512x36.xco | 213 - ..._fifo_progfull504_progempty128_512x36.xise | 74 - FEE_ADC32board/project/ipcore_dir/vio36.asy | 13 - FEE_ADC32board/project/ipcore_dir/vio36.gise | 53 - FEE_ADC32board/project/ipcore_dir/vio36.ngc | 3 - FEE_ADC32board/project/ipcore_dir/vio36.vhd | 30 - FEE_ADC32board/project/ipcore_dir/vio36.vho | 38 - FEE_ADC32board/project/ipcore_dir/vio36.xco | 56 - FEE_ADC32board/project/ipcore_dir/vio36.xise | 72 - .../project/ipcore_dir/vio36_readme.txt | 57 - .../iseconfig/FEE_ADC32board.projectmgr | 97 - .../iseconfig/FEE_adc32_module.xreport | 215 - FEE_ADC32board/project/iseconfig/top.xreport | 215 - FEE_ADC32board/project/top.bit | Bin 5465079 -> 0 bytes SODA_addressmap | 106 - SODA_addressmap.odt | Bin 16092 -> 0 bytes SODA_quadsource_addressmap | 70 - code/Cu_trb3_periph_soda_client.vhd | 567 --- code/Cu_trb3_periph_soda_hub.vhd | 706 --- code/Cu_trb_net16_soda_syncUP_ecp3_sfp.vhd | 1052 ----- code/Cu_trb_net16_soda_sync_ecp3_sfp.vhd | 1073 ----- code/TB_soda_chain.vhd | 217 - code/TB_soda_source.vhd | 139 - code/ip/serdes_4_sync_downstream.ipx | 11 - code/ip/serdes_4_sync_hub_downstream.ipx | 11 - code/ip/serdes_4_sync_hub_downstream.lpc | 258 - code/ip/serdes_4_sync_hub_downstream.vhd | 2810 ----------- code/ip/serdes_soda_upstream.ipx | 11 - code/ip/serdes_soda_upstream.lpc | 258 - code/ip/serdes_soda_upstream.vhd | 2701 ----------- code/ip/serdes_sync_source_downstream.ipx | 11 - code/ip/serdes_sync_source_downstream.lpc | 258 - code/ip/serdes_sync_source_downstream.txt | 58 - code/ip/serdes_sync_source_downstream.vhd | 2702 ----------- code/ip/serdes_sync_upstream.ipx | 11 - code/ip/serdes_sync_upstream.txt | 58 - code/ip/sfp_1_125_int.ipx | 11 - code/ip/sfp_1_125_int.lpc | 258 - code/ip/sfp_1_125_int.txt | 58 - code/ip/sfp_1_125_int.vhd | 3162 ------------- code/ip/sfp_1_200_int.ipx | 11 - code/ip/sfp_1_200_int.lpc | 258 - code/ip/sfp_1_200_int.txt | 58 - code/ip/sfp_1_200_int.vhd | 3162 ------------- code/ip/sfp_2_200_int.ipx | 11 - code/ip/sfp_2_200_int.lpc | 258 - code/ip/sfp_2_200_int.txt | 93 - code/ip/sfp_2_200_int.vhd | 2739 ----------- code/med_ecp3_sfp_4_SODA.vhd | 666 --- code/med_ecp3_sfp_4_sync_down.vhd | 662 --- code/med_ecp3_sfp_4_sync_down_EP.vhd | 651 --- code/med_ecp3_sfp_sync_down.vhd | 573 --- code/med_ecp3_sfp_sync_up.vhd | 558 --- code/soda_4source.vhd | 409 -- code/soda_4source_synconstraints.fdc | 67 - code/soda_SOB_faker.vhd | 51 - code/soda_client_synconstraints.fdc | 66 - code/soda_clockscaler.vhd | 50 - code/soda_cmd_handler.vhd | 170 - code/soda_cmd_window_generator.vhd | 60 - code/soda_hub_synconstraints.fdc | 67 - code/soda_only_ecp3_sfp_4_sync_down.vhd | 666 --- code/soda_only_ecp3_sfp_sync_up.vhd | 543 --- code/soda_reply_handler.vhd | 73 - code/soda_source_clock_constraints.sdc | 11 - code/soda_source_syn_translated.fdc | 66 - code/soda_source_synconstraints.fdc | 48 - code/soda_tx_control.vhd | 517 -- code/trb3_periph_EP_soda4source.vhd | 760 --- code/trb3_periph_EP_sodahub.vhd | 804 ---- code/trb3_periph_sodaclient.vhd | 662 --- code/trb3_periph_sodahub.vhd | 828 ---- code/trb3_periph_sodasource.vhd | 719 --- code/trb_net16_med_1_2sync_3_ecp3_sfp.vhd | 1151 ----- code/trb_net16_soda_sync_ecp3_sfp.vhd | 1021 ---- code/trb_net_CRC.vhd | 74 - code/trb_net_CRC8.vhd | 61 - cores/README.txt | 1 - ctsc.ldf | 302 -- ctsc.lpf | 156 - ctsh.ldf | 320 -- ctsh.lpf | 162 - .../DataConcentrator_KC705.xdc | 183 + .../DataConcentrator_KC705.xpr | 2260 +++++++++ .../KC705_Rev1_0_U1.ucf.xdc | 1168 +++++ .../trb3_kc705_data_concentrator.vhd | 1821 +++++++ .../sources/cluster/CN_checkcluster.vhd | 251 + .../sources/cluster/CN_checkdata.vhd | 247 + .../sources/cluster/CN_cluster_XY_LUT.vhd | 4174 +++++++++++++++++ .../sources/cluster/CN_cluster_build.vhd | 1397 ++++++ .../sources/cluster/CN_cluster_findgap.vhd | 419 ++ .../sources/cluster/CN_cluster_onedge_LUT.vhd | 68 + .../sources/cluster/CN_clustering.vhd | 578 +++ .../sources/cluster/CN_combine2clusters.vhd | 584 +++ .../sources/cluster/CN_combineclusters.vhd | 263 ++ .../sources/cluster/CN_fiforead2write.vhd | 144 + .../sources/cluster/CN_package.vhd | 468 ++ .../sources/cluster/CN_precluster_build.vhd | 1305 ++++++ .../sources/cluster/CN_precluster_findgap.vhd | 395 ++ .../sources/cluster/CN_preclustering.vhd | 668 +++ .../sources/cluster/blockmemdirectread.vhd | 95 + .../sources/div_pipe_r4_arch2/cond_add.vhd | 37 + .../sources/div_pipe_r4_arch2/div_r4_pipe.vhd | 149 + .../div_pipe_r4_arch2/implement_32by32.pdf | Bin 0 -> 14079 bytes .../sources/div_pipe_r4_arch2/mypack.vhd | 10 + .../sources/div_pipe_r4_arch2/nr_r4_cel.vhd | 61 + .../sources/div_pipe_r4_arch2/test_tb.vhd | 165 + ...rter for FPGA __ Overview __ OpenCores.pdf | Bin 0 -> 190287 bytes .../sources/heap_sorter/dpram4_synth.vhd | 65 + .../sources/heap_sorter/sort_dpram.vhd | 157 + .../sources/heap_sorter/sorter_ctrl.vhd | 288 ++ .../sources/heap_sorter/sorter_pkg.vhd | 192 + .../sources/heap_sorter/sorter_sys.vhd | 290 ++ .../sources/heap_sorter/sys_config.vhd | 9 + .../async_fifo_nn_thfull_FWFT_512x36_try1.vhd | 181 - .../async_fifo_nn_thfull_FWFT_512x36_try2.vhd | 117 - .../trb_net16_med_1_2sync_3_ecp3_sfp_old.vhd | 1151 ----- .../sources/xilinx/DC_SODAserdesWrapper.vhd | 612 +++ .../sources/xilinx/DC_data16to8.vhd | 114 + .../sources/xilinx/DC_data8to16.vhd | 86 + .../sources/xilinx/DC_rxBitLock.vhd | 175 + .../Kintex7/GTX/GTX_trb3_2gb_wrapper.vhd | 627 +++ .../GTX/GTX_trb3_2gb_wrapper_ver3.4.vhd | 621 +++ .../Kintex7/GTX/gtx_trb3_2gb_common.vhd | 247 + .../Kintex7/GTX/gtx_trb3_2gb_common_reset.vhd | 154 + .../GTX/gtx_trb3_2gb_gt_usrclk_source.vhd | 183 + .../GTX_SODA/GTX_quadSODA_wrapper_old.vhd | 1793 +++++++ .../GTX_SODA/GTX_quadSODA_wrapper_old2.vhd | 1593 +++++++ .../GTX_SODA/GTX_quadSODA_wrapper_old3.vhd | 1693 +++++++ .../Kintex7/GTX_SODA/gtx_quadsoda_common.vhd | 247 + .../GTX_SODA/gtx_quadsoda_common_reset.vhd | 154 + .../gtx_quadsoda_gt_usrclk_source.vhd | 234 + .../Kintex7/GTX_SODA/gtx_quadsoda_support.vhd | 1693 +++++++ .../Kintex7/GTX_SODAinput/GTX_SODAinput.xci | 1242 +++++ .../IPsources/gtx_sodainput.vhd | 403 ++ .../gtx_sodainput_auto_phase_align.vhd | 198 + .../IPsources/gtx_sodainput_cpll_railing.vhd | 144 + .../IPsources/gtx_sodainput_gt.vhd | 834 ++++ .../IPsources/gtx_sodainput_init.vhd | 882 ++++ .../IPsources/gtx_sodainput_multi_gt.vhd | 509 ++ .../gtx_sodainput_rx_startup_fsm.vhd | 788 ++++ .../IPsources/gtx_sodainput_sync_block.vhd | 194 + .../gtx_sodainput_tx_startup_fsm.vhd | 609 +++ .../gtx_sodainput_clock_module.vhd | 468 +- .../gtx_sodainput_common.vhd | 247 + .../gtx_sodainput_common_reset.vhd | 154 + .../gtx_sodainput_gt_usrclk_source.vhd | 208 + .../gtx_sodainput_support.vhd | 665 +++ .../Kintex7/GTX_dataoutput/GTX_dataoutput.xci | 1249 +++++ .../gtx_dataoutput_clock_module.vhd | 454 +- .../gtx_dataoutput_common.vhd | 247 + .../gtx_dataoutput_common_reset.vhd | 154 + .../gtx_dataoutput_gt_usrclk_source.vhd | 205 + .../gtx_dataoutput_support.vhd | 656 +++ .../Kintex7/GTX_dualSODA/GTX_dualSODA.xci | 1249 +++++ .../gtx_dualsoda_common.vhd | 247 + .../gtx_dualsoda_common_reset.vhd | 154 + .../gtx_dualsoda_gt_usrclk_source.vhd | 201 + .../gtx_dualsoda_support.vhd | 1017 ++++ .../Kintex7/GTX_quadSODA/GTX_quadSODA.xci | 1250 +++++ .../xilinx/Kintex7/GTX_quadSODA/xci/ila_0.xci | 2102 +++++++++ .../xilinx/Kintex7/GTX_quadSODA/xci/ila_1.xci | 2102 +++++++++ .../xilinx/Kintex7/GTX_quadSODA/xci/vio_0.xci | 826 ++++ .../Kintex7/GTX_trb3_2gb/GTX_trb3_2gb.xci | 1191 +++++ .../GTX_trb3_sync_2gb/GTX_trb3_sync_2gb.xci | 1245 +++++ .../IPsources/gtx_trb3_sync_2gb.vhd | 403 ++ .../gtx_trb3_sync_2gb_auto_phase_align.vhd | 198 + .../gtx_trb3_sync_2gb_cpll_railing.vhd | 144 + .../IPsources/gtx_trb3_sync_2gb_gt.vhd | 834 ++++ .../IPsources/gtx_trb3_sync_2gb_init.vhd | 885 ++++ .../IPsources/gtx_trb3_sync_2gb_multi_gt.vhd | 509 ++ .../gtx_trb3_sync_2gb_rx_startup_fsm.vhd | 788 ++++ .../gtx_trb3_sync_2gb_sync_block.vhd | 194 + .../gtx_trb3_sync_2gb_tx_startup_fsm.vhd | 609 +++ .../gtx_trb3_sync_2gb_clock_module.vhd | 245 + .../gtx_trb3_sync_2gb_common.vhd | 247 + .../gtx_trb3_sync_2gb_common_reset.vhd | 154 + .../gtx_trb3_sync_2gb_gt_usrclk_source.vhd | 206 + .../gtx_trb3_sync_2gb_support.vhd | 661 +++ .../async_fifo_16x8/async_fifo_16x8.xci | 423 ++ .../async_fifo_256x66/async_fifo_256x66.xci | 407 ++ .../async_fifo_512x32/async_fifo_512x32.xci | 423 ++ .../async_fifo_512x99/async_fifo_512x99.xci | 423 ++ .../async_fifo_nn_4096x103.xci | 424 ++ .../async_fifo_nn_4096x36.xci | 424 ++ ...o_nn_progfull1900_progempty128_2048x36.xci | 430 ++ ..._progfull980_progempty768_FWFT_1024x99.xci | 426 ++ .../async_fifo_nn_th_1024x36.xci | 422 ++ .../async_fifo_nn_thfull_FWFT_2048x36.xci | 428 ++ .../async_fifo_nn_thfull_FWFT_512x36.xci | 428 ++ .../Kintex7/clock100to200/clock100to200.xci | 522 +++ .../fifo_18x512_oreg/fifo_18x512_oreg.xci | 407 ++ .../fifo_36x16k_oreg/fifo_36x16k_oreg.xci | 407 ++ .../fifo_36x32k_oreg/fifo_36x32k_oreg.xci | 407 ++ .../fifo_36x512_oreg/fifo_36x512_oreg.xci | 407 ++ .../pll_in200_out200/pll_in200_out200.xci | 539 +++ .../pll_in200_out200_160_100_80.xci | 519 ++ .../sync_fifo_512x41/sync_fifo_512x41.xci | 422 ++ .../syncfifo_1024x66_almostempty256.xci | 418 ++ .../xilinx_fifo_18x16/xilinx_fifo_18x16.xci | 407 ++ .../xilinx_fifo_18x1k/xilinx_fifo_18x1k.xci | 407 ++ .../xilinx_fifo_18x1k_datacount.xci | 407 ++ .../xilinx_fifo_18x32/xilinx_fifo_18x32.xci | 407 ++ .../xilinx_fifo_18x64/xilinx_fifo_18x64.xci | 407 ++ .../xilinx_fifo_19x16_obuf.xci | 407 ++ .../xilinx_fifo_dualport_18x1k.xci | 407 ++ .../xilinx_fifo_sbuf/xilinx_fifo_sbuf.xci | 407 ++ .../sources/xilinx/fifo_19x16_obuf.vhd | 66 + .../sources/xilinx/fifo_sbuf.vhd | 59 + .../sources/xilinx/fifo_var_oreg.vhd | 176 + .../sources/xilinx/jittercleaner_200M.vhd | 179 + .../sources/xilinx/lattice_ecp2m_fifo.vhd | 30 + .../sources/xilinx/serdesDualMUXwrapper.vhd | 783 ++++ .../sources/xilinx/serdesQuadMUXwrapper.vhd | 1146 +++++ .../xilinx/spi_dpram_32_to_8_dummy.vhd | 30 + data_concentrator/sources/xilinx/sync_bit.vhd | 94 + .../sources/xilinx/trb_net16_fifo.vhd | 233 + .../sources/xilinx/trb_net16_fifo_arch.vhd | 233 + .../xilinx/trb_net16_med_gtx2_kintex7_sfp.vhd | 713 +++ .../trb_net16_med_sync_gtx2_kintex7_sfp.vhd | 1035 ++++ .../trb_net_fifo_16bit_bram_dualport.vhd | 71 + .../trb_net_fifo_16bit_bram_dualport_arch.vhd | 71 + data_concentrator/test_module.vhd | 174 - .../trb3_periph_data_concentrator.sdc | 17 + ...ph_data_concentrator_only1error_200MHz.lpf | 268 -- .../trb_net16_endpoint_data_concentrator.vhd | 1079 ----- ...t16_endpoint_data_concentrator_handler.vhd | 801 ---- hub_SODA/sources/HUB_16to8_SODA.vhd | 180 + hub_SODA/sources/HUB_8to16_SODA.vhd | 140 + hub_SODA/sources/HUB_SODA_clockcrossing.vhd | 125 + hub_SODA/sources/HUB_posedge_to_pulse.vhd | 72 + hub_SODA/sources/lattice/async_fifo_16x8.vhd | 51 + .../lattice/ecp3/async_fifo_16x8_ecp3.edn | 1375 ++++++ .../lattice/ecp3/async_fifo_16x8_ecp3.ipx | 9 + .../lattice/ecp3/async_fifo_16x8_ecp3.lpc | 50 + .../lattice/ecp3/async_fifo_16x8_ecp3.vhd | 642 +++ .../lattice/ecp3/serdes_sync_200_full.ipx | 11 + .../lattice/ecp3/serdes_sync_200_full.lpc | 30 +- .../lattice/ecp3/serdes_sync_200_full.pp | 191 + .../lattice/ecp3/serdes_sync_200_full.tft | 100 + .../lattice/ecp3/serdes_sync_200_full.txt | 14 +- .../lattice/ecp3/serdes_sync_200_full.vhd | 16 +- .../lattice/ecp3/sfp_3sync_200_int.ipx | 11 + .../lattice/ecp3/sfp_3sync_200_int.lpc | 56 +- .../sources/lattice/ecp3/sfp_3sync_200_int.pp | 191 + .../lattice/ecp3/sfp_3sync_200_int.tft | 100 + .../lattice/ecp3/sfp_3sync_200_int.txt | 58 + .../lattice/ecp3/sfp_3sync_200_int.vhd | 287 +- .../sources/lattice/serdes_rx_reset_sm.vhd | 196 + .../sources/lattice/serdes_tx_reset_sm.vhd | 174 + .../lattice/trb_net16_med_sync3_ecp3_sfp.vhd | 851 ++++ .../trb_net16_med_syncfull_ecp3_sfp.vhd | 998 ++++ .../trb3_periph_hub_SODA.ldf | 184 +- hub_SODA/trb3_periph_hub_SODA.lpf | 313 ++ .../trb3_periph_hub_SODA.vhd | 517 +- .../trb3_periph_hub_SODA.xcf | 41 +- .../serdes_sync_200_full.txt | 14 +- .../sfp_3sync_200_int.txt | 58 + ...3_periph_hub_SODA_trb3_periph_hub_SODA.bit | Bin 3804522 -> 3804554 bytes linkdesignfiles.sh | 1 - soda4srcEP.ldf | 278 -- soda4srcEP.lpf | 167 - soda_4source_EP.lpf | 197 - soda_addressmap.txt | 61 - soda_client.ldf | 325 -- soda_client.ldf~ | 316 -- soda_client.lpf | 165 - soda_client/serdes_sync_upstream.txt | 58 - soda_client_probe.rvl | 168 - soda_hub.ldf | 353 -- soda_hub.lpf | 1 - soda_hub/serdes_sync_upstream.txt | 58 - soda_hub_frankfurt.lpf | 222 - soda_hub_groningen.lpf | 211 - soda_hub_probe.rvl | 303 -- soda_slave/project/README.txt | 1 - soda_slave/sim/README.txt | 1 - soda_slave/trb3_periph_sodaslave.p2t | 21 - soda_slave/trb3_periph_sodaslave.prj | 160 - soda_slave/trb3_periph_sodaslave.vhd | 615 --- .../trb3_periph_sodaslave_constraints.lpf | 53 - soda_slave/workdir/.gitignore | 10 - .../pmi_ram_dpEbnonessdn208256208256.ngo | 1 - .../workdir/pmi_ram_dpEbnonessdn96649664.ngo | 1 - soda_slave/workdir/serdes_ch4.txt | 1 - soda_slave/workdir/serdes_full_ctc.txt | 1 - soda_slave/workdir/serdes_gbe_0ch.txt | 1 - soda_slave/workdir/serdes_onboard_full.txt | 1 - soda_slave/workdir/serdes_sync_0.txt | 1 - soda_slave/workdir/serdes_sync_125_0.txt | 1 - soda_slave/workdir/sfp_0_200_ctc.txt | 1 - soda_slave/workdir/sfp_0_200_int.txt | 1 - soda_slave/workdir/sfp_1_125_int.txt | 1 - soda_slave/workdir/sfp_1_200_int.txt | 1 - soda_slave/workdir/sgmii_gbe_pcs35.ngo | 1 - soda_slave/workdir/tsmac35.ngo | 1 - soda_source.ldf | 340 -- soda_source.lpf | 1 - soda_source/compile_kvi_periph.sh | 9 - soda_source/compile_periph_kvi.pl | 153 - soda_source/serdes_sync_source_downstream.txt | 58 - soda_source/sim/README.txt | 1 - soda_source/trb3_periph_sodasource.p2t | 21 - soda_source/trb3_periph_sodasource.vhd | 719 --- .../trb3_periph_sodasource_constraints.lpf | 53 - soda_source/workdir/.gitignore | 10 - .../pmi_ram_dpEbnonessdn208256208256.ngo | 1 - .../workdir/pmi_ram_dpEbnonessdn96649664.ngo | 1 - soda_source/workdir/serdes_ch4.txt | 1 - soda_source/workdir/serdes_full_ctc.txt | 1 - soda_source/workdir/serdes_gbe_0ch.txt | 1 - soda_source/workdir/serdes_onboard_full.txt | 1 - soda_source/workdir/serdes_sync_0.txt | 1 - soda_source/workdir/serdes_sync_125_0.txt | 1 - soda_source/workdir/sfp_0_200_ctc.txt | 1 - soda_source/workdir/sfp_0_200_int.txt | 1 - soda_source/workdir/sfp_1_125_int.txt | 1 - soda_source/workdir/sfp_1_200_int.txt | 1 - soda_source/workdir/sgmii_gbe_pcs35.ngo | 1 - soda_source/workdir/tsmac35.ngo | 1 - soda_source_frankfurt.lpf | 202 - soda_source_groningen.lpf | 200 - soda_source_probe.rvl | 370 -- soft/README.txt | 1 - {code => source}/posedge_to_pulse.vhd | 0 {code => source}/soda_calibration_timer.vhd | 2 +- {code => source}/soda_client.vhd | 32 +- {code => source}/soda_components.vhd | 4 + {code => source}/soda_d8crc8.vhd | 12 +- {code => source}/soda_hub.vhd | 19 +- {code => source}/soda_packet_builder.vhd | 418 +- {code => source}/soda_packet_handler.vhd | 35 +- source/soda_reply_handler.vhd | 87 + {code => source}/soda_reply_pkt_builder.vhd | 92 +- {code => source}/soda_source.vhd | 64 +- .../soda_start_of_burst_control.vhd | 6 +- {code => source}/soda_superburst_gen.vhd | 0 trb3_soda_client.xcf | 227 - trb3_soda_dual_client.xcf | 222 - trb3_soda_source.xcf | 227 - 642 files changed, 126483 insertions(+), 85728 deletions(-) create mode 100644 FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/ADC32dualgain.xdc create mode 100644 FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/ADC32dualgain_debug.xdc create mode 100644 FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/FEE_Kintex_ADCboard.vhd create mode 100644 FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/FEE_Kintex_ADCboard_Vivado.xpr create mode 100644 FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/FEE_startup.vhd create mode 100644 FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/LMK04806.vhd create mode 100644 FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/ADC_SLOW_CTRL.vhd rename FEE_ADC32board/{modules/ADCrefdesign => FEE_Kintex_ADCboard_Vivado/sources/adc}/AdcClock.vhd (75%) create mode 100644 FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcData.vhd create mode 100644 FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcFrame.vhd create mode 100644 FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcSerialProg.vhd create mode 100644 FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcToplevel.vhd rename FEE_ADC32board/{modules => FEE_Kintex_ADCboard_Vivado/sources/adc}/FEE_ADCinput_module.vhd (65%) create mode 100644 FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/FEE_Kintex_ADCboard.ucf create mode 100644 FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_SODAfrequencydiv5.vhd create mode 100644 FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_data16to8.vhd create mode 100644 FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_data8to16.vhd create mode 100644 FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_gtxModule.vhd create mode 100644 FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_gtxWrapper_Kintex7.vhd create mode 100644 FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/gtx_common.vhd create mode 100644 FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80.vhd create mode 100644 FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_auto_phase_align.vhd rename FEE_ADC32board/{project/ipcore_dir/clockmodule80to80M.vhd => FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_clock_module.vhd} (73%) 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hub_SODA/sources/lattice/ecp3/async_fifo_16x8_ecp3.edn create mode 100644 hub_SODA/sources/lattice/ecp3/async_fifo_16x8_ecp3.ipx create mode 100644 hub_SODA/sources/lattice/ecp3/async_fifo_16x8_ecp3.lpc create mode 100644 hub_SODA/sources/lattice/ecp3/async_fifo_16x8_ecp3.vhd create mode 100644 hub_SODA/sources/lattice/ecp3/serdes_sync_200_full.ipx rename code/ip/serdes_4_sync_downstream.lpc => hub_SODA/sources/lattice/ecp3/serdes_sync_200_full.lpc (92%) create mode 100644 hub_SODA/sources/lattice/ecp3/serdes_sync_200_full.pp create mode 100644 hub_SODA/sources/lattice/ecp3/serdes_sync_200_full.tft rename code/ip/serdes_4_sync_downstream.txt => hub_SODA/sources/lattice/ecp3/serdes_sync_200_full.txt (96%) rename code/ip/serdes_4_sync_downstream.vhd => hub_SODA/sources/lattice/ecp3/serdes_sync_200_full.vhd (99%) create mode 100644 hub_SODA/sources/lattice/ecp3/sfp_3sync_200_int.ipx rename code/ip/serdes_sync_upstream.lpc => hub_SODA/sources/lattice/ecp3/sfp_3sync_200_int.lpc (87%) create mode 100644 hub_SODA/sources/lattice/ecp3/sfp_3sync_200_int.pp create mode 100644 hub_SODA/sources/lattice/ecp3/sfp_3sync_200_int.tft create mode 100644 hub_SODA/sources/lattice/ecp3/sfp_3sync_200_int.txt rename code/ip/serdes_sync_upstream.vhd => hub_SODA/sources/lattice/ecp3/sfp_3sync_200_int.vhd (95%) create mode 100644 hub_SODA/sources/lattice/serdes_rx_reset_sm.vhd create mode 100644 hub_SODA/sources/lattice/serdes_tx_reset_sm.vhd create mode 100644 hub_SODA/sources/lattice/trb_net16_med_sync3_ecp3_sfp.vhd create mode 100644 hub_SODA/sources/lattice/trb_net16_med_syncfull_ecp3_sfp.vhd rename soda_source/project/SODA_source.ldf => hub_SODA/trb3_periph_hub_SODA.ldf (59%) create mode 100644 hub_SODA/trb3_periph_hub_SODA.lpf rename code/trb3_periph_hub.vhd => hub_SODA/trb3_periph_hub_SODA.vhd (68%) rename trb3_soda_hub.xcf => hub_SODA/trb3_periph_hub_SODA.xcf (81%) rename soda_hub/serdes_4_sync_downstream.txt => hub_SODA/trb3_periph_hub_SODA/serdes_sync_200_full.txt (96%) create mode 100644 hub_SODA/trb3_periph_hub_SODA/sfp_3sync_200_int.txt rename ctsc_20141217.bit => hub_SODA/trb3_periph_hub_SODA/trb3_periph_hub_SODA_trb3_periph_hub_SODA.bit (60%) delete mode 120000 linkdesignfiles.sh delete mode 100644 soda4srcEP.ldf delete mode 100644 soda4srcEP.lpf delete mode 100644 soda_4source_EP.lpf delete mode 100644 soda_addressmap.txt delete mode 100644 soda_client.ldf delete mode 100644 soda_client.ldf~ delete mode 100644 soda_client.lpf delete mode 100644 soda_client/serdes_sync_upstream.txt delete mode 100644 soda_client_probe.rvl delete mode 100644 soda_hub.ldf delete mode 120000 soda_hub.lpf delete mode 100644 soda_hub/serdes_sync_upstream.txt delete mode 100644 soda_hub_frankfurt.lpf delete mode 100644 soda_hub_groningen.lpf delete mode 100644 soda_hub_probe.rvl delete mode 100644 soda_slave/project/README.txt delete mode 100644 soda_slave/sim/README.txt delete mode 100644 soda_slave/trb3_periph_sodaslave.p2t delete mode 100644 soda_slave/trb3_periph_sodaslave.prj delete mode 100644 soda_slave/trb3_periph_sodaslave.vhd delete mode 100644 soda_slave/trb3_periph_sodaslave_constraints.lpf delete mode 100644 soda_slave/workdir/.gitignore delete mode 120000 soda_slave/workdir/pmi_ram_dpEbnonessdn208256208256.ngo delete mode 120000 soda_slave/workdir/pmi_ram_dpEbnonessdn96649664.ngo delete mode 120000 soda_slave/workdir/serdes_ch4.txt delete mode 120000 soda_slave/workdir/serdes_full_ctc.txt delete mode 120000 soda_slave/workdir/serdes_gbe_0ch.txt delete mode 120000 soda_slave/workdir/serdes_onboard_full.txt delete mode 120000 soda_slave/workdir/serdes_sync_0.txt delete mode 120000 soda_slave/workdir/serdes_sync_125_0.txt delete mode 120000 soda_slave/workdir/sfp_0_200_ctc.txt delete mode 120000 soda_slave/workdir/sfp_0_200_int.txt delete mode 120000 soda_slave/workdir/sfp_1_125_int.txt delete mode 120000 soda_slave/workdir/sfp_1_200_int.txt delete mode 120000 soda_slave/workdir/sgmii_gbe_pcs35.ngo delete mode 120000 soda_slave/workdir/tsmac35.ngo delete mode 100644 soda_source.ldf delete mode 120000 soda_source.lpf delete mode 100755 soda_source/compile_kvi_periph.sh delete mode 100755 soda_source/compile_periph_kvi.pl delete mode 100644 soda_source/serdes_sync_source_downstream.txt delete mode 100644 soda_source/sim/README.txt delete mode 100644 soda_source/trb3_periph_sodasource.p2t delete mode 100644 soda_source/trb3_periph_sodasource.vhd delete mode 100644 soda_source/trb3_periph_sodasource_constraints.lpf delete mode 100644 soda_source/workdir/.gitignore delete mode 120000 soda_source/workdir/pmi_ram_dpEbnonessdn208256208256.ngo delete mode 120000 soda_source/workdir/pmi_ram_dpEbnonessdn96649664.ngo delete mode 120000 soda_source/workdir/serdes_ch4.txt delete mode 120000 soda_source/workdir/serdes_full_ctc.txt delete mode 120000 soda_source/workdir/serdes_gbe_0ch.txt delete mode 120000 soda_source/workdir/serdes_onboard_full.txt delete mode 120000 soda_source/workdir/serdes_sync_0.txt delete mode 120000 soda_source/workdir/serdes_sync_125_0.txt delete mode 120000 soda_source/workdir/sfp_0_200_ctc.txt delete mode 120000 soda_source/workdir/sfp_0_200_int.txt delete mode 120000 soda_source/workdir/sfp_1_125_int.txt delete mode 120000 soda_source/workdir/sfp_1_200_int.txt delete mode 120000 soda_source/workdir/sgmii_gbe_pcs35.ngo delete mode 120000 soda_source/workdir/tsmac35.ngo delete mode 100644 soda_source_frankfurt.lpf delete mode 100644 soda_source_groningen.lpf delete mode 100644 soda_source_probe.rvl delete mode 100644 soft/README.txt rename {code => source}/posedge_to_pulse.vhd (100%) rename {code => source}/soda_calibration_timer.vhd (99%) rename {code => source}/soda_client.vhd (99%) rename {code => source}/soda_components.vhd (99%) rename {code => source}/soda_d8crc8.vhd (99%) rename {code => source}/soda_hub.vhd (95%) rename {code => source}/soda_packet_builder.vhd (78%) rename {code => source}/soda_packet_handler.vhd (87%) create mode 100644 source/soda_reply_handler.vhd rename {code => source}/soda_reply_pkt_builder.vhd (98%) rename {code => source}/soda_source.vhd (95%) rename {code => source}/soda_start_of_burst_control.vhd (99%) rename {code => source}/soda_superburst_gen.vhd (100%) delete mode 100644 trb3_soda_client.xcf delete mode 100644 trb3_soda_dual_client.xcf delete mode 100644 trb3_soda_source.xcf diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/ADC32dualgain.xdc b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/ADC32dualgain.xdc new file mode 100644 index 0000000..72c2212 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/ADC32dualgain.xdc @@ -0,0 +1,944 @@ +set_property DIFF_TERM TRUE [get_ports AD11A_N] +set_property IOSTANDARD LVDS [get_ports AD11A_N] +set_property DIFF_TERM TRUE [get_ports AD11A_P] +set_property IOSTANDARD LVDS [get_ports AD11A_P] +set_property PACKAGE_PIN AB8 [get_ports AD11A_P] +set_property DIFF_TERM TRUE [get_ports AD21A_N] +set_property IOSTANDARD LVDS_25 [get_ports AD21A_N] +set_property DIFF_TERM TRUE [get_ports AD21A_P] +set_property IOSTANDARD LVDS_25 [get_ports AD21A_P] +set_property PACKAGE_PIN AA21 [get_ports AD21A_P] +set_property DIFF_TERM TRUE [get_ports AD31A_N] +set_property IOSTANDARD LVDS_25 [get_ports AD31A_N] +set_property DIFF_TERM TRUE [get_ports AD31A_P] +set_property IOSTANDARD LVDS_25 [get_ports AD31A_P] +set_property PACKAGE_PIN P16 [get_ports AD31A_P] +set_property DIFF_TERM TRUE [get_ports AD41A_N] +set_property IOSTANDARD LVDS_25 [get_ports AD41A_N] +set_property DIFF_TERM TRUE [get_ports AD41A_P] +set_property IOSTANDARD LVDS_25 [get_ports AD41A_P] +set_property PACKAGE_PIN B18 [get_ports AD41A_P] +set_property DIFF_TERM TRUE [get_ports AD11B_N] +set_property IOSTANDARD LVDS [get_ports AD11B_N] +set_property DIFF_TERM TRUE [get_ports AD11B_P] +set_property IOSTANDARD LVDS [get_ports AD11B_P] +set_property PACKAGE_PIN AA6 [get_ports AD11B_P] +set_property DIFF_TERM TRUE [get_ports AD21B_N] +set_property IOSTANDARD LVDS_25 [get_ports AD21B_N] +set_property DIFF_TERM TRUE [get_ports AD21B_P] +set_property IOSTANDARD LVDS_25 [get_ports AD21B_P] +set_property PACKAGE_PIN W17 [get_ports AD21B_P] +set_property DIFF_TERM TRUE [get_ports AD31B_N] +set_property IOSTANDARD LVDS_25 [get_ports AD31B_N] +set_property DIFF_TERM TRUE [get_ports AD31B_P] +set_property IOSTANDARD LVDS_25 [get_ports AD31B_P] +set_property PACKAGE_PIN P21 [get_ports AD31B_P] +set_property DIFF_TERM TRUE [get_ports AD41B_N] +set_property IOSTANDARD LVDS_25 [get_ports AD41B_N] +set_property DIFF_TERM TRUE [get_ports AD41B_P] +set_property IOSTANDARD LVDS_25 [get_ports AD41B_P] +set_property PACKAGE_PIN C19 [get_ports AD41B_P] +set_property DIFF_TERM TRUE [get_ports AD12A_N] +set_property IOSTANDARD LVDS [get_ports AD12A_N] +set_property DIFF_TERM TRUE [get_ports AD12A_P] +set_property IOSTANDARD LVDS [get_ports AD12A_P] +set_property PACKAGE_PIN U7 [get_ports AD12A_P] +set_property DIFF_TERM TRUE [get_ports AD22A_N] +set_property IOSTANDARD LVDS_25 [get_ports AD22A_N] +set_property DIFF_TERM TRUE [get_ports AD22A_P] +set_property IOSTANDARD LVDS_25 [get_ports AD22A_P] +set_property PACKAGE_PIN W16 [get_ports AD22A_P] +set_property DIFF_TERM TRUE [get_ports AD32A_N] +set_property IOSTANDARD LVDS_25 [get_ports AD32A_N] +set_property DIFF_TERM TRUE [get_ports AD32A_P] +set_property IOSTANDARD LVDS_25 [get_ports AD32A_P] +set_property PACKAGE_PIN R18 [get_ports AD32A_P] +set_property DIFF_TERM TRUE [get_ports AD42A_N] +set_property IOSTANDARD LVDS_25 [get_ports AD42A_N] +set_property DIFF_TERM TRUE [get_ports AD42A_P] +set_property IOSTANDARD LVDS_25 [get_ports AD42A_P] +set_property PACKAGE_PIN C22 [get_ports AD42A_P] +set_property DIFF_TERM TRUE [get_ports AD12B_N] +set_property IOSTANDARD LVDS [get_ports AD12B_N] +set_property DIFF_TERM TRUE [get_ports AD12B_P] +set_property IOSTANDARD LVDS [get_ports AD12B_P] +set_property PACKAGE_PIN AA5 [get_ports AD12B_P] +set_property DIFF_TERM TRUE [get_ports AD22B_N] +set_property IOSTANDARD LVDS_25 [get_ports AD22B_N] +set_property DIFF_TERM TRUE [get_ports AD22B_P] +set_property IOSTANDARD LVDS_25 [get_ports AD22B_P] +set_property PACKAGE_PIN AA16 [get_ports AD22B_P] +set_property DIFF_TERM TRUE [get_ports AD32B_N] +set_property IOSTANDARD LVDS_25 [get_ports AD32B_N] +set_property DIFF_TERM TRUE [get_ports AD32B_P] +set_property IOSTANDARD LVDS_25 [get_ports AD32B_P] +set_property PACKAGE_PIN R21 [get_ports AD32B_P] +set_property DIFF_TERM TRUE [get_ports AD42B_N] +set_property IOSTANDARD LVDS_25 [get_ports AD42B_N] +set_property DIFF_TERM TRUE [get_ports AD42B_P] +set_property IOSTANDARD LVDS_25 [get_ports AD42B_P] +set_property PACKAGE_PIN A20 [get_ports AD42B_P] +set_property DIFF_TERM TRUE [get_ports AD13A_N] +set_property IOSTANDARD LVDS [get_ports AD13A_N] +set_property DIFF_TERM TRUE [get_ports AD13A_P] +set_property IOSTANDARD LVDS [get_ports AD13A_P] +set_property PACKAGE_PIN V7 [get_ports AD13A_P] +set_property DIFF_TERM TRUE [get_ports AD23A_N] +set_property IOSTANDARD LVDS_25 [get_ports AD23A_N] +set_property DIFF_TERM TRUE [get_ports AD23A_P] +set_property IOSTANDARD LVDS_25 [get_ports AD23A_P] +set_property PACKAGE_PIN AB15 [get_ports AD23A_P] +set_property DIFF_TERM TRUE [get_ports AD33A_N] +set_property IOSTANDARD LVDS_25 [get_ports AD33A_N] +set_property DIFF_TERM TRUE [get_ports AD33A_P] +set_property IOSTANDARD LVDS_25 [get_ports AD33A_P] +set_property PACKAGE_PIN R17 [get_ports AD33A_P] +set_property DIFF_TERM TRUE [get_ports AD43A_N] +set_property IOSTANDARD LVDS_25 [get_ports AD43A_N] +set_property DIFF_TERM TRUE [get_ports AD43A_P] +set_property IOSTANDARD LVDS_25 [get_ports AD43A_P] +set_property PACKAGE_PIN B20 [get_ports AD43A_P] +set_property DIFF_TERM TRUE [get_ports AD13B_N] +set_property IOSTANDARD LVDS [get_ports AD13B_N] +set_property DIFF_TERM TRUE [get_ports AD13B_P] +set_property IOSTANDARD LVDS [get_ports AD13B_P] +set_property PACKAGE_PIN AA9 [get_ports AD13B_P] +set_property DIFF_TERM TRUE [get_ports AD23B_N] +set_property IOSTANDARD LVDS_25 [get_ports AD23B_N] +set_property DIFF_TERM TRUE [get_ports AD23B_P] +set_property IOSTANDARD LVDS_25 [get_ports AD23B_P] +set_property PACKAGE_PIN U17 [get_ports AD23B_P] +set_property DIFF_TERM TRUE [get_ports AD33B_N] +set_property IOSTANDARD LVDS_25 [get_ports AD33B_N] +set_property DIFF_TERM TRUE [get_ports AD33B_P] +set_property IOSTANDARD LVDS_25 [get_ports AD33B_P] +set_property PACKAGE_PIN N22 [get_ports AD33B_P] +set_property DIFF_TERM TRUE [get_ports AD43B_N] +set_property IOSTANDARD LVDS_25 [get_ports AD43B_N] +set_property DIFF_TERM TRUE [get_ports AD43B_P] +set_property IOSTANDARD LVDS_25 [get_ports AD43B_P] +set_property PACKAGE_PIN B17 [get_ports AD43B_P] +set_property DIFF_TERM TRUE [get_ports AD14A_N] +set_property IOSTANDARD LVDS [get_ports AD14A_N] +set_property DIFF_TERM TRUE [get_ports AD14A_P] +set_property IOSTANDARD LVDS [get_ports AD14A_P] +set_property PACKAGE_PIN W6 [get_ports AD14A_P] +set_property DIFF_TERM TRUE [get_ports AD24A_N] +set_property IOSTANDARD LVDS_25 [get_ports AD24A_N] +set_property DIFF_TERM TRUE [get_ports AD24A_P] +set_property IOSTANDARD LVDS_25 [get_ports AD24A_P] +set_property PACKAGE_PIN AA14 [get_ports AD24A_P] +set_property DIFF_TERM TRUE [get_ports AD34A_N] +set_property IOSTANDARD LVDS_25 [get_ports AD34A_N] +set_property DIFF_TERM TRUE [get_ports AD34A_P] +set_property IOSTANDARD LVDS_25 [get_ports AD34A_P] +set_property PACKAGE_PIN P19 [get_ports AD34A_P] +set_property DIFF_TERM TRUE [get_ports AD44A_N] +set_property IOSTANDARD LVDS_25 [get_ports AD44A_N] +set_property DIFF_TERM TRUE [get_ports AD44A_P] +set_property IOSTANDARD LVDS_25 [get_ports AD44A_P] +set_property PACKAGE_PIN D21 [get_ports AD44A_P] +set_property DIFF_TERM TRUE [get_ports AD14B_N] +set_property IOSTANDARD LVDS [get_ports AD14B_N] +set_property DIFF_TERM TRUE [get_ports AD14B_P] +set_property IOSTANDARD LVDS [get_ports AD14B_P] +set_property PACKAGE_PIN U8 [get_ports AD14B_P] +set_property DIFF_TERM TRUE [get_ports AD24B_N] +set_property IOSTANDARD LVDS_25 [get_ports AD24B_N] +set_property DIFF_TERM TRUE [get_ports AD24B_P] +set_property IOSTANDARD LVDS_25 [get_ports AD24B_P] +set_property PACKAGE_PIN AA20 [get_ports AD24B_P] +set_property DIFF_TERM TRUE [get_ports AD34B_N] +set_property IOSTANDARD LVDS_25 [get_ports AD34B_N] +set_property DIFF_TERM TRUE [get_ports AD34B_P] +set_property IOSTANDARD LVDS_25 [get_ports AD34B_P] +set_property PACKAGE_PIN K21 [get_ports AD34B_P] +set_property DIFF_TERM TRUE [get_ports AD44B_N] +set_property IOSTANDARD LVDS_25 [get_ports AD44B_N] +set_property DIFF_TERM TRUE [get_ports AD44B_P] +set_property IOSTANDARD LVDS_25 [get_ports AD44B_P] +set_property PACKAGE_PIN D19 [get_ports AD44B_P] +set_property DIFF_TERM TRUE [get_ports AD15A_N] +set_property IOSTANDARD LVDS [get_ports AD15A_N] +set_property DIFF_TERM TRUE [get_ports AD15A_P] +set_property IOSTANDARD LVDS [get_ports AD15A_P] +set_property PACKAGE_PIN V10 [get_ports AD15A_P] +set_property DIFF_TERM TRUE [get_ports AD25A_N] +set_property IOSTANDARD LVDS_25 [get_ports AD25A_N] +set_property DIFF_TERM TRUE [get_ports AD25A_P] +set_property IOSTANDARD LVDS_25 [get_ports AD25A_P] +set_property PACKAGE_PIN W21 [get_ports AD25A_P] +set_property DIFF_TERM TRUE [get_ports AD35A_N] +set_property IOSTANDARD LVDS_25 [get_ports AD35A_N] +set_property DIFF_TERM TRUE [get_ports AD35A_P] +set_property IOSTANDARD LVDS_25 [get_ports AD35A_P] +set_property PACKAGE_PIN M20 [get_ports AD35A_P] +set_property DIFF_TERM TRUE [get_ports AD45A_N] +set_property IOSTANDARD LVDS_25 [get_ports AD45A_N] +set_property DIFF_TERM TRUE [get_ports AD45A_P] +set_property IOSTANDARD LVDS_25 [get_ports AD45A_P] +set_property PACKAGE_PIN B15 [get_ports AD45A_P] +set_property DIFF_TERM TRUE [get_ports AD15B_N] +set_property IOSTANDARD LVDS [get_ports AD15B_N] +set_property DIFF_TERM TRUE [get_ports AD15B_P] +set_property IOSTANDARD LVDS [get_ports AD15B_P] +set_property PACKAGE_PIN W11 [get_ports AD15B_P] +set_property DIFF_TERM TRUE [get_ports AD25B_N] +set_property IOSTANDARD LVDS_25 [get_ports AD25B_N] +set_property DIFF_TERM TRUE [get_ports AD25B_P] +set_property IOSTANDARD LVDS_25 [get_ports AD25B_P] +set_property PACKAGE_PIN V20 [get_ports AD25B_P] +set_property DIFF_TERM TRUE [get_ports AD35B_N] +set_property IOSTANDARD LVDS_25 [get_ports AD35B_N] +set_property DIFF_TERM TRUE [get_ports AD35B_P] +set_property IOSTANDARD LVDS_25 [get_ports AD35B_P] +set_property PACKAGE_PIN M17 [get_ports AD35B_P] +set_property DIFF_TERM TRUE [get_ports AD45B_N] +set_property IOSTANDARD LVDS_25 [get_ports AD45B_N] +set_property DIFF_TERM TRUE [get_ports AD45B_P] +set_property IOSTANDARD LVDS_25 [get_ports AD45B_P] +set_property PACKAGE_PIN C14 [get_ports AD45B_P] +set_property DIFF_TERM TRUE [get_ports AD16A_N] +set_property IOSTANDARD LVDS [get_ports AD16A_N] +set_property DIFF_TERM TRUE [get_ports AD16A_P] +set_property IOSTANDARD LVDS [get_ports AD16A_P] +set_property PACKAGE_PIN AA11 [get_ports AD16A_P] +set_property DIFF_TERM TRUE [get_ports AD26A_N] +set_property IOSTANDARD LVDS_25 [get_ports AD26A_N] +set_property DIFF_TERM TRUE [get_ports AD26A_P] +set_property IOSTANDARD LVDS_25 [get_ports AD26A_P] +set_property PACKAGE_PIN Y21 [get_ports AD26A_P] +set_property DIFF_TERM TRUE [get_ports AD36A_N] +set_property IOSTANDARD LVDS_25 [get_ports AD36A_N] +set_property DIFF_TERM TRUE [get_ports AD36A_P] +set_property IOSTANDARD LVDS_25 [get_ports AD36A_P] +set_property PACKAGE_PIN H22 [get_ports AD36A_P] +set_property DIFF_TERM TRUE [get_ports AD46A_N] +set_property IOSTANDARD LVDS_25 [get_ports AD46A_N] +set_property DIFF_TERM TRUE [get_ports AD46A_P] +set_property IOSTANDARD LVDS_25 [get_ports AD46A_P] +set_property PACKAGE_PIN D15 [get_ports AD46A_P] +set_property DIFF_TERM TRUE [get_ports AD16B_N] +set_property IOSTANDARD LVDS [get_ports AD16B_N] +set_property DIFF_TERM TRUE [get_ports AD16B_P] +set_property IOSTANDARD LVDS [get_ports AD16B_P] +set_property PACKAGE_PIN AB13 [get_ports AD16B_P] +set_property DIFF_TERM TRUE [get_ports AD26B_N] +set_property IOSTANDARD LVDS_25 [get_ports AD26B_N] +set_property DIFF_TERM TRUE [get_ports AD26B_P] +set_property IOSTANDARD LVDS_25 [get_ports AD26B_P] +set_property PACKAGE_PIN U16 [get_ports AD26B_P] +set_property DIFF_TERM TRUE [get_ports AD36B_N] +set_property IOSTANDARD LVDS_25 [get_ports AD36B_N] +set_property DIFF_TERM TRUE [get_ports AD36B_P] +set_property IOSTANDARD LVDS_25 [get_ports AD36B_P] +set_property PACKAGE_PIN J20 [get_ports AD36B_P] +set_property DIFF_TERM TRUE [get_ports AD46B_N] +set_property IOSTANDARD LVDS_25 [get_ports AD46B_N] +set_property DIFF_TERM TRUE [get_ports AD46B_P] +set_property IOSTANDARD LVDS_25 [get_ports AD46B_P] +set_property PACKAGE_PIN F15 [get_ports AD46B_P] +set_property DIFF_TERM TRUE [get_ports AD17A_N] +set_property IOSTANDARD LVDS [get_ports AD17A_N] +set_property DIFF_TERM TRUE [get_ports AD17A_P] +set_property IOSTANDARD LVDS [get_ports AD17A_P] +set_property PACKAGE_PIN V13 [get_ports AD17A_P] +set_property DIFF_TERM TRUE [get_ports AD27A_N] +set_property IOSTANDARD LVDS_25 [get_ports AD27A_N] +set_property DIFF_TERM TRUE [get_ports AD27A_P] +set_property IOSTANDARD LVDS_25 [get_ports AD27A_P] +set_property PACKAGE_PIN T21 [get_ports AD27A_P] +set_property DIFF_TERM TRUE [get_ports AD37A_N] +set_property IOSTANDARD LVDS_25 [get_ports AD37A_N] +set_property DIFF_TERM TRUE [get_ports AD37A_P] +set_property IOSTANDARD LVDS_25 [get_ports AD37A_P] +set_property PACKAGE_PIN G20 [get_ports AD37A_P] +set_property DIFF_TERM TRUE [get_ports AD47A_N] +set_property IOSTANDARD LVDS_25 [get_ports AD47A_N] +set_property DIFF_TERM TRUE [get_ports AD47A_P] +set_property IOSTANDARD LVDS_25 [get_ports AD47A_P] +set_property PACKAGE_PIN C13 [get_ports AD47A_P] +set_property DIFF_TERM TRUE [get_ports AD17B_N] +set_property IOSTANDARD LVDS [get_ports AD17B_N] +set_property DIFF_TERM TRUE [get_ports AD17B_P] +set_property IOSTANDARD LVDS [get_ports AD17B_P] +set_property PACKAGE_PIN T13 [get_ports AD17B_P] +set_property DIFF_TERM TRUE [get_ports AD27B_N] +set_property IOSTANDARD LVDS_25 [get_ports AD27B_N] +set_property DIFF_TERM TRUE [get_ports AD27B_P] +set_property IOSTANDARD LVDS_25 [get_ports AD27B_P] +set_property PACKAGE_PIN T18 [get_ports AD27B_P] +set_property DIFF_TERM TRUE [get_ports AD37B_N] +set_property IOSTANDARD LVDS_25 [get_ports AD37B_N] +set_property DIFF_TERM TRUE [get_ports AD37B_P] +set_property IOSTANDARD LVDS_25 [get_ports AD37B_P] +set_property PACKAGE_PIN G21 [get_ports AD37B_P] +set_property DIFF_TERM TRUE [get_ports AD47B_N] +set_property IOSTANDARD LVDS_25 [get_ports AD47B_N] +set_property DIFF_TERM TRUE [get_ports AD47B_P] +set_property IOSTANDARD LVDS_25 [get_ports AD47B_P] +set_property PACKAGE_PIN C12 [get_ports AD47B_P] +set_property DIFF_TERM TRUE [get_ports AD18A_N] +set_property IOSTANDARD LVDS [get_ports AD18A_N] +set_property DIFF_TERM TRUE [get_ports AD18A_P] +set_property IOSTANDARD LVDS [get_ports AD18A_P] +set_property PACKAGE_PIN W12 [get_ports AD18A_P] +set_property DIFF_TERM TRUE [get_ports AD28A_N] +set_property IOSTANDARD LVDS_25 [get_ports AD28A_N] +set_property DIFF_TERM TRUE [get_ports AD28A_P] +set_property IOSTANDARD LVDS_25 [get_ports AD28A_P] +set_property PACKAGE_PIN U22 [get_ports AD28A_P] +set_property DIFF_TERM TRUE [get_ports AD38A_N] +set_property IOSTANDARD LVDS_25 [get_ports AD38A_N] +set_property DIFF_TERM TRUE [get_ports AD38A_P] +set_property IOSTANDARD LVDS_25 [get_ports AD38A_P] +set_property PACKAGE_PIN L18 [get_ports AD38A_P] +set_property DIFF_TERM TRUE [get_ports AD48A_N] +set_property IOSTANDARD LVDS_25 [get_ports AD48A_N] +set_property DIFF_TERM TRUE [get_ports AD48A_P] +set_property IOSTANDARD LVDS_25 [get_ports AD48A_P] +set_property PACKAGE_PIN A13 [get_ports AD48A_P] +set_property DIFF_TERM TRUE [get_ports AD18B_N] +set_property IOSTANDARD LVDS [get_ports AD18B_N] +set_property DIFF_TERM TRUE [get_ports AD18B_P] +set_property IOSTANDARD LVDS [get_ports AD18B_P] +set_property PACKAGE_PIN Y13 [get_ports AD18B_P] +set_property DIFF_TERM TRUE [get_ports AD28B_N] +set_property IOSTANDARD LVDS_25 [get_ports AD28B_N] +set_property DIFF_TERM TRUE [get_ports AD28B_P] +set_property IOSTANDARD LVDS_25 [get_ports AD28B_P] +set_property PACKAGE_PIN T20 [get_ports AD28B_P] +set_property DIFF_TERM TRUE [get_ports AD38B_N] +set_property IOSTANDARD LVDS_25 [get_ports AD38B_N] +set_property DIFF_TERM TRUE [get_ports AD38B_P] +set_property IOSTANDARD LVDS_25 [get_ports AD38B_P] +set_property PACKAGE_PIN E21 [get_ports AD38B_P] +set_property DIFF_TERM TRUE [get_ports AD48B_N] +set_property IOSTANDARD LVDS_25 [get_ports AD48B_N] +set_property DIFF_TERM TRUE [get_ports AD48B_P] +set_property IOSTANDARD LVDS_25 [get_ports AD48B_P] +set_property PACKAGE_PIN E14 [get_ports AD48B_P] +set_property DIFF_TERM TRUE [get_ports DCOA1_N] +set_property IOSTANDARD LVDS [get_ports DCOA1_N] +set_property DIFF_TERM TRUE [get_ports DCOA1_P] +set_property IOSTANDARD LVDS [get_ports DCOA1_P] +set_property LOC ILOGIC_X1Y74 [get_cells FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_Master] +set_property LOC BUFIO_X1Y5 [get_cells FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcClock/AdcClock_I_Bufio] +set_property LOC IDELAY_X1Y74 [get_cells FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcClock/AdcClock_I_Iodly] +set_property PACKAGE_PIN W9 [get_ports DCOA1_P] +set_property DIFF_TERM TRUE [get_ports DCOB1_N] +set_property IOSTANDARD LVDS [get_ports DCOB1_N] +set_property DIFF_TERM TRUE [get_ports DCOB1_P] +set_property IOSTANDARD LVDS [get_ports DCOB1_P] +set_property LOC ILOGIC_X1Y76 [get_cells FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_Master] +set_property LOC BUFIO_X1Y6 [get_cells FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcClock/AdcClock_I_Bufio] +set_property LOC IDELAY_X1Y76 [get_cells FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcClock/AdcClock_I_Iodly] +set_property PACKAGE_PIN Y8 [get_ports DCOB1_P] +set_property DIFF_TERM TRUE [get_ports FRA1_N] +set_property IOSTANDARD LVDS [get_ports FRA1_N] +set_property DIFF_TERM TRUE [get_ports FRA1_P] +set_property IOSTANDARD LVDS [get_ports FRA1_P] +set_property PACKAGE_PIN U10 [get_ports FRA1_P] +set_property DIFF_TERM TRUE [get_ports FRB1_N] +set_property IOSTANDARD LVDS [get_ports FRB1_N] +set_property DIFF_TERM TRUE [get_ports FRB1_P] +set_property IOSTANDARD LVDS [get_ports FRB1_P] +set_property PACKAGE_PIN AA10 [get_ports FRB1_P] +set_property DIFF_TERM TRUE [get_ports DCOA2_N] +set_property IOSTANDARD LVDS_25 [get_ports DCOA2_N] +set_property DIFF_TERM TRUE [get_ports DCOA2_P] +set_property IOSTANDARD LVDS_25 [get_ports DCOA2_P] +set_property LOC ILOGIC_X0Y76 [get_cells FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_Master] +set_property LOC BUFIO_X0Y6 [get_cells FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcClock/AdcClock_I_Bufio] +set_property LOC IDELAY_X0Y76 [get_cells FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcClock/AdcClock_I_Iodly] +set_property PACKAGE_PIN V19 [get_ports DCOA2_P] +set_property DIFF_TERM TRUE [get_ports DCOB2_N] +set_property IOSTANDARD LVDS_25 [get_ports DCOB2_N] +set_property DIFF_TERM TRUE [get_ports DCOB2_P] +set_property IOSTANDARD LVDS_25 [get_ports DCOB2_P] +set_property LOC ILOGIC_X0Y74 [get_cells FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_Master] +set_property LOC BUFIO_X0Y5 [get_cells FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcClock/AdcClock_I_Bufio] +set_property LOC IDELAY_X0Y74 [get_cells FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcClock/AdcClock_I_Iodly] +set_property PACKAGE_PIN Y18 [get_ports DCOB2_P] +set_property DIFF_TERM TRUE [get_ports FRA2_N] +set_property IOSTANDARD LVDS_25 [get_ports FRA2_N] +set_property DIFF_TERM TRUE [get_ports FRA2_P] +set_property IOSTANDARD LVDS_25 [get_ports FRA2_P] +set_property PACKAGE_PIN AA18 [get_ports FRA2_P] +set_property DIFF_TERM TRUE [get_ports FRB2_N] +set_property IOSTANDARD LVDS_25 [get_ports FRB2_N] +set_property DIFF_TERM TRUE [get_ports FRB2_P] +set_property IOSTANDARD LVDS_25 [get_ports FRB2_P] +set_property PACKAGE_PIN AA19 [get_ports FRB2_P] +set_property DIFF_TERM TRUE [get_ports DCOA3_N] +set_property IOSTANDARD LVDS_25 [get_ports DCOA3_N] +set_property DIFF_TERM TRUE [get_ports DCOA3_P] +set_property IOSTANDARD LVDS_25 [get_ports DCOA3_P] +set_property LOC ILOGIC_X0Y126 [get_cells FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_Master] +set_property LOC BUFIO_X0Y10 [get_cells FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcClock/AdcClock_I_Bufio] +set_property LOC IDELAY_X0Y126 [get_cells FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcClock/AdcClock_I_Iodly] +set_property PACKAGE_PIN L19 [get_ports DCOA3_P] +set_property DIFF_TERM TRUE [get_ports DCOB3_N] +set_property IOSTANDARD LVDS_25 [get_ports DCOB3_N] +set_property DIFF_TERM TRUE [get_ports DCOB3_P] +set_property IOSTANDARD LVDS_25 [get_ports DCOB3_P] +set_property LOC ILOGIC_X0Y124 [get_cells FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_Master] +set_property LOC BUFIO_X0Y9 [get_cells FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcClock/AdcClock_I_Bufio] +set_property LOC IDELAY_X0Y124 [get_cells FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcClock/AdcClock_I_Iodly] +set_property PACKAGE_PIN N18 [get_ports DCOB3_P] +set_property DIFF_TERM TRUE [get_ports FRA3_N] +set_property IOSTANDARD LVDS_25 [get_ports FRA3_N] +set_property DIFF_TERM TRUE [get_ports FRA3_P] +set_property IOSTANDARD LVDS_25 [get_ports FRA3_P] +set_property PACKAGE_PIN N20 [get_ports FRA3_P] +set_property DIFF_TERM TRUE [get_ports FRB3_N] +set_property IOSTANDARD LVDS_25 [get_ports FRB3_N] +set_property DIFF_TERM TRUE [get_ports FRB3_P] +set_property IOSTANDARD LVDS_25 [get_ports FRB3_P] +set_property PACKAGE_PIN J21 [get_ports FRB3_P] +set_property DIFF_TERM TRUE [get_ports DCOA4_N] +set_property IOSTANDARD LVDS_25 [get_ports DCOA4_N] +set_property DIFF_TERM TRUE [get_ports DCOA4_P] +set_property IOSTANDARD LVDS_25 [get_ports DCOA4_P] +set_property LOC ILOGIC_X0Y176 [get_cells FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_Master] +set_property LOC BUFIO_X0Y14 [get_cells FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcClock/AdcClock_I_Bufio] +set_property LOC IDELAY_X0Y176 [get_cells FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcClock/AdcClock_I_Iodly] +set_property PACKAGE_PIN C17 [get_ports DCOA4_P] +set_property DIFF_TERM TRUE [get_ports DCOB4_N] +set_property IOSTANDARD LVDS_25 [get_ports DCOB4_N] +set_property DIFF_TERM TRUE [get_ports DCOB4_P] +set_property IOSTANDARD LVDS_25 [get_ports DCOB4_P] +set_property LOC ILOGIC_X0Y174 [get_cells FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_Master] +set_property LOC BUFIO_X0Y13 [get_cells FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcClock/AdcClock_I_Bufio] +set_property LOC IDELAY_X0Y174 [get_cells FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcClock/AdcClock_I_Iodly] +set_property PACKAGE_PIN E17 [get_ports DCOB4_P] +set_property DIFF_TERM TRUE [get_ports FRA4_N] +set_property IOSTANDARD LVDS_25 [get_ports FRA4_N] +set_property DIFF_TERM TRUE [get_ports FRA4_P] +set_property IOSTANDARD LVDS_25 [get_ports FRA4_P] +set_property PACKAGE_PIN B16 [get_ports FRA4_P] +set_property DIFF_TERM TRUE [get_ports FRB4_N] +set_property IOSTANDARD LVDS_25 [get_ports FRB4_N] +set_property DIFF_TERM TRUE [get_ports FRB4_P] +set_property IOSTANDARD LVDS_25 [get_ports FRB4_P] +set_property PACKAGE_PIN E16 [get_ports FRB4_P] + +set_property PACKAGE_PIN W15 [get_ports {CSA[1]}] +set_property IOSTANDARD LVCMOS25 [get_ports {CSA[1]}] +set_property PACKAGE_PIN V15 [get_ports {CSB[1]}] +set_property IOSTANDARD LVCMOS25 [get_ports {CSB[1]}] +set_property PACKAGE_PIN U12 [get_ports SCK] +set_property IOSTANDARD LVCMOS18 [get_ports SCK] +set_property PACKAGE_PIN U11 [get_ports SDI] +set_property IOSTANDARD LVCMOS18 [get_ports SDI] +set_property PACKAGE_PIN W14 [get_ports {SDOA[1]}] +set_property IOSTANDARD LVCMOS25 [get_ports {SDOA[1]}] +set_property PACKAGE_PIN Y14 [get_ports {SDOB[1]}] +set_property IOSTANDARD LVCMOS25 [get_ports {SDOB[1]}] +set_property PACKAGE_PIN T16 [get_ports {CSA[2]}] +set_property IOSTANDARD LVCMOS25 [get_ports {CSA[2]}] +set_property PACKAGE_PIN R16 [get_ports {CSB[2]}] +set_property IOSTANDARD LVCMOS25 [get_ports {CSB[2]}] +set_property PACKAGE_PIN T15 [get_ports {SDOA[2]}] +set_property IOSTANDARD LVCMOS25 [get_ports {SDOA[2]}] +set_property PACKAGE_PIN U15 [get_ports {SDOB[2]}] +set_property IOSTANDARD LVCMOS25 [get_ports {SDOB[2]}] +set_property PACKAGE_PIN H17 [get_ports {CSA[3]}] +set_property IOSTANDARD LVCMOS25 [get_ports {CSA[3]}] +set_property PACKAGE_PIN G17 [get_ports {CSB[3]}] +set_property IOSTANDARD LVCMOS25 [get_ports {CSB[3]}] +set_property PACKAGE_PIN J16 [get_ports {SDOA[3]}] +set_property IOSTANDARD LVCMOS25 [get_ports {SDOA[3]}] +set_property PACKAGE_PIN J17 [get_ports {SDOB[3]}] +set_property IOSTANDARD LVCMOS25 [get_ports {SDOB[3]}] +set_property PACKAGE_PIN F18 [get_ports {CSA[4]}] +set_property IOSTANDARD LVCMOS25 [get_ports {CSA[4]}] +set_property PACKAGE_PIN E19 [get_ports {CSB[4]}] +set_property IOSTANDARD LVCMOS25 [get_ports {CSB[4]}] +set_property PACKAGE_PIN G15 [get_ports {SDOA[4]}] +set_property IOSTANDARD LVCMOS25 [get_ports {SDOA[4]}] +set_property PACKAGE_PIN G16 [get_ports {SDOB[4]}] +set_property IOSTANDARD LVCMOS25 [get_ports {SDOB[4]}] + +set_property PACKAGE_PIN K17 [get_ports GEO] +set_property IOSTANDARD LVCMOS25 [get_ports GEO] +set_property SLEW SLOW [get_ports GEO] +set_property PULLUP true [get_ports GEO] + +#Bank 16 = 2.5V +set_property PACKAGE_PIN H12 [get_ports SYS_CLK] +set_property IOSTANDARD LVCMOS25 [get_ports SYS_CLK] + +set_property PACKAGE_PIN D11 [get_ports INTCOMC1_N] +set_property PACKAGE_PIN E11 [get_ports INTCOMC1_P] +set_property PACKAGE_PIN G10 [get_ports INTCOMC2_N] +set_property PACKAGE_PIN G11 [get_ports INTCOMC2_P] +set_property PACKAGE_PIN E9 [get_ports INTCOM0_N] +set_property PACKAGE_PIN F9 [get_ports INTCOM0_P] +set_property PACKAGE_PIN H8 [get_ports INTCOM1_N] +set_property PACKAGE_PIN H9 [get_ports INTCOM1_P] +set_property PACKAGE_PIN F8 [get_ports INTCOM2_N] +set_property PACKAGE_PIN G8 [get_ports INTCOM2_P] +set_property PACKAGE_PIN C9 [get_ports INTCOM3_N] +set_property PACKAGE_PIN D9 [get_ports INTCOM3_P] +set_property PACKAGE_PIN B10 [get_ports INTCOM4_N] +set_property PACKAGE_PIN B11 [get_ports INTCOM4_P] +set_property PACKAGE_PIN A8 [get_ports INTCOM5_N] +set_property PACKAGE_PIN A9 [get_ports INTCOM5_P] +set_property PACKAGE_PIN B8 [get_ports INTCOM6_N] +set_property PACKAGE_PIN C8 [get_ports INTCOM6_P] +set_property PACKAGE_PIN A10 [get_ports INTCOM7_N] +set_property PACKAGE_PIN A11 [get_ports INTCOM7_P] + +set_property IOSTANDARD LVCMOS25 [get_ports INTCOMC1_N] +set_property IOSTANDARD LVCMOS25 [get_ports INTCOMC1_P] +set_property IOSTANDARD LVCMOS25 [get_ports INTCOMC2_N] +set_property IOSTANDARD LVCMOS25 [get_ports INTCOMC2_P] +set_property IOSTANDARD LVCMOS25 [get_ports INTCOM0_N] +set_property IOSTANDARD LVCMOS25 [get_ports INTCOM0_P] +set_property IOSTANDARD LVCMOS25 [get_ports INTCOM1_N] +set_property IOSTANDARD LVCMOS25 [get_ports INTCOM1_P] +set_property IOSTANDARD LVCMOS25 [get_ports INTCOM2_N] +set_property IOSTANDARD LVCMOS25 [get_ports INTCOM2_P] +set_property IOSTANDARD LVCMOS25 [get_ports INTCOM3_N] +set_property IOSTANDARD LVCMOS25 [get_ports INTCOM3_P] +set_property IOSTANDARD LVCMOS25 [get_ports INTCOM4_N] +set_property IOSTANDARD LVCMOS25 [get_ports INTCOM4_P] +set_property IOSTANDARD LVCMOS25 [get_ports INTCOM5_N] +set_property IOSTANDARD LVCMOS25 [get_ports INTCOM5_P] +set_property IOSTANDARD LVCMOS25 [get_ports INTCOM6_N] +set_property IOSTANDARD LVCMOS25 [get_ports INTCOM6_P] +set_property IOSTANDARD LVCMOS25 [get_ports INTCOM7_N] +set_property IOSTANDARD LVCMOS25 [get_ports INTCOM7_P] + +set_property PACKAGE_PIN F10 [get_ports RCV_CLK_N] +set_property DIFF_TERM TRUE [get_ports RCV_CLK_N] +set_property IOSTANDARD LVDS_25 [get_ports RCV_CLK_N] +set_property PACKAGE_PIN F11 [get_ports RCV_CLK_P] +set_property DIFF_TERM TRUE [get_ports RCV_CLK_P] +set_property IOSTANDARD LVDS_25 [get_ports RCV_CLK_P] + +set_property PACKAGE_PIN E12 [get_ports S_CTRL] +set_property IOSTANDARD LVCMOS25 [get_ports S_CTRL] +set_property PACKAGE_PIN E13 [get_ports T_CTRL] +set_property IOSTANDARD LVCMOS25 [get_ports T_CTRL] + +#bank 34: 3.3V +set_property PACKAGE_PIN W5 [get_ports SYNC] +set_property IOSTANDARD LVCMOS18 [get_ports SYNC] +set_property PACKAGE_PIN AA4 [get_ports CLKu] +set_property IOSTANDARD LVCMOS18 [get_ports CLKu] +set_property PACKAGE_PIN AA3 [get_ports DATAu] +set_property IOSTANDARD LVCMOS18 [get_ports DATAu] +set_property PACKAGE_PIN Y4 [get_ports LEu] +set_property IOSTANDARD LVCMOS18 [get_ports LEu] +set_property PACKAGE_PIN AB3 [get_ports RDu] +set_property IOSTANDARD LVCMOS18 [get_ports RDu] +#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets RDu] + +set_property IOSTANDARD LVCMOS18 [get_ports ST_CLK_N] +set_property PACKAGE_PIN T4 [get_ports ST_CLK_P] +set_property PACKAGE_PIN U3 [get_ports ST_CLK_N] +set_property IOSTANDARD LVCMOS18 [get_ports ST_CLK_P] +#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets ST_CLK_N] + +set_property PACKAGE_PIN R3 [get_ports GCLK_P] +set_property PACKAGE_PIN T3 [get_ports GCLK_N] +set_property IOSTANDARD LVDS [get_ports GCLK_P] +set_property IOSTANDARD LVDS [get_ports GCLK_N] +#//set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets GCLK_N] + +set_property PACKAGE_PIN D6 [get_ports MGTREFCLK_P] +set_property PACKAGE_PIN D5 [get_ports MGTREFCLK_N] + +set_property PACKAGE_PIN G3 [get_ports RX_N] +set_property PACKAGE_PIN G4 [get_ports RX_P] +set_property PACKAGE_PIN F1 [get_ports TX_N] +set_property PACKAGE_PIN F2 [get_ports TX_P] +set_property PACKAGE_PIN K1 [get_ports LOS] +set_property IOSTANDARD LVCMOS18 [get_ports LOS] +set_property PACKAGE_PIN L1 [get_ports TX_DIS] +set_property IOSTANDARD LVCMOS18 [get_ports TX_DIS] + +set_property PACKAGE_PIN M2 [get_ports {MOD_DEF[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {MOD_DEF[0]}] +set_property PACKAGE_PIN M1 [get_ports {MOD_DEF[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {MOD_DEF[1]}] +set_property PACKAGE_PIN K3 [get_ports {MOD_DEF[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {MOD_DEF[2]}] + +set_property PACKAGE_PIN T10 [get_ports TEMP_OUT] +set_property IOSTANDARD LVCMOS18 [get_ports TEMP_OUT] +set_property PACKAGE_PIN T11 [get_ports TEMP_IN] +set_property IOSTANDARD LVCMOS18 [get_ports TEMP_IN] + +set_property PACKAGE_PIN Y1 [get_ports MON1_N] +set_property IOSTANDARD LVCMOS18 [get_ports MON1_N] +#set_property IOSTANDARD LVDS [get_ports MON1_N] +set_property PACKAGE_PIN W1 [get_ports MON1_P] +#set_property IOSTANDARD LVCMOS18 [get_ports MON1_P] +set_property IOSTANDARD LVDS [get_ports MON1_P] + +set_property PACKAGE_PIN Y2 [get_ports MON2_N] +#set_property IOSTANDARD LVCMOS18 [get_ports MON2_N] +set_property IOSTANDARD LVDS [get_ports MON2_N] +set_property PACKAGE_PIN Y3 [get_ports MON2_P] +#set_property IOSTANDARD LVCMOS18 [get_ports MON2_P] +set_property IOSTANDARD LVDS [get_ports MON2_P] + +set_property PACKAGE_PIN G13 [get_ports JTAG_OUT1_TCK_F] +set_property IOSTANDARD LVCMOS25 [get_ports JTAG_OUT1_TCK_F] +set_property PACKAGE_PIN H14 [get_ports JTAG_OUT1_TDI_F] +set_property IOSTANDARD LVCMOS25 [get_ports JTAG_OUT1_TDI_F] +set_property PACKAGE_PIN H13 [get_ports JTAG_OUT1_TDO_F] +set_property IOSTANDARD LVCMOS25 [get_ports JTAG_OUT1_TDO_F] +set_property PACKAGE_PIN F13 [get_ports JTAG_OUT1_TMS_F] +set_property IOSTANDARD LVCMOS25 [get_ports JTAG_OUT1_TMS_F] + +set_property PACKAGE_PIN D1 [get_ports GT_A2B_0_N] +set_property PACKAGE_PIN D2 [get_ports GT_A2B_0_P] +set_property PACKAGE_PIN B1 [get_ports GT_A2B_1_N] +set_property PACKAGE_PIN B2 [get_ports GT_A2B_1_P] +set_property PACKAGE_PIN E3 [get_ports GT_B2A_0_N] +set_property PACKAGE_PIN E4 [get_ports GT_B2A_0_P] +set_property PACKAGE_PIN C3 [get_ports GT_B2A_1_N] +set_property PACKAGE_PIN C4 [get_ports GT_B2A_1_P] + +#NET "DONE_P1" LOC = P6; +#NET "CF_D0_I1" LOC = H18; +#NET "CF_D1_I1" LOC = H19; +#NET "CF_D2_I1" LOC = G18; +#NET "CF_D3_I1" LOC = F19; +#NET "CF_EMCL_I1" LOC = H12; +#NET "CF_EMCL_I1" LOC = J19; +#NET "CF_FCS_I1" LOC = L16; +#NET "CF_PUDC_I1" LOC = K18; +#NET "CCLK1_P1" LOC = G7; +#NET "JTAG_IN1_TCK" LOC = K7; +#NET "JTAG_IN1_TDI" LOC = K6; +#NET "JTAG_IN1_TDO" LOC = J6; +#NET "JTAG_IN1_TMS" LOC = L6; + + +########################################################################################## +# done inside clockmodule100Mto80M # create_clock -period 10.000 -name SYS_CLK [get_ports SYS_CLK] +create_clock -period 6.430 -name ST_CLK_N [get_ports ST_CLK_N] + + + + + +create_pblock pblock_adc_1 +add_cells_to_pblock [get_pblocks pblock_adc_1] [get_cells {FEE_ADCinput_module1/AdcToplevel2356_1/* FEE_ADCinput_module1/AdcToplevel1458_1/*}] +add_cells_to_pblock [get_pblocks pblock_adc_1] [get_cells {FEE_ADCinput_module1/AdcToplevel1458_1 FEE_ADCinput_module1/AdcToplevel2356_1}] +resize_pblock [get_pblocks pblock_adc_1] -add {SLICE_X106Y50:SLICE_X109Y99} +#add_cells_to_pblock [get_pblocks pblock_adc_1] [get_cells -quiet [list FEE_ADCinput_module1/AdcToplevel2356_1 FEE_ADCinput_module1/AdcToplevel1458_1]] +create_pblock pblock_adc_2 +add_cells_to_pblock [get_pblocks pblock_adc_2] [get_cells {FEE_ADCinput_module1/AdcToplevel1458_2/* FEE_ADCinput_module1/AdcToplevel2356_2/*}] +add_cells_to_pblock [get_pblocks pblock_adc_2] [get_cells {FEE_ADCinput_module1/AdcToplevel1458_2 FEE_ADCinput_module1/AdcToplevel2356_2}] +resize_pblock [get_pblocks pblock_adc_2] -add {SLICE_X0Y50:SLICE_X3Y99} +#add_cells_to_pblock [get_pblocks pblock_adc_2] [get_cells -quiet [list FEE_ADCinput_module1/AdcToplevel1458_2 FEE_ADCinput_module1/AdcToplevel2356_2]] +create_pblock pblock_adc_3 +add_cells_to_pblock [get_pblocks pblock_adc_3] [get_cells {FEE_ADCinput_module1/AdcToplevel1458_3/* FEE_ADCinput_module1/AdcToplevel2356_3/*}] +add_cells_to_pblock [get_pblocks pblock_adc_3] [get_cells {FEE_ADCinput_module1/AdcToplevel1458_3 FEE_ADCinput_module1/AdcToplevel2356_3}] +resize_pblock [get_pblocks pblock_adc_3] -add {SLICE_X0Y100:SLICE_X3Y149} +#add_cells_to_pblock [get_pblocks pblock_adc_3] [get_cells -quiet [list FEE_ADCinput_module1/AdcToplevel1458_3 FEE_ADCinput_module1/AdcToplevel2356_3]] +create_pblock pblock_adc_4 +add_cells_to_pblock [get_pblocks pblock_adc_4] [get_cells {FEE_ADCinput_module1/AdcToplevel2356_4/* FEE_ADCinput_module1/AdcToplevel1458_4/*}] +add_cells_to_pblock [get_pblocks pblock_adc_4] [get_cells {FEE_ADCinput_module1/AdcToplevel1458_4 FEE_ADCinput_module1/AdcToplevel2356_4}] +resize_pblock [get_pblocks pblock_adc_4] -add {SLICE_X0Y151:SLICE_X3Y199} +#add_cells_to_pblock [get_pblocks pblock_adc_4] [get_cells -quiet [list FEE_ADCinput_module1/AdcToplevel2356_4 FEE_ADCinput_module1/AdcToplevel1458_4]] + +############################################################################################# +# Timing constraints +############################################################################################# +# The DCLK input clock, bit clock from the ADC, doesn't need a timespec. +# This clock passes from the IOB through the BUFIO and to the .CLK input of all used ISERDES. +# This path is made from dedicated routing. +# From the IOB to theBUFIO.I is a dedicated connection only availabel with Clock Capable_IO. +# This connection takes for all IO-banks in a FPGA and from all FPGAs of the familly an +# average value of 220 ps. +# The connection from the BUFIO.O to all ISERDES.CLK is also a dedicated connection, it +# takes on average 330 ps. +# The BUFIO average delay is: 869 ps and an LVDS IOB is average: 1094 ps. +# A MAXSKEW constraint is used to detect the skew on the CLK net. + +# +# The connection from the BUFR.O to the ISERDES.CLKDIV inputs runs over normal clock nets. +# Oposite to the BUFIO.O - ISERDES.CLK routing, the BUFR.O net not only connects to the +# ISERDES.CLKDIV pins of the I/O SERDES in the IO-bank the BUFR is located in but to all +# clocked elements (FFs, BRAM, DSP, ..) in that clock area. +# It also connects to the adjacent upper and lower clock areas. +# Therefore it is necessary to put timing constraints on this clock. +# A MAXSKEW constraint to keep the skew as low as possible. makes sure the ISERDES are clocked +# at the same time so that early-late data cannot appear at the outputs of the ISERDES. + + +set_false_path -through [get_nets GEO] +set_false_path -through [get_ports GEO] +set_false_path -from [get_ports GEO] +set_false_path -from [get_ports S_CTRL] +set_false_path -to [get_ports T_CTRL] + +create_clock -period 12.500 -name ADC_clk_S [get_pins FEE_ADCinput_module1/ADCclkbuf/O] + +#//create_generated_clock -name clock40MHz_S [get_pins clockmodule100Mto80Ma/inst/mmcm_adv_inst/CLKOUT0] +create_generated_clock -name clock40MHz_S [get_pins clockmodule100Mto80Ma/inst/mmcm_adv_inst/CLKOUT0] +create_generated_clock -name clock_S [get_pins clockmodule100Mto80Ma/inst/mmcm_adv_inst/CLKOUT1] +#//create_generated_clock -name clock100MHz_S [get_pins clockmodule100Mto80Ma/inst/mmcm_adv_inst/CLKOUT2] +create_generated_clock -name clock200MHz_S [get_pins clockmodule100Mto80Ma/inst/mmcm_adv_inst/CLKOUT3] +create_generated_clock -name async_clock_S [get_pins clockmodule100Mto80Ma/inst/mmcm_adv_inst/CLKOUT4] +#create_generated_clock -name rxSodaClk80_S [get_pins clockmodule40Mto80M1/inst/mmcm_adv_inst/CLKOUT1] +#create_generated_clock -name rxSodaClk40_S [get_pins FEE_gtxModule1/FEE_SODAfrequencydiv51/clockdiv5buf/O] +#create_generated_clock -name rxSodaClk_S [get_pins FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/FEE_data16to8_1/clock100to200_1/inst/mmcm_adv_inst/CLKOUT1] +#create_generated_clock -name RXOUTCLK [get_pins FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/gtx_i/gtxKintex7FEE80_init_i/U0/gtxKintex7FEE80_i/gt0_gtxKintex7FEE80_i/gtxe2_i/RXOUTCLK] + +create_clock -name aurora_clock -period 10.000 [get_pins gen_combine.aurora_dual_module1/aurora_module_i/clock_module_i/user_clk_buf_i/I] +#create_generated_clock -name aurora_clock [get_pins gen_combine.aurora_dual_module1/aurora_module_i/aurora_dual_i/U0/gt_wrapper_i/aurora_dual_multi_gt_i/gt0_aurora_dual_i/gtxe2_i/TXOUTCLK + +set_false_path -to [get_cells -hierarchical -filter {NAME =~ *data_sync_reg1}] + + + +################################# GTX ##################### +#NET "MGTREFCLK_P" TNM_NET = "MGTREFCLK_P"; +#TIMESPEC TS_MGTREFCLK_P = PERIOD "MGTREFCLK_P" 8 ns HIGH 50 %; +#NET "MGTREFCLK_N" TNM_NET = "MGTREFCLK_N"; +#TIMESPEC TS_MGTREFCLK_N = PERIOD "MGTREFCLK_N" 8 ns HIGH 50 %; +create_clock -period 12.500 -name GCLK_P [get_ports GCLK_P] +#create_clock -period 12.500 -name GCLK_N [get_ports GCLK_N] +create_clock -period 12.500 [get_ports MGTREFCLK_P] +#set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/CLR}] +#set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/D}] +#set_false_path -to [get_pins -hierarchical -filter {NAME =~ *reset_on_error_in_r*/D}] +##---------- Set placement for gt0_gtx_wrapper_i/GTXE2_CHANNEL ------ +#set_property LOC GTXE2_CHANNEL_X0Y0 [get_cells gtxKintex7FEE80_support_i/gtxKintex7FEE80_init_i/inst/gtxKintex7FEE80_i/gt0_gtxKintex7FEE80_i/gtxe2_i] + +#create_generated_clock -name rxSodaClk [get_pins FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/FEE_data16to8_1/clock100to200_1/inst/mmcm_adv_inst/CLKOUT1] +create_clock -period 5.0 -name rxSodaClk [get_pins FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/FEE_data16to8_1/clock100to200_1/inst/mmcm_adv_inst/CLKOUT1] +create_clock -period 12.5 [get_pins -hier -filter {name=~*gt0_gtxKintex7FEE80_i*gtxe2_i*TXOUTCLK}] +#create_clock -period 10.0 [get_pins -hier -filter {name=~*gt0_gtxKintex7FEE80_i*gtxe2_i*RXOUTCLK}] +create_clock -period 10.0 -name RXOUTCLK [get_pins FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/gtx_i/gtxKintex7FEE80_init_i/U0/gtxKintex7FEE80_i/gt0_gtxKintex7FEE80_i/gtxe2_i/RXOUTCLK] + +#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_gtxKintex7FEE80_i*gtxe2_i*TXOUTCLK}]] +#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_gtxKintex7FEE80_i*gtxe2_i*TXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]] +#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_gtxKintex7FEE80_i*gtxe2_i*RXOUTCLK}]] +#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_gtxKintex7FEE80_i*gtxe2_i*RXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]] + +#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clockmodule40Mto80M1/inst/clk_out2] + + +create_clock -period 3.125 -name BitClk_0 [get_pins FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcClock/AdcClock_I_Bufio/O] +create_clock -period 3.125 -name BitClk_1 [get_pins FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcClock/AdcClock_I_Bufio/O] +create_clock -period 3.125 -name BitClk_2 [get_pins FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcClock/AdcClock_I_Bufio/O] +create_clock -period 3.125 -name BitClk_3 [get_pins FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcClock/AdcClock_I_Bufio/O] +create_clock -period 3.125 -name BitClk_4 [get_pins FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcClock/AdcClock_I_Bufio/O] +create_clock -period 3.125 -name BitClk_5 [get_pins FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcClock/AdcClock_I_Bufio/O] +create_clock -period 3.125 -name BitClk_6 [get_pins FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcClock/AdcClock_I_Bufio/O] +create_clock -period 3.125 -name BitClk_7 [get_pins FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcClock/AdcClock_I_Bufio/O] + +create_clock -period 3.125 -name DCOA1_P -waveform {0.000 1.563} [get_ports DCOA1_P] +create_clock -period 3.125 -name DCOA2_P -waveform {0.000 1.563} [get_ports DCOA2_P] +create_clock -period 3.125 -name DCOA3_P -waveform {0.000 1.563} [get_ports DCOA3_P] +create_clock -period 3.125 -name DCOA4_P -waveform {0.000 1.563} [get_ports DCOA4_P] +create_clock -period 3.125 -name DCOB1_P -waveform {0.000 1.563} [get_ports DCOB1_P] +create_clock -period 3.125 -name DCOB2_P -waveform {0.000 1.563} [get_ports DCOB2_P] +create_clock -period 3.125 -name DCOB3_P -waveform {0.000 1.563} [get_ports DCOB3_P] +create_clock -period 3.125 -name DCOB4_P -waveform {0.000 1.563} [get_ports DCOB4_P] +#create_clock -period 1000.000 -name GEO -waveform {0.000 500.000} [get_ports GEO] + +#create_clock -period 12.500 -name clock_S -waveform {0.000 6.250} [get_nets clock_S] +#create_clock -period 10.000 -name clock100MHz_S -waveform {0.000 5.000} [get_nets clock100MHz_S] +#create_clock -period 5.000 -name clock200MHz_S -waveform {0.000 2.500} [get_nets clock200MHz_S] +#create_clock -period 15.833 -name async_clock_S [get_nets async_clock_S] + +#create_clock -period 12.500 -name adcclockA0 -waveform {0.000 6.250} [get_nets FEE_ADCinput_module1/AdcToplevel1458_1/IntClkDiv] +#create_clock -period 12.500 -name adcclockA1 -waveform {0.000 6.250} [get_nets FEE_ADCinput_module1/AdcToplevel1458_2/IntClkDiv] +#create_clock -period 12.500 -name adcclockA2 -waveform {0.000 6.250} [get_nets FEE_ADCinput_module1/AdcToplevel1458_3/IntClkDiv] +#create_clock -period 12.500 -name adcclockA3 -waveform {0.000 6.250} [get_nets FEE_ADCinput_module1/AdcToplevel1458_4/IntClkDiv] +#create_clock -period 12.500 -name adcclockB0 -waveform {0.000 6.250} [get_nets FEE_ADCinput_module1/AdcToplevel2356_1/IntClkDiv] +#create_clock -period 12.500 -name adcclockB1 -waveform {0.000 6.250} [get_nets FEE_ADCinput_module1/AdcToplevel2356_2/IntClkDiv] +#create_clock -period 12.500 -name adcclockB2 -waveform {0.000 6.250} [get_nets FEE_ADCinput_module1/AdcToplevel2356_3/IntClkDiv] +#create_clock -period 12.500 -name adcclockB3 -waveform {0.000 6.250} [get_nets FEE_ADCinput_module1/AdcToplevel2356_4/IntClkDiv] + +create_clock -period 12.500 -name adcclockA0 -waveform {0.000 6.250} [get_pins FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcClock/AdcClock_I_Bufr/O] +create_clock -period 12.500 -name adcclockA1 -waveform {0.000 6.250} [get_pins FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcClock/AdcClock_I_Bufr/O] +create_clock -period 12.500 -name adcclockA2 -waveform {0.000 6.250} [get_pins FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcClock/AdcClock_I_Bufr/O] +create_clock -period 12.500 -name adcclockA3 -waveform {0.000 6.250} [get_pins FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcClock/AdcClock_I_Bufr/O] +create_clock -period 12.500 -name adcclockB0 -waveform {0.000 6.250} [get_pins FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcClock/AdcClock_I_Bufr/O] +create_clock -period 12.500 -name adcclockB1 -waveform {0.000 6.250} [get_pins FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcClock/AdcClock_I_Bufr/O] +create_clock -period 12.500 -name adcclockB2 -waveform {0.000 6.250} [get_pins FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcClock/AdcClock_I_Bufr/O] +create_clock -period 12.500 -name adcclockB3 -waveform {0.000 6.250} [get_pins FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcClock/AdcClock_I_Bufr/O] + + +set_false_path -from [get_clocks SYS_CLK] -to [get_clocks {ST_CLK_N GCLK_P ADC_clk_S BitClk_0 BitClk_1 BitClk_2 BitClk_3 BitClk_4 BitClk_5 BitClk_6 BitClk_7}] +set_false_path -from [get_clocks ST_CLK_N] -to [get_clocks {SYS_CLK GCLK_P ADC_clk_S BitClk_0 BitClk_1 BitClk_2 BitClk_3 BitClk_4 BitClk_5 BitClk_6 BitClk_7}] +set_false_path -from [get_clocks GCLK_P] -to [get_clocks {SYS_CLK ST_CLK_N ADC_clk_S BitClk_0 BitClk_1 BitClk_2 BitClk_3 BitClk_4 BitClk_5 BitClk_6 BitClk_7}] +set_false_path -from [get_clocks ADC_clk_S] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P BitClk_0 BitClk_1 BitClk_2 BitClk_3 BitClk_4 BitClk_5 BitClk_6 BitClk_7}] +set_false_path -from [get_clocks BitClk_0] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P ADC_clk_S BitClk_1 BitClk_2 BitClk_3 BitClk_4 BitClk_5 BitClk_6 BitClk_7}] +set_false_path -from [get_clocks BitClk_1] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P ADC_clk_S BitClk_0 BitClk_2 BitClk_3 BitClk_4 BitClk_5 BitClk_6 BitClk_7}] +set_false_path -from [get_clocks BitClk_2] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P ADC_clk_S BitClk_0 BitClk_1 BitClk_3 BitClk_4 BitClk_5 BitClk_6 BitClk_7}] +set_false_path -from [get_clocks BitClk_3] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P ADC_clk_S BitClk_0 BitClk_1 BitClk_2 BitClk_4 BitClk_5 BitClk_6 BitClk_7}] +set_false_path -from [get_clocks BitClk_4] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P ADC_clk_S BitClk_0 BitClk_1 BitClk_2 BitClk_3 BitClk_5 BitClk_6 BitClk_7}] +set_false_path -from [get_clocks BitClk_5] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P ADC_clk_S BitClk_0 BitClk_1 BitClk_2 BitClk_3 BitClk_4 BitClk_6 BitClk_7}] +set_false_path -from [get_clocks BitClk_6] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P ADC_clk_S BitClk_0 BitClk_1 BitClk_2 BitClk_3 BitClk_4 BitClk_5 BitClk_7}] +set_false_path -from [get_clocks BitClk_7] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P ADC_clk_S BitClk_0 BitClk_1 BitClk_2 BitClk_3 BitClk_4 BitClk_5 BitClk_6}] + +#//set_false_path -from [get_clocks clock_S] -to [get_clocks -include_generated_clocks {clock100MHz_S clock200MHz_S ADC_clk_S }] +set_false_path -from [get_clocks clock_S] -to [get_clocks -include_generated_clocks {clock200MHz_S ADC_clk_S RXOUTCLK rxSodaClk aurora_clock}] +#//set_false_path -from [get_clocks clock100MHz_S] -to [get_clocks -include_generated_clocks {clock_S ADC_clk_S}] +set_false_path -from [get_clocks clock200MHz_S] -to [get_clocks -include_generated_clocks {clock_S ADC_clk_S aurora_clock}] +#//set_false_path -from [get_clocks ADC_clk_S] -to [get_clocks -include_generated_clocks {clock_S clock100MHz_S clock200MHz_S}] +set_false_path -from [get_clocks ADC_clk_S] -to [get_clocks -include_generated_clocks {clock_S clock200MHz_S aurora_clock}] +set_false_path -from [get_clocks RXOUTCLK] -to [get_clocks -include_generated_clocks {clock_S clock200MHz_S aurora_clock}] +set_false_path -from [get_clocks rxSodaClk] -to [get_clocks -include_generated_clocks {clock_S clock200MHz_S aurora_clock}] +set_false_path -from [get_clocks aurora_clock] -to [get_clocks -include_generated_clocks {clock_S clock200MHz_S ADC_clk_S RXOUTCLK rxSodaClk}] + +set_false_path -from [get_clocks adcclockA0] -to [get_clocks BitClk_0] +set_false_path -from [get_clocks adcclockB0] -to [get_clocks BitClk_1] +set_false_path -from [get_clocks adcclockA1] -to [get_clocks BitClk_2] +set_false_path -from [get_clocks adcclockB1] -to [get_clocks BitClk_3] +set_false_path -from [get_clocks adcclockA2] -to [get_clocks BitClk_4] +set_false_path -from [get_clocks adcclockB2] -to [get_clocks BitClk_5] +set_false_path -from [get_clocks adcclockA3] -to [get_clocks BitClk_6] +set_false_path -from [get_clocks adcclockB3] -to [get_clocks BitClk_7] + +set_false_path -from [get_clocks adcclockA0] -to [get_clocks -include_generated_clocks {clock_S async_clock_S}] +set_false_path -from [get_clocks adcclockB0] -to [get_clocks -include_generated_clocks {clock_S async_clock_S}] +set_false_path -from [get_clocks adcclockA1] -to [get_clocks -include_generated_clocks {clock_S async_clock_S}] +set_false_path -from [get_clocks adcclockB1] -to [get_clocks -include_generated_clocks {clock_S async_clock_S}] +set_false_path -from [get_clocks adcclockA2] -to [get_clocks -include_generated_clocks {clock_S async_clock_S}] +set_false_path -from [get_clocks adcclockB2] -to [get_clocks -include_generated_clocks {clock_S async_clock_S}] +set_false_path -from [get_clocks adcclockA3] -to [get_clocks -include_generated_clocks {clock_S async_clock_S}] +set_false_path -from [get_clocks adcclockB3] -to [get_clocks -include_generated_clocks {clock_S async_clock_S}] + +set_false_path -from [get_clocks -include_generated_clocks async_clock_S] -to [get_clocks {adcclockA0 adcclockB0 adcclockA1 adcclockB1 adcclockA2 adcclockB2 adcclockA3 adcclockB3}] + +#//set_false_path -from [get_clocks -include_generated_clocks async_clock_S] -to [get_clocks -include_generated_clocks clock40MHz_S] +set_false_path -from [get_clocks -include_generated_clocks async_clock_S] -to [get_clocks -include_generated_clocks clock_S] +#//set_false_path -from [get_clocks -include_generated_clocks async_clock_S] -to [get_clocks -include_generated_clocks clock100MHz_S] +set_false_path -from [get_clocks -include_generated_clocks async_clock_S] -to [get_clocks -include_generated_clocks clock200MHz_S] +#//set_false_path -from [get_clocks -include_generated_clocks clock40MHz_S] -to [get_clocks -include_generated_clocks async_clock_S] + +#//set_false_path -from [get_clocks -include_generated_clocks clock40MHz_S] -to [get_clocks -include_generated_clocks async_clock_S] +set_false_path -from [get_clocks -include_generated_clocks clock_S] -to [get_clocks -include_generated_clocks async_clock_S] +#//set_false_path -from [get_clocks -include_generated_clocks clock100MHz_S] -to [get_clocks -include_generated_clocks async_clock_S] +set_false_path -from [get_clocks -include_generated_clocks clock200MHz_S] -to [get_clocks -include_generated_clocks async_clock_S] + +set_max_delay -from [get_clocks rxSodaClk] -to [get_clocks -include_generated_clocks {ADC_clk_S}] 3.0 + +################################################################################ +# Timespec between groups +################################################################################ +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcClock/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcClock/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcClock/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcClock/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcClock/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcClock/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcClock/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcClock/*}] 3.000 + +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcFrame/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcFrame/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcFrame/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcFrame/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcFrame/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcFrame/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcFrame/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcFrame/*}] 3.000 + +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/*}] 3.000 + +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/*}] 3.000 + +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/*}] 3.000 + +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/*}] 3.000 + + +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/*}] 3.000 + + +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/*}] 3.000 + + +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/*}] 3.000 + + +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/*}] 3.000 +set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/*}] 3.000 + +set_max_delay -from [get_clocks BitClk_0] 1.000 +set_max_delay -from [get_clocks BitClk_1] 1.000 +set_max_delay -from [get_clocks BitClk_2] 1.000 +set_max_delay -from [get_clocks BitClk_3] 1.000 +set_max_delay -from [get_clocks BitClk_4] 1.000 +set_max_delay -from [get_clocks BitClk_5] 1.000 +set_max_delay -from [get_clocks BitClk_6] 1.000 +set_max_delay -from [get_clocks BitClk_7] 1.000 +set_max_delay -from [get_clocks adcclockA0] -to [get_clocks ADC_clk_S] 2.600 +set_max_delay -from [get_clocks adcclockA1] -to [get_clocks ADC_clk_S] 2.600 +set_max_delay -from [get_clocks adcclockA2] -to [get_clocks ADC_clk_S] 2.600 +set_max_delay -from [get_clocks adcclockA3] -to [get_clocks ADC_clk_S] 2.600 +set_max_delay -from [get_clocks adcclockB0] -to [get_clocks ADC_clk_S] 2.600 +set_max_delay -from [get_clocks adcclockB1] -to [get_clocks ADC_clk_S] 2.600 +set_max_delay -from [get_clocks adcclockB2] -to [get_clocks ADC_clk_S] 2.600 +set_max_delay -from [get_clocks adcclockB3] -to [get_clocks ADC_clk_S] 2.600 +#--//set_max_delay -from [get_clocks ADC_clk_S] 3.000 + + +#set_input_delay -clock [get_clocks BitClk_0] -clock_fall -min -add_delay 0.000 [get_ports AD11A_N] +#set_input_delay -clock [get_clocks BitClk_0] -clock_fall -max -add_delay 1.000 [get_ports AD11A_N] +#set_input_delay -clock [get_clocks BitClk_0] -min -add_delay 0.000 [get_ports AD11A_N] +#set_input_delay -clock [get_clocks BitClk_0] -max -add_delay 1.000 [get_ports AD11A_N] +#set_input_delay -clock [get_clocks BitClk_0] -clock_fall -min -add_delay 0.000 [get_ports AD11A_P] +#set_input_delay -clock [get_clocks BitClk_0] -clock_fall -max -add_delay 1.000 [get_ports AD11A_P] +#set_input_delay -clock [get_clocks BitClk_0] -min -add_delay 0.000 [get_ports AD11A_P] +#set_input_delay -clock [get_clocks BitClk_0] -max -add_delay 1.000 [get_ports AD11A_P] + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clockmodule40Mto80M1/inst/clk_out2] + +# TXOUTCLK Constraint: Value is selected based on the line rate (4.0 Gbps) and lane width (4-Byte) +#create_clock -period 10.000 [get_pins -hier -filter {name=~*gt_wrapper_i*aurora_dual_multi_gt_i*gt0_aurora_dual_i*gtxe2_i*TXOUTCLK}] +#### CDC Path ##### +set_false_path -to [get_pins -hier *cdc_to*] +set_false_path -to [get_cells -hierarchical -filter {NAME =~ *data_sync_reg1}] +set_false_path -to [get_cells -hierarchical -filter {NAME =~ *ack_sync_reg1}] +############################### GT LOC (For use in top level design) ################################### +set_property LOC GTXE2_CHANNEL_X0Y1 [get_cells gen_combine.aurora_dual_module1/aurora_module_i/aurora_dual_i/U0/gt_wrapper_i/aurora_dual_multi_gt_i/gt0_aurora_dual_i/gtxe2_i] +set_property LOC GTXE2_CHANNEL_X0Y2 [get_cells gen_combine.aurora_dual_module1/aurora_module_i/aurora_dual_i/U0/gt_wrapper_i/aurora_dual_multi_gt_i/gt1_aurora_dual_i/gtxe2_i] + +#//set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/CLR}] +#//set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/D}] +#//set_false_path -to [get_pins -hierarchical -filter {NAME =~ *reset_on_error_in_r*/D}] +#//set_property LOC GTXE2_CHANNEL_X0Y1 [get_cells gtxconn1_module1/gtxconn1_support_i/gtxconn1_init_i/U0/gtxconn1_i/gt0_gtxconn1_i/gtxe2_i] +#//set_property LOC GTXE2_CHANNEL_X0Y2 [get_cells gtxconn2_module1/gtxconn2_support_i/gtxconn2_init_i/U0/gtxconn2_i/gt0_gtxconn2_i/gtxe2_i] + + +# Configuration options +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/ADC32dualgain_debug.xdc b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/ADC32dualgain_debug.xdc new file mode 100644 index 0000000..e69de29 diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/FEE_Kintex_ADCboard.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/FEE_Kintex_ADCboard.vhd new file mode 100644 index 0000000..b45cf56 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/FEE_Kintex_ADCboard.vhd @@ -0,0 +1,2383 @@ + +library IEEE; +use IEEE.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.std_logic_arith.all; +library UNISIM; +use UNISIM.VComponents.all; +--library Adc_Interface; +-- use Adc_Interface.all; +library work; +USE work.panda_package.all; +use work.soda_components.all; + +entity FEE_Kintex_ADCboard is + Port ( + GEO : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2 + SYS_CLK : in std_logic; -- 100MHz + GCLK_P : in std_logic; + GCLK_N : in std_logic; + ST_CLK_P : in std_logic; + ST_CLK_N : in std_logic; + +----ADC1--------------------------------------------- + AD11A_P : in std_logic; + AD11A_N : in std_logic; + AD11B_P : in std_logic; + AD11B_N : in std_logic; + AD12A_P : in std_logic; + AD12A_N : in std_logic; + AD12B_P : in std_logic; + AD12B_N : in std_logic; + AD13A_P : in std_logic; + AD13A_N : in std_logic; + AD13B_P : in std_logic; + AD13B_N : in std_logic; + AD14A_P : in std_logic; + AD14A_N : in std_logic; + AD14B_P : in std_logic; + AD14B_N : in std_logic; + AD15A_P : in std_logic; + AD15A_N : in std_logic; + AD15B_P : in std_logic; + AD15B_N : in std_logic; + AD16A_P : in std_logic; + AD16A_N : in std_logic; + AD16B_P : in std_logic; + AD16B_N : in std_logic; + AD17A_P : in std_logic; + AD17A_N : in std_logic; + AD17B_P : in std_logic; + AD17B_N : in std_logic; + AD18A_P : in std_logic; + AD18A_N : in std_logic; + AD18B_P : in std_logic; + AD18B_N : in std_logic; + + DCOA1_P : in std_logic; + DCOA1_N : in std_logic; + DCOB1_P : in std_logic; + DCOB1_N : in std_logic; + + FRA1_P : in std_logic; + FRA1_N : in std_logic; + FRB1_P : in std_logic; + FRB1_N : in std_logic; + + +----ADC2--------------------------------------------- + AD21A_P : in std_logic; + AD21A_N : in std_logic; + AD21B_P : in std_logic; + AD21B_N : in std_logic; + AD22A_P : in std_logic; + AD22A_N : in std_logic; + AD22B_P : in std_logic; + AD22B_N : in std_logic; + AD23A_P : in std_logic; + AD23A_N : in std_logic; + AD23B_P : in std_logic; + AD23B_N : in std_logic; + AD24A_P : in std_logic; + AD24A_N : in std_logic; + AD24B_P : in std_logic; + AD24B_N : in std_logic; + AD25A_P : in std_logic; + AD25A_N : in std_logic; + AD25B_P : in std_logic; + AD25B_N : in std_logic; + AD26A_P : in std_logic; + AD26A_N : in std_logic; + AD26B_P : in std_logic; + AD26B_N : in std_logic; + AD27A_P : in std_logic; + AD27A_N : in std_logic; + AD27B_P : in std_logic; + AD27B_N : in std_logic; + AD28A_P : in std_logic; + AD28A_N : in std_logic; + AD28B_P : in std_logic; + AD28B_N : in std_logic; + + DCOA2_P : in std_logic; + DCOA2_N : in std_logic; + DCOB2_P : in std_logic; + DCOB2_N : in std_logic; + + FRA2_P : in std_logic; + FRA2_N : in std_logic; + FRB2_P : in std_logic; + FRB2_N : in std_logic; + +----ADC3--------------------------------------------- + AD31A_P : in std_logic; + AD31A_N : in std_logic; + AD31B_P : in std_logic; + AD31B_N : in std_logic; + AD32A_P : in std_logic; + AD32A_N : in std_logic; + AD32B_P : in std_logic; + AD32B_N : in std_logic; + AD33A_P : in std_logic; + AD33A_N : in std_logic; + AD33B_P : in std_logic; + AD33B_N : in std_logic; + AD34A_P : in std_logic; + AD34A_N : in std_logic; + AD34B_P : in std_logic; + AD34B_N : in std_logic; + AD35A_P : in std_logic; + AD35A_N : in std_logic; + AD35B_P : in std_logic; + AD35B_N : in std_logic; + AD36A_P : in std_logic; + AD36A_N : in std_logic; + AD36B_P : in std_logic; + AD36B_N : in std_logic; + AD37A_P : in std_logic; + AD37A_N : in std_logic; + AD37B_P : in std_logic; + AD37B_N : in std_logic; + AD38A_P : in std_logic; + AD38A_N : in std_logic; + AD38B_P : in std_logic; + AD38B_N : in std_logic; + + DCOA3_P : in std_logic; + DCOA3_N : in std_logic; + DCOB3_P : in std_logic; + DCOB3_N : in std_logic; + + FRA3_P : in std_logic; + FRA3_N : in std_logic; + FRB3_P : in std_logic; + FRB3_N : in std_logic; + +----ADC4--------------------------------------------- + AD41A_P : in std_logic; + AD41A_N : in std_logic; + AD41B_P : in std_logic; + AD41B_N : in std_logic; + AD42A_P : in std_logic; + AD42A_N : in std_logic; + AD42B_P : in std_logic; + AD42B_N : in std_logic; + AD43A_P : in std_logic; + AD43A_N : in std_logic; + AD43B_P : in std_logic; + AD43B_N : in std_logic; + AD44A_P : in std_logic; + AD44A_N : in std_logic; + AD44B_P : in std_logic; + AD44B_N : in std_logic; + AD45A_P : in std_logic; + AD45A_N : in std_logic; + AD45B_P : in std_logic; + AD45B_N : in std_logic; + AD46A_P : in std_logic; + AD46A_N : in std_logic; + AD46B_P : in std_logic; + AD46B_N : in std_logic; + AD47A_P : in std_logic; + AD47A_N : in std_logic; + AD47B_P : in std_logic; + AD47B_N : in std_logic; + AD48A_P : in std_logic; + AD48A_N : in std_logic; + AD48B_P : in std_logic; + AD48B_N : in std_logic; + + DCOA4_P : in std_logic; + DCOA4_N : in std_logic; + DCOB4_P : in std_logic; + DCOB4_N : in std_logic; + + FRA4_P : in std_logic; + FRA4_N : in std_logic; + FRB4_P : in std_logic; + FRB4_N : in std_logic; + +----ADCconfiguration--------------------------------------------- + SCK : out std_logic; + SDI : out std_logic; + CSA : out std_logic_vector(1 to 4); + CSB : out std_logic_vector(1 to 4); + SDOA : in std_logic_vector(1 to 4); -- out for parallel init + SDOB : in std_logic_vector(1 to 4); -- out for parallel init + +----GTX--------------------------------------------- + MOD_DEF : in std_logic_vector(2 downto 0); + LOS : in std_logic; + TX_DIS : out std_logic; + MGTREFCLK_P : in std_logic; + MGTREFCLK_N : in std_logic; + + RX_P : in std_logic; + RX_N : in std_logic; + TX_P : out std_logic; + TX_N : out std_logic; + +----PLL--------------------------------------------- + S_CTRL : in std_logic; -- 1 : FPGA1 controls PLL&JTAG, 0 : FPGA2 controls PLL&JTAG + T_CTRL : out std_logic; -- T_CTRL from FPGA1<>T_CTRL from FPGA2 : FPGA2 controls PLL&JTAG + RDu : in std_logic; + CLKu : inout std_logic; + DATAu : inout std_logic; + LEu : inout std_logic; + SYNC : out std_logic; + RCV_CLK_P : out std_logic; -- ref clock for PLL LMK04806 + RCV_CLK_N : out std_logic; + +----interconnection--------------------------------------------- + INTCOMC1_P : inout std_logic; + INTCOMC1_N : inout std_logic; + INTCOMC2_P : inout std_logic; + INTCOMC2_N : inout std_logic; + + INTCOM0_P : inout std_logic; + INTCOM0_N : inout std_logic; + INTCOM1_P : inout std_logic; + INTCOM1_N : inout std_logic; + INTCOM2_P : inout std_logic; + INTCOM2_N : inout std_logic; + INTCOM3_P : inout std_logic; + INTCOM3_N : inout std_logic; + INTCOM4_P : inout std_logic; + INTCOM4_N : inout std_logic; + INTCOM5_P : inout std_logic; + INTCOM5_N : inout std_logic; + INTCOM6_P : inout std_logic; + INTCOM6_N : inout std_logic; + INTCOM7_P : inout std_logic; + INTCOM7_N : inout std_logic; + +----Temperature------------------------------------- + TEMP_IN : out std_logic; + TEMP_OUT : in std_logic; + +----Interconnection------------------------------------- + GT_A2B_0_P : out std_logic; + GT_A2B_0_N : out std_logic; + GT_A2B_1_P : out std_logic; + GT_A2B_1_N : out std_logic; + GT_B2A_0_P : in std_logic; + GT_B2A_0_N : in std_logic; + GT_B2A_1_P : in std_logic; + GT_B2A_1_N : in std_logic; + +----JTAG out------------------------------------- + JTAG_OUT1_TCK_F : inout std_logic; + JTAG_OUT1_TDI_F : inout std_logic; + JTAG_OUT1_TDO_F : inout std_logic; + JTAG_OUT1_TMS_F : inout std_logic; + +----Test,Monitor------------------------------------- + MON1_P : out std_logic; + MON1_N : out std_logic; -- in + MON2_P : out std_logic; + MON2_N : out std_logic + ); +end FEE_Kintex_ADCboard; + + + +architecture Behavioral of FEE_Kintex_ADCboard is +constant FPGA_IN_CONTROL : std_logic := '0'; +constant ADC_PARALLELINIT : boolean := true; +constant SWAPFPGAS : boolean := false; +constant SECOND_FE_MODULE : boolean := true; +constant MWD_DOUBLEFILTER : boolean := true; +constant MWD_PU_DOUBLEFILTER : boolean := true; +constant MWD_WIDTHBITS : natural := 4; +constant MWD_SCALEBITS : natural := 12; +constant MWD2_WIDTHBITS : natural := 1; +constant MWD2_SCALEBITS : natural := 8; +constant BASELINE_BWBITS : natural := 10; +constant WAVEFORMBUFFERSIZE : natural := 9; +constant CF_DELAYBITS : natural := 3; +constant MAXPILEUPHITS : natural := 3; +constant IDIVMAXBITS : natural := 6; +constant INTEGRALRATIOBITS : natural := 3; + + +component clockmodule100to80M +port( + CLK_IN1 : in std_logic; + CLK_OUT1 : out std_logic; + CLK_OUT2 : out std_logic; + CLK_OUT3 : out std_logic; + CLK_OUT4 : out std_logic; + CLK_OUT5 : out std_logic; + CLK_OUT6 : out std_logic; + RESET : in std_logic; + LOCKED : out std_logic + ); +end component; + +component clockmodule40Mto80M +port( + CLK_IN1 : in std_logic; + CLK_OUT1 : out std_logic; + CLK_OUT2 : out std_logic; + RESET : in std_logic; + LOCKED : out std_logic + ); +end component; + +component LMK04806 is + generic( + CLK_DIV : integer := 2 -- slow down transfer : mayb 1 + ); + port( + clock : in std_logic; --Master clock + reset : in std_logic; --reset + CLKu : out std_logic; --Clk to LMK + DATAu : out std_logic; --Data to LMK + LEu : out std_logic; --Data Latch to LMK + RDu : in std_logic; --Read back + SYNC : out std_logic; --Sync CLK outputs LMK + boot_PLL : in std_logic; --Start booting when set high + booting : out std_logic --busy signal + ); +end component; + +component FEE_startup is + port( + clock : in std_logic; + ADCclock : in std_logic; + clock_from_PLL : in std_logic; + reset : in std_logic; + GEO : in std_logic; + IcontrolPLL : in std_logic; + ADCchip_init : out std_logic; + PLL_init : out std_logic; + PLL_booting : in std_logic; + GTX_reset : out std_logic; + GTX_LOS : in std_logic; + GTX_rxLocked : in std_logic; + GTX_txLocked : in std_logic; + GTX_error : in std_logic; + PLLuseGTXclock : out std_logic; + PLL_locked : in std_logic; + ADCs_reset : out std_logic; + ADCs_ready : in std_logic; + FEE_reset : out std_logic; + startupready : out std_logic + ); +end component; + +component FEE_ADCinput_module is + port ( + clock200MHz : in std_logic; + clock80MHz : in std_logic; + clockAsync : in std_logic; + reset : in std_logic; + ADCs_enable : in std_logic; +----ADC1--------------------------------------------- + AD11A_P : in std_logic; + AD11A_N : in std_logic; + AD11B_P : in std_logic; + AD11B_N : in std_logic; + AD12A_P : in std_logic; + AD12A_N : in std_logic; + AD12B_P : in std_logic; + AD12B_N : in std_logic; + AD13A_P : in std_logic; + AD13A_N : in std_logic; + AD13B_P : in std_logic; + AD13B_N : in std_logic; + AD14A_P : in std_logic; + AD14A_N : in std_logic; + AD14B_P : in std_logic; + AD14B_N : in std_logic; + AD15A_P : in std_logic; + AD15A_N : in std_logic; + AD15B_P : in std_logic; + AD15B_N : in std_logic; + AD16A_P : in std_logic; + AD16A_N : in std_logic; + AD16B_P : in std_logic; + AD16B_N : in std_logic; + AD17A_P : in std_logic; + AD17A_N : in std_logic; + AD17B_P : in std_logic; + AD17B_N : in std_logic; + AD18A_P : in std_logic; + AD18A_N : in std_logic; + AD18B_P : in std_logic; + AD18B_N : in std_logic; + + DCOA1_P : in std_logic; + DCOA1_N : in std_logic; + DCOB1_P : in std_logic; + DCOB1_N : in std_logic; + + FRA1_P : in std_logic; + FRA1_N : in std_logic; + FRB1_P : in std_logic; + FRB1_N : in std_logic; + +----ADC2--------------------------------------------- + AD21A_P : in std_logic; + AD21A_N : in std_logic; + AD21B_P : in std_logic; + AD21B_N : in std_logic; + AD22A_P : in std_logic; + AD22A_N : in std_logic; + AD22B_P : in std_logic; + AD22B_N : in std_logic; + AD23A_P : in std_logic; + AD23A_N : in std_logic; + AD23B_P : in std_logic; + AD23B_N : in std_logic; + AD24A_P : in std_logic; + AD24A_N : in std_logic; + AD24B_P : in std_logic; + AD24B_N : in std_logic; + AD25A_P : in std_logic; + AD25A_N : in std_logic; + AD25B_P : in std_logic; + AD25B_N : in std_logic; + AD26A_P : in std_logic; + AD26A_N : in std_logic; + AD26B_P : in std_logic; + AD26B_N : in std_logic; + AD27A_P : in std_logic; + AD27A_N : in std_logic; + AD27B_P : in std_logic; + AD27B_N : in std_logic; + AD28A_P : in std_logic; + AD28A_N : in std_logic; + AD28B_P : in std_logic; + AD28B_N : in std_logic; + + DCOA2_P : in std_logic; + DCOA2_N : in std_logic; + DCOB2_P : in std_logic; + DCOB2_N : in std_logic; + + FRA2_P : in std_logic; + FRA2_N : in std_logic; + FRB2_P : in std_logic; + FRB2_N : in std_logic; + +----ADC3--------------------------------------------- + AD31A_P : in std_logic; + AD31A_N : in std_logic; + AD31B_P : in std_logic; + AD31B_N : in std_logic; + AD32A_P : in std_logic; + AD32A_N : in std_logic; + AD32B_P : in std_logic; + AD32B_N : in std_logic; + AD33A_P : in std_logic; + AD33A_N : in std_logic; + AD33B_P : in std_logic; + AD33B_N : in std_logic; + AD34A_P : in std_logic; + AD34A_N : in std_logic; + AD34B_P : in std_logic; + AD34B_N : in std_logic; + AD35A_P : in std_logic; + AD35A_N : in std_logic; + AD35B_P : in std_logic; + AD35B_N : in std_logic; + AD36A_P : in std_logic; + AD36A_N : in std_logic; + AD36B_P : in std_logic; + AD36B_N : in std_logic; + AD37A_P : in std_logic; + AD37A_N : in std_logic; + AD37B_P : in std_logic; + AD37B_N : in std_logic; + AD38A_P : in std_logic; + AD38A_N : in std_logic; + AD38B_P : in std_logic; + AD38B_N : in std_logic; + + DCOA3_P : in std_logic; + DCOA3_N : in std_logic; + DCOB3_P : in std_logic; + DCOB3_N : in std_logic; + + FRA3_P : in std_logic; + FRA3_N : in std_logic; + FRB3_P : in std_logic; + FRB3_N : in std_logic; + +----ADC4--------------------------------------------- + AD41A_P : in std_logic; + AD41A_N : in std_logic; + AD41B_P : in std_logic; + AD41B_N : in std_logic; + AD42A_P : in std_logic; + AD42A_N : in std_logic; + AD42B_P : in std_logic; + AD42B_N : in std_logic; + AD43A_P : in std_logic; + AD43A_N : in std_logic; + AD43B_P : in std_logic; + AD43B_N : in std_logic; + AD44A_P : in std_logic; + AD44A_N : in std_logic; + AD44B_P : in std_logic; + AD44B_N : in std_logic; + AD45A_P : in std_logic; + AD45A_N : in std_logic; + AD45B_P : in std_logic; + AD45B_N : in std_logic; + AD46A_P : in std_logic; + AD46A_N : in std_logic; + AD46B_P : in std_logic; + AD46B_N : in std_logic; + AD47A_P : in std_logic; + AD47A_N : in std_logic; + AD47B_P : in std_logic; + AD47B_N : in std_logic; + AD48A_P : in std_logic; + AD48A_N : in std_logic; + AD48B_P : in std_logic; + AD48B_N : in std_logic; + + DCOA4_P : in std_logic; + DCOA4_N : in std_logic; + DCOB4_P : in std_logic; + DCOB4_N : in std_logic; + + FRA4_P : in std_logic; + FRA4_N : in std_logic; + FRB4_P : in std_logic; + FRB4_N : in std_logic; + ADC_clk : out std_logic; + ADCs_ready : out std_logic; + adcdata : out array_adc_type + ); +end component; + +component AdcSerialProg is + port ( + clock : in std_logic; + reset : in std_logic; + init : in std_logic; + clock_out : out std_logic; + dataA_in : in std_logic_vector(3 downto 0); + dataB_in : in std_logic_vector(3 downto 0); + data_out : out std_logic; + chipnselectA : out std_logic_vector(3 downto 0); + chipnselectB : out std_logic_vector(3 downto 0); + selREGS : in std_logic_vector(2 downto 0) + ); +end component; + +component FEE_gtxModule is + Port ( + gtpClk_P : in std_logic; + gtpClk_N : in std_logic; + refclk_out : out std_logic; + sysClk : in std_logic; + asyncclk : in std_logic; + reset : in std_logic; + disable_GTX_reset : in std_logic; + + TX_DLM : in std_logic; + TX_DLM_WORD : in std_logic_vector(7 downto 0); + RX_DLM : out std_logic; + RX_DLM_WORD : out std_logic_vector(7 downto 0); + + txAsyncClk : in std_logic; + txAsyncData : in std_logic_vector(31 downto 0); + txAsyncDataWrite : in std_logic; + txAsyncFirstData : in std_logic; + txAsyncLastData : in std_logic; + txAsyncFifoFull : out std_logic; + txUsrClk : out std_logic; + txLocked : out std_logic; + + rxAsyncClk : in std_logic; + rxAsyncData : out std_logic_vector(31 downto 0); + rxAsyncFirstData : out std_logic; + rxAsyncLastData : out std_logic; + rxAsyncDataRead : in std_logic; + rxError : out std_logic; + rxAsyncDataOverflow : out std_logic; + rxAsyncDataPresent : out std_logic; + rxUsrClkdiv2 : out std_logic; + rxSodaClk : out std_logic; + rxSodaClk40 : out std_logic; + rxLocked : out std_logic; + + gtpTxP0 : out std_logic; + gtpTxN0 : out std_logic; + gtpRxP0 : in std_logic; + gtpRxN0 : in std_logic; + GT0_QPLLOUTCLK_IN : in std_logic; + GT0_QPLLOUTREFCLK_IN : in std_logic + ); +end component; + +component gtx_common is +generic +( + -- Simulation attributes + WRAPPER_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- Set to "true" to speed up sim reset + SIM_QPLLREFCLK_SEL : bit_vector := "001" +); +port +( + QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0); + GTREFCLK1_IN : in std_logic; + GTREFCLK0_IN : in std_logic; + QPLLLOCK_OUT : out std_logic; + QPLLLOCKDETCLK_IN : in std_logic; + QPLLOUTCLK_OUT : out std_logic; + QPLLOUTREFCLK_OUT : out std_logic; + QPLLREFCLKLOST_OUT : out std_logic; + QPLLRESET_IN : in std_logic +); + +end component; + +component FEE_adc32_module is + generic ( + NROFADCS : natural := NROFFEEADCS; + ADCBITS : natural := ADCBITS; + MWD_WIDTHBITS : natural := MWD_WIDTHBITS; + MWD2_WIDTHBITS : natural := MWD2_WIDTHBITS; + MWD_SCALEBITS : natural := MWD_SCALEBITS; + MWD2_SCALEBITS : natural := MWD2_SCALEBITS; + MWD_DOUBLEFILTER : boolean := MWD_DOUBLEFILTER; + MWD_PU_DOUBLEFILTER : boolean := MWD_PU_DOUBLEFILTER; + BASELINE_BWBITS : natural := BASELINE_BWBITS; + WAVEFORMBUFFERSIZE : natural := WAVEFORMBUFFERSIZE; + ADCCLOCKFREQUENCY : natural := ADCCLOCKFREQUENCY; + CF_DELAYBITS : natural := CF_DELAYBITS; + MAXPILEUPHITS : natural := MAXPILEUPHITS; + IDIVMAXBITS : natural := IDIVMAXBITS; + INTEGRALRATIOBITS : natural := INTEGRALRATIOBITS; + SECOND_FE_MODULE : boolean := SECOND_FE_MODULE + ); + port ( + clock : in std_logic; + reset : in std_logic; + enable_data : in std_logic; + GEO : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2 + ADCdata : in array_adc_type; + superburst_start : in std_logic; + superburst_received : in std_logic_vector(30 downto 0); + force_hit : in std_logic; + onesecondpulse : in std_logic; + rxNotInTable : in std_logic; + startupready : in std_logic; + request_init : in std_logic; + packet_in_data : in std_logic_vector (31 downto 0); + packet_in_present : in std_logic; + packet_in_read : out std_logic; + packet_out_data : out std_logic_vector(31 downto 0); + packet_out_first : out std_logic; + packet_out_last : out std_logic; + packet_out_write : out std_logic; + packet_out_inpipe : out std_logic; + packet_out_fifofull : in std_logic; + errorbyte_out : out std_logic_vector(7 downto 0); + errorbyte_in : in std_logic_vector(7 downto 0); + smaart_in : in std_logic; + smaart_out : out std_logic; + sysmon_data : in std_logic_vector(15 downto 0); + sysmon_reset : out std_logic; + sysmon_address : out std_logic_vector(6 downto 0); + sysmon_read : out std_logic; + second_module_zero : in std_logic; + enable_waveform : out std_logic; + compare_error : out std_logic + ); +end component; + +component FEE_receive_split is + port ( + clock_in : in std_logic; + clock_local : in std_logic; + clock_remote : in std_logic; + reset : in std_logic; + GEO : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2 + data_in : in std_logic_vector (31 downto 0); + data_in_first : in std_logic; + data_in_last : in std_logic; + data_in_present : in std_logic; + data_in_fifofull : out std_logic; + data_in_read : out std_logic; + data_local : out std_logic_vector(31 downto 0); + data_local_first : out std_logic; + data_local_last : out std_logic; + data_local_present : out std_logic; + data_local_read : in std_logic; + data_remote : out std_logic_vector(31 downto 0); + data_remote_first : out std_logic; + data_remote_last : out std_logic; + data_remote_present : out std_logic; + data_remote_read : in std_logic; + error : out std_logic + ); +end component; + +component FEE_transmit_combine is + port ( + clock_local : in std_logic; + clock_remote : in std_logic; + clock_out : in std_logic; + reset : in std_logic; + GEO : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2 + enable_waveform : in std_logic; + data_local : in std_logic_vector (31 downto 0); + data_local_first : in std_logic; + data_local_last : in std_logic; + data_local_write : in std_logic; + data_local_inpipe : in std_logic; + data_local_fifofull : out std_logic; + data_remote : in std_logic_vector(31 downto 0); + data_remote_first : in std_logic; + data_remote_last : in std_logic; + data_remote_write : in std_logic; + data_remote_inpipe : in std_logic; + data_remote_fifofull : out std_logic; + data_remote_almostfull : out std_logic; + data_out : out std_logic_vector(31 downto 0); + data_out_first : out std_logic; + data_out_last : out std_logic; + data_out_write : out std_logic; + data_out_inpipe : out std_logic; + data_out_fifofull : in std_logic; + error : out std_logic + ); +end component; + +component FEE_soda_client is + port( + SYSCLK : in std_logic; -- fabric clock + SODACLK : in std_logic; -- recovered clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; + + RX_DLM_WORD_IN : in std_logic_vector(7 downto 0); + RX_DLM_IN : in std_logic; + TX_DLM_OUT : out std_logic; + TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0); + TX_DLM_PREVIEW_OUT : out std_logic := '0'; + LINK_PHASE_IN : in std_logic; + + START_OF_SUPERBURST : out std_logic; -- PS + SUPER_BURST_NR : out std_logic_vector(30 downto 0); -- PS + SODA_CMD_VALID : out std_logic; -- PS + SODA_CMD_WORD : out std_logic_vector(30 downto 0); -- PS + + SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); + SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0'); + SODA_ADDR_IN : in std_logic_vector(3 downto 0) := (others => '0'); + SODA_READ_IN : in std_logic := '0'; + SODA_WRITE_IN : in std_logic := '0'; + SODA_ACK_OUT : out std_logic := '0'; + LEDS_OUT : out std_logic_vector(3 downto 0); + LINK_DEBUG_IN : in std_logic_vector(31 downto 0) := (others => '0') + ); +end component; + +component SystemMonitorModule is + Port ( + clock : in std_logic; + reset : in std_logic; + address : in std_logic_vector(6 downto 0); + data_write : in std_logic; + data_in : in std_logic_vector(15 downto 0); + data_read : in std_logic; + data_out : out std_logic_vector(15 downto 0); + alarms : out std_logic_vector(7 downto 0) + ); +end component; + +component reboot is + port ( + TRIGGER : in std_logic; + SYSCLK : in std_logic + ); +end component; + +component sem_module is + port ( + clk : in std_logic; + status_heartbeat : out std_logic; + status_initialization : out std_logic; + status_observation : out std_logic; + status_correction : out std_logic; + status_classification : out std_logic; + status_injection : out std_logic; + status_essential : out std_logic; + status_uncorrectable : out std_logic + ); +end component; + +component aurora_dual_module is + port ( + stable_clock : in std_logic; -- 80MHz + reset : in std_logic; + user_clock : out std_logic; + tx_data : in std_logic_vector(31 downto 0); + tx_first : in std_logic; + tx_last : in std_logic; + tx_write : in std_logic; + tx_allowed : out std_logic; + tx_inpipe : in std_logic; + rx_data : out std_logic_vector(31 downto 0); + rx_first : out std_logic; + rx_last : out std_logic; + rx_write : out std_logic; + rx_almostfull : in std_logic; + rx_inpipe : out std_logic; + locked : out std_logic; + error : out std_logic; + RXP : in std_logic_vector(0 to 1); + RXN : in std_logic_vector(0 to 1); + TXP : out std_logic_vector(0 to 1); + TXN : out std_logic_vector(0 to 1); + GTXQ0_P : in std_logic; + GTXQ0_N : in std_logic; + gt0_refclk_in : in std_logic; + gt0_qplllock_in : in std_logic; + gt0_qpllrefclklost_in : in std_logic; + gt0_qpllreset_out : out std_logic; + GT_QPLLOUTCLK_IN : in std_logic; + GT_QPLLOUTREFCLK_IN : in std_logic + ); +end component; + +component FEE_fiforead2write is + generic( + BITS : integer := 32 + ); + port( + clock : in std_logic; + data_in : in std_logic_vector(BITS-1 downto 0); + data_in_empty : in std_logic; + data_in_read : out std_logic; + data_out : out std_logic_vector(BITS-1 downto 0); + data_out_write : out std_logic; + data_out_allowed : in std_logic + ); +end component; + +component posedge_to_pulse is + port ( + clock_in : in std_logic; + clock_out : in std_logic; + en_clk : in std_logic; + signal_in :in std_logic; + pulse : out std_logic + ); +end component; + +component vio_debug is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in3 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); +end component; + +component vio36 + Port ( + clk : IN STD_LOGIC; + probe_out0 : OUT STD_LOGIC_VECTOR(35 DOWNTO 0) + ); +end component; + +type adcdata_type is array(0 to 7) of std_logic_vector(15 downto 0); +type AdcDataOut_type is array(0 to 3) of std_logic_vector((32*((4/2)*2))-1 downto 0); +type adcdataserial_type is array(0 to 3) of std_logic_vector(7 downto 0); + +-- clocking +signal clock_S : std_logic; -- main clock, frequency equal to ADC clock, PLL reference during boot +signal clock40MHz_S : std_logic; +signal clock100MHz_S : std_logic; +signal clock160MHz_S : std_logic; +signal clock200MHz_S : std_logic; +signal gclk_S : std_logic; +signal ST_CLK_S : std_logic; +signal async_clock_S : std_logic; +signal RCV_CLK_S : std_logic; +signal ADC_clk_S : std_logic; +signal onesecondpulse_S : std_logic; + +-- resetting +signal IcontrolPLL_S : std_logic := '0'; +signal IcontrolPLLnot_S : std_logic := '1'; +signal clockmodule_locked_S : std_logic; +signal reset_S : std_logic := '0'; +signal reset_FEE_S : std_logic; +signal reset_FEE_ADCclk_S : std_logic := '0'; +signal reset_rxSodaClk_S : std_logic; +signal startupready_S : std_logic; +signal request_init_S : std_logic := '0'; +signal GEO_S : std_logic := '0'; +signal GEObuf_S : std_logic := '0'; +signal T_CTRL_S : std_logic := '0'; +signal S_CTRL_S : std_logic := '0'; +signal enable_waveform_S : std_logic; + +-- PLL +signal CLKu_S : std_logic; +signal DATAu_S : std_logic; +signal LEu_S : std_logic; +signal RDu_S : std_logic; +signal SYNC_S : std_logic; +signal pll_boot_s : std_logic; +signal pll_boot1_s : std_logic; +signal PLL_booting_busy_S : std_logic; + +signal PLLuseGTXclock_S : std_logic; +signal PLLuseGTXclock0_S : std_logic; +signal PLLuseGTXclock1_S : std_logic; +signal clockswitch_locked_S : std_logic; +signal clockswitch_reset_S : std_logic; + + +-- system monitor +signal sysmon_data_S : std_logic_vector(15 downto 0); +signal sysmon_reset_S : std_logic; +signal sysmon_address_S : std_logic_vector(6 downto 0); +signal sysmon_read_S : std_logic; + +signal TEMP_OUT_S : std_logic := '0'; +signal TEMP_IN_S : std_logic := '0'; + +-- SODA +signal EnableDataTaking_S : std_logic := '0'; +signal DisableDataTaking_S : std_logic := '0'; +signal enable_data_S : std_logic := '0'; +signal DataTaking_enabled_out_S : std_logic := '0'; +signal DataTaking_enabled_in_S : std_logic := '0'; +signal SODA_cmd_valid_S : std_logic := '0'; +signal SODA_cmd_word_S : std_logic_vector(30 downto 0); +signal superburst_out0_S : std_logic_vector(30 downto 0); +signal superburst_out_S : std_logic_vector(15 downto 0); +signal superburst_startout0_S : std_logic; +signal superburst_startout_S : std_logic; +signal superburst0_in_S : std_logic_vector(15 downto 0); +signal superburst_in_S : std_logic_vector(30 downto 0); +signal superburst_start_S : std_logic; +signal superburst_startin0_S : std_logic; +signal superburst_startin0sync_S : std_logic; +signal clear_superburst_startin_S : std_logic; +signal superburst_startin1_S : std_logic; +signal superburst_startin2_S : std_logic; +signal superburst_startin3_S : std_logic; + +signal force_hit_S : std_logic; +signal force_hit_out0_S : std_logic; +signal force_hit_out_S : std_logic; + +-- ADCs +signal SCK_S : std_logic; +signal SDI_S : std_logic; +signal CSA_S : std_logic_vector(1 to 4); +signal CSB_S : std_logic_vector(1 to 4); +signal SDOA_S : std_logic_vector(1 to 4); +signal SDOB_S : std_logic_vector(1 to 4); +signal ADCchip_init_S : std_logic; +signal ADCchip_init1_S : std_logic; +signal reset_ADCs_S : std_logic; +signal reset_ADCs0_S : std_logic; +signal reset_ADCs1_S : std_logic; +signal adcdata_S : array_adc_type; +signal ADCs_enable_S : std_logic; +signal ADCs_ready_S : std_logic; + +-- gtx +signal GTX_reset_S : std_logic; +signal LOS_S : std_logic; +signal LOS_GEO_S : std_logic; +signal rxUsrClkdiv2_S : std_logic; +signal rxSodaClk_S : std_logic; +signal rxSodaClk40_S : std_logic; +signal rxSodaClk80_S : std_logic; +signal TX_DLM_S : std_logic; +signal TX_DLM_WORD_S : std_logic_vector(7 downto 0); +signal RX_DLM_S : std_logic; +signal RX_DLM_WORD_S : std_logic_vector(7 downto 0); +signal disable_GTX_reset_S : std_logic := '0'; +signal GTX_txLocked_S : std_logic; +signal GTX_txLocked_GEO_S : std_logic; +signal GTX_rxLocked_S : std_logic; +signal GTX_rxLocked_GEO_S : std_logic; +signal GTX_rxclockLocked_S : std_logic; +signal GTX_Error_S : std_logic; +signal GTX_Error_GEO_S : std_logic; + +-- gtx common +signal refclk_S : std_logic; +signal gt0_qplllock_S : std_logic; +signal gt0_qplloutclk_S : std_logic; +signal gt0_qplloutrefclk_S : std_logic; +signal gt0_qpllrefclklost_S : std_logic; +signal gt0_qpllreset_S : std_logic; + +-- FE output data +signal FE_in_data_S : std_logic_vector(31 downto 0); +signal FE_out_data_S : std_logic_vector(31 downto 0); +signal FE_in_present_S : std_logic; +signal FE_in_read_S : std_logic; +signal FE_out_first_S : std_logic; +signal FE_out_last_S : std_logic; +signal FE_out_write_S : std_logic; +signal FE_out_inpipe_S : std_logic; +signal FE_out_fifofull_S : std_logic; + +-- fiber data +signal packet_out_clock_S : std_logic; +signal packet_in_data_S : std_logic_vector(31 downto 0); +signal packet_out_data_S : std_logic_vector(31 downto 0); +signal packet_in_present_S : std_logic; +signal packet_in_read_S : std_logic; +signal packet_in_first_S : std_logic; +signal packet_in_last_S : std_logic; +signal packet_out_first_S : std_logic; +signal packet_out_last_S : std_logic; +signal packet_out_write_S : std_logic; +signal packet_out_fifofull_S : std_logic; +signal rxNotInTable_S : std_logic; +signal errorbyte_S : std_logic_vector(7 downto 0) := (others => '0'); + +-- SEM +signal doreboot_S : std_logic := '0'; +signal status_heartbeat_S : std_logic; +signal status_initialization_S : std_logic; +signal status_observation_S : std_logic; +signal status_correction_S : std_logic; +signal status_classification_S : std_logic; +signal status_injection_S : std_logic; +signal status_essential_S : std_logic; +signal status_uncorrectable_S : std_logic; + +-- interconnection +signal aurora_clock_S : std_logic; +signal aurora_tx_data_S : std_logic_vector(31 downto 0); +signal aurora_tx_allowed_S : std_logic; +signal aurora_tx_first_S : std_logic; +signal aurora_tx_last_S : std_logic; +signal aurora_tx_write_S : std_logic; +signal aurora_tx_inpipe_S : std_logic; +signal aurora_rx_data_S : std_logic_vector(31 downto 0); +signal aurora_rx_first_S : std_logic; +signal aurora_rx_last_S : std_logic; +signal aurora_rx_write_S : std_logic; +signal aurora_rx_almostfull_S : std_logic; +signal aurora_rx_inpipe_S : std_logic; +signal aurora_locked_S : std_logic; +signal aurora_error_S : std_logic; + +-- split received data +signal split_in_S : std_logic_vector(31 downto 0); +signal split_in_first_S : std_logic; +signal split_in_last_S : std_logic; +signal split_in_present_S : std_logic; +signal split_in_fifofull_S : std_logic; +signal split_in_read_S : std_logic; +signal split_local_S : std_logic_vector(31 downto 0); +signal split_local_first_S : std_logic; +signal split_local_last_S : std_logic; +signal split_local_present_S : std_logic; +signal split_local_read_S : std_logic; +signal split_remote_S : std_logic_vector(31 downto 0); +signal split_remote_first_S : std_logic; +signal split_remote_last_S : std_logic; +signal split_remote_present_S : std_logic; +signal split_remote_read_S : std_logic; +signal split_error_S : std_logic; + +-- combine FE data +signal comb_local_S : std_logic_vector(31 downto 0); +signal comb_local_first_S : std_logic; +signal comb_local_last_S : std_logic; +signal comb_local_write_S : std_logic; +signal comb_local_inpipe_S : std_logic; +signal comb_local_fifofull_S : std_logic; +signal comb_remote_S : std_logic_vector(31 downto 0); +signal comb_remote_first_S : std_logic; +signal comb_remote_last_S : std_logic; +signal comb_remote_write_S : std_logic; +signal comb_remote_inpipe_S : std_logic; +signal comb_remote_fifofull_S : std_logic; +signal comb_remote_almostfull_S : std_logic; +signal comb_out_S : std_logic_vector(31 downto 0); +signal comb_out_first_S : std_logic; +signal comb_out_last_S : std_logic; +signal comb_out_write_S : std_logic; +signal comb_out_inpipe_S : std_logic; +signal comb_out_fifofull_S : std_logic; +signal comb_error_S : std_logic; + +signal split_remote_wr_S : std_logic_vector(31 downto 0); +signal split_remote_wr_first_S : std_logic; +signal split_remote_wr_last_S : std_logic; +signal split_remote_wr_write_S : std_logic; +signal split_remote_wr_allowed_S : std_logic; +signal split_remote_fifoempty_S : std_logic; + +signal gt0_qpllreset1_S : std_logic; +signal gt0_qpllreset2_S : std_logic; + +-- test compare feature extraction results +signal vioword_S : std_logic_vector(35 downto 0) := (others => '0'); +signal compare_error_S : std_logic; +signal compare_error1_S : std_logic; + +attribute keep : string; +attribute keep of clock_S : signal is "TRUE"; +attribute keep of ADC_clk_S : signal is "TRUE"; +--attribute keep of clock100MHz_S : signal is "TRUE"; +attribute keep of clock200MHz_S : signal is "TRUE"; +attribute keep of async_clock_S : signal is "TRUE"; + +-- test + +-- signal aurora1_txclock_Sdiv10_S : std_logic; +-- signal aurora1_rxclock_Sdiv10_S : std_logic; +-- signal aurora2_txclock_Sdiv10_S : std_logic; +-- signal aurora2_rxclock_Sdiv10_S : std_logic; + +--signal vio_LMK04806_wr0_S : std_logic; +--signal vio_LMK04806_wr_S : std_logic; +signal debug_reset_S : std_logic := '0'; + +signal debug_packet_out_data_S : std_logic_vector(31 downto 0); +signal debug_packet_out_first_S : std_logic; +signal debug_packet_out_last_S : std_logic; + +attribute mark_debug : string; +-- attribute mark_debug of GEO_S : signal is "true"; +-- attribute mark_debug of T_CTRL_S : signal is "true"; +-- attribute mark_debug of S_CTRL_S : signal is "true"; +-- attribute mark_debug of reset_S : signal is "true"; +-- attribute mark_debug of clockmodule_locked_S : signal is "true"; +-- attribute mark_debug of IcontrolPLL_S : signal is "true"; +-- attribute mark_debug of ADCchip_init_S : signal is "true"; +-- attribute mark_debug of PLL_boot_S : signal is "true"; +-- attribute mark_debug of PLL_booting_busy_S : signal is "true"; +-- attribute mark_debug of GTX_reset_S : signal is "true"; +-- attribute mark_debug of LOS_GEO_S : signal is "true"; +-- attribute mark_debug of GTX_rxclockLocked_S : signal is "true"; +-- attribute mark_debug of GTX_txLocked_GEO_S : signal is "true"; +-- attribute mark_debug of GTX_Error_GEO_S : signal is "true"; +-- attribute mark_debug of PLLuseGTXclock_S : signal is "true"; +-- attribute mark_debug of PLLuseGTXclock0_S : signal is "true"; +-- attribute mark_debug of reset_ADCs_S : signal is "true"; +-- attribute mark_debug of ADCs_ready_S : signal is "true"; +-- attribute mark_debug of reset_FEE_S : signal is "true"; +-- attribute mark_debug of startupready_S : signal is "true"; +-- attribute mark_debug of reset_rxSodaClk_S : signal is "true"; + +-- attribute mark_debug of status_heartbeat_S : signal is "true"; +-- attribute mark_debug of status_initialization_S : signal is "true"; +-- attribute mark_debug of status_observation_S : signal is "true"; +-- attribute mark_debug of status_correction_S : signal is "true"; +-- attribute mark_debug of status_classification_S : signal is "true"; +-- attribute mark_debug of status_injection_S : signal is "true"; +-- attribute mark_debug of status_essential_S : signal is "true"; +-- attribute mark_debug of status_uncorrectable_S : signal is "true"; +-- attribute mark_debug of doreboot_S : signal is "true"; + +-- attribute mark_debug of LOS : signal is "true"; +-- attribute mark_debug of INTCOMC1_P : signal is "true"; +-- attribute mark_debug of INTCOMC1_N : signal is "true"; +-- attribute mark_debug of INTCOMC2_P : signal is "true"; +-- attribute mark_debug of INTCOMC2_N : signal is "true"; + + +-- attribute mark_debug of FE_in_data_S : signal is "true"; +-- attribute mark_debug of FE_in_present_S : signal is "true"; +-- attribute mark_debug of FE_in_read_S : signal is "true"; +-- attribute mark_debug of FE_out_data_S : signal is "true"; +-- attribute mark_debug of FE_out_first_S : signal is "true"; +-- attribute mark_debug of FE_out_last_S : signal is "true"; +-- attribute mark_debug of FE_out_write_S : signal is "true"; +-- attribute mark_debug of FE_out_inpipe_S : signal is "true"; +-- attribute mark_debug of FE_out_fifofull_S : signal is "true"; + +-- attribute mark_debug of aurora_tx_data_S : signal is "true"; +-- attribute mark_debug of aurora_tx_write_S : signal is "true"; +-- attribute mark_debug of aurora_tx_allowed_S : signal is "true"; +-- attribute mark_debug of aurora_rx_data_S : signal is "true"; +-- attribute mark_debug of aurora_rx_write_S : signal is "true"; +-- attribute mark_debug of aurora_locked_S : signal is "true"; +-- attribute mark_debug of aurora_error_S : signal is "true"; + +-- attribute mark_debug of packet_in_data_S : signal is "true"; +-- attribute mark_debug of packet_in_first_S : signal is "true"; +-- attribute mark_debug of packet_in_last_S : signal is "true"; +-- attribute mark_debug of packet_in_read_S : signal is "true"; +-- attribute mark_debug of packet_in_present_S : signal is "true"; +-- attribute mark_debug of packet_out_data_S : signal is "true"; +-- attribute mark_debug of packet_out_write_S : signal is "true"; +-- attribute mark_debug of packet_out_first_S : signal is "true"; +-- attribute mark_debug of packet_out_last_S : signal is "true"; +-- attribute mark_debug of packet_out_fifofull_S : signal is "true"; + +--attribute mark_debug of debug_packet_out_data_S : signal is "true"; +--attribute mark_debug of debug_packet_out_first_S : signal is "true"; +--attribute mark_debug of debug_packet_out_last_S : signal is "true"; +-- attribute mark_debug of superburst_out_S : signal is "true"; +-- attribute mark_debug of superburst_startout0_S : signal is "true"; +-- attribute mark_debug of superburst_startout_S : signal is "true"; +-- attribute mark_debug of superburst0_in_S : signal is "true"; +-- attribute mark_debug of superburst_in_S : signal is "true"; +-- attribute mark_debug of superburst_start_S : signal is "true"; +-- attribute mark_debug of superburst_startin0_S : signal is "true"; +-- attribute mark_debug of superburst_startin0sync_S : signal is "true"; +-- attribute mark_debug of clear_superburst_startin_S : signal is "true"; +-- attribute mark_debug of superburst_startin1_S : signal is "true"; +-- attribute mark_debug of superburst_startin2_S : signal is "true"; +-- attribute mark_debug of superburst_startin3_S : signal is "true"; + +begin + +-- IO buffers ------------------------------------------------ +T_CTRL_inst : OBUF port map(O => T_CTRL,I => T_CTRL_S); +S_CTRL_inst : IBUF port map (O => S_CTRL_S, I => S_CTRL); +GEO_inst : IBUF port map (O => GEObuf_S, I => GEO); +RDu_inst : IBUF port map (O => RDu_S, I => RDu); + +GEO_S <= GEObuf_S when SWAPFPGAS=false else not GEObuf_S; + + +--IOBUF1 : IOBUF port map (O => PLLuseGTXclock0_S, IO => INTCOMC1_P, I => PLLuseGTXclock_S, T => IcontrolPLLnot_S); +--IOBUF2 : IOBUF port map (O => superburst_start0_S, IO => INTCOMC1_N, I => superburst_startout_S, T => IcontrolPLLnot_S); +--IOBUF3 : IOBUF port map (O => DataTaking_enabled_in_S, IO => INTCOMC2_N, I => DataTaking_enabled_out_S, T => IcontrolPLLnot_S); +--IOBUF4 : IOBUF port map (O => open, IO => CLKu, I => CLKu_S, T => IcontrolPLLnot_S); +--IOBUF5 : IOBUF port map (O => open, IO => DATAu, I => DATAu_S, T => IcontrolPLLnot_S); +--IOBUF6 : IOBUF port map (O => open, IO => LEu, I => LEu_S, T => IcontrolPLLnot_S); + +INTCOMC1_P <= PLLuseGTXclock_S when IcontrolPLLnot_S='0' else 'Z'; +PLLuseGTXclock0_S <= INTCOMC1_P; + +INTCOMC1_N <= superburst_startout_S when IcontrolPLLnot_S='0' else 'Z'; +superburst_startin0_S <= INTCOMC1_N; + +INTCOMC2_N <= DataTaking_enabled_out_S when IcontrolPLLnot_S='0' else 'Z'; +DataTaking_enabled_in_S <= INTCOMC2_N; + +INTCOMC2_P <= force_hit_out_S when IcontrolPLLnot_S='0' else 'Z'; +force_hit_S <= INTCOMC2_P; + +CLKu <= CLKu_S when IcontrolPLLnot_S='0' else 'Z'; +DATAu <= DATAu_S when IcontrolPLLnot_S='0' else 'Z'; +LEu <= LEu_S when IcontrolPLLnot_S='0' else 'Z'; +SYNC <= SYNC_S when IcontrolPLLnot_S='0' else 'Z'; + +JTAG_IOBUF1 : IOBUF port map ( + O => open, + IO => JTAG_OUT1_TCK_F, + I => '0', + T => '1' + ); +JTAG_IOBUF2 : IOBUF port map ( + O => open, + IO => JTAG_OUT1_TDI_F, + I => '0', + T => '1' + ); +JTAG_IOBUF3 : IOBUF port map ( + O => open, + IO => JTAG_OUT1_TDO_F, + I => '0', + T => '1' + ); +JTAG_IOBUF4 : IOBUF port map ( + O => open, + IO => JTAG_OUT1_TMS_F, + I => '0', + T => '1' + ); + +TEMP_OUT_S <= TEMP_OUT; +TEMP_IN <= TEMP_IN_S; + + +--SCK <= SCK_S; +--SDI <= SDI_S; +--CSA <= CSA_S; +--CSB <= CSB_S; +SDOA_S <= SDOA; +SDOB_S <= SDOB; + +SCK_inst : OBUF port map(O => SCK,I => SCK_S); +SDI_inst : OBUF port map(O => SDI,I => SDI_S); +CSA1_inst : OBUF port map(O => CSA(1),I => CSA_S(1)); +CSA2_inst : OBUF port map(O => CSA(2),I => CSA_S(2)); +CSA3_inst : OBUF port map(O => CSA(3),I => CSA_S(3)); +CSA4_inst : OBUF port map(O => CSA(4),I => CSA_S(4)); +CSB1_inst : OBUF port map(O => CSB(1),I => CSB_S(1)); +CSB2_inst : OBUF port map(O => CSB(2),I => CSB_S(2)); +CSB3_inst : OBUF port map(O => CSB(3),I => CSB_S(3)); +CSB4_inst : OBUF port map(O => CSB(4),I => CSB_S(4)); +-- +--GEN_SDO_parallel: if ADC_PARALLELINIT=true generate +-- SDOA1_inst : OBUF port map (O => SDOA(1), I => SDOA_S(1)); +-- SDOA2_inst : OBUF port map (O => SDOA(2), I => SDOA_S(2)); +-- SDOA3_inst : OBUF port map (O => SDOA(3), I => SDOA_S(3)); +-- SDOA4_inst : OBUF port map (O => SDOA(4), I => SDOA_S(4)); +-- SDOB1_inst : OBUF port map (O => SDOB(1), I => SDOB_S(1)); +-- SDOB2_inst : OBUF port map (O => SDOB(2), I => SDOB_S(2)); +-- SDOB3_inst : OBUF port map (O => SDOB(3), I => SDOB_S(3)); +-- SDOB4_inst : OBUF port map (O => SDOB(4), I => SDOB_S(4)); +--end generate; +--GEN_SDO_serial: if ADC_PARALLELINIT=false generate +-- SDOA1_inst : IBUF port map (O => SDOA_S(1), I => SDOA(1)); +-- SDOA2_inst : IBUF port map (O => SDOA_S(2), I => SDOA(2)); +-- SDOA3_inst : IBUF port map (O => SDOA_S(3), I => SDOA(3)); +-- SDOA4_inst : IBUF port map (O => SDOA_S(4), I => SDOA(4)); +-- SDOB1_inst : IBUF port map (O => SDOB_S(1), I => SDOB(1)); +-- SDOB2_inst : IBUF port map (O => SDOB_S(2), I => SDOB(2)); +-- SDOB3_inst : IBUF port map (O => SDOB_S(3), I => SDOB(3)); +-- SDOB4_inst : IBUF port map (O => SDOB_S(4), I => SDOB(4)); +--end generate; + + +--GEN_SDO_parallel: if ADC_PARALLELINIT=true generate +-- SDOA1_inst : IOBUF port map (O => open, IO => SDOA(1), I => SDOA_S(1), T => '0'); +-- SDOA2_inst : IOBUF port map (O => open, IO => SDOA(2), I => SDOA_S(2), T => '0'); +-- SDOA3_inst : IOBUF port map (O => open, IO => SDOA(3), I => SDOA_S(3), T => '0'); +-- SDOA4_inst : IOBUF port map (O => open, IO => SDOA(4), I => SDOA_S(4), T => '0'); +-- SDOB1_inst : IOBUF port map (O => open, IO => SDOB(1), I => SDOB_S(1), T => '0'); +-- SDOB2_inst : IOBUF port map (O => open, IO => SDOB(2), I => SDOB_S(2), T => '0'); +-- SDOB3_inst : IOBUF port map (O => open, IO => SDOB(3), I => SDOB_S(3), T => '0'); +-- SDOB4_inst : IOBUF port map (O => open, IO => SDOB(4), I => SDOB_S(4), T => '0'); +--end generate; +--GEN_SDO_serial: if ADC_PARALLELINIT=false generate +-- SDOA1_inst : IOBUF port map (O => SDOA_S(1), IO => SDOA(1), I => '0', T => '1'); +-- SDOA2_inst : IOBUF port map (O => SDOA_S(2), IO => SDOA(2), I => '0', T => '1'); +-- SDOA3_inst : IOBUF port map (O => SDOA_S(3), IO => SDOA(3), I => '0', T => '1'); +-- SDOA4_inst : IOBUF port map (O => SDOA_S(4), IO => SDOA(4), I => '0', T => '1'); +-- SDOB1_inst : IOBUF port map (O => SDOB_S(1), IO => SDOB(1), I => '0', T => '1'); +-- SDOB2_inst : IOBUF port map (O => SDOB_S(2), IO => SDOB(2), I => '0', T => '1'); +-- SDOB3_inst : IOBUF port map (O => SDOB_S(3), IO => SDOB(3), I => '0', T => '1'); +-- SDOB4_inst : IOBUF port map (O => SDOB_S(4), IO => SDOB(4), I => '0', T => '1'); +--end generate; + + +-- process(clock_S,clockmodule_locked_S,GEO_S) +-- variable T_CTRL_count_V : integer range 0 to 3 := 0; +-- begin + -- if (clockmodule_locked_S='0') then + -- T_CTRL_S <= GEO_S; + -- elsif (rising_edge(clock_S)) then + -- if GEO_S='0' then + -- if (FPGA_IN_CONTROL='0') then + -- if (S_CTRL_S='0') and (T_CTRL_count_V=3) then -- wrong value + -- T_CTRL_S <= not T_CTRL_S; + -- T_CTRL_count_V := 0; + -- elsif T_CTRL_count_V/=3 then + -- T_CTRL_count_V := T_CTRL_count_V+1; + -- end if; + -- else + -- T_CTRL_S <= GEO_S; + -- end if; + -- else + -- if (FPGA_IN_CONTROL='1') then + -- if (S_CTRL_S='1') and (T_CTRL_count_V=3) then -- wrong value + -- T_CTRL_S <= not T_CTRL_S; + -- T_CTRL_count_V := 0; + -- elsif T_CTRL_count_V/=3 then + -- T_CTRL_count_V := T_CTRL_count_V+1; + -- end if; + -- else + -- T_CTRL_S <= GEO_S; + -- end if; + -- end if; + -- end if; +-- end process; +T_CTRL_S <= '0'; + +--IcontrolPLL_S <= '1' when (GEO='0') and (S_CTRL='1') else '0'; +--IcontrolPLL_S <= '1' when ((GEO_S='0') and (S_CTRL_S='1')) or ((GEO_S='1') and (S_CTRL_S='0')) else '0'; + +IcontrolPLL_S <= '1' when (GEO_S='0') else '0'; +IcontrolPLLnot_S <= '0' when (GEO_S='0') else '1'; + +-- process(clock_S,clockmodule_locked_S) +-- begin + -- if clockmodule_locked_S='0' then + -- IcontrolPLLnot_S <= '1'; + -- elsif (rising_edge(clock_S)) then + -- IcontrolPLLnot_S <= not IcontrolPLL_S; + -- end if; +-- end process; + +-- main reset ----------------------------------------------- +process(clock_S,clockmodule_locked_S,debug_reset_S) +variable S_CTRL_V : std_logic := '0'; +variable count_V : std_logic_vector(5 downto 0) := (others => '0'); +begin + if (clockmodule_locked_S='0') or (debug_reset_S='1') then + reset_S <= '1'; + count_V := (others => '0'); + elsif (rising_edge(clock_S)) then + if S_CTRL_V/=S_CTRL_S then + reset_S <= '1'; + count_V := (others => '0'); + else + if (count_V(count_V'left)='1') then + reset_S <= '0'; + else + count_V := count_V+1; + reset_S <= '1'; + end if; + end if; + S_CTRL_V := S_CTRL_S; + end if; +end process; + + +-- main clock ----------------------------------------------- + +clockmodule100Mto80Ma: clockmodule100to80M port map( + CLK_IN1 => SYS_CLK, + CLK_OUT1 => clock40MHz_S, + CLK_OUT2 => clock_S, -- 80MHz + CLK_OUT3 => clock100MHz_S, + CLK_OUT4 => clock200MHz_S, + CLK_OUT5 => async_clock_S, + CLK_OUT6 => clock160MHz_S, + RESET => '0', + LOCKED => clockmodule_locked_S); + +sysclk_buf : IBUFGDS + generic map( + IOSTANDARD => "LVDS" + ) + port map ( + I => GCLK_P, + IB => GCLK_N, + O => gclk_S + ); + +--gclk_S <= GCLK_P; -- when GEO_S='0' else clock_S; --// assign fixed clock to gclk due to hardware error? + + + +-- clock to external PLL LMK04806 ------------------------------------- + + +select_RCV_CLK : BUFGMUX + generic map ( + CLK_SEL_TYPE => "ASYNC" --//ASYNC + ) + port map( -- + O => RCV_CLK_S, + I0 => clock_S, -- clock40MHz_S, -- clock_S, + I1 => rxSodaClk80_S, --clock40MHz_S, -- clock_S, -- rxSodaClk40_S, + S => PLLuseGTXclock1_S); +PLLuseGTXclock1_S <= PLLuseGTXclock_S when IcontrolPLLnot_S='0' else '0'; + +clockmodule40Mto80M1: clockmodule40Mto80M port map( + CLK_IN1 => rxSodaClk40_S, + CLK_OUT1 => open, + CLK_OUT2 => rxSodaClk80_S, -- RCV_CLK_S, + RESET => IcontrolPLLnot_S, + LOCKED => clockswitch_locked_S); + +process(clock_S,reset_S) +variable GTX_rxLocked_V : std_logic; +variable timer_V : std_logic_vector(3 downto 0); +begin + if reset_S='1' then + GTX_rxclockLocked_S <= '0'; + timer_V := (others => '0'); + elsif (rising_edge(clock_S)) then + if ((GTX_rxLocked_GEO_S='1') and (GTX_rxLocked_V='0')) then + timer_V := (others => '0'); + GTX_rxclockLocked_S <= '0'; + else + if timer_V(timer_V'left)='0' then + timer_V := timer_V+1; + GTX_rxclockLocked_S <= '0'; + else + if (GTX_rxLocked_GEO_S='1') and ((clockswitch_locked_S='1') or (IcontrolPLLnot_S='1')) then + GTX_rxclockLocked_S <= '1'; + else + GTX_rxclockLocked_S <= '0'; + end if; + end if; + end if; + GTX_rxLocked_V := GTX_rxLocked_GEO_S; + end if; +end process; + +--sends clock to PLL +OBUFDS_inst : OBUFDS + generic map( + IOSTANDARD => "LVDS_25") + port map( + O => RCV_CLK_P, + OB => RCV_CLK_N, + I => RCV_CLK_S); + + +-- external PLL LMK04806 ------------------------------------- +LMK04806_1: LMK04806 port map( + clock => clock_S, + reset => reset_S, + CLKu => CLKu_S, + DATAu => DATAu_S, + LEu => LEu_S, + RDu => RDu_S, + SYNC => SYNC_S, + boot_PLL => PLL_boot_S, + booting => PLL_booting_busy_S); +PLL_boot1_S <= '1' when (PLL_boot_S='1') else '0'; + +SystemMonitorModule1: SystemMonitorModule port map( + clock => ADC_clk_S, + reset => sysmon_reset_S, + address => sysmon_address_S, + data_write => '0', + data_in => (others => '0'), + data_read => sysmon_read_S, + data_out => sysmon_data_S, + alarms => open); + +-- startup ---------------------------------------------------- +FEE_startup1: FEE_startup port map( + clock => clock_S, + ADCclock => ADC_clk_S, + clock_from_PLL => gclk_S, + reset => reset_S, + GEO => GEO_S, + IcontrolPLL => IcontrolPLL_S, + ADCchip_init => ADCchip_init_S, + PLL_init => PLL_boot_S, + PLL_booting => PLL_booting_busy_S, + GTX_reset => GTX_reset_S, + GTX_LOS => LOS_GEO_S, + GTX_rxLocked => GTX_rxclockLocked_S, --GTX_rxLocked_S, + GTX_txLocked => GTX_txLocked_GEO_S, + GTX_error => GTX_Error_GEO_S, + PLLuseGTXclock => PLLuseGTXclock_S, + PLL_locked => PLLuseGTXclock0_S, + ADCs_reset => reset_ADCs_S, + ADCs_ready => ADCs_ready_S, + FEE_reset => reset_FEE_S, + startupready => startupready_S + ); + +-- ADC configuration (PARALLEL or SERIAL)-------------------------------------------------------------- + +gen_adcparallelprog: if ADC_PARALLELINIT=true generate + SCK_S <= '0'; -- 2-lane 16-bits serialization + SDI_S <= '0'; -- normal mode (not sleeping) + CSA_S <= (others => '0'); -- 2-lane 16-bits serialization + CSB_S <= (others => '0'); -- 2-lane 16-bits serialization + SDOA_S <= (others => '0'); -- no internal termination + SDOB_S <= (others => '0'); -- no internal termination +end generate; + +gen_adcserialprog: if ADC_PARALLELINIT=false generate +AdcSerialProg1: AdcSerialProg port map( + clock => clock_S, + reset => reset_S, + init => ADCchip_init1_S, + clock_out => SCK_S, + dataA_in(0) => SDOA_S(1), + dataA_in(1) => SDOA_S(2), + dataA_in(2) => SDOA_S(3), + dataA_in(3) => SDOA_S(4), + dataB_in(0) => SDOB_S(1), + dataB_in(1) => SDOB_S(2), + dataB_in(2) => SDOB_S(3), + dataB_in(3) => SDOB_S(4), + data_out => SDI_S, + chipnselectA(0) => CSA_S(1), + chipnselectA(1) => CSA_S(2), + chipnselectA(2) => CSA_S(3), + chipnselectA(3) => CSA_S(4), + chipnselectB(0) => CSB_S(1), + chipnselectB(1) => CSB_S(2), + chipnselectB(2) => CSB_S(3), + chipnselectB(3) => CSB_S(4), + selREGS => (others => '0') + ); +ADCchip_init1_S <= '1' when (ADCchip_init_S='1') else '0'; +end generate; + +-- ADC inputs ---------------------------------------------------------------------- +reset_ADCs1_S <= '1' when (reset_ADCs_S='1') else '0'; + +FEE_ADCinput_module1: FEE_ADCinput_module port map( + clock200MHz => clock200MHz_S, + clock80MHz => clock_S, + clockAsync => async_clock_S, + reset => reset_ADCs1_S, + ADCs_enable => ADCs_enable_S, +----ADC1--------------------------------------------- + AD11A_P => AD11A_P, + AD11A_N => AD11A_N, + AD11B_P => AD11B_P, + AD11B_N => AD11B_N, + AD12A_P => AD12A_P, + AD12A_N => AD12A_N, + AD12B_P => AD12B_P, + AD12B_N => AD12B_N, + AD13A_P => AD13A_P, + AD13A_N => AD13A_N, + AD13B_P => AD13B_P, + AD13B_N => AD13B_N, + AD14A_P => AD14A_P, + AD14A_N => AD14A_N, + AD14B_P => AD14B_P, + AD14B_N => AD14B_N, + AD15A_P => AD15A_P, + AD15A_N => AD15A_N, + AD15B_P => AD15B_P, + AD15B_N => AD15B_N, + AD16A_P => AD16A_P, + AD16A_N => AD16A_N, + AD16B_P => AD16B_P, + AD16B_N => AD16B_N, + AD17A_P => AD17A_P, + AD17A_N => AD17A_N, + AD17B_P => AD17B_P, + AD17B_N => AD17B_N, + AD18A_P => AD18A_P, + AD18A_N => AD18A_N, + AD18B_P => AD18B_P, + AD18B_N => AD18B_N, + + DCOA1_P => DCOA1_P, + DCOA1_N => DCOA1_N, + DCOB1_P => DCOB1_P, + DCOB1_N => DCOB1_N, + + FRA1_P => FRA1_P , + FRA1_N => FRA1_N , + FRB1_P => FRB1_P , + FRB1_N => FRB1_N , + + ----ADC2--------------------------------------------- + AD21A_P => AD21A_P, + AD21A_N => AD21A_N, + AD21B_P => AD21B_P, + AD21B_N => AD21B_N, + AD22A_P => AD22A_P, + AD22A_N => AD22A_N, + AD22B_P => AD22B_P, + AD22B_N => AD22B_N, + AD23A_P => AD23A_P, + AD23A_N => AD23A_N, + AD23B_P => AD23B_P, + AD23B_N => AD23B_N, + AD24A_P => AD24A_P, + AD24A_N => AD24A_N, + AD24B_P => AD24B_P, + AD24B_N => AD24B_N, + AD25A_P => AD25A_P, + AD25A_N => AD25A_N, + AD25B_P => AD25B_P, + AD25B_N => AD25B_N, + AD26A_P => AD26A_P, + AD26A_N => AD26A_N, + AD26B_P => AD26B_P, + AD26B_N => AD26B_N, + AD27A_P => AD27A_P, + AD27A_N => AD27A_N, + AD27B_P => AD27B_P, + AD27B_N => AD27B_N, + AD28A_P => AD28A_P, + AD28A_N => AD28A_N, + AD28B_P => AD28B_P, + AD28B_N => AD28B_N, + + DCOA2_P => DCOA2_P, + DCOA2_N => DCOA2_N, + DCOB2_P => DCOB2_P, + DCOB2_N => DCOB2_N, + + FRA2_P => FRA2_P , + FRA2_N => FRA2_N , + FRB2_P => FRB2_P , + FRB2_N => FRB2_N , + + ----ADC3--------------------------------------------- + AD31A_P => AD31A_P, + AD31A_N => AD31A_N, + AD31B_P => AD31B_P, + AD31B_N => AD31B_N, + AD32A_P => AD32A_P, + AD32A_N => AD32A_N, + AD32B_P => AD32B_P, + AD32B_N => AD32B_N, + AD33A_P => AD33A_P, + AD33A_N => AD33A_N, + AD33B_P => AD33B_P, + AD33B_N => AD33B_N, + AD34A_P => AD34A_P, + AD34A_N => AD34A_N, + AD34B_P => AD34B_P, + AD34B_N => AD34B_N, + AD35A_P => AD35A_P, + AD35A_N => AD35A_N, + AD35B_P => AD35B_P, + AD35B_N => AD35B_N, + AD36A_P => AD36A_P, + AD36A_N => AD36A_N, + AD36B_P => AD36B_P, + AD36B_N => AD36B_N, + AD37A_P => AD37A_P, + AD37A_N => AD37A_N, + AD37B_P => AD37B_P, + AD37B_N => AD37B_N, + AD38A_P => AD38A_P, + AD38A_N => AD38A_N, + AD38B_P => AD38B_P, + AD38B_N => AD38B_N, + + DCOA3_P => DCOA3_P, + DCOA3_N => DCOA3_N, + DCOB3_P => DCOB3_P, + DCOB3_N => DCOB3_N, + + FRA3_P => FRA3_P , + FRA3_N => FRA3_N , + FRB3_P => FRB3_P , + FRB3_N => FRB3_N , + + ----ADC4--------------------------------------------- + AD41A_P => AD41A_P, + AD41A_N => AD41A_N, + AD41B_P => AD41B_P, + AD41B_N => AD41B_N, + AD42A_P => AD42A_P, + AD42A_N => AD42A_N, + AD42B_P => AD42B_P, + AD42B_N => AD42B_N, + AD43A_P => AD43A_P, + AD43A_N => AD43A_N, + AD43B_P => AD43B_P, + AD43B_N => AD43B_N, + AD44A_P => AD44A_P, + AD44A_N => AD44A_N, + AD44B_P => AD44B_P, + AD44B_N => AD44B_N, + AD45A_P => AD45A_P, + AD45A_N => AD45A_N, + AD45B_P => AD45B_P, + AD45B_N => AD45B_N, + AD46A_P => AD46A_P, + AD46A_N => AD46A_N, + AD46B_P => AD46B_P, + AD46B_N => AD46B_N, + AD47A_P => AD47A_P, + AD47A_N => AD47A_N, + AD47B_P => AD47B_P, + AD47B_N => AD47B_N, + AD48A_P => AD48A_P, + AD48A_N => AD48A_N, + AD48B_P => AD48B_P, + AD48B_N => AD48B_N, + + DCOA4_P => DCOA4_P, + DCOA4_N => DCOA4_N, + DCOB4_P => DCOB4_P, + DCOB4_N => DCOB4_N, + + FRA4_P => FRA4_P , + FRA4_N => FRA4_N , + FRB4_P => FRB4_P , + FRB4_N => FRB4_N , + + ADC_clk => ADC_clk_S, + ADCs_ready => ADCs_ready_S, + adcdata => adcdata_S + ); +ADCs_enable_S <= '1'; + +-- Superburst -------------------------------------------------------------- + +--IOBUF_superburst00: IOBUF port map (O => superburst_in_S(0), IO => INTCOM0_P, I => superburst_out_S(0), T => IcontrolPLLnot_S); +--IOBUF_superburst01: IOBUF port map (O => superburst_in_S(1), IO => INTCOM0_N, I => superburst_out_S(1), T => IcontrolPLLnot_S); +--IOBUF_superburst02: IOBUF port map (O => superburst_in_S(2), IO => INTCOM1_P, I => superburst_out_S(2), T => IcontrolPLLnot_S); +--IOBUF_superburst03: IOBUF port map (O => superburst_in_S(3), IO => INTCOM1_N, I => superburst_out_S(3), T => IcontrolPLLnot_S); +--IOBUF_superburst04: IOBUF port map (O => superburst_in_S(4), IO => INTCOM2_P, I => superburst_out_S(4), T => IcontrolPLLnot_S); +--IOBUF_superburst05: IOBUF port map (O => superburst_in_S(5), IO => INTCOM2_N, I => superburst_out_S(5), T => IcontrolPLLnot_S); +--IOBUF_superburst06: IOBUF port map (O => superburst_in_S(6), IO => INTCOM3_P, I => superburst_out_S(6), T => IcontrolPLLnot_S); +--IOBUF_superburst07: IOBUF port map (O => superburst_in_S(7), IO => INTCOM3_N, I => superburst_out_S(7), T => IcontrolPLLnot_S); +--IOBUF_superburst08: IOBUF port map (O => superburst_in_S(8), IO => INTCOM4_P, I => superburst_out_S(8), T => IcontrolPLLnot_S); +--IOBUF_superburst09: IOBUF port map (O => superburst_in_S(9), IO => INTCOM4_N, I => superburst_out_S(9), T => IcontrolPLLnot_S); +--IOBUF_superburst10: IOBUF port map (O => superburst_in_S(10), IO => INTCOM5_P, I => superburst_out_S(10), T => IcontrolPLLnot_S); +--IOBUF_superburst11: IOBUF port map (O => superburst_in_S(11), IO => INTCOM5_N, I => superburst_out_S(11), T => IcontrolPLLnot_S); +--IOBUF_superburst12: IOBUF port map (O => superburst_in_S(12), IO => INTCOM6_P, I => superburst_out_S(12), T => IcontrolPLLnot_S); +--IOBUF_superburst13: IOBUF port map (O => superburst_in_S(13), IO => INTCOM6_N, I => superburst_out_S(13), T => IcontrolPLLnot_S); +--IOBUF_superburst14: IOBUF port map (O => superburst_in_S(14), IO => INTCOM7_P, I => superburst_out_S(14), T => IcontrolPLLnot_S); +--IOBUF_superburst15: IOBUF port map (O => superburst_in_S(15), IO => INTCOM7_N, I => superburst_out_S(15), T => IcontrolPLLnot_S); + +INTCOM0_P <= superburst_out_S(0) when IcontrolPLLnot_S='0' else 'Z'; +INTCOM0_N <= superburst_out_S(1) when IcontrolPLLnot_S='0' else 'Z'; +INTCOM1_P <= superburst_out_S(2) when IcontrolPLLnot_S='0' else 'Z'; +INTCOM1_N <= superburst_out_S(3) when IcontrolPLLnot_S='0' else 'Z'; +INTCOM2_P <= superburst_out_S(4) when IcontrolPLLnot_S='0' else 'Z'; +INTCOM2_N <= superburst_out_S(5) when IcontrolPLLnot_S='0' else 'Z'; +INTCOM3_P <= superburst_out_S(6) when IcontrolPLLnot_S='0' else 'Z'; +INTCOM3_N <= superburst_out_S(7) when IcontrolPLLnot_S='0' else 'Z'; +INTCOM4_P <= superburst_out_S(8) when IcontrolPLLnot_S='0' else 'Z'; +INTCOM4_N <= superburst_out_S(9) when IcontrolPLLnot_S='0' else 'Z'; +INTCOM5_P <= superburst_out_S(10) when IcontrolPLLnot_S='0' else 'Z'; +INTCOM5_N <= superburst_out_S(11) when IcontrolPLLnot_S='0' else 'Z'; +INTCOM6_P <= superburst_out_S(12) when IcontrolPLLnot_S='0' else 'Z'; +INTCOM6_N <= superburst_out_S(13) when IcontrolPLLnot_S='0' else 'Z'; +INTCOM7_P <= superburst_out_S(14) when IcontrolPLLnot_S='0' else 'Z'; +INTCOM7_N <= superburst_out_S(15) when IcontrolPLLnot_S='0' else 'Z'; + + +superburst_out_S(15 downto 0) <= superburst_out0_S(15 downto 0) when superburst_startout_S='1' else '0' & superburst_out0_S(30 downto 16); + +process(rxSodaClk_S) +variable count_V : std_logic_vector(2 downto 0) := (others => '0'); +begin + if (rising_edge(rxSodaClk_S)) then + if (superburst_startout0_S='1') then + superburst_startout_S <= '1'; + count_V := (others => '0'); + elsif count_V="011" then + superburst_startout_S <= '0'; + elsif count_V/="111" then + count_V := count_V+1; + end if; + end if; +end process; + +superburst0_in_S(0) <= INTCOM0_P; +superburst0_in_S(1) <= INTCOM0_N; +superburst0_in_S(2) <= INTCOM1_P; +superburst0_in_S(3) <= INTCOM1_N; +superburst0_in_S(4) <= INTCOM2_P; +superburst0_in_S(5) <= INTCOM2_N; +superburst0_in_S(6) <= INTCOM3_P; +superburst0_in_S(7) <= INTCOM3_N; +superburst0_in_S(8) <= INTCOM4_P; +superburst0_in_S(9) <= INTCOM4_N; +superburst0_in_S(10) <= INTCOM5_P; +superburst0_in_S(11) <= INTCOM5_N; +superburst0_in_S(12) <= INTCOM6_P; +superburst0_in_S(13) <= INTCOM6_N; +superburst0_in_S(14) <= INTCOM7_P; +superburst0_in_S(15) <= INTCOM7_N; + +process(superburst_startin0_S,clear_superburst_startin_S) +begin + if clear_superburst_startin_S='1' then + superburst_startin1_S <= '0'; + elsif (rising_edge(superburst_startin0_S)) then + superburst_startin1_S <= '1'; + end if; +end process; +process(ADC_clk_S) +variable done_V : std_logic:= '0'; +begin + if (rising_edge(ADC_clk_S)) then + clear_superburst_startin_S <= '0'; + superburst_start_S <= '0'; + superburst_startin2_S <= superburst_startin1_S; + superburst_startin3_S <= superburst_startin2_S; + superburst_startin0sync_S <= superburst_startin0_S; + if (superburst_startin3_S='0') and (superburst_startin2_S='1') then + superburst_in_S(15 downto 0) <= superburst0_in_S(15 downto 0); + done_V := '0'; + elsif (superburst_startin2_S='1') and (superburst_startin0sync_S='0') and (done_V='0') then + superburst_in_S(30 downto 16) <= superburst0_in_S(14 downto 0); + clear_superburst_startin_S <= '1'; + superburst_start_S <= '1'; + done_V := '1'; + elsif (done_V='1') and (superburst_startin3_S='1') and (superburst_startin2_S='1') and (superburst_startin0sync_S='0') then + clear_superburst_startin_S <= '1'; + end if; + end if; +end process; + +-- GTX ---------------------------------------------------- + +LOS_S <= '1' when (LOS='1') or (MOD_DEF(0)='1') else '0'; +TX_DIS <= '0'; -- SFP always enabled + + +FEE_gtxModule1: FEE_gtxModule port map( + gtpClk_P => MGTREFCLK_P, + gtpClk_N => MGTREFCLK_N, + refclk_out => refclk_S, + sysClk => clock_S, + asyncclk => async_clock_S, + reset => GTX_reset_S, + disable_GTX_reset => disable_GTX_reset_S, + + TX_DLM => TX_DLM_S, + TX_DLM_WORD => TX_DLM_WORD_S, + RX_DLM => RX_DLM_S, + RX_DLM_WORD => RX_DLM_WORD_S, + + txAsyncClk => packet_out_clock_S, + txAsyncData => packet_out_data_S, + txAsyncDataWrite => packet_out_write_S, + txAsyncFirstData => packet_out_first_S, + txAsyncLastData => packet_out_last_S, + txAsyncFifoFull => packet_out_fifofull_S, + txUsrClk => open, + txLocked => GTX_txLocked_S, + + rxAsyncClk => packet_out_clock_S, + rxAsyncData => packet_in_data_S, + rxAsyncFirstData => packet_in_first_S, + rxAsyncLastData => packet_in_last_S, + rxAsyncDataRead => packet_in_read_S, + rxError => GTX_Error_S, + rxAsyncDataOverflow => open, + rxAsyncDataPresent => packet_in_present_S, + rxUsrClkdiv2 => rxUsrClkdiv2_S, + rxSodaClk => rxSodaClk_S, + rxSodaClk40 => rxSodaClk40_S, + rxLocked => GTX_rxLocked_S, + + gtpTxP0 => TX_P, + gtpTxN0 => TX_N, + gtpRxP0 => RX_P, + gtpRxN0 => RX_N, + GT0_QPLLOUTCLK_IN => '0', -- gt0_qplloutclk_S, + GT0_QPLLOUTREFCLK_IN => '0' -- gt0_qplloutrefclk_S, + ); + + + +process(rxSodaClk_S) +begin + if (rising_edge(rxSodaClk_S)) then + reset_rxSodaClk_S <= not startupready_S; + end if; +end process; + +gtx_common1: gtx_common port map( + QPLLREFCLKSEL_IN => "001", + GTREFCLK0_IN => refclk_S, + GTREFCLK1_IN => '0', + QPLLLOCK_OUT => gt0_qplllock_S, + QPLLLOCKDETCLK_IN => clock_S, + QPLLOUTCLK_OUT => gt0_qplloutclk_S, + QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_S, + QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_S, + QPLLRESET_IN => gt0_qpllreset_S + ); + +posedge_to_pulse_notintable: posedge_to_pulse port map( + clock_in => rxSodaClk_S, + clock_out => ADC_clk_S, + en_clk => '1', + signal_in => GTX_Error_GEO_S, + pulse => rxNotInTable_S); + + +-- SODA ---------------------------------------------------- +FEE_soda_client1: FEE_soda_client port map( + SYSCLK => clock_S, + SODACLK => rxSodaClk_S, + RESET => reset_rxSodaClk_S, + CLEAR => '0', + CLK_EN => '1', + RX_DLM_WORD_IN => RX_DLM_WORD_S, + RX_DLM_IN => RX_DLM_S, + TX_DLM_OUT => TX_DLM_S, + TX_DLM_WORD_OUT => TX_DLM_WORD_S, + TX_DLM_PREVIEW_OUT => open, + LINK_PHASE_IN => c_PHASE_H, + + START_OF_SUPERBURST => superburst_startout0_S, + SUPER_BURST_NR => superburst_out0_S, + SODA_CMD_VALID => SODA_cmd_valid_S, + SODA_CMD_WORD => SODA_cmd_word_S, + + SODA_DATA_IN => (others => '0'), + SODA_DATA_OUT => open, + SODA_ADDR_IN => (others => '0'), + SODA_READ_IN => '0', + SODA_WRITE_IN => '0', + SODA_ACK_OUT => open, + LEDS_OUT => open, + LINK_DEBUG_IN => (others => '0')); + +posedge_to_pulse_force_hit_out_S: posedge_to_pulse port map( + clock_in => rxSodaClk_S, + clock_out => ADC_clk_S, + en_clk => '1', + signal_in => force_hit_out0_S, + pulse => force_hit_out_S); + + +process(rxSodaClk_S) +begin + if (rising_edge(rxSodaClk_S)) then + reset_rxSodaClk_S <= not startupready_S; + end if; +end process; + +EnableDataTaking_S <= '1' when (SODA_cmd_valid_S='1') and (SODA_cmd_word_S(29)='1') else '0'; +DisableDataTaking_S <= '1' when (SODA_cmd_valid_S='1') and (SODA_cmd_word_S(28)='1') else '0'; +force_hit_out0_S <= '1' when (SODA_cmd_valid_S='1') and (SODA_cmd_word_S(26)='1') else '0'; + +datatakingprocess: process(rxSodaClk_S) +begin + if (rising_edge(rxSodaClk_S)) then + if DisableDataTaking_S='1' then + DataTaking_enabled_out_S <= '0'; + elsif EnableDataTaking_S='1' then + DataTaking_enabled_out_S <= '1'; + end if; + end if; +end process; + +process(ADC_clk_S,startupready_S) +variable enable_data_V : std_logic := '0'; +variable DataTaking_enabled_V : std_logic := '0'; +begin + if (startupready_S='0') then + enable_data_V := '0'; + enable_data_S <= '0'; + elsif (rising_edge(ADC_clk_S)) then + enable_data_S <= DataTaking_enabled_V; + DataTaking_enabled_V := DataTaking_enabled_in_S; + end if; +end process; + +process(ADC_clk_S) +variable counter : integer range 0 to ADCCLOCKFREQUENCY-1 := 0; +begin + if (rising_edge(ADC_clk_S)) then + if counter/=0 then + counter := counter-1; + onesecondpulse_S <= '0'; + else + counter := ADCCLOCKFREQUENCY-1; + onesecondpulse_S <= '1'; + end if; + end if; +end process; + +-- Feature extraction module ---------------------------------------------------- +process(ADC_clk_S) -- synchronise to 1 clock +begin + if (rising_edge(ADC_clk_S)) then + reset_FEE_ADCclk_S <= reset_FEE_S; + end if; +end process; + +FEE_module1: FEE_adc32_module port map( + clock => ADC_clk_S, + reset => reset_FEE_ADCclk_S, + enable_data => enable_data_S, + GEO => GEO_S, + ADCdata => adcdata_S, + superburst_start => superburst_start_S, + superburst_received => superburst_in_S, + force_hit => force_hit_S, + onesecondpulse => onesecondpulse_S, + rxNotInTable => rxNotInTable_S, + startupready => startupready_S, + request_init => request_init_S, + packet_in_data => FE_in_data_S, + packet_in_present => FE_in_present_S, + packet_in_read => FE_in_read_S, + packet_out_data => FE_out_data_S, + packet_out_first => FE_out_first_S, + packet_out_last => FE_out_last_S, + packet_out_write => FE_out_write_S, + packet_out_inpipe => FE_out_inpipe_S, + packet_out_fifofull => FE_out_fifofull_S, + errorbyte_out => errorbyte_S, + errorbyte_in => errorbyte_S, + smaart_in => TEMP_OUT_S, + smaart_out => TEMP_IN_S, + sysmon_data => sysmon_data_S, + sysmon_reset => sysmon_reset_S, + sysmon_address => sysmon_address_S, + sysmon_read => sysmon_read_S, + second_module_zero => vioword_S(9), + enable_waveform => enable_waveform_S, + compare_error => compare_error_S + ); + + +gen_nocombine: if NROFFEEFPGAS=1 generate + + GTX_txLocked_GEO_S <= GTX_txLocked_S; + GTX_Error_GEO_S <= GTX_Error_S; + GTX_rxLocked_GEO_S <= GTX_rxLocked_S; + LOS_GEO_S <= LOS_S; + + packet_out_clock_S <= ADC_clk_S; + FE_in_data_S <= packet_in_data_S; + FE_in_present_S <= packet_in_present_S; + packet_in_read_S <= FE_in_read_S; +-- FE_in_first_S <= packet_in_first_S; +-- FE_in_last_S <= packet_in_last_S; + packet_out_data_S <= FE_out_data_S; + packet_out_first_S <= FE_out_first_S; + packet_out_last_S <= FE_out_last_S; + packet_out_write_S <= FE_out_write_S; + FE_out_fifofull_S <= packet_out_fifofull_S; + +end generate; + +gen_combine: if NROFFEEFPGAS=2 generate + + packet_out_clock_S <= aurora_clock_S; + GTX_txLocked_GEO_S <= GTX_txLocked_S when GEO_S='0' else '1'; + GTX_rxLocked_GEO_S <= GTX_rxLocked_S when GEO_S='0' else '1'; + GTX_Error_GEO_S <= GTX_Error_S when GEO_S='0' else '0'; + LOS_GEO_S <= LOS_S when GEO_S='0' else '0'; + + FE_in_data_S <= split_local_S; +-- FE_in_first_S <= split_local_first_S; +-- FE_in_last_S <= split_local_last_S; + FE_in_present_S <= split_local_present_S; + split_local_read_S <= FE_in_read_S; + + split_in_S <= packet_in_data_S when GEO_S='0' else aurora_rx_data_S; + split_in_first_S <= packet_in_first_S when GEO_S='0' else aurora_rx_first_S; + split_in_last_S <= packet_in_last_S when GEO_S='0' else aurora_rx_last_S; + split_in_present_S <= packet_in_present_S when GEO_S='0' else aurora_rx_write_S; + packet_in_read_S <= split_in_read_S when GEO_S='0' else '1'; + + aurora_tx_data_S <= split_remote_wr_S when GEO_S='0' else comb_out_S; + aurora_tx_first_S <= split_remote_wr_first_S when GEO_S='0' else comb_out_first_S; + aurora_tx_last_S <= split_remote_wr_last_S when GEO_S='0' else comb_out_last_S; + aurora_tx_inpipe_S <= '0' when GEO_S='0' else comb_out_inpipe_S; + aurora_tx_write_S <= split_remote_wr_write_S when GEO_S='0' else comb_out_write_S; + FEE_fiforead2write1: FEE_fiforead2write + generic map( + BITS => 34) + port map( + clock => aurora_clock_S, + data_in(31 downto 0) => split_remote_S, + data_in(32) => split_remote_first_S, + data_in(33) => split_remote_last_S, + data_in_empty => split_remote_fifoempty_S, + data_in_read => split_remote_read_S, + data_out(31 downto 0) => split_remote_wr_S, + data_out(32) => split_remote_wr_first_S, + data_out(33) => split_remote_wr_last_S, + data_out_write => split_remote_wr_write_S, + data_out_allowed => split_remote_wr_allowed_S); + split_remote_fifoempty_S <= '1' when split_remote_present_S='0' else '0'; + split_remote_wr_allowed_S <= aurora_tx_allowed_S when GEO_S='0' else '1'; + + packet_out_data_S <= comb_out_S; + packet_out_write_S <= comb_out_write_S; + packet_out_first_S <= comb_out_first_S; + packet_out_last_S <= comb_out_last_S; + comb_out_fifofull_S <= packet_out_fifofull_S when GEO_S='0' else not aurora_tx_allowed_S; + + comb_local_S <= FE_out_data_S; + comb_local_first_S <= FE_out_first_S; + comb_local_last_S <= FE_out_last_S; + comb_local_write_S <= FE_out_write_S; + comb_local_inpipe_S <= FE_out_inpipe_S; + FE_out_fifofull_S <= comb_local_fifofull_S; + + comb_remote_S <= aurora_rx_data_S; + comb_remote_first_S <= aurora_rx_first_S; + comb_remote_last_S <= aurora_rx_last_S; + comb_remote_write_S <= aurora_rx_write_S when GEO_S='0' else '0'; + comb_remote_inpipe_S <= aurora_rx_inpipe_S when GEO_S='0' else '0'; + aurora_rx_almostfull_S <= comb_remote_almostfull_S when GEO_S='0' else '0'; + -- error <= '1' when aurora_rx_write_S='1' and comb_remote_fifofull_S='1' else '0'; + + aurora_dual_module1: aurora_dual_module port map( + stable_clock => clock_S, + reset => reset_FEE_S, + user_clock => aurora_clock_S, + tx_data => aurora_tx_data_S, + tx_first => aurora_tx_first_S, + tx_last => aurora_tx_last_S, + tx_write => aurora_tx_write_S, + tx_allowed => aurora_tx_allowed_S, + tx_inpipe => aurora_tx_inpipe_S, + rx_data => aurora_rx_data_S, + rx_first => aurora_rx_first_S, + rx_last => aurora_rx_last_S, + rx_write => aurora_rx_write_S, + rx_almostfull => aurora_rx_almostfull_S, + rx_inpipe => aurora_rx_inpipe_S, + locked => aurora_locked_S, + error => aurora_error_S, + RXP(0) => GT_B2A_0_P, + RXP(1) => GT_B2A_1_P, + RXN(0) => GT_B2A_0_N, + RXN(1) => GT_B2A_1_N, + TXP(0) => GT_A2B_0_P, + TXP(1) => GT_A2B_1_P, + TXN(0) => GT_A2B_0_N, + TXN(1) => GT_A2B_1_N, + GTXQ0_P => MGTREFCLK_P, + GTXQ0_N => MGTREFCLK_N, + gt0_refclk_in => refclk_S, + gt0_qplllock_in => gt0_qplllock_S, + gt0_qpllrefclklost_in => gt0_qpllrefclklost_S, + gt0_qpllreset_out => gt0_qpllreset_S, + GT_QPLLOUTCLK_IN => gt0_qplloutclk_S, + GT_QPLLOUTREFCLK_IN => gt0_qplloutrefclk_S + ); + + FEE_receive_split1: FEE_receive_split port map( + clock_in => aurora_clock_S, + clock_local => ADC_clk_S, + clock_remote => aurora_clock_S, + reset => reset_FEE_S, + GEO => GEO_S, + data_in => split_in_S, + data_in_first => split_in_first_S, + data_in_last => split_in_last_S, + data_in_present => split_in_present_S, + data_in_fifofull => split_in_fifofull_S, + data_in_read => split_in_read_S, + data_local => split_local_S, + data_local_first => split_local_first_S, + data_local_last => split_local_last_S, + data_local_present => split_local_present_S, + data_local_read => split_local_read_S, + data_remote => split_remote_S, + data_remote_first => split_remote_first_S, + data_remote_last => split_remote_last_S, + data_remote_present => split_remote_present_S, + data_remote_read => split_remote_read_S, + error => split_error_S); + + FEE_transmit_combine1: FEE_transmit_combine port map( + clock_local => ADC_clk_S, + clock_remote => aurora_clock_S, + clock_out => aurora_clock_S, + reset => reset_FEE_S, + GEO => GEO_S, + enable_waveform => enable_waveform_S, + data_local => comb_local_S, + data_local_first => comb_local_first_S, + data_local_last => comb_local_last_S, + data_local_write => comb_local_write_S, + data_local_inpipe => comb_local_inpipe_S, + data_local_fifofull => comb_local_fifofull_S, + data_remote => comb_remote_S, + data_remote_first => comb_remote_first_S, + data_remote_last => comb_remote_last_S, + data_remote_write => comb_remote_write_S, + data_remote_inpipe => comb_remote_inpipe_S, + data_remote_fifofull => comb_remote_fifofull_S, + data_remote_almostfull => comb_remote_almostfull_S, + data_out => comb_out_S, + data_out_first => comb_out_first_S, + data_out_last => comb_out_last_S, + data_out_write => comb_out_write_S, + data_out_inpipe => comb_out_inpipe_S, + data_out_fifofull => comb_out_fifofull_S, + error => comb_error_S); + +end generate; + +reboot1: reboot port map( + TRIGGER => doreboot_S, + SYSCLK => clock40MHz_S); + +pulse_wr: posedge_to_pulse port map( + clock_in => ADC_clk_S, + clock_out => clock_S, + en_clk => '1', + signal_in => compare_error_S, + pulse => compare_error1_S); + + +sem_module1: sem_module port map( + clk => clock40MHz_S, + status_heartbeat => status_heartbeat_S, + status_initialization => status_initialization_S, + status_observation => status_observation_S, + status_correction => status_correction_S, + status_classification => status_classification_S, + status_injection => status_injection_S, + status_essential => status_essential_S, + status_uncorrectable => status_uncorrectable_S); + +process(clock40MHz_S) +variable prev_status_correction_V : std_logic := '1'; +begin + if (rising_edge(clock40MHz_S)) then + doreboot_S <= '0'; + if (status_correction_S='0') and (prev_status_correction_V/='1') then + if status_uncorrectable_S='1' then + doreboot_S <= '1'; + end if; + end if; + if (compare_error1_S='1') and (startupready_S='1') then +--// doreboot_S <= '1'; + end if; + prev_status_correction_V := status_correction_S; + end if; +end process; + +superburst_lvds_out1 : OBUFDS + generic map( + IOSTANDARD => "LVDS") + port map( + O => MON2_P, + OB => MON2_N, + I => superburst_startout0_S); +superburst_lvds_out2 : OBUFDS + generic map( + IOSTANDARD => "LVDS") + port map( + O => MON1_P, + OB => MON1_N, + I => superburst_startout_S); + + + +-- pulse_wr: posedge_to_pulse port map( + -- clock_in => clock_S, + -- clock_out => clock_S, + -- en_clk => '1', + -- signal_in => vio_LMK04806_wr0_S, + -- pulse => vio_LMK04806_wr_S); + + +-- vio_debug1: vio_debug port map( + -- clk => clock_S, + -- probe_in0(0) => RDu_S, + -- probe_in1(0) => PLL_booting_busy_S, + -- probe_in2(0) => GTX_rxLocked_S, + -- probe_in3(0) => startupready_S, + -- probe_out0(0) => debug_reset_S, + -- probe_out1(0) => vio_LMK04806_wr0_S, + -- probe_out2 => vio_LMK04806_dta_S); + +vio36_1: vio36 port map( + clk => ADC_clk_S, + probe_out0 => vioword_S); + + +process(packet_out_clock_S) +begin + if (rising_edge(packet_out_clock_S)) then + if packet_out_write_S='1' then + debug_packet_out_data_S <= packet_out_data_S; + debug_packet_out_first_S <= packet_out_first_S; + debug_packet_out_last_S <= packet_out_last_S; + end if; + end if; +end process; + + +end Behavioral; + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/FEE_Kintex_ADCboard_Vivado.xpr b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/FEE_Kintex_ADCboard_Vivado.xpr new file mode 100644 index 0000000..953b628 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/FEE_Kintex_ADCboard_Vivado.xpr @@ -0,0 +1,1826 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Similar to Peformance_Explore, but enables the physical optimization step (phys_opt_design) with the Explore directive after routing. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/FEE_startup.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/FEE_startup.vhd new file mode 100644 index 0000000..44d7f6d --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/FEE_startup.vhd @@ -0,0 +1,428 @@ +--------------------------------------------------------------------------------- +-- Company: KVI/RUG/Groningen University +-- Engineer: Peter Schakel +-- Create Date: 27-10-2014 +-- Module Name: FEE_startup +-- Description: Startup FEE : reset, PLL, ADCs, GTX ... +-- Modifications: +-- 30-03-2015 GTX_LOS signal added +-- 09-09-2015 GTX_LOS synchronized and longer waiting times +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all ; +USE ieee.std_logic_arith.all ; +USE work.panda_package.all; +library UNISIM; +use UNISIM.VComponents.all; + +---------------------------------------------------------------------------------- +-- FEE_startup +-- +-- +-- Library: +-- +-- Generics: +-- +-- Inputs: +-- clock : stable main clock, frequency equal to ADC clock +-- ADCclock : clock for ADC data, stable after GTX lock / ADCs init +-- clock_from_PLL : clock from external PLL, frequency equal to ADC clock +-- reset : reset all +-- GEO : first ('0') or second ('1') FPGA +-- IcontrolPLL : this FPGA controls the PLL/jtag +-- PLL_booting : PLL initializing busy +-- GTX_LOS : Los Off Signal from SFP module +-- GTX_rxLocked : GTX receiver is locked to SODA frequency +-- GTX_txLocked : GTX transmitter is locked +-- GTX_error : error in GTX +-- PLL_locked : external PLL is locked +-- ADCs_ready : frame start signals from ADCs, LVDS negative +-- +-- Outputs: +-- ADCchip_init : start initialize ADC chip with serial interface +-- PLL_init : initialize the PLL +-- GTX_reset : reset the GTX +-- PLLuseGTXclock : use the GTX recovered clock as reference for the external PLL +-- ADCs_reset : reset the ADCs +-- FEE_reset : reset the FEE module (feature extraction / slow control / ...) +-- startupready : startup procedure is done +-- +-- Components: +-- +---------------------------------------------------------------------------------- + +entity FEE_startup is + port ( + clock : in std_logic; + ADCclock : in std_logic; + clock_from_PLL : in std_logic; + reset : in std_logic; + GEO : in std_logic; + IcontrolPLL : in std_logic; + ADCchip_init : out std_logic; + PLL_init : out std_logic; + PLL_booting : in std_logic; + GTX_LOS : in std_logic; + GTX_reset : out std_logic; + GTX_rxLocked : in std_logic; + GTX_txLocked : in std_logic; + GTX_error : in std_logic; + PLLuseGTXclock : out std_logic; + PLL_locked : in std_logic; + ADCs_reset : out std_logic; + ADCs_ready : in std_logic; + FEE_reset : out std_logic; + startupready : out std_logic + ); +end FEE_startup; + +architecture Behavioral of FEE_startup is + +type stage_type is (resetting,initPLL,waitPLLready,waitPLLlocked,resetGTX,waitGTXlocked,switchPLLclock,enableADCs,waitADCsready,enableFEE,readystate); +signal stage_S : stage_type := resetting; + +signal PLLclockdiv255_S : std_logic; +signal PLLclockdiv255sync0_S : std_logic; +signal PLLclockdiv255sync1_S : std_logic; +signal PLLclockdiv255_prev_S : std_logic; +signal PLLfrequencyERROR_S : std_logic; +signal PLLfrequcounter_V : integer range 0 to 255 := 0; + +signal IcontrolPLL_S : std_logic; +signal IcontrolPLL1_S : std_logic; +signal PLL_init_S : std_logic := '0'; +signal ADCchip_init_S : std_logic; +signal GTX_LOS_S : std_logic; +signal GTX_LOS0_S : std_logic; +signal GTX_reset_S : std_logic := '1'; +signal PLLuseGTXclock_S : std_logic := '0'; +signal PLL_booting_S : std_logic; +signal PLL_locked_S : std_logic; +signal GTX_rxLocked0_S : std_logic; +signal GTX_rxLocked_S : std_logic; +signal GTX_txLocked0_S : std_logic; +signal GTX_txLocked_S : std_logic; +signal GTX_error0_S : std_logic; +signal GTX_error_S : std_logic; +signal ADCs_ready0_S : std_logic; +signal ADCs_ready_S : std_logic; +signal ADCs_reset_S : std_logic := '1'; +signal FEE_reset_S : std_logic := '1'; +signal FEE_reset0_S : std_logic := '1'; +signal startupready_S : std_logic := '0'; + +-- attribute mark_debug : string; +-- attribute mark_debug of IcontrolPLL_S : signal is "true"; +-- attribute mark_debug of PLL_init_S : signal is "true"; +-- attribute mark_debug of ADCchip_init_S : signal is "true"; +-- attribute mark_debug of GTX_LOS_S : signal is "true"; +-- attribute mark_debug of GTX_reset_S : signal is "true"; +-- attribute mark_debug of PLLuseGTXclock_S : signal is "true"; +-- attribute mark_debug of PLL_booting_S : signal is "true"; +-- attribute mark_debug of PLL_locked_S : signal is "true"; +-- attribute mark_debug of GTX_rxLocked_S : signal is "true"; +-- attribute mark_debug of GTX_txLocked_S : signal is "true"; +-- attribute mark_debug of GTX_error_S : signal is "true"; +-- attribute mark_debug of ADCs_ready_S : signal is "true"; +-- attribute mark_debug of ADCs_reset_S : signal is "true"; +-- attribute mark_debug of FEE_reset_S : signal is "true"; +-- attribute mark_debug of startupready_S : signal is "true"; +-- attribute mark_debug of stage_S : signal is "true"; + +begin + + +-- FPGA1: +-- reset , PLL unlocked +-- initialize external PLL +-- wait for external PLL ready +-- wait for fiber locked +-- switch PLL reference to reconstructed clock +-- enable ADCs & enable FPGA2 +-- wait for ADCs ready +-- enable FEE module + +-- FPGA2 with fiber: +-- reset , PLL unlocked +-- wait for fiber locked +-- wait for enable ADCs +-- enable ADCs +-- wait for ADCs ready +-- enable FEE module + +-- FPGA2 without fiber: +-- reset , PLL unlocked +-- wait for aurora locked +-- wait for enable ADCs +-- enable ADCs +-- wait for ADCs ready +-- enable FEE module + +-- synchronize to the right clock, if necessary ----------------- +PLL_init <= PLL_init_S; +PLL_booting_S <= PLL_booting; +ADCchip_init <= ADCchip_init_S; +GTX_reset <= GTX_reset_S; +PLLuseGTXclock <= PLLuseGTXclock_S; +ADCs_reset <= ADCs_reset_S; +startupready <= startupready_S; + +process(clock) +begin + if (rising_edge(clock)) then + IcontrolPLL_S <= IcontrolPLL; + GTX_LOS_S <= GTX_LOS0_S; + GTX_LOS0_S <= GTX_LOS; + PLL_locked_S <= PLL_locked; + GTX_rxLocked0_S <= GTX_rxLocked; + GTX_rxLocked_S <= GTX_rxLocked0_S; + GTX_txLocked0_S <= GTX_txLocked; + GTX_txLocked_S <= GTX_txLocked0_S; + GTX_error0_S <= GTX_error; + GTX_error_S <= GTX_error0_S; + ADCs_ready0_S <= ADCs_ready; + ADCs_ready_S <= ADCs_ready0_S; + end if; +end process; + +process(ADCclock,reset) +begin + if reset='1' then + FEE_reset0_S <= '1'; + FEE_reset <= '1'; + elsif (rising_edge(ADCclock)) then + + FEE_reset0_S <= FEE_reset_S; + FEE_reset <= FEE_reset0_S; + end if; +end process; +-------------------------------------------------------------------------- + +-- check PLL frequency --------------------------------------------------- +process(clock_from_PLL) +variable counter_V : std_logic_vector(7 downto 0) := (others => '0'); +begin + if (rising_edge(clock_from_PLL)) then + PLLclockdiv255_S <= counter_V(7); + counter_V := counter_V+1; + end if; +end process; +process(clock) +begin + if (rising_edge(clock)) then + PLLfrequencyERROR_S <= '0'; + PLLclockdiv255sync0_S <= PLLclockdiv255_S; + PLLclockdiv255sync1_S <= PLLclockdiv255sync0_S; + PLLclockdiv255_prev_S <= PLLclockdiv255sync1_S; + if PLLclockdiv255_prev_S/=PLLclockdiv255sync1_S then + if (PLLfrequcounter_V<125) or (PLLfrequcounter_V>129) then + PLLfrequencyERROR_S <= '1'; + end if; + PLLfrequcounter_V <= 0; + elsif PLLfrequcounter_V<255 then + PLLfrequcounter_V <= PLLfrequcounter_V+1; + end if; + end if; +end process; +-------------------------------------------------------------------------- + +process(clock,reset,IcontrolPLL) +variable wait_V : std_logic_vector(17 downto 0); +variable waitADC_V : std_logic_vector(8 downto 0); +begin + if reset='1' then + stage_S <= resetting; + ADCchip_init_S <= '0'; + PLL_init_S <= '0'; + GTX_reset_S <= '1'; + PLLuseGTXclock_S <= '0'; + ADCs_reset_S <= '1'; + FEE_reset_S <= '1'; + startupready_S <= '0'; + IcontrolPLL1_S <= IcontrolPLL; + elsif (rising_edge(clock)) then + startupready_S <= '0'; + case stage_S is + when resetting => + wait_V := (others => '0'); + ADCchip_init_S <= '1'; + PLL_init_S <= '0'; + FEE_reset_S <= '1'; + GTX_reset_S <= '1'; + PLLuseGTXclock_S <= '0'; + ADCs_reset_S <= '1'; + FEE_reset_S <= '1'; + if IcontrolPLL_S='1' then + stage_S <= initPLL; + else + stage_S <= waitPLLlocked; + end if; + when initPLL => + ADCchip_init_S <= '0'; + PLL_init_S <= '1'; + FEE_reset_S <= '1'; + GTX_reset_S <= '1'; + PLLuseGTXclock_S <= '0'; + ADCs_reset_S <= '1'; + FEE_reset_S <= '1'; + if PLL_booting_S='1' then + wait_V := (others => '0'); + stage_S <= waitPLLready; + else + if wait_V(17)='0' then + wait_V := wait_V+1; + else + stage_S <= resetting; + end if; + end if; + when waitPLLready => + PLL_init_S <= '0'; + FEE_reset_S <= '1'; + GTX_reset_S <= '1'; + PLLuseGTXclock_S <= '0'; + ADCs_reset_S <= '1'; + FEE_reset_S <= '1'; + if PLL_booting_S='0' then + wait_V := (others => '0'); + stage_S <= resetGTX; + else + if wait_V(16)='0' then + wait_V := wait_V+1; + else + stage_S <= resetting; + end if; + end if; + when waitPLLlocked => + ADCchip_init_S <= '0'; + PLL_init_S <= '0'; + FEE_reset_S <= '1'; + GTX_reset_S <= '1'; + PLLuseGTXclock_S <= '0'; + ADCs_reset_S <= '1'; + FEE_reset_S <= '1'; + if ((IcontrolPLL_S='1') or (PLL_locked_S='1')) and (GTX_LOS_S='0') then + stage_S <= resetGTX; + end if; + when resetGTX => + ADCchip_init_S <= '0'; + PLL_init_S <= '0'; + FEE_reset_S <= '1'; + GTX_reset_S <= '1'; + PLLuseGTXclock_S <= '0'; + ADCs_reset_S <= '1'; + FEE_reset_S <= '1'; + if wait_V(3)='0' then + wait_V := wait_V+1; + else + wait_V := (others => '0'); + stage_S <= waitGTXlocked; + end if; + if GTX_LOS_S='1' then + stage_S <= waitPLLlocked; + end if; + when waitGTXlocked => + ADCchip_init_S <= '0'; + PLL_init_S <= '0'; + FEE_reset_S <= '1'; + GTX_reset_S <= '0'; + PLLuseGTXclock_S <= '0'; + ADCs_reset_S <= '1'; + FEE_reset_S <= '1'; + if (GTX_rxLocked_S='1') and (GTX_txLocked_S='1') and (GTX_LOS_S='0') then + stage_S <= switchPLLclock; + else + if wait_V(13)='1' then + wait_V := wait_V+1; + else + if (PLLfrequencyERROR_S='1') or (GTX_LOS_S='1') then + stage_S <= resetting; + end if; + end if; + end if; + when switchPLLclock => -- not necessary if IcontrolPLL_S='0', but does not harm + ADCchip_init_S <= '0'; + PLL_init_S <= '0'; + FEE_reset_S <= '1'; + GTX_reset_S <= '0'; + PLLuseGTXclock_S <= '1'; + ADCs_reset_S <= '1'; + FEE_reset_S <= '1'; + stage_S <= enableADCs; + when enableADCs => + ADCchip_init_S <= '0'; + PLL_init_S <= '0'; + FEE_reset_S <= '1'; + GTX_reset_S <= '0'; + PLLuseGTXclock_S <= '1'; + ADCs_reset_S <= '0'; + FEE_reset_S <= '1'; + wait_V := (others => '0'); + waitADC_V := (others => '0'); + stage_S <= waitADCsready; + when waitADCsready => + ADCchip_init_S <= '0'; + PLL_init_S <= '0'; + FEE_reset_S <= '1'; + GTX_reset_S <= '0'; + PLLuseGTXclock_S <= '1'; + ADCs_reset_S <= '0'; + FEE_reset_S <= '1'; + if PLLfrequencyERROR_S='1' then + stage_S <= resetting; + elsif (ADCs_ready_S='1') then + if waitADC_V(8)='1' then + stage_S <= enableFEE; + else + waitADC_V := waitADC_V+1; + end if; + elsif wait_V(17)='0' then + wait_V := wait_V+1; + waitADC_V := (others => '0'); + else + stage_S <= resetting; + end if; + when enableFEE => + PLL_init_S <= '0'; + FEE_reset_S <= '1'; + GTX_reset_S <= '0'; + PLLuseGTXclock_S <= '1'; + ADCs_reset_S <= '0'; + stage_S <= readystate; + when readystate => + PLL_init_S <= '0'; + FEE_reset_S <= '0'; + GTX_reset_S <= '0'; + PLLuseGTXclock_S <= '1'; + ADCs_reset_S <= '0'; + if PLLfrequencyERROR_S='1' then + stage_S <= resetting; + elsif (GTX_rxLocked_S='0') or (GTX_txLocked_S='0') or (GTX_LOS_S='1') then + stage_S <= waitPLLlocked; +stage_S <= resetting; + elsif ADCs_ready_S='0' then + ADCs_reset_S <= '1'; + ADCchip_init_S <= '0'; + stage_S <= enableADCs; + else + startupready_S <= '1'; + end if; + when others => + PLL_init_S <= '0'; + FEE_reset_S <= '1'; + GTX_reset_S <= '1'; + PLLuseGTXclock_S <= '0'; + ADCs_reset_S <= '1'; + FEE_reset_S <= '1'; + startupready_S <= '0'; + stage_S <= resetting; + end case; + if IcontrolPLL1_S/=IcontrolPLL_S then -- check if the same FPGA controls PLL + stage_S <= resetting; + end if; + IcontrolPLL1_S <= IcontrolPLL_S; + end if; +end process; + +end Behavioral; diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/LMK04806.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/LMK04806.vhd new file mode 100644 index 0000000..4cc432d --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/LMK04806.vhd @@ -0,0 +1,414 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library UNISIM; +use UNISIM.VComponents.all; +--use work.util_pack.ALL; + +entity LMK04806 is + generic( + CLK_DIV : integer := 2 -- slow down transfer + ); + PORT( + clock : in std_logic; --Master clock + reset : in std_logic; --reset + CLKu : out std_logic; --Clk to LMK + DATAu : out std_logic; --Data to LMK + LEu : out std_logic; --Data Latch to LMK + RDu : in std_logic; --Read back + SYNC : out std_logic; --Sync CLK outputs LMK + boot_PLL : in std_logic; --Start booting when set high + booting : out std_logic --busy signal + ); +end LMK04806; + +architecture Behavioral of LMK04806 is +constant NROFREGS : integer := 27; +type RomType is array (0 to NROFREGS-1) of std_logic_vector(31 downto 0); +type RomType32 is array (0 to 31) of std_logic_vector(31 downto 0); +-- parameters based on 'Clock design tool' from National Semiconductor +--CONSTANT TAB62M5 : RomType := -- 62.5MHz +-- ( +-- x"00020000", -- R0 (Reset=1) +-- x"00000500", -- R0 (Reset=0) +-- X"00000500", -- R0, out0,1 (Power_Down=0, input=VCO, delay=off, Reset=0, Div=40 OUT0,1 62.5MHz) +-- X"00000501", -- R1, out2,3 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=40 OUT2,3 62.5MHz) +-- X"00000502", -- R2, out4,5 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=40 OUT2,3 125MHz) GTX & gclk +-- X"00000503", -- R3, out6,7 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=40 OUT2,3 125MHz) GTX & gclk +-- X"00000504", -- R4, out8,9 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=40 OUT2,3 62.5MHz) +-- X"00000505", -- R5, out10,11 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=40 OUT2,3 62.5MHz) +-- x"11110006", -- R6 (OUT 3,2,1,0:LVDS, no delay) +-- x"11110007", -- R7 (OUT 7,6,5,4:LVDS, no delay) +-- x"11110008", -- R8 (OUT 11,10,9,8:LVDS, no delay) +-- x"55555549", -- R9 (fixed pattern) +-- x"0000806A", -- R10 (OSCout1=LVPECL-700mV, OSCout0=disabled, OSCout1,0=disabled, OSC0,1=bypass_divider, OSCoutDIV=8, VCOdiv=1, FEEDbackMUX=CLKout6) +-- x"4402800B", -- R11 (mode=singlePLL, 0delay, SYNC=enabled, active=high, SYNC_QUAL=1?, auto_sync=1, sSYNC=input, externalXTAL=disabled) +-- x"030C00aC", -- R12 (LD=0, no force SYNC, no DAC tracking, no HOLDOVER) +-- x"3B00800D", -- R13 (HOLDOVER pin=uwire, status pins=0, no DLD1DET, status CLKin=0, CLKin not used) +-- x"0000000E", -- R14 (LOS after 1200ns, CLKin not used, no DAC trip) +-- x"8000800F", -- R15 (MAN_DAC=512, disabled, HOLDOVER count=512, disabled) +-- x"01550410", -- R16 (xtal=1.65V, fixed pattern) +-- x"000000D8", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm, delay=0ps, window=40ns) -- DD0000D8 +-- x"010100D9", -- R25 (DAC clkdiv=4, PLL2 DLD cont=1024) +-- x"83A8001A", -- R26 (PLL2 window=3.7ns, no 2*frequ, neg slope, chargepump=100u, PLL2 DLD count=8192???, CPout2=active) +-- x"0008003B", -- R27 (PLL1 not used: neg slope, div=1, PLL1 DLD count=8192, CPout1=tristate) +-- x"0010005C", -- R28 (PLL2 R_divider=1, PLL1 N_divider=1) +-- x"0000015D", -- R29 (OSCin=0..63MHz, <100MHz, PLL2 N_CALdivider=10) +-- x"0400015E", -- R30 (N_prescaler=4, N_divider=10) +---- X"00000500", -- R0, again to force SYNC (Power_Down=0, input=VCO, delay=off, Reset=0, Div=40 OUT0,1 62.5MHz) ??? +-- x"0002001F" -- R31 (ReadbackReg=0 Regs:unlocked) 001F001F +-- ); +-- CONSTANT TAB80 : RomType := -- 80MHz + -- ( + -- x"00020000", -- R0 (Reset=1) + -- x"00000400", -- R0 (Reset=0) + -- X"00000400", -- R0, out0,1 (Power_Down=0, input=VCO, delay=off, Reset=0, Div=40 OUT0,1 80MHz) + -- X"00000401", -- R1, out2,3 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz) + -- X"00000402", -- R2, out4,5 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz) GTX & gclk + -- X"00000403", -- R3, out6,7 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz) GTX & gclk + -- X"00000404", -- R4, out8,9 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz) + -- X"00000405", -- R5, out10,11 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=40 OUT2,3 80MHz) + -- x"11110006", -- R6 (OUT 3,2,1,0:LVDS, no delay) + -- x"11110007", -- R7 (OUT 7,6,5,4:LVDS, no delay) + -- x"11110008", -- R8 (OUT 11,10,9,8:LVDS, no delay) + -- x"55555549", -- R9 (fixed pattern) + -- x"0000806A", -- R10 (OSCout1=LVPECL-700mV, OSCout0=disabled, OSCout1,0=disabled, OSC0,1=bypass_divider, OSCoutDIV=8, VCOdiv=1, FEEDbackMUX=CLKout6) + -- x"4400800B", -- R11 (mode=singlePLL, 0delay, SYNC=enabled, active=high, SYNC_QUAL=0?, auto_sync=1, sSYNC=input, externalXTAL=disabled) + -- x"030000aC", -- R12 (LD[31..27]=0, LD_type[26..24]=3, SYNC_PLLX_DLD[23..22]=0, EN_TRACK[8]=disable, force_SYNC, no DAC tracking, no HOLDOVER) + -- x"6B00800D", --3B... R13 (HOLDOVER pin=uwire, status pins=0, no DLD1DET, status CLKin=0, CLKin not used) + -- x"0000000E", -- R14 (LOS after 1200ns, CLKin not used, no DAC trip) + -- x"8000800F", -- R15 (MAN_DAC=512, disabled, HOLDOVER count=512, disabled) + -- x"01550410", -- R16 (xtal=1.65V, fixed pattern) + -- x"000000D8", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm, delay=0ps, window=40ns) -- DD0000D8 + -- x"010100D9", -- R25 (DAC clkdiv=4, PLL2 DLD cont=1024) + -- x"83A8001A", -- R26 (PLL2 window=3.7ns, no 2*frequ, neg slope, chargepump=100u, PLL2 DLD count=8192???, CPout2=active) + -- x"0008003B", -- R27 (PLL1 not used: neg slope, div=1, PLL1 DLD count=8192, CPout1=tristate) + -- x"0010005C", -- R28 (PLL2 R_divider=1, PLL1 N_divider=1) + -- x"0100015D", -- R29 (OSCin=63..127MHz, <100MHz, PLL2 N_CALdivider=10) + -- x"0400015E", -- R30 (N_prescaler=4, N_divider=10) +--//-- X"00000400", -- R0, again to force SYNC (Power_Down=0, input=VCO, delay=off, Reset=0, Div=40 OUT0,1 80MHz) ??? + -- x"000b001F" -- R31 (ReadbackReg=11 Regs:unlocked) 001F001F + -- ); + + +-- CONSTANT TAB_orig : RomType := -- test + -- ( + -- x"00020000", -- R0 (Reset=1) + -- x"00000400", -- R0 (Reset=0) + -- X"00000400", -- R0, out0,1 (Power_Down=0, input=VCO, delay=off, Reset=0, Div=32 OUT0,1 80MHz) + -- X"00000401", -- R1, out2,3 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz) + -- X"00000402", -- R2, out4,5 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz) GTX & gclk + -- X"00000403", -- R3, out6,7 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz) GTX & gclk + -- X"00000404", -- R4, out8,9 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz) + -- X"00000405", -- R5, out10,11 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz) + -- x"11110006", -- R6 (OUT 3,2,1,0:LVDS, no delay) + -- x"11110007", -- R7 (OUT 7,6,5,4:LVDS, no delay) x"61160007", for cmos_out + -- x"11110008", -- R8 (OUT 11,10,9,8:LVDS, no delay) + -- x"55555549", -- R9 (fixed pattern) + -- x"1000480A", -- R10 (OSCout1[31..30]=700mV, OSCout0[27..24]=disabled, OSCout1,0[23..22]=disabled, OSC0,1[21..20]=bypass_divider, PD_OSCin[19]=0(powered), OSCoutDIV[18..16]=8, VCOdiv[12]=select, EN_FEEDBACK_MUX[11]=1, VCOdiv[10..8]=8 FEEDbackMUX[7..5]=3=CLKout6) + -- x"4402800B", -- R11 (mode[31..27]=singlePLL+0delay, SYNC[26]=enabled, NO_SYNC_CLKoutX_Y[25..20]=0, SYNC_mux[19..18]=0, SYNC_QUAL[17]=1, sync[16]=0=high, auto_sync[15]=1, sSYNC[14..12]=input, externalXTAL[5]=disabled) + -- x"0300006C", -- R12 (LD[31..27]=0, LD_type[26..24]=3, SYNC_PLLX_DLD[23..22]=0, EN_TRACK[8]=disable, HOLDOVER[7..6]=disable) + -- x"9300000D", --..3B R13 (HOLDOVER_pin[31..27]=uwire, output[26..25]=pushpull, CLK1_mux[22..20]=0, CLK0_mux[18..16]=0, DLD1DET[15]=0,CLKin[14..12]=0, CLKin_mode[11..9]=0, CLKin[8]=high, EN_CLKinX[6..5]=0 + -- x"0000000E", -- R14 (LOS[31..30] after 1200ns, LOS[28]=disabled, CLKin[26..24], CLKinX_BUF_TYPE[21..20]=0, DAC_trip[19..14][11..6]=0, EN_VTUNE_RAIL_DET[5]=0) + -- x"0000004F", -- R15 (MAN_DAC [31:22]=0 (sets dac value when in manual DAC mode, set to 0), EN_MAN_DAC[20]=0 (enables manual DAC), HOLDOVER DLD+CNT[19:6]=1 (how many clocks of PLL1 PDF before HOLDOVER mode is exited. 1, I guess, if we're not using holdover mode), FORCE_HOLDOVER[5]=0,(diabled)) + -- x"01550410", -- R16 (xtal=1.65V, fixed pattern) + -- x"00000018", -- R24 (PLL2_C4_LF[31:28]=0(10pF), PLL2_C3_LF[27:23]=0(10pF), PLL2_R4_LF[22:20]=0(200 Ohm), PLL2_R3_LF[18:16]=0(200 Ohm), PLL1_N_DLY[14:12]=0 (PLL1, doesn't matter and setting to 0 delay), PLL1_R_DLY[10:8]=0(same), PLL1_WIND_SIZE[7:6]=0 (setting 0) + -- x"00400059", -- R25 (DAC_CLK_DIV[31:22]=1 (PLL1 relevant, setting to 1), PLL1_DLD_CNT[19:6]=1, + -- x"8fA0801A", -- R26 (PLL2 window[31:30]=3.7ns, PLL2_doublefreq[29]=0, slope[28]=neg, chargepump[27..26]=max?100u, PLL2 DLD count19..6]=1024, CPout2[5]=active) + -- x"0008003B", -- R27 (PLL1 not used: slope[28]=neg, div=1, PLL1 DLD count=8192, CPout1=tristate) + -- x"0018001C", -- R28 (PLL2 R_divider[31..20]=1, PLL1 N_divider[19..6]=maxbit) + -- x"0100009D", -- R29 (OSCin[26..24]=63..127MHz, phasedet[23]<100MHz, PLL2 N_CALdivider[22..5]=DIVX*PLL2_N/PLL2_P=32*1/8=4) + -- x"0000003E", -- R30 (N_prescaler=PLL2_P[26:24]=8, not used, PLL1_N_divider[22..5]=1) +-- x"00000f00", -- R0, again to force SYNC (Power_Down=0, input=VCO, delay=off, Reset=0, Div=40 OUT0,1 80MHz) ??? + -- x"002b001F" -- R31 (LE must be high ReadbackReg=2 Regs:unlocked) 001F001F + -- ); + +constant TAB : RomType := + ( + x"00020000", -- R0 (Reset=1) + x"00000400", -- R0 (Reset=0) + X"00000400", -- R0, out0,1 (Power_Down=0, input=VCO, delay=off, Reset=0, Div=32 OUT0,1 80MHz) + X"00000401", -- R1, out2,3 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz) + X"00000402", -- R2, out4,5 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz) GTX & gclk + X"00000403", -- R3, out6,7 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz) GTX & gclk + X"00000404", -- R4, out8,9 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz) + X"00000405", -- R5, out10,11 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz) + x"11110006", -- R6 (OUT 3,2,1,0:LVDS, no delay) + x"11110007", -- R7 (OUT 7,6,5,4:LVDS, no delay) x"61160007", for cmos_out + x"11110008", -- R8 (OUT 11,10,9,8:LVDS, no delay) + x"55555549", -- R9 (fixed pattern) + x"1000486A", -- R10 (OSCout1[31..30]=700mV, OSCout0[27..24]=disabled, OSCout1,0[23..22]=disabled, OSC0,1[21..20]=bypass_divider, PD_OSCin[19]=0(powered), OSCoutDIV[18..16]=8, VCOdiv[12]=select, EN_FEEDBACK_MUX[11]=1, VCOdiv[10..8]=8 FEEDbackMUX[7..5]=3=CLKout6) + x"4402a00B", -- R11 (mode[31..27]=singlePLL+0delay, SYNC[26]=enabled, NO_SYNC_CLKoutX_Y[25..20]=0, SYNC_mux[19..18]=0, SYNC_QUAL[17]=1, sync[16]=0=high, auto_sync[15]=1, sSYNC[14..12]=input, externalXTAL[5]=disabled) + x"030C006C", -- R12 (LD[31..27]=0, LD_type[26..24]=3, SYNC_PLLX_DLD[23..22]=0, EN_TRACK[8]=disable, HOLDOVER[7..6]=disable) + x"2300000D", --..3B R13 (HOLDOVER_pin[31..27]=status, output[26..25]=pushpull, CLK1_mux[22..20]=0, CLK0_mux[18..16]=0, DLD1DET[15]=0,CLKin[14..12]=0, CLKin_mode[11..9]=0, CLKin[8]=high, EN_CLKinX[6..5]=0 + x"0000000E", -- R14 (LOS[31..30] after 1200ns, LOS[28]=disabled, CLKin[26..24], CLKinX_BUF_TYPE[21..20]=0, DAC_trip[19..14][11..6]=0, EN_VTUNE_RAIL_DET[5]=0) + x"0000004F", -- R15 (MAN_DAC [31:22]=0 (sets dac value when in manual DAC mode, set to 0), EN_MAN_DAC[20]=0 (enables manual DAC), HOLDOVER DLD+CNT[19:6]=1 (how many clocks of PLL1 PDF before HOLDOVER mode is exited. 1, I guess, if we're not using holdover mode), FORCE_HOLDOVER[5]=0,(diabled)) + x"01550410", -- R16 (xtal=1.65V, fixed pattern) + x"88110018", -- R24 (PLL2_C4_LF[31:28]=8(29pF), PLL2_C3_LF[27:23]=0(29pF), PLL2_R4_LF[22:20]=1(1k), PLL2_R3_LF[18:16]=1(1k), PLL1_N_DLY[14:12]=0 (PLL1, doesn't matter and setting to 0 delay), PLL1_R_DLY[10:8]=0(same), PLL1_WIND_SIZE[7:6]=0 (setting 0) + x"00400059", -- R25 (DAC_CLK_DIV[31:22]=1 (PLL1 relevant, setting to 1), PLL1_DLD_CNT[19:6]=1, + x"87A0801A", -- R26 (PLL2 window[31:30]=3.7ns, PLL2_doublefreq[29]=0, slope[28]=neg, chargepump[27..26]=11=3200,01=400,00=100u, PLL2 DLD count19..6]=1024, CPout2[5]=active) + x"0008003B", -- R27 (PLL1 not used: slope[28]=neg, div=1, PLL1 DLD count=8192, CPout1=tristate) + x"0018001C", -- R28 (PLL2 R_divider[31..20]=1, PLL1 N_divider[19..6]=maxbit) + x"0100009D", -- R29 (OSCin[26..24]=63..127MHz, phasedet[23]<100MHz, PLL2 N_CALdivider[22..5]=DIVX*PLL2_N/PLL2_P=32*1/8=4) + x"0000003E", -- R30 (N_prescaler=PLL2_P[26:24]=8, not used, PLL1_N_divider[22..5]=1) +-- x"00000f00", -- R0, again to force SYNC (Power_Down=0, input=VCO, delay=off, Reset=0, Div=40 OUT0,1 80MHz) ??? + x"002b001F" -- R31 (LE must be high ReadbackReg=2 Regs:unlocked) 001F001F + ); + +--CONSTANT TAB_Pawel : RomType := -- |Pawel +-- ( +-- x"80020140", --R0 (CLKout_1_PD = 1, RESET=1, CLKout0_1_DIV=10) +-- x"000003C0", --R0 (CLKout0_1_DIV=30) +-- x"000003C0", --R0 (CLKout0_1_DIV=30) +-- x"000003C0", --R0 (CLKout0_1_DIV=30) +-- x"000003C1", --R1 (CLKout2_3_DIV=30) +-- x"00000602", --R2 (CLKout4_5_DIV=48) --35 +-- --00000000000000000000010110100010 +-- x"00000603", --R3 (CLKout6_7_DIV=48) +-- x"000003C4", --R4 (CLKout8_9_DIV=30) +-- x"000003C5", --R5 (CLKout10_11_DIV=30) +-- x"11110006", --R6 (CLKout3_TYPE=1, CLKout2_TYPE=1, CLKout1_TYPE=1, CLKout0_TYPE=1) +-- x"11110007", --R7 (CLKout7_TYPE=1, CLKout6_TYPE=1, CLKout5_TYPE=1, CLKout4_TYPE=1) +-- x"11110008", --R8 (CLKout11_TYPE=1, CLKout10_TYPE=1, CLKout9_TYPE=1, CLKout8_TYPE=1) +-- x"55555549", --R9 (fixed pattern) +-- x"910141CA", --R10 (OSCout1_LVPECL_AMP=3(-1600mV), OSCout0_TYPE=1(LVDS), EN_OSCout1[23]=0 (disabled), EN_OSCout0[22]=0 (disabled), OSCout1_MUX[21]=0 (bypass MUX), OSC_out1_MUX[20]=0(bypass MUX), PD_OSCin[19]=0(powered), OSCout_DIV[18:16]=2(divide by 2), VCO_MUX[12]=0(select VCO), EN_FEEDBACK_MUX[11]=0 (feedback mux powered down), VCO_DIV[10:8]=2(divide by 2), FEEDBACK_MUX[7:5]=3(guess it doens't matter. taking FBCLKin) +-- x"2400800D", --R11 +-- x"130C006C", --R12 (LD_MUX[31:27]=2 (PLL2 DLD (digital lock detect)), LD_TYPE[26:24]=3 (output push-pull), SYNC_PLL2_DLD[23]=0? (sync not forced), SYNC_PLL1_DLD[22]=0? (sync not forced), EN_TRACK[8]=0 (tracks the PLL1` which we're not using, set to 0), HOLDOVER_MODE[7:6]=1 (disabled)) +-- x"0301880D", --R13 (holdover_mux[31:27]=0 (logic low), holdover_type[26:24]=3(output (push-pull)), status_clkin1_mux[22:20]=0(logic low), status_clkin0_Type[18:16]=1 (they're both disconnected as far as I can tell, thus we want pull-up), disable_dld1_det[15]=1(disables, because we won't use PLL1), status+clkin0_mux[14:12]=0(logic low), clkin_select_mode[11:9]=4(I think this is the case, take auto, because I don't think it will be used), clk_in_select_inv[7]=0 (not inversed), en_clkin1[6]=0 (disable), en_clkin0[5]=0 (diable) +-- x"013FC00E", --R14 !!!see above!!! +-- x"0000004F", --R15 (MAN_DAC [31:22]=0 (sets dac value when in manual DAC mode, set to 0), EN_MAN_DAC[20]=0 (enables manual DAC), HOLDOVER DLD+CNT[19:6]=1 (how many clocks of PLL1 PDF before HOLDOVER mode is exited. 1, I guess, if we're not using holdover mode), FORCE_HOLDOVER[5]=0,(diabled)) +-- x"01550410", --R16 (XTAL_LVL[31:30]=0 (sets the peak amplitude on the tunable crystal. --assuming 0, the lowest)) +-- x"00000018", --R24 (PLL2_C4_LF[31:28]=0(10pF), PLL2_C3_LF[27:23]=0(10pF), PLL2_R4_LF[22:20]=0(200 Ohm), PLL2_R3_LF[18:16]=0(200 Ohm), PLL1_N_DLY[14:12]=0 (PLL1, doesn't matter and setting to 0 delay), PLL1_R_DLY[10:8]=0(same), PLL1_WIND_SIZE[7:6]=0 (setting 0) +-- x"00400059", --R25 (DAC_CLK_DIV[31:22]=1 (PLL1 relevant, setting to 1), PLL1_DLD_CNT[19:6]=1, +-- x"4FA8001A", --R26 (PLL2_WIND_SIZE[31:30]=2 (has to be =2 according to documentation), EN_PLL2_REF_2X[29]=0 (according to schematics), PLL2_CP_POL[28]=0 (must be negative to use internal VCO), PLL2_CP_GAIN[27:26]=3 (according to LMK03806), PLL2_DLD_CNT[19:6]=2000 (leftmost bit =1 according to LMK03806), PLL2_CP_TRI=0 (according to LMK03806) +-- x"0000005B", --R27 (PLL1_CP_POL[28]=0, PLL1_CP_GAIN[27:26]=0, CLKin1_PreR_DIV[23:22]=0, CLKin0_PreR_DIV[21:20]=0, PLL1_R[19:6]=1, PLL1_CP_TRI=0(because PLL1_CP_GAIN is not equal to XXXX) +-- x"0010005C", --R28 (PLL2_R[31:20]=1, PLL1_N[19:6]=1(not used)) +-- --!!! 0000 0000 0XXX XXXX XXXX XXXX XX11 1101 --R29 +-- --x"0000003D", --R29 !!!see above!!! +-- x"0100021D", --R29 +-- x"0200021E", --R30 (PLL2_P[26:24]=2, PLL2_N[22:5]=16) +-- x"001F001F" --R31 (READBACK_LE[21] (guessing low)=0, READBACK_ADDRESS[20:16]=31 (from LMK03806), uWire_LOCK[5]=0 (from LMK03806)n +-- ); + +type stage_type is (waiting,starting,DATAu_set,CLKu_high,CLKu_low,LEu_wait, + LEu_high,LEu_high0,LEu_high1,LEu_high2,LEu_high3,LEu_high4,LEu_high5,LEu_low,reading0,reading1,lockdelay); +signal stage_S : stage_type := waiting; + +signal cnt_dly : std_logic_vector(3 downto 0) := (others => '0'); +signal regcount_S : integer range 0 to NROFREGS-1 := 0; +signal bitcount_S : integer range 0 to 31 := 31; +signal lockcount_S : std_logic_vector(11 downto 0) := (others => '0'); + +signal boot_PLL_S : std_logic := '0'; +signal CLKu_S : std_logic; +signal DATAu_S : std_logic; +signal LEu_S : std_logic; +signal SYNC_S : std_logic; + + +-------------------------------------------------------------------- +BEGIN + + +booting <= '0' when (stage_S=waiting) else '1'; +SYNC_S <= '0'; +SYNC <= SYNC_S; +CLKu <= CLKu_S; +DATAu <= DATAu_S; +LEu <= LEu_S; +SYNC <= SYNC_S; + +--****************************************************************** +-- PLL BOOT STATEMACHINE +--****************************************************************** + +process(clock,reset) +begin + if reset = '1' then + stage_S <= waiting; + CLKu_S <= '0'; + DATAu_S <= '0'; + LEu_S <= '0'; + elsif rising_edge(clock) then +--// boot_PLL_S <= boot_PLL; + case stage_S is + when waiting => + CLKu_S <= '0'; + DATAu_S <= '0'; + LEu_S <= '0'; + bitcount_S <= 31; + regcount_S <= 0; +--// if (boot_PLL='1') then --and (boot_PLL_S='0') then + if (boot_PLL='1') or (boot_PLL_S='1') then --and (boot_PLL_S='0') then + stage_S <= starting; + end if; + cnt_dly <= (others => '0'); + lockcount_S <= (others => '0'); + when starting => + CLKu_S <= '0'; + DATAu_S <= '0'; + LEu_S <= '0'; + stage_S <= DATAu_set; + when DATAu_set => + CLKu_S <= '0'; + DATAu_S <= TAB(regcount_S)(bitcount_S); + LEu_S <= '0'; + if cnt_dly > CLK_DIV then + cnt_dly <= (others => '0'); + stage_S <= CLKu_high; + else + cnt_dly <= cnt_dly + 1; + end if; + when CLKu_high => + CLKu_S <= '1'; + LEu_S <= '0'; + if cnt_dly > CLK_DIV then + cnt_dly <= (others => '0'); + stage_S <= CLKu_low; + else + cnt_dly <= cnt_dly + 1; + end if; + when CLKu_low => + CLKu_S <= '0'; + LEu_S <= '0'; + cnt_dly <= (others => '0'); + if bitcount_S>0 then + bitcount_S <= bitcount_S-1; + stage_S <= DATAu_set; + else + stage_S <= LEu_wait; + end if; + when LEu_wait => + CLKu_S <= '0'; + LEu_S <= '0'; + if cnt_dly > CLK_DIV then + cnt_dly <= (others => '0'); + stage_S <= LEu_high; + else + cnt_dly <= cnt_dly + 1; + end if; + when LEu_high => + CLKu_S <= '0'; + LEu_S <= '1'; + if cnt_dly > CLK_DIV then + cnt_dly <= (others => '0'); + if conv_integer(unsigned(TAB(regcount_S)(4 downto 0)))<6 then + stage_S <= LEu_high0; + else + stage_S <= LEu_low; + end if; + else + cnt_dly <= cnt_dly + 1; + end if; + + when LEu_high0 => + CLKu_S <= '1'; + LEu_S <= '1'; + if cnt_dly > CLK_DIV then + cnt_dly <= (others => '0'); + stage_S <= LEu_high1; + else + cnt_dly <= cnt_dly + 1; + end if; + when LEu_high1 => + CLKu_S <= '0'; + LEu_S <= '1'; + if cnt_dly > CLK_DIV then + cnt_dly <= (others => '0'); + stage_S <= LEu_high2; + else + cnt_dly <= cnt_dly + 1; + end if; + when LEu_high2 => + CLKu_S <= '1'; + LEu_S <= '1'; + if cnt_dly > CLK_DIV then + cnt_dly <= (others => '0'); + stage_S <= LEu_high3; + else + cnt_dly <= cnt_dly + 1; + end if; + when LEu_high3 => + CLKu_S <= '0'; + LEu_S <= '1'; + if cnt_dly > CLK_DIV then + cnt_dly <= (others => '0'); + stage_S <= LEu_high4; + else + cnt_dly <= cnt_dly + 1; + end if; + when LEu_high4 => + CLKu_S <= '1'; + LEu_S <= '1'; + if cnt_dly > CLK_DIV then + cnt_dly <= (others => '0'); + stage_S <= LEu_high5; + else + cnt_dly <= cnt_dly + 1; + end if; + when LEu_high5 => + CLKu_S <= '0'; + LEu_S <= '1'; + if cnt_dly > CLK_DIV then + cnt_dly <= (others => '0'); + stage_S <= LEu_low; + else + cnt_dly <= cnt_dly + 1; + end if; + + when LEu_low => + CLKu_S <= '0'; +-- LEu_S <= '0'; + if regcount_S + CLKu_S <= '0'; + LEu_S <= '1'; + if cnt_dly > CLK_DIV then + cnt_dly <= (others => '0'); + stage_S <= reading1; + else + cnt_dly <= cnt_dly + 1; + end if; + when reading1 => + CLKu_S <= '1'; + LEu_S <= '1'; + if cnt_dly > CLK_DIV then + cnt_dly <= (others => '0'); + if bitcount_S>0 then + bitcount_S <= bitcount_S-1; + stage_S <= reading0; + else + bitcount_S <= 31; + stage_S <= lockdelay; + end if; + else + cnt_dly <= cnt_dly + 1; + end if; + when lockdelay => + if lockcount_S(lockcount_S'left)='0' then + lockcount_S <= lockcount_S+1; + else + stage_S <= waiting; + end if; + when others => + stage_S <= waiting; + end case; + end if; +end process; + + + +END Behavioral; + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/ADC_SLOW_CTRL.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/ADC_SLOW_CTRL.vhd new file mode 100644 index 0000000..8405b66 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/ADC_SLOW_CTRL.vhd @@ -0,0 +1,155 @@ +----------------------------------------------------------- +-- LTM9009 SLOW CONTROL UNIT -- +----------------------------------------------------------- +-- Device: xc7vlx160t-1ffG484 -- +-- +-- created by P. Marciniewski -- +-- Uppsala University, Dept of Physics and Astronomy -- +----------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use work.panda_pkg.all; +use work.util_pack.ALL; + +library UNISIM; +use UNISIM.VComponents.all; + + +entity LTM9009_SLOW_CONTROL is + PORT( + CLK75 : in std_logic; + RES : in std_logic; + SCK : out std_logic; + SDI : in std_logic_vector(7 downto 0); + SDO : out std_logic; + CS : out std_logic_vector(7 downto 0) + ); +end LTM9009_SLOW_CONTROL; + +---------------------------------------------------------------- + +architecture Behavioral of LTM9009_SLOW_CONTROL is + + signal clk_cnt : std_logic_vector(6 downto 0); + signal sck_i : std_logic; + signal sdo_sh : std_logic_vector(15 downto 0); + signal vio_vector : std_logic_vector(19 downto 0); + signal bit_cnt : std_logic_vector(3 downto 0); + signal sequencer_stm : std_logic_vector(1 downto 0); + signal adc_adr : std_logic_vector(2 downto 0); + signal adc_rd : std_logic; + signal sdi_sh : std_logic_vector(7 downto 0); + signal adc_ctrl_ila_vector : std_logic_vector(31 downto 0); + signal adc_ctrl_vio_vector : std_logic_vector(19 downto 0); + + +BEGIN + +-- vio_vector <= "00010000000101101001"; + adc_rd <= vio_vector(15); + adc_adr <= vio_vector(18 downto 16); + +---------------------------------------------------------------------------------------------- +-- CLOCK DIVIDER +---------------------------------------------------------------------------------------------- + + process(RES,CLK75) + begin + if RES = '1' then + clk_cnt <= "0000000"; + elsif rising_edge(CLK75) then + clk_cnt <= clk_cnt + 1; + end if; + end process; + + sc_clk_bufg: BUFG + PORT MAP ( +-- I => clk_cnt(1), + I => clk_cnt(6), + O => sck_i + ); + +---------------------------------------------------------------------------------------------- +-- SEQUENCER STATE MACHINE +---------------------------------------------------------------------------------------------- + + process(RES,sck_i) + begin + if RES = '1' then + sdo_sh <= x"0000"; + bit_cnt <= x"0"; + sequencer_stm <= "00"; + + elsif rising_edge(sck_i) then + + vio_vector <= adc_ctrl_vio_vector; + + case sequencer_stm is + when "00" => + sdo_sh <= vio_vector(15 downto 0); + bit_cnt <= x"0"; + if vio_vector(19) = '1' then + sequencer_stm <= "01"; + end if; + when "01" => + sdo_sh <= sdo_sh(14 downto 0) & '0'; + if bit_cnt = 15 then + sequencer_stm <= "10"; + else + bit_cnt <= bit_cnt + 1; + end if; + when "10" => + if vio_vector(19) = '0' then + sequencer_stm <= "00"; + end if; + when others => + sequencer_stm <= "00"; + end case; + end if; + end process; + +---------------------------------------------------------------------------------------------- +-- INPUT MULTIPLEXER +---------------------------------------------------------------------------------------------- + + process(RES,sck_i) + begin + if RES = '1' then + sdi_sh <= x"00"; + elsif falling_edge(sck_i) then + if sequencer_stm = "01" then + if (adc_rd = '1' and bit_cnt > 7) then + sdi_sh(0) <= SDI(slv2int(adc_adr)); + sdi_sh(7 downto 1) <= sdi_sh(6 downto 0); + end if; + end if; + end if; + end process; + +---------------------------------------------------------------------------------------------- +-- OUTPUT BUFFERS +---------------------------------------------------------------------------------------------- + + SCK <= not clk_cnt(1) when sequencer_stm = "01" else '1'; + SDO <= sdo_sh(15) when sequencer_stm = "01" else '1'; + CS_DEMUX: for i in 0 to 7 generate + process(sequencer_stm, adc_adr) + begin + if sequencer_stm = "01" then + if (int2slv(i,4) = '0' & adc_adr) then + CS(i) <= '0'; + else + CS(i) <= '1'; + end if; + else + CS(i) <= '1'; + end if; + end process; + end generate; +-- adc_ctrl_vio_vector <= "00000000000000000000"; + +END Behavioral; diff --git a/FEE_ADC32board/modules/ADCrefdesign/AdcClock.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcClock.vhd similarity index 75% rename from FEE_ADC32board/modules/ADCrefdesign/AdcClock.vhd rename to FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcClock.vhd index 1a22311..a5d2b49 100644 --- a/FEE_ADC32board/modules/ADCrefdesign/AdcClock.vhd +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcClock.vhd @@ -1,523 +1,485 @@ ------------------------------------------------------------------------------------------------ --- © Copyright 2007 - 2009, Xilinx, Inc. All rights reserved. --- This file contains confidential and proprietary information of Xilinx, Inc. and is --- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------------ --- --- Disclaimer: --- This disclaimer is not a license and does not grant any rights to the materials --- distributed herewith. Except as otherwise provided in a valid license issued to you --- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS --- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL --- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED --- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR --- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including --- negligence, or under any other theory of liability) for any loss or damage of any --- kind or nature related to, arising under or in connection with these materials, --- including for any direct, or any indirect, special, incidental, or consequential --- loss or damage (including loss of data, profits, goodwill, or any type of loss or --- damage suffered as a result of any action brought by a third party) even if such --- damage or loss was reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail-safe, or for use in any --- application requiring fail-safe performance, such as life-support or safety devices --- or systems, Class III medical devices, nuclear facilities, applications related to --- the deployment of airbags, or any other applications that could lead to death, --- personal injury, or severe property or environmental damage (individually and --- collectively, "Critical Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical Applications, subject only to --- applicable laws and regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. --- --- Contact: e-mail hotline@xilinx.com phone + 1 800 255 7778 --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx --- \ \ \/ Version: --- \ \ Filename: AdcClock.vhd --- / / Date Last Modified: 16 Jun 09 --- /___/ /\ Date Created: 08/06/06 --- \ \ / \ --- \___\/\___\ --- --- Device: Virtex-6 --- Author: Marc Defossez --- Entity Name: AdcClock --- Purpose: High-speed local clock control for an interface between a FPGA and a --- Texas Instruments ADC. --- Tools: ISE - XST --- Limitations: none --- --- Revision History: --- Rev. --- ------------------------------------------------------------------------------------------------ --- Naming Conventions: --- active low signals: "*_n" --- clock signals: "clk", "clk_div#", "clk_#x" --- reset signals: "rst", "rst_n" --- generics: "C_*" --- user defined types: "*_TYPE" --- state machine next state: "*_ns" --- state machine current state: "*_cs" --- combinatorial signals: "*_com" --- pipelined or register delay signals: "*_d#" --- counter signals: "*cnt*" --- clock enable signals: "*_ce" --- internal version of output port: "*_i" --- device pins: "*_pin" --- ports: "- Names begin with Uppercase" --- processes: "*_PROCESS" --- component instantiations: "I_<#|FUNC>" ------------------------------------------------------------------------------------------------ --- -library IEEE; - use IEEE.std_logic_1164.all; - use IEEE.std_logic_UNSIGNED.all; - use IEEE.std_logic_arith.all; -library UNISIM; - use UNISIM.VCOMPONENTS.all; ------------------------------------------------------------------------------------------------ --- Entity pin description ------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------ -entity AdcClock is - generic ( - C_BufioLoc : string := "BUFIODQS_X0Y12"; - C_BufrLoc : string := "BUFR_X0Y6"; - C_AdcBits : integer := 16; - C_StatTaps : integer := 16 - ); - port ( - BitClk : in std_logic; - BitClkRst : in std_logic; - BitClkEna : in std_logic; - BitClkReSync : in std_logic; - BitClkDivReset : in std_logic; - BitClk_MonClkOut : out std_logic; -- CLK output - BitClk_MonClkIn : in std_logic; -- ISERDES.CLK input - BitClk_RefClkOut : out std_logic; -- CLKDIV & logic output - BitClk_RefClkIn : in std_logic; -- CLKDIV & logic input - BitClkAlignWarn : out std_logic; - BitClkInvrtd : out std_logic; - BitClkDone : out std_logic - ); -end AdcClock; ------------------------------------------------------------------------------------------------ --- Arcitecture section ------------------------------------------------------------------------------------------------ -architecture AdcClock_struct of AdcClock is ------------------------------------------------------------------------------------------------ --- Component Instantiation ------------------------------------------------------------------------------------------------ --- Components are instantiated by means / through the use of library references. ------------------------------------------------------------------------------------------------ --- Constants, Signals and Attributes Declarations ------------------------------------------------------------------------------------------------ --- Constants -constant Low : std_logic := '0'; -constant LowNibble : std_logic_vector(4 downto 0) := "00000"; -constant High : std_logic := '1'; --- Signals -signal IntBitClkRst : std_logic; ----------- ISRDS signals ------------------ -signal IntClkCtrlDlyCe : std_logic; -signal IntClkCtrlDlyInc : std_logic; -signal IntClkCtrlDlyRst : std_logic; - -signal IntBitClk_Ddly : std_logic; -signal IntBitClk : std_logic; -signal IntClkCtrlIsrdsMtoS1 : std_logic; -signal IntClkCtrlIsrdsMtoS2 : std_logic; -signal IntClkCtrlOut : std_logic_vector(7 downto 0); ----------- Controller signals ------------- -signal IntCal : std_logic; -signal IntVal : std_logic; -signal IntCalVal : std_logic_vector (1 downto 0); -signal IntProceedCnt : std_logic_vector (2 downto 0); -signal IntproceedCntTc : std_logic; -signal IntproceedCntTc_d : std_logic; -signal IntProceed : std_logic; -signal IntProceedDone : std_logic; - -type StateType is (Idle, A, B, C, D, E, F, G, G1, H, K, K1, K2, IdlyIncDec, Done); -signal State : StateType; -signal ReturnState : StateType; - -signal PassedSubState : std_logic; -signal IntNumIncDecIdly : std_logic_vector (3 downto 0); -signal IntAction : std_logic_vector (1 downto 0); -signal IntClkCtrlDone : std_logic; -signal IntClkCtrlAlgnWrn : std_logic; -signal IntClkCtrlInvrtd : std_logic; -signal IntTurnAroundBit : std_logic; -signal IntCalValReg : std_logic_vector (1 downto 0); -signal IntTimeOutCnt : std_logic_vector (3 downto 0); -signal IntStepCnt : std_logic_vector (3 downto 0); --- Attributes -attribute LOC : string; - attribute LOC of AdcClock_I_Bufio : label is C_BufioLoc; --- The BUFR is generated through a generate statement and therefore the LOC attribute --- must be place into the generate statement. --- See the BUFR generation down in the source code. ------------------------------------------------------------------------------------------------ -signal reset_clockdiv_S : std_logic; - - -begin ------------------------------------------------------------------------------------------------ --- Bit clock capture ISERDES Master-Slave combination ------------------------------------------------------------------------------------------------ --- -AdcClock_I_Iodly : IODELAYE1 - generic map ( - SIGNAL_PATTERN => "CLOCK", - REFCLK_FREQUENCY => 200.0, - HIGH_PERFORMANCE_MODE => TRUE, - DELAY_SRC => "I", - CINVCTRL_SEL => FALSE, - IDELAY_TYPE => "VARIABLE", - IDELAY_VALUE => C_StatTaps, - ODELAY_TYPE => "FIXED", - ODELAY_VALUE => 0 - ) - port map ( - DATAIN => Low, -- in input from FPGA fabric - IDATAIN => BitClk, -- in input from IOB - ODATAIN => Low, -- in input from I/O SERDES - CLKIN => Low, -- in input from BUFIO. BUFG, or BUFR - CE => IntClkCtrlDlyCe, -- in - INC => IntClkCtrlDlyInc, -- in - C => BitClk_RefClkIn, -- in - RST => IntClkCtrlDlyRst, -- in - T => Low, -- in - DATAOUT => IntBitClk_Ddly, -- out Delayed data - CINVCTRL => Low, -- in - CNTVALUEIN => LowNibble, -- in [4:0] - CNTVALUEOUT => open -- out [4:0] - ); -IntClkCtrlDlyRst <= BitClkRst; --- -AdcClock_I_Isrds_Master : ISERDESE1 - generic map ( - SERDES_MODE => "MASTER", -- - INTERFACE_TYPE => "NETWORKING",-- - IOBDELAY => "IBUF", -- - DATA_RATE => "SDR", -- - DATA_WIDTH => 8, -- - DYN_CLKDIV_INV_EN => FALSE, -- - DYN_CLK_INV_EN => FALSE, -- - NUM_CE => 1, -- - OFB_USED => FALSE -- - ) - port map ( - D => BitClk, -- in Clock from clock input IBUFDS - DDLY => IntBitClk_Ddly, -- in - DYNCLKDIVSEL => Low, -- in - DYNCLKSEL => Low, -- in - OFB => Low, -- in - BITSLIP => Low, -- in !!!!! - CE1 => BitClkEna, -- in - CE2 => Low, -- in - RST => IntBitClkRst, -- in - CLK => BitClk_MonClkIn, -- in Clock from BUFIO.O = BitClk - CLKB => Low, -- in - CLKDIV => BitClk_RefClkIn, -- in Clock from BUFR.O = BitClkDiv - OCLK => Low, -- in - SHIFTOUT1 => IntClkCtrlIsrdsMtoS1,-- out - SHIFTOUT2 => IntClkCtrlIsrdsMtoS2,-- out - O => IntBitClk, -- out Clock to BUFIO.I - Q1 => IntClkCtrlOut(0), -- out - Q2 => IntClkCtrlOut(1), -- out - Q3 => IntClkCtrlOut(2), -- out - Q4 => IntClkCtrlOut(3), -- out - Q5 => IntClkCtrlOut(4), -- out - Q6 => IntClkCtrlOut(5), -- out - SHIFTIN1 => Low, -- in - SHIFTIN2 => Low -- in - ); --- -AdcClock_I_Isrds_Slave : ISERDESE1 - generic map ( - SERDES_MODE => "SLAVE", -- - INTERFACE_TYPE => "NETWORKING",-- - IOBDELAY => "NONE", -- - DATA_RATE => "SDR", -- - DATA_WIDTH => 8, -- - DYN_CLKDIV_INV_EN => FALSE, -- - DYN_CLK_INV_EN => FALSE, -- - NUM_CE => 1, -- - OFB_USED => FALSE -- - ) - port map ( - D => Low, -- in - DDLY => Low, -- in - DYNCLKDIVSEL => Low, -- in - DYNCLKSEL => Low, -- in - OFB => Low, -- in - BITSLIP => Low, -- in !!!!! - CE1 => BitClkEna, -- in - CE2 => Low, -- in - RST => IntBitClkRst, -- in - CLK => BitClk_MonClkIn, -- in - CLKB => Low, -- in - CLKDIV => BitClk_RefClkIn, -- in - OCLK => Low, -- in - SHIFTOUT1 => open, -- out - SHIFTOUT2 => open, -- out - O => open, -- out - Q1 => open, -- out - Q2 => open, -- out - Q3 => IntClkCtrlOut(6), -- out - Q4 => IntClkCtrlOut(7), -- out - Q5 => open, -- out - Q6 => open, -- out - SHIFTIN1 => IntClkCtrlIsrdsMtoS1,-- in - SHIFTIN2 => IntClkCtrlIsrdsMtoS2 -- in - ); --- Input from ISERDES.O -- Output and CLK for all ISERDES -AdcClock_I_Bufio : BUFIO - port map (I => IntBitClk, O => BitClk_MonClkOut); --- -Gen_Bufr_Div_3 : if (C_AdcBits = 12) generate - attribute LOC of AdcClock_I_Bufr : label is C_BufrLoc; -begin - AdcClock_I_Bufr : BUFR - generic map (BUFR_DIVIDE => "3", SIM_DEVICE => "VIRTEX6") -- 12-bit = DIV by 3 --- ISERDES.CLK, from BUFIO.O -- ISERDES.CLKDIV, word clock for all ISERDES. - port map (I => IntBitClk, O => BitClk_RefClkOut, - CE => High, CLR => BitClkDivReset); -end generate; --- -Gen_Bufr_Div_4 : if (C_AdcBits /= 12) generate - attribute LOC of AdcClock_I_Bufr : label is C_BufrLoc; -begin - AdcClock_I_Bufr : BUFR - generic map (BUFR_DIVIDE => "4", SIM_DEVICE => "VIRTEX6") -- 14- and 16-bit = DIV by 4 --- ISERDES.CLK, from BUFIO.O -- ISERDES.CLKDIV, word clock for all ISERDES. - port map (I => IntBitClk, O => BitClk_RefClkOut, - CE => High, CLR => BitClkDivReset); -end generate; - - ------------------------------------------------------------------------------------------------ --- Bit clock re-synchronizer ------------------------------------------------------------------------------------------------ -IntBitClkRst <= BitClkRst or BitClkReSync; ------------------------------------------------------------------------------------------------ --- Bit clock controller for clock alignment input. ------------------------------------------------------------------------------------------------ --- This input section makes sure 64 bits are captured before action is taken to pass to --- the statemachine for evaluation. --- 8 samples of the Bit Clock are taken by the ISERDES and then transferred to the parallel --- FPGA world. The Proceed counter needs 8 reference clock rising edges before terminal count. --- The Proceed counter terminal count then loads the 2 control bits (made from sampled clock) --- into an intermediate register (IntCalVal). --- --- IntCal = '1' when all outputs of the ISERDES are '1 else it's '0'. --- IntVal = '1' when all outputs are '0' or '1'. --- -IntCal <= IntClkCtrlOut(7) and IntClkCtrlOut(6) and IntClkCtrlOut(5) and - IntClkCtrlOut(4) and IntClkCtrlOut(3) and IntClkCtrlOut(2) and - IntClkCtrlOut(1) and IntClkCtrlOut(0); -IntVal <= '1' when (IntClkCtrlOut = "11111111" or IntClkCtrlOut = "00000000") else '0'; --- -AdcClock_Proceed_PROCESS : process (BitClkEna, IntBitClkRst, BitClk_RefClkIn, IntProceedDone, IntClkCtrlDone) -begin - if (IntBitClkRst = '1') then - IntProceedCnt <= (others => '0'); - IntProceedCntTc_d <= '0'; - IntCalVal <= (others => '0'); - IntProceed <= '0'; - elsif (BitClk_RefClkIn'event and BitClk_RefClkIn = '1') then - if (BitClkEna = '1' and IntClkCtrlDone = '0') then - IntProceedCnt <= IntProceedCnt + 1; - IntProceedCntTc_d <= IntProceedCntTc; - if (IntProceedCntTc_d = '1') then - IntCalVal <= IntCal & IntVal; - end if; - if (IntProceedCntTc_d = '1') then - IntProceed <= '1'; - elsif (IntProceedDone = '1') then - IntProceed <= '0'; - end if; - end if; - end if; -end process; -IntProceedCntTc <= '1' when (IntProceedCnt = "110") else '0'; ------------------------------------------------------------------------------------------------ --- Bit clock controller for clock alignment state machine. ------------------------------------------------------------------------------------------------ -BitClkAlignWarn <= IntClkCtrlAlgnWrn; -BitClkInvrtd <= IntClkCtrlInvrtd; -BitClkDone <= IntClkCtrlDone; - -AdcClock_State_PROCESS : process (BitClk_RefClkIn, IntBitClkRst, BitClkEna, IntProceed, IntCalVal) -subtype ActCalVal is std_logic_vector (4 downto 0); -begin - if (IntBitClkRst = '1') then - State <= Idle; - ReturnState <= Idle; - PassedSubState <= '0'; - -- - IntNumIncDecIdly <= "0000"; -- Max. 16 - IntAction <= "00"; - IntClkCtrlDlyInc <= '1'; - IntClkCtrlDlyCe <= '0'; - IntClkCtrlDone <= '0'; - IntClkCtrlAlgnWrn <= '0'; - IntClkCtrlInvrtd <= '0'; - IntTurnAroundBit <= '0'; - IntProceedDone <= '0'; - IntClkCtrlDone <= '0'; - IntCalValReg <= (others => '0'); -- 2-bit - IntTimeOutCnt <= (others => '0'); -- 4-bit - IntStepCnt <= (others => '0'); -- 4-bit (16) - elsif (BitClk_RefClkIn'event and BitClk_RefClkIn = '1') then - if (BitClkEna = '1' and IntClkCtrlDone = '0') then - case State is - when Idle => - IntProceedDone <= '0'; - PassedSubState <= '0'; - case ActCalVal'(IntAction(1 downto 0) & IntCalVal (1 downto 0) & IntProceed) is - when "00001" => State <= A; - when "01001" => State <= B; - when "10001" => State <= B; - when "11001" => State <= B; - when "01111" => State <= C; - when "01101" => State <= D; - when "01011" => State <= D; - when "00011" => State <= E; - when "00101" => State <= E; - when "00111" => State <= E; - when "10011" => State <= F; - when "11011" => State <= F; - when "10101" => State <= F; - when "11101" => State <= F; - when "10111" => State <= F; - when "11111" => State <= F; - when others => State <= Idle; - end case; - when A => -- First time and sampling in jitter or cross area. - IntAction <= "01"; -- Set the action bits and go to next step. - State <= B; - when B => -- Input is samples in jitter or clock cross area. - if (PassedSubState = '1') then - PassedSubState <= '0'; -- Clear the pass through the substate bit. - IntProceedDone <= '1'; -- Reset the proceed bit. - State <= Idle; -- Return for a new sample of the input. - elsif (IntTimeOutCnt = "1111") then -- When arriving here something is wrong. - IntTimeOutCnt <= "0000"; -- Reset the counter. - IntAction <= "00"; -- reset the action bits. - IntClkCtrlAlgnWrn <= '1'; -- Raise a FLAG. - IntProceedDone <= '1'; -- Reset the proceed bit. - State <= Idle; -- Retry, return for new sample of input. - else - IntTimeOutCnt <= IntTimeOutCnt + 1; - IntNumIncDecIdly <= "0010"; -- Number increments or decrements to do. - ReturnState <= State; -- This state is the state to return too. - IntProceedDone <= '1'; -- Reset the proceed bit. - IntClkCtrlDlyInc <= '1'; -- Set for increment. - State <= IdlyIncDec; -- Jump to Increment/decrement sub-state. - end if; - when C => -- After first sample, jitter or cross, is now high. - IntNumIncDecIdly <= "0010"; -- Number increments or decrements to do. - ReturnState <= Done; -- This state is the state to return too. - IntClkCtrlDlyInc <= '0'; -- Set for decrement. - State <= IdlyIncDec; - when D => -- Same as C but with indication of 180-deg shift. - IntClkCtrlInvrtd <= '1'; - State <= C; - when E => -- First saple with valid data. - IntCalValReg <= IntCalVal; -- Register the sampled value - IntAction <= "10"; - IntProceedDone <= '1'; -- Reset the proceed bit. - IntNumIncDecIdly <= "0001"; -- Number increments or decrements to do. - ReturnState <= Idle; -- When increment is done return sampling. - IntClkCtrlDlyInc <= '1'; -- Set for increment - State <= IdlyIncDec; -- Jump to Increment/decrement sub-state. - when F => -- Next samples with valid data. - if (IntCalVal /= IntCalValReg) then - State <= G; -- The new CalVal value is different from the first. - else - if (IntStepCnt = "1111") then -- Step counter at the end, 15 - if (IntTurnAroundBit = '0') then - State <= H; -- No edge found and first time here. - elsif (IntCalValReg = "11") then - State <= K; -- A turnaround already happend. - else -- No edge is found (large 1/2 period). - State <= K1; -- Move the clock edge to near the correct - end if; -- edge. - else - IntStepCnt <= IntStepCnt + 1; - IntNumIncDecIdly <= "0001"; -- Number increments or decrements to do. - IntProceedDone <= '1'; -- Reset the proceed bit. - ReturnState <= Idle; -- When increment is done return sampling. - IntClkCtrlDlyInc <= '1'; -- Set for increment - State <= IdlyIncDec; -- Jump to Increment/decrement sub-state. - end if; - end if; - when G => - if (IntCalValReg /= "01") then - IntClkCtrlInvrtd <= '1'; - State <= G1; - else - State <= G1; - end if; - when G1 => - if (IntTimeOutCnt = "00") then - State <= Done; - else - IntNumIncDecIdly <= "0010"; -- Number increments or decrements to do. - ReturnState <= Done; -- After decrement it's finished. - IntClkCtrlDlyInc <= '0'; -- Set for decrement - State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state. - end if; - when H => - IntTurnAroundBit <= '1'; -- Indicate that the Idelay jumps to 0. - IntStepCnt <= IntStepCnt + 1; -- Set all registers to zero. - IntAction <= "00"; -- Take one step, let the counter flow over - IntCalValReg <= "00"; -- The idelay turn over to 0. - IntTimeOutCnt <= "0000"; -- Start sampling from scratch. - IntNumIncDecIdly <= "0001"; -- Number increments or decrements to do. - IntProceedDone <= '1'; -- Reset the proceed bit. - ReturnState <= Idle; -- After increment go sampling for new. - IntClkCtrlDlyInc <= '1'; -- Set for increment. - State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state. - when K => - IntNumIncDecIdly <= "1111"; -- Number increments or decrements to do. - ReturnState <= K2; -- After increment it is done. - IntClkCtrlDlyInc <= '1'; -- Set for increment. - State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state. - when K1 => - IntNumIncDecIdly <= "1110"; -- Number increments or decrements to do. - ReturnState <= K2; -- After increment it is done. - IntClkCtrlDlyInc <= '1'; -- Set for increment. - State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state. - when K2 => - IntNumIncDecIdly <= "0001"; -- Number increments or decrements to do. - ReturnState <= Done; -- After increment it is done. - IntClkCtrlDlyInc <= '1'; -- Set for increment. - State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state. - -- - when IdlyIncDec => -- Increment or decrement by enable. - if (IntNumIncDecIdly /= "0000") then -- Check number of tap jumps - IntNumIncDecIdly <= IntNumIncDecIdly - 1; -- If not 0 jump and decrement. - IntClkCtrlDlyCe <= '1'; -- Do the jump. enable it. - else - IntClkCtrlDlyCe <= '0'; -- when it is enabled, disbale it - PassedSubState <= '1'; -- Set a check bit "I've been here and passed". - State <= ReturnState; -- Return to origin. - end if; - when Done => -- Alignment done. - IntClkCtrlDone <= '1'; -- Alignment is done. - end case; - end if; - end if; -end process; --- ------------------------------------------------------------------------------------------------- +----------------------------------------------------------------------------------------------- +-- © Copyright 2012, Xilinx, Inc. All rights reserved. +-- This file contains confidential and proprietary information of Xilinx, Inc. and is +-- protected under U.S. and international copyright and other intellectual property laws. +----------------------------------------------------------------------------------------------- +-- +-- Disclaimer: +-- This disclaimer is not a license and does not grant any rights to the materials +-- distributed herewith. Except as otherwise provided in a valid license issued to you +-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS +-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL +-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED +-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR +-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including +-- negligence, or under any other theory of liability) for any loss or damage of any +-- kind or nature related to, arising under or in connection with these materials, +-- including for any direct, or any indirect, special, incidental, or consequential +-- loss or damage (including loss of data, profits, goodwill, or any type of loss or +-- damage suffered as a result of any action brought by a third party) even if such +-- damage or loss was reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail-safe, or for use in any +-- application requiring fail-safe performance, such as life-support or safety devices +-- or systems, Class III medical devices, nuclear facilities, applications related to +-- the deployment of airbags, or any other applications that could lead to death, +-- personal injury, or severe property or environmental damage (individually and +-- collectively, "Critical Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical Applications, subject only to +-- applicable laws and regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +-- +-- Contact: e-mail hotline@xilinx.com phone + 1 800 255 7778 +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version: V0,03 +-- \ \ Filename: AdcClock.vhd +-- / / Date Last Modified: 24 Jul 12 +-- /___/ /\ Date Created: 08 Jun 09 +-- \ \ / \ +-- \___\/\___\ +-- +-- Device: 7-series +-- Author: Marc Defossez +-- Entity Name: AdcClock +-- Purpose: Clock control for an ADC interface. +-- Tools: ISE_14.1 +-- Limitations: none +-- +-- Revision History: +-- Rev. +-- +----------------------------------------------------------------------------------------------- +-- Naming Conventions: +-- active low signals: "*_n" +-- clock signals: "clk", "clk_div#", "clk_#x" +-- reset signals: "rst", "rst_n" +-- generics: "C_*" +-- user defined types: "*_TYPE" +-- state machine next state: "*_ns" +-- state machine current state: "*_cs" +-- combinatorial signals: "*_com" +-- pipelined or register delay signals: "*_d#" +-- counter signals: "*cnt*" +-- clock enable signals: "*_ce" +-- internal version of output port: "*_i" +-- device pins: "*_pin" +-- ports: "- Names begin with Uppercase" +-- processes: "*_PROCESS" +-- component instantiations: "I_<#|FUNC>" +----------------------------------------------------------------------------------------------- +-- +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.std_logic_UNSIGNED.all; + use IEEE.std_logic_arith.all; +library UNISIM; + use UNISIM.VCOMPONENTS.all; +----------------------------------------------------------------------------------------------- +-- Entity pin description +----------------------------------------------------------------------------------------------- +entity AdcClock is + generic ( + C_BufioLoc : string := "BUFIO_X0Y17"; -- IO-bank 16 + C_BufrLoc : string := "BUFR_X0Y17"; + C_IserdesLoc: string := "BUFR_X0Y17"; + C_StatTaps : integer := 16 + ); + port ( + BitClk : in std_logic; + BitClkRst : in std_logic; + BitClkEna : in std_logic; + BitClkReSync : in std_logic; + BitClk_MonClkOut : out std_logic; -- CLK output + BitClk_MonClkIn : in std_logic; -- ISERDES.CLK input + BitClk_RefClkOut : out std_logic; -- CLKDIV & logic output + BitClk_RefClkIn : in std_logic; -- CLKDIV & logic input + BitClkAlignWarn : out std_logic; + BitClkInvrtd : out std_logic; + BitClkDone : out std_logic + ); +end AdcClock; +----------------------------------------------------------------------------------------------- +-- Arcitecture section +----------------------------------------------------------------------------------------------- +architecture AdcClock_struct of AdcClock is +----------------------------------------------------------------------------------------------- +-- Component Instantiation +----------------------------------------------------------------------------------------------- +-- Components are instantiated by means / through the use of library references. +----------------------------------------------------------------------------------------------- +-- Constants, Signals and Attributes Declarations +----------------------------------------------------------------------------------------------- +-- Constants +constant Low : std_logic := '0'; +constant LowNibble : std_logic_vector(4 downto 0) := "00000"; +constant High : std_logic := '1'; +-- Signals +signal IntBitClkRst : std_logic; +---------- ISRDS signals ------------------ +signal IntClkCtrlDlyCe : std_logic; +signal IntClkCtrlDlyInc : std_logic; +signal IntClkCtrlDlyRst : std_logic; + +signal IntBitClk_Ddly : std_logic; +signal IntBitClk : std_logic; +signal BitClk_inv : std_logic; + +signal IntClkCtrlIsrdsMtoS1 : std_logic; +signal IntClkCtrlIsrdsMtoS2 : std_logic; +signal IntClkCtrlOut : std_logic_vector(7 downto 0); +---------- Controller signals ------------- +signal IntCal : std_logic; +signal IntVal : std_logic; +signal IntCalVal : std_logic_vector (1 downto 0); +signal IntProceedCnt : std_logic_vector (2 downto 0); +signal IntproceedCntTc : std_logic; +signal IntproceedCntTc_d : std_logic; +signal IntProceed : std_logic; +signal IntProceedDone : std_logic; + +type StateType is (Idle, A, B, C, D, E, F, G, G1, H, K, K1, K2, IdlyIncDec, Done); +signal State : StateType; +signal ReturnState : StateType; + +signal PassedSubState : std_logic; +signal IntNumIncDecIdly : std_logic_vector (3 downto 0); +signal IntAction : std_logic_vector (1 downto 0); +signal IntClkCtrlDone : std_logic; +signal IntClkCtrlAlgnWrn : std_logic; +signal IntClkCtrlInvrtd : std_logic; +signal IntTurnAroundBit : std_logic; +signal IntCalValReg : std_logic_vector (1 downto 0); +signal IntTimeOutCnt : std_logic_vector (3 downto 0); +signal IntStepCnt : std_logic_vector (4 downto 0); --// +-- Attributes +attribute KEEP_HIERARCHY : string; + attribute KEEP_HIERARCHY of AdcClock_struct : architecture is "YES"; +attribute LOC : string; + attribute LOC of AdcClock_I_Bufio : label is C_BufioLoc; + attribute LOC of AdcClock_I_Bufr : label is C_BufrLoc; + attribute LOC of AdcClock_I_Isrds_Master : label is C_IserdesLoc; +--attribute keep : string; +--attribute keep of BitClk_inv : signal is "TRUE"; + +----------------------------------------------------------------------------------------------- +begin +----------------------------------------------------------------------------------------------- +-- Bit clock capture ISERDES Master-Slave combination +----------------------------------------------------------------------------------------------- +-- +BitClk_inv <= not BitClk; -- peterS: invert clock for better optimal delay point +AdcClock_I_Iodly : IDELAYE2 --_FINEDELAY + generic map ( + SIGNAL_PATTERN => "CLOCK", + REFCLK_FREQUENCY => 200.0, + HIGH_PERFORMANCE_MODE => "TRUE", + --FINEDELAY => "BYPASS", + DELAY_SRC => "IDATAIN", + CINVCTRL_SEL => "FALSE", + IDELAY_TYPE => "VARIABLE", + IDELAY_VALUE => C_StatTaps, + PIPE_SEL => "FALSE" + ) + port map ( + DATAIN => Low, -- in + IDATAIN => BitClk_inv, -- in + CE => IntClkCtrlDlyCe, -- in + INC => IntClkCtrlDlyInc, -- in + C => BitClk_RefClkIn, -- in + LD => IntClkCtrlDlyRst, -- in + LDPIPEEN => Low, -- in + REGRST => '0', --//IntClkCtrlDlyRst, -- in + DATAOUT => IntBitClk_Ddly, -- out + CINVCTRL => Low, -- in + CNTVALUEOUT => open, -- out [4:0] + CNTVALUEIN => LowNibble -- in [4:0] + ); +IntClkCtrlDlyRst <= BitClkRst; + +AdcClock_I_Isrds_Master : ISERDESE2 + generic map ( + SERDES_MODE => "MASTER", + INTERFACE_TYPE => "NETWORKING", + IOBDELAY => "IBUF", + DATA_RATE => "SDR", + DATA_WIDTH => 8, + DYN_CLKDIV_INV_EN => "FALSE", + DYN_CLK_INV_EN => "FALSE", + NUM_CE => 1, + OFB_USED => "FALSE", + INIT_Q1 => '0', + INIT_Q2 => '0', + INIT_Q3 => '0', + INIT_Q4 => '0', + SRVAL_Q1 => '0', + SRVAL_Q2 => '0', + SRVAL_Q3 => '0', + SRVAL_Q4 => '0' + ) + port map ( + D => BitClk_inv, -- in Clock from clock input IBUFDS + DDLY => IntBitClk_Ddly, -- in + DYNCLKDIVSEL => Low, -- in + DYNCLKSEL => Low, -- in + OFB => Low, -- in + BITSLIP => Low, -- in + CE1 => BitClkEna, -- in + CE2 => Low, -- in + RST => IntBitClkRst, -- in + CLK => BitClk_MonClkIn, -- in + CLKB => Low, -- in + CLKDIV => BitClk_RefClkIn, -- in + CLKDIVP => Low, -- in + OCLK => Low, -- in + OCLKB => Low, -- in + SHIFTIN1 => Low, -- in + SHIFTIN2 => Low, -- in + O => IntBitClk, -- out + Q1 => IntClkCtrlOut(0), -- out + Q2 => IntClkCtrlOut(1), -- out + Q3 => IntClkCtrlOut(2), -- out + Q4 => IntClkCtrlOut(3), -- out + Q5 => IntClkCtrlOut(4), -- out + Q6 => IntClkCtrlOut(5), -- out + Q7 => IntClkCtrlOut(6), -- out + Q8 => IntClkCtrlOut(7), -- out + SHIFTOUT1 => open, -- out + SHIFTOUT2 => open -- out + ); +-- Input from ISERDES.O -- Output and CLK for all ISERDES +AdcClock_I_Bufio : BUFIO + port map (I => IntBitClk, O => BitClk_MonClkOut); + +AdcClock_I_Bufr : BUFR + generic map (BUFR_DIVIDE => "4", SIM_DEVICE => "7SERIES") -- 14- and 16-bit = DIV by 4 +-- ISERDES.CLK, from BUFIO.O -- ISERDES.CLKDIV, word clock for all ISERDES. + port map (I => IntBitClk, O => BitClk_RefClkOut, + CE => High, CLR => BitClkReSync); --// ); --//peter low + + +----------------------------------------------------------------------------------------------- +-- Bit clock re-synchronizer +----------------------------------------------------------------------------------------------- +IntBitClkRst <= BitClkRst; --// or BitClkReSync; +----------------------------------------------------------------------------------------------- +-- Bit clock controller for clock alignment input. +----------------------------------------------------------------------------------------------- +-- This input section makes sure 64 bits are captured before action is taken to pass to +-- the statemachine for evaluation. +-- 8 samples of the Bit Clock are taken by the ISERDES and then transferred to the parallel +-- FPGA world. The Proceed counter needs 8 reference clock rising edges before terminal count. +-- The Proceed counter terminal count then loads the 2 control bits (made from sampled clock) +-- into an intermediate register (IntCalVal). +-- +-- IntCal = '1' when all outputs of the ISERDES are '1 else it's '0'. +-- IntVal = '1' when all outputs are '0' or '1'. +-- +IntCal <= IntClkCtrlOut(7) and IntClkCtrlOut(6) and IntClkCtrlOut(5) and + IntClkCtrlOut(4) and IntClkCtrlOut(3) and IntClkCtrlOut(2) and + IntClkCtrlOut(1) and IntClkCtrlOut(0); +IntVal <= '1' when (IntClkCtrlOut = "11111111" or IntClkCtrlOut = "00000000") else '0'; +-- +AdcClock_Proceed_PROCESS : process (BitClkEna, IntBitClkRst, BitClk_RefClkIn, IntProceedDone, IntClkCtrlDone) +begin + if (IntBitClkRst = '1') then + IntProceedCnt <= (others => '0'); + IntProceedCntTc_d <= '0'; + IntCalVal <= (others => '0'); + IntProceed <= '0'; + elsif (BitClk_RefClkIn'event and BitClk_RefClkIn = '1') then + if (BitClkEna = '1' and IntClkCtrlDone = '0') then + IntProceedCnt <= IntProceedCnt + 1; + IntProceedCntTc_d <= IntProceedCntTc; + if (IntProceedCntTc_d = '1') then + IntCalVal <= IntCal & IntVal; + end if; + if (IntProceedCntTc_d = '1') then + IntProceed <= '1'; + elsif (IntProceedDone = '1') then + IntProceed <= '0'; + end if; + end if; + end if; +end process; +IntProceedCntTc <= '1' when (IntProceedCnt = "110") else '0'; +----------------------------------------------------------------------------------------------- +-- Bit clock controller for clock alignment state machine. +----------------------------------------------------------------------------------------------- +BitClkAlignWarn <= IntClkCtrlAlgnWrn; +BitClkInvrtd <= IntClkCtrlInvrtd; +BitClkDone <= IntClkCtrlDone; + +AdcClock_State_PROCESS : process (BitClk_RefClkIn, IntBitClkRst, BitClkEna, IntProceed, IntCalVal) +subtype ActCalVal is std_logic_vector (4 downto 0); +begin + if (IntBitClkRst = '1') then + State <= Idle; + ReturnState <= Idle; + PassedSubState <= '0'; + -- + IntNumIncDecIdly <= "0000"; -- Max. 16 + IntAction <= "00"; + IntClkCtrlDlyInc <= '1'; + IntClkCtrlDlyCe <= '0'; + IntClkCtrlDone <= '0'; + IntClkCtrlAlgnWrn <= '0'; + IntClkCtrlInvrtd <= '0'; + IntTurnAroundBit <= '0'; + IntProceedDone <= '0'; + IntClkCtrlDone <= '0'; + IntCalValReg <= (others => '0'); -- 2-bit + IntTimeOutCnt <= (others => '0'); -- 4-bit + IntStepCnt <= (others => '0'); -- 4-bit (16) + elsif (BitClk_RefClkIn'event and BitClk_RefClkIn = '1') then + if (BitClkEna = '1' and IntClkCtrlDone = '0') then + case State is + when Idle => + IntProceedDone <= '0'; + PassedSubState <= '0'; + case ActCalVal'(IntAction(1 downto 0) & IntCalVal (1 downto 0) & IntProceed) is + when "00001" => State <= A; + when "01001" => State <= B; + when "10001" => State <= B; + when "11001" => State <= B; + when "01111" => State <= C; + when "01101" => State <= D; + when "01011" => State <= D; + when "00011" => State <= E; + when "00101" => State <= E; + when "00111" => State <= E; + when "10011" => State <= F; + when "11011" => State <= F; + when "10101" => State <= F; + when "11101" => State <= F; + when "10111" => State <= F; + when "11111" => State <= F; + when others => State <= Idle; + end case; + when A => -- First time and sampling in jitter or cross area. + IntAction <= "01"; -- Set the action bits and go to next step. + State <= B; + when B => -- Input is samples in jitter or clock cross area. + if (PassedSubState = '1') then + PassedSubState <= '0'; -- Clear the pass through the substate bit. + IntProceedDone <= '1'; -- Reset the proceed bit. + State <= Idle; -- Return for a new sample of the input. + elsif (IntTimeOutCnt = "1111") then -- When arriving here something is wrong. + IntTimeOutCnt <= "0000"; -- Reset the counter. + IntAction <= "00"; -- reset the action bits. + IntClkCtrlAlgnWrn <= '1'; -- Raise a FLAG. + IntProceedDone <= '1'; -- Reset the proceed bit. + State <= Idle; -- Retry, return for new sample of input. + else + IntTimeOutCnt <= IntTimeOutCnt + 1; + IntNumIncDecIdly <= "0010"; -- Number increments or decrements to do. + ReturnState <= State; -- This state is the state to return too. + IntProceedDone <= '1'; -- Reset the proceed bit. + IntClkCtrlDlyInc <= '1'; -- Set for increment. + State <= IdlyIncDec; -- Jump to Increment/decrement sub-state. + end if; + when C => -- After first sample, jitter or cross, is now high. + IntNumIncDecIdly <= "0010"; -- Number increments or decrements to do. + ReturnState <= Done; -- This state is the state to return too. + IntClkCtrlDlyInc <= '0'; -- Set for decrement. + State <= IdlyIncDec; + when D => -- Same as C but with indication of 180-deg shift. + IntClkCtrlInvrtd <= '1'; + State <= C; + when E => -- First sample with valid data. + IntCalValReg <= IntCalVal; -- Register the sampled value + IntAction <= "10"; + IntProceedDone <= '1'; -- Reset the proceed bit. + IntNumIncDecIdly <= "0001"; -- Number increments or decrements to do. + ReturnState <= Idle; -- When increment is done return sampling. + IntClkCtrlDlyInc <= '1'; -- Set for increment + State <= IdlyIncDec; -- Jump to Increment/decrement sub-state. + when F => -- Next samples with valid data. + if (IntCalVal /= IntCalValReg) then + State <= G; -- The new CalVal value is different from the first. + else + if (IntStepCnt = "11111") then -- Step counter at the end, 15 --// + if (IntTurnAroundBit = '0') then + State <= H; -- No edge found and first time here. + elsif (IntCalValReg = "11") then + State <= K; -- A turnaround already happend. + else -- No edge is found (large 1/2 period). + State <= K1; -- Move the clock edge to near the correct + end if; -- edge. + else + IntStepCnt <= IntStepCnt + 1; + IntNumIncDecIdly <= "0001"; -- Number increments or decrements to do. + IntProceedDone <= '1'; -- Reset the proceed bit. + ReturnState <= Idle; -- When increment is done return sampling. + IntClkCtrlDlyInc <= '1'; -- Set for increment + State <= IdlyIncDec; -- Jump to Increment/decrement sub-state. + end if; + end if; + when G => + if (IntCalValReg /= "01") then + IntClkCtrlInvrtd <= '1'; + State <= G1; + else + State <= G1; + end if; + when G1 => + if (IntTimeOutCnt = "00") then + State <= Done; + else + IntNumIncDecIdly <= "0010"; -- Number increments or decrements to do. + ReturnState <= Done; -- After decrement it's finished. + IntClkCtrlDlyInc <= '0'; -- Set for decrement + State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state. + end if; + when H => + IntTurnAroundBit <= '1'; -- Indicate that the Idelay jumps to 0. + IntStepCnt <= IntStepCnt + 1; -- Set all registers to zero. + IntAction <= "00"; -- Take one step, let the counter flow over + IntCalValReg <= "00"; -- The idelay turn over to 0. + IntTimeOutCnt <= "0000"; -- Start sampling from scratch. + IntNumIncDecIdly <= "0001"; -- Number increments or decrements to do. + IntProceedDone <= '1'; -- Reset the proceed bit. + ReturnState <= Idle; -- After increment go sampling for new. + IntClkCtrlDlyInc <= '1'; -- Set for increment. + State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state. + when K => + IntNumIncDecIdly <= "1111"; -- Number increments or decrements to do. + ReturnState <= K2; -- After increment it is done. + IntClkCtrlDlyInc <= '1'; -- Set for increment. + State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state. + when K1 => + IntNumIncDecIdly <= "1110"; -- Number increments or decrements to do. + ReturnState <= K2; -- After increment it is done. + IntClkCtrlDlyInc <= '1'; -- Set for increment. + State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state. + when K2 => + IntNumIncDecIdly <= "0001"; -- Number increments or decrements to do. + ReturnState <= Done; -- After increment it is done. + IntClkCtrlDlyInc <= '1'; -- Set for increment. + State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state. + -- + when IdlyIncDec => -- Increment or decrement by enable. + if (IntNumIncDecIdly /= "0000") then -- Check number of tap jumps + IntNumIncDecIdly <= IntNumIncDecIdly - 1; -- If not 0 jump and decrement. + IntClkCtrlDlyCe <= '1'; -- Do the jump. enable it. + else + IntClkCtrlDlyCe <= '0'; -- when it is enabled, disbale it + PassedSubState <= '1'; -- Set a check bit "I've been here and passed". + State <= ReturnState; -- Return to origin. + end if; + when Done => -- Alignment done. + IntClkCtrlDone <= '1'; -- Alignment is done. + end case; + end if; + end if; +end process; +-- +------------------------------------------------------------------------------------------------ + + + end AdcClock_struct; \ No newline at end of file diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcData.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcData.vhd new file mode 100644 index 0000000..3dde4c1 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcData.vhd @@ -0,0 +1,350 @@ +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.std_logic_UNSIGNED.all; +library UNISIM; + use UNISIM.VCOMPONENTS.all; + +entity AdcData is + port ( + DatD0_n : in std_logic; + DatD0_p : in std_logic; + DatD1_n : in std_logic; + DatD1_p : in std_logic; + DatClk : in std_logic; + DatClkDiv : in std_logic; + DatRst : in std_logic; + DatEna : in std_logic; + DatDone : in std_logic; + DatOut : out std_logic_vector(31 downto 0) + ); +end AdcData; +----------------------------------------------------------------------------------------------- +-- Arcitecture section +----------------------------------------------------------------------------------------------- +architecture AdcData_struct of AdcData is +signal IntDatClk : std_logic; +signal IntDatClk_n : std_logic; +-- +signal IntDatSrds0Out : std_logic_vector(7 downto 0); +signal IntDatSrds1Out : std_logic_vector(7 downto 0); +signal IntDatSrds0 : std_logic_vector(7 downto 0); +signal IntDatSrds1 : std_logic_vector(7 downto 0); +signal IntDat0 : std_logic_vector(7 downto 0); +signal IntDat1 : std_logic_vector(7 downto 0); +signal IntDat0Mux : std_logic_vector(7 downto 0); +signal IntDat1Mux : std_logic_vector(7 downto 0); +signal IntDat0Swp : std_logic_vector(7 downto 0); +signal IntDat1Swp : std_logic_vector(7 downto 0); +signal IntDatSwpBus : std_logic_vector(31 downto 0); +signal IntDatDone : std_logic; +signal IntDatEna : std_logic; +-- Attributes +attribute KEEP_HIERARCHY : string; +attribute KEEP_HIERARCHY of AdcData_struct : architecture is "YES"; +----------------------------------------------------------------------------------------------- + +begin +-- +-- DatRst and DatEna are synchronised to DatClkDiv on the level were this component "AdcData" +-- is used. This higher level is "AdcToplevel". +AdcData_Done_PROCESS : process (DatClkDiv, DatRst) +begin + if (DatRst = '1') then + IntDatDone <= '0'; + elsif (DatClkDiv'event and DatClkDiv = '1') then + IntDatDone <= DatDone; + end if; +end process; +-- +IntDatEna <= '1' when (IntDatDone = '1' and DatEna = '1') else '0'; +----------------------------------------------------------------------------------------------- +IntDatClk <= DatClk; -- CLOCK FOR P-side ISERDES +IntDatClk_n <= not DatClk; -- CLOCK FOR N_side ISERDES +----------------------------------------------------------------------------------------------- +-- ISERDES for channel ZERO +----------------------------------------------------------------------------------------------- +AdcData_I_Isrds_D0_p : ISERDESE2 + generic map ( + SERDES_MODE => "MASTER", -- string + INTERFACE_TYPE => "NETWORKING", -- string + IOBDELAY => "NONE", -- string + DATA_RATE => "SDR", -- string + DATA_WIDTH => 4, -- integer <-- Number of bits + DYN_CLKDIV_INV_EN => "FALSE", -- string + DYN_CLK_INV_EN => "FALSE", -- string + NUM_CE => 1, -- integer + OFB_USED => "FALSE", -- string + INIT_Q1 => '0', -- bit; + INIT_Q2 => '0', -- bit; + INIT_Q3 => '0', -- bit; + INIT_Q4 => '0', -- bit; + SRVAL_Q1 => '0', -- bit; + SRVAL_Q2 => '0', -- bit; + SRVAL_Q3 => '0', -- bit; + SRVAL_Q4 => '0' -- bit + ) + port map ( + D => DatD0_p, -- in + DDLY => '0', -- in + OFB => '0', -- in + BITSLIP => '0',-- in + CE1 => IntDatDone, -- in + CE2 => '0', -- in + RST => DatRst, -- in + CLK => IntDatClk, -- in + CLKB => '0', -- in + CLKDIV => DatClkDiv, -- in + CLKDIVP => '0', -- in + OCLK => '0', -- in + OCLKB => '0', -- in + DYNCLKDIVSEL => '0', -- in + DYNCLKSEL => '0', -- in + SHIFTOUT1 => open, -- out + SHIFTOUT2 => open, -- out + O => open, -- out + Q1 => IntDatSrds0Out(6), -- out (0) + Q2 => IntDatSrds0Out(4), -- out (2) + Q3 => IntDatSrds0Out(2), -- out (4) + Q4 => IntDatSrds0Out(0), -- out (6) + Q5 => open, -- out + Q6 => open, -- out + Q7 => open, -- out + Q8 => open, -- out + SHIFTIN1 => '0', -- in + SHIFTIN2 => '0' -- in + ); +AdcData_I_Isrds_D0_n : ISERDESE2 + generic map ( + SERDES_MODE => "MASTER", -- + INTERFACE_TYPE => "NETWORKING", -- + IOBDELAY => "NONE", -- + DATA_RATE => "SDR", -- + DATA_WIDTH => 4, -- <-- Number of bits + DYN_CLKDIV_INV_EN => "FALSE", -- + DYN_CLK_INV_EN => "FALSE", -- + NUM_CE => 1, -- + OFB_USED => "FALSE", -- + INIT_Q1 => '0', -- bit; + INIT_Q2 => '0', -- bit; + INIT_Q3 => '0', -- bit; + INIT_Q4 => '0', -- bit; + SRVAL_Q1 => '0', -- bit; + SRVAL_Q2 => '0', -- bit; + SRVAL_Q3 => '0', -- bit; + SRVAL_Q4 => '0' -- bit + ) + port map ( + D => DatD0_n, -- in + DDLY => '0', -- in + OFB => '0', -- in + BITSLIP => '0',-- in + CE1 => IntDatDone, -- in + CE2 => '0', -- in + RST => DatRst, -- in + CLK => IntDatClk_n, -- in + CLKB => '0', -- in + CLKDIV => DatClkDiv, -- in + CLKDIVP => '0', -- in + OCLK => '0', -- in + OCLKB => '0', -- in + DYNCLKDIVSEL => '0', -- in + DYNCLKSEL => '0', -- in + SHIFTOUT1 => open, -- out + SHIFTOUT2 => open, -- out + O => open, -- out + Q1 => IntDatSrds0Out(7), -- out (1) + Q2 => IntDatSrds0Out(5), -- out (3) + Q3 => IntDatSrds0Out(3), -- out (5) + Q4 => IntDatSrds0Out(1), -- out (7) + Q5 => open, -- out + Q6 => open, -- out + Q7 => open, -- out + Q8 => open, -- out + SHIFTIN1 => '0', -- in + SHIFTIN2 => '0' -- in + ); +----------------------------------------------------------------------------------------------- +-- ISERDES for channel ONE +----------------------------------------------------------------------------------------------- +AdcData_I_Isrds_D1_p : ISERDESE2 + generic map ( + SERDES_MODE => "MASTER", -- string + INTERFACE_TYPE => "NETWORKING", -- string + IOBDELAY => "NONE", -- string + DATA_RATE => "SDR", -- string + DATA_WIDTH => 4, -- integer <-- Number of bits + DYN_CLKDIV_INV_EN => "FALSE", -- string + DYN_CLK_INV_EN => "FALSE", -- string + NUM_CE => 1, -- integer + OFB_USED => "FALSE", -- string + INIT_Q1 => '0', -- bit; + INIT_Q2 => '0', -- bit; + INIT_Q3 => '0', -- bit; + INIT_Q4 => '0', -- bit; + SRVAL_Q1 => '0', -- bit; + SRVAL_Q2 => '0', -- bit; + SRVAL_Q3 => '0', -- bit; + SRVAL_Q4 => '0' -- bit + ) + port map ( + D => DatD1_p, -- in + DDLY => '0', -- in + OFB => '0', -- in + BITSLIP => '0',-- in + CE1 => IntDatDone, -- in + CE2 => '0', -- in + RST => DatRst, -- in + CLK => IntDatClk, -- in + CLKB => '0', -- in + CLKDIV => DatClkDiv, -- in + CLKDIVP => '0', -- in + OCLK => '0', -- in + OCLKB => '0', -- in + DYNCLKDIVSEL => '0', -- in + DYNCLKSEL => '0', -- in + SHIFTOUT1 => open, -- out + SHIFTOUT2 => open, -- out + O => open, -- out + Q1 => IntDatSrds1Out(6), -- out (0) + Q2 => IntDatSrds1Out(4), -- out (2) + Q3 => IntDatSrds1Out(2), -- out (4) + Q4 => IntDatSrds1Out(0), -- out (6) + Q5 => open, -- out + Q6 => open, -- out + Q7 => open, -- out + Q8 => open, -- out + SHIFTIN1 => '0', -- in + SHIFTIN2 => '0' -- in + ); +AdcData_I_Isrds_D1_n : ISERDESE2 + generic map ( + SERDES_MODE => "MASTER", -- + INTERFACE_TYPE => "NETWORKING", -- + IOBDELAY => "NONE", -- + DATA_RATE => "SDR", -- + DATA_WIDTH => 4, -- <-- Number of bits + DYN_CLKDIV_INV_EN => "FALSE", -- + DYN_CLK_INV_EN => "FALSE", -- + NUM_CE => 1, -- + OFB_USED => "FALSE", -- + INIT_Q1 => '0', -- bit; + INIT_Q2 => '0', -- bit; + INIT_Q3 => '0', -- bit; + INIT_Q4 => '0', -- bit; + SRVAL_Q1 => '0', -- bit; + SRVAL_Q2 => '0', -- bit; + SRVAL_Q3 => '0', -- bit; + SRVAL_Q4 => '0' -- bit + ) + port map ( + D => DatD1_n, -- in + DDLY => '0', -- in + OFB => '0', -- in + BITSLIP => '0',-- in + CE1 => IntDatDone, -- in + CE2 => '0', -- in + RST => DatRst, -- in + CLK => IntDatClk_n, -- in + CLKB => '0', -- in + CLKDIV => DatClkDiv, -- in + CLKDIVP => '0', -- in + OCLK => '0', -- in + OCLKB => '0', -- in + DYNCLKDIVSEL => '0', -- in + DYNCLKSEL => '0', -- in + SHIFTOUT1 => open, -- out + SHIFTOUT2 => open, -- out + O => open, -- out + Q1 => IntDatSrds1Out(7), -- out (1) + Q2 => IntDatSrds1Out(5), -- out (3) + Q3 => IntDatSrds1Out(3), -- out (5) + Q4 => IntDatSrds1Out(1), -- out (7) + Q5 => open, -- out + Q6 => open, -- out + Q7 => open, -- out + Q8 => open, -- out + SHIFTIN1 => '0', -- in + SHIFTIN2 => '0' -- in + ); +----------------------------------------------------------------------------------------------- + + + IntDatSrds0 <= not IntDatSrds0Out(7) & IntDatSrds0Out(6) & + not IntDatSrds0Out(5) & IntDatSrds0Out(4) & + not IntDatSrds0Out(3) & IntDatSrds0Out(2) & + not IntDatSrds0Out(1) & IntDatSrds0Out(0); + IntDatSrds1 <= not IntDatSrds1Out(7) & IntDatSrds1Out(6) & + not IntDatSrds1Out(5) & IntDatSrds1Out(4) & + not IntDatSrds1Out(3) & IntDatSrds1Out(2) & + not IntDatSrds1Out(1) & IntDatSrds1Out(0); + +----------------------------------------------------------------------------------------------- +-- DATA REGISTER +----------------------------------------------------------------------------------------------- +Gen_1_DatReg : for n in 7 downto 0 generate + AdcData_I_Fdce_Reg0 : FDCE + generic map (INIT => '0') -- bit +--// port map (D => IntDatSrds0(n), C => DatClkDiv, CE => IntDatEna, CLR => DatRst, + port map (D => IntDatSrds0(n), C => DatClkDiv, CE => '1', CLR => '0', + Q => IntDat0(n)); + AdcData_I_Fdce_Reg1 : FDCE + generic map (INIT => '0') -- bit +--// port map (D => IntDatSrds1(n), C => DatClkDiv, CE => IntDatEna, CLR => DatRst, + port map (D => IntDatSrds1(n), C => DatClkDiv, CE => '1', CLR => '0', + Q => IntDat1(n)); +end generate Gen_1_DatReg; + + +IntDat0Mux <= IntDat0; +IntDat1Mux <= IntDat1; + +Gen_3_DatReg : for n in 7 downto 0 generate + AdcData_I_Fdce_Reg2 : FDCE + generic map (INIT => '0') -- bit +--// port map (D => IntDat0Mux(n), C => DatClkDiv, CE => IntDatEna, CLR => DatRst, + port map (D => IntDat0Mux(n), C => DatClkDiv, CE => '1', CLR => '0', + Q => IntDat0Swp(n)); + AdcData_I_Fdce_Reg3 : FDCE + generic map (INIT => '0') -- bit +--// port map (D => IntDat1Mux(n), C => DatClkDiv, CE => IntDatEna, CLR => DatRst, + port map (D => IntDat1Mux(n), C => DatClkDiv, CE => '1', CLR => '0', + Q => IntDat1Swp(n)); +end generate Gen_3_DatReg; + + + +----------------------------------------------------------------------------------------------- +-- 2-WIRE, 16x SERIALIZATION for 14-bit and 16-bit ADCs +-- Only one of these options can be chosen at a time. +-- 2-wire, Msb-Bit or Msb-Byte +-- 2-wire, Lsb-Bit or Lsb-Byte +----------------------------------------------------------------------------------------------- + +-- Bit mode, MSB First, 14-bits (16-bits) +-- Bit : 7, 6, 5, 4, 3, 2, 1, 0 +-- Channel 0 : 0/(D14), D12, D10, D8, D6, D4, D2, D0 +-- Channel 1 : 0/(D15), D13, D11, D9, D7, D5, D3, D1 +IntDatSwpBus <= IntDat1Swp(5) & IntDat0Swp(5) & IntDat1Swp(4) & IntDat0Swp(4) + & IntDat1Swp(7) & IntDat0Swp(7) & IntDat1Swp(6) & IntDat0Swp(6) + & IntDat1Swp(1) & IntDat0Swp(1) & IntDat1Swp(0) & IntDat0Swp(0) + & IntDat1Swp(3) & IntDat0Swp(3) & IntDat1Swp(2) & IntDat0Swp(2) + & IntDat1Swp(5) & IntDat0Swp(5) & IntDat1Swp(4) & IntDat0Swp(4) + & IntDat1Swp(7) & IntDat0Swp(7) & IntDat1Swp(6) & IntDat0Swp(6) + & IntDat1Swp(1) & IntDat0Swp(1) & IntDat1Swp(0) & IntDat0Swp(0) + & IntDat1Swp(3) & IntDat0Swp(3) & IntDat1Swp(2) & IntDat0Swp(2); +Gen_1_H : for n in 0 to 15 generate + I_Fdce_H : FDCE + generic map (INIT => '0') + port map (D => IntDatSwpBus(n+16), CE => '1', C => DatClkDiv, +--// CLR => DatRst, Q => DatOut(n+16)); + CLR => '0', Q => DatOut(n+16)); + I_Fdce_L : FDCE + generic map (INIT => '0') + port map (D => IntDatSwpBus(n), CE => '1', C => DatClkDiv, +--// CLR => DatRst, Q => DatOut(n)); + CLR => '0', Q => DatOut(n)); +end generate Gen_1_H; +----------------------------------------------------------------------------------------------- + + +end AdcData_struct; \ No newline at end of file diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcFrame.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcFrame.vhd new file mode 100644 index 0000000..ad33620 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcFrame.vhd @@ -0,0 +1,182 @@ +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.std_logic_UNSIGNED.all; + use IEEE.std_logic_textio.all; +library UNISIM; + use UNISIM.VCOMPONENTS.all; + +entity AdcFrame is + port ( + FrmClk_n : in std_logic; -- input n from IBUFDS_DIFF_OUT + FrmClk_p : in std_logic; -- input p from IBUFDS_DIFF_OUT + FrmClkRst : in std_logic; + FrmClkEna : in std_logic; + FrmClk : in std_logic; + FrmClkDiv : in std_logic; + FrmClkDone : in std_logic; -- Input from clock syncronisation. + Frame_out : out std_logic; + Frame_OK : out std_logic + ); +end AdcFrame; +----------------------------------------------------------------------------------------------- +-- Architecture section +----------------------------------------------------------------------------------------------- +architecture AdcFrame_struct of AdcFrame is +----------------------------------------------------------------------------------------------- +-- Constants, Signals and Attributes Declarations +----------------------------------------------------------------------------------------------- +-- +-- Constants + +-- Signals +signal IntFrmClk : std_logic := '0'; +signal IntFrmClk_n : std_logic := '0'; +signal IntFrmSrdsOut : std_logic_vector (7 downto 0); +signal IntFrmEna : std_logic := '0'; +signal Frame_out_S : std_Logic := '0'; +signal Frame_OK_S : std_Logic := '0'; +-- Attributes +attribute keep : string; +attribute KEEP_HIERARCHY : string; +attribute KEEP_HIERARCHY of AdcFrame_struct : architecture is "YES"; +attribute keep of Frame_out_S : signal is "TRUE"; +----------------------------------------------------------------------------------------------- +attribute mark_debug : string; +-- attribute mark_debug of FrmClkRst : signal is "true"; +-- attribute mark_debug of IntFrmSrdsOut : signal is "true"; +-- attribute mark_debug of IntFrmEna : signal is "true"; + +begin + +AdcFrame_I_Fdce_Done : FDCE + generic map (INIT => '0') -- bit + port map(D => FrmClkDone, CE => FrmClkEna, C => FrmClkDiv, CLR => FrmClkRst, + Q => IntFrmEna); + +----------------------------------------------------------------------------------------------- +-- ISERDES FOR FRAME CAPTURE +----------------------------------------------------------------------------------------------- +IntFrmClk <= FrmClk; +IntFrmClk_n <= not FrmClk; +-- +AdcFrame_I_Isrds_p : ISERDESE2 + generic map ( + SERDES_MODE => "MASTER", -- string + INTERFACE_TYPE => "NETWORKING", -- string + IOBDELAY => "NONE", -- string + DATA_RATE => "SDR", -- string + DATA_WIDTH => 4, -- integer <-- Number of bits + DYN_CLKDIV_INV_EN => "FALSE", -- string + DYN_CLK_INV_EN => "FALSE", -- string + NUM_CE => 1, -- integer + OFB_USED => "FALSE", -- string + INIT_Q1 => '0', -- bit; + INIT_Q2 => '0', -- bit; + INIT_Q3 => '0', -- bit; + INIT_Q4 => '0', -- bit; + SRVAL_Q1 => '0', -- bit; + SRVAL_Q2 => '0', -- bit; + SRVAL_Q3 => '0', -- bit; + SRVAL_Q4 => '0' -- bit + ) + port map ( + D => FrmClk_p, -- in + DDLY => '0', -- in + OFB => '0', -- in + BITSLIP => '0', -- in + CE1 => IntFrmEna, -- in + CE2 => '0', -- in + RST => FrmClkRst, -- in + CLK => IntFrmClk, -- in + CLKB => '0', -- in + CLKDIV => FrmClkDiv, -- in + CLKDIVP => '0', -- in + OCLK => '0', -- in + OCLKB => '0', -- in + DYNCLKDIVSEL => '0', -- in + DYNCLKSEL => '0', -- in + SHIFTOUT1 => open, -- out + SHIFTOUT2 => open, -- out + O => Frame_out_S, -- open, -- out + Q1 => IntFrmSrdsOut(6), -- out (0) + Q2 => IntFrmSrdsOut(4), -- out (2) + Q3 => IntFrmSrdsOut(2), -- out (4) + Q4 => IntFrmSrdsOut(0), -- out (6) + Q5 => open, -- out + Q6 => open, -- out + Q7 => open, -- out + Q8 => open, -- out + SHIFTIN1 => '0', -- in + SHIFTIN2 => '0' -- in + ); +Frame_out <= Frame_out_S; +-- +AdcFrame_I_Isrds_n : ISERDESE2 + generic map ( + SERDES_MODE => "MASTER", -- string + INTERFACE_TYPE => "NETWORKING", -- string + IOBDELAY => "NONE", -- string + DATA_RATE => "SDR", -- string + DATA_WIDTH => 4, -- integer 12-bit = 3 and 14/16 b its = 4 + DYN_CLKDIV_INV_EN => "FALSE", -- string + DYN_CLK_INV_EN => "FALSE", -- string + NUM_CE => 1, -- integer + OFB_USED => "FALSE", -- string + INIT_Q1 => '0', -- bit; + INIT_Q2 => '0', -- bit; + INIT_Q3 => '0', -- bit; + INIT_Q4 => '0', -- bit; + SRVAL_Q1 => '0', -- bit; + SRVAL_Q2 => '0', -- bit; + SRVAL_Q3 => '0', -- bit; + SRVAL_Q4 => '0' -- bit + ) + port map ( + D => FrmClk_n, -- in + DDLY => '0', -- in + OFB => '0', -- in + BITSLIP => '0', -- in + CE1 => IntFrmEna, -- in + CE2 => '0', -- in + RST => FrmClkRst, -- in + CLK => IntFrmClk_n, -- in + CLKB => '0', -- in + CLKDIV => FrmClkDiv, -- in + CLKDIVP => '0', -- in + OCLK => '0', -- in + OCLKB => '0', -- in + DYNCLKDIVSEL => '0', -- in + DYNCLKSEL => '0', -- in + SHIFTOUT1 => open, -- out + SHIFTOUT2 => open, -- out + O => open, -- out + Q1 => IntFrmSrdsOut(7), -- out (1) + Q2 => IntFrmSrdsOut(5), -- out (3) + Q3 => IntFrmSrdsOut(3), -- out (5) + Q4 => IntFrmSrdsOut(1), -- out (7) + Q5 => open, -- out + Q6 => open, -- out + Q7 => open, -- out + Q8 => open, -- out + SHIFTIN1 => '0', -- in + SHIFTIN2 => '0' -- in + ); + +----------------------------------------------------------------------------------------------- +-- FRAME PATTERN COMPARATOR +----------------------------------------------------------------------------------------------- +process(FrmClkDiv,FrmClkRst) +begin + if FrmClkRst='1' then + Frame_OK_S <= '0'; + elsif rising_edge(FrmClkDiv) then + if IntFrmSrdsOut=x"a5" then + Frame_OK_S <= '1'; + else + Frame_OK_S <= '0'; + end if; + end if; +end process; +Frame_OK <= Frame_OK_S; + +end AdcFrame_struct; diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcSerialProg.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcSerialProg.vhd new file mode 100644 index 0000000..f9d328f --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcSerialProg.vhd @@ -0,0 +1,320 @@ +--------------------------------------------------------------------------------- +-- Company: KVI/RUG/Groningen University +-- Engineer: Peter Schakel +-- Create Date: 06-11-2014 +-- Module Name: AdcSerialProg +-- Description: Serial programming of LTM9009 +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all ; +USE ieee.std_logic_arith.all ; +USE work.panda_package.all; +library UNISIM; +use UNISIM.VComponents.all; + +---------------------------------------------------------------------------------- +-- AdcSerialProg +-- Module to convert serial data from ADCs (LTM9009-14) to parallel +-- Based on Xilinx serial ADC reference design +-- +-- +-- Library: +-- +-- Generics: +-- +-- Inputs: +-- clock200MHz : 200MHz clock input for IODELAYCTRL +-- reset : reset ADCs +-- ADCs_enable : enable signal for ADCs +-- AD*_P : serial data links from ADCs, LVDS positive +-- AD*_N : serial data links from ADCs, LVDS negative +-- DCO*_P : data clock from ADCs, LVDS positive +-- DCO*_N : data clock from ADCs, LVDS negative +-- FRA*_P : frame start signals from ADCs, LVDS positive +-- FRA*_N : frame start signals from ADCs, LVDS negative +-- +-- Outputs: +-- ADC_clk : clock for parallel ADC data +-- adcdata : parallel ADC data +-- +-- Components: +-- AdcToplevel : top-level module from Xilinx serial ADC reference design +-- +---------------------------------------------------------------------------------- + +entity AdcSerialProg is + port ( + clock : in std_logic; + reset : in std_logic; + init : in std_logic; + clock_out : out std_logic; + dataA_in : in std_logic_vector(3 downto 0); + dataB_in : in std_logic_vector(3 downto 0); + data_out : out std_logic; + chipnselectA : out std_logic_vector(3 downto 0); + chipnselectB : out std_logic_vector(3 downto 0); + selREGS : in std_logic_vector(2 downto 0) + ); +end AdcSerialProg; + +architecture Behavioral of AdcSerialProg is + +constant NROFREGS : integer := 10; +type RomType is array (0 to 8*16-1) of std_logic_vector(16 downto 0); -- highest bit : csa/csb +--type RomType is array (0 to NROFREGS-1) of std_logic_vector(15 downto 0); +--CONSTANT REGS : RomType := -- bit15:0=CSA,1=CSB +-- ( +-- "0000000010000000", -- A0 (bit7=Reset) +-- "1000000010000000", -- A0 (bit7=Reset) +-- "0000000100000000", -- A1 (clock stabilize no random binary normal) +-- "1000000100000000", -- A1 (clock stabilize no random binary normal) +-- "0000001000000000", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits) +-- "1000001000000000", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits) +-- "0000001100000000", -- A3 (no test pattern) +-- "1000001100000000", -- A3 (no test pattern) +-- "0000010000000000", -- A4 (test pattern) +-- "1000010000000000" -- A4 (test pattern) +-- ); +CONSTANT REGS : RomType := -- bit15:0=CSA,1=CSB + ( + "00000000010000000", -- A0 (bit7=Reset) + "10000000010000000", -- A0 (bit7=Reset) + "00000000100000000", -- A1 (clock stabilize no random binary normal) + "10000000100000000", -- A1 (clock stabilize no random binary normal) + "00000001000000000", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits) + "10000001000000000", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits) + "00000001100000000", -- A3 (no test pattern) + "10000001100000000", -- A3 (no test pattern) + "00000010000000000", -- A4 (test pattern) + "10000010000000000", -- A4 (test pattern) + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + + "00000000010000000", -- A0 (bit7=Reset) + "10000000010000000", -- A0 (bit7=Reset) + "00000000100000000", -- A1 (clock stabilize no random binary normal) + "10000000100000000", -- A1 (clock stabilize no random binary normal) + "00000001000000001", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits) + "10000001000000001", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits) +-- "00000001000000000", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits) +-- "10000001000000000", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits) + "00000001100000000", -- A3 (no test pattern) + "10000001100000000", -- A3 (no test pattern) + "00000010000000000", -- A4 (test pattern) + "10000010000000000", -- A4 (test pattern) + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + + "00000000010000000", -- A0 (bit7=Reset) + "10000000010000000", -- A0 (bit7=Reset) + "00000000100000000", -- A1 (clock stabilize no random binary normal) + "10000000100000000", -- A1 (clock stabilize no random binary normal) + "00000001000100111", -- A2 (4mA LVDS no termination enabled 2lanes 16bits) + "10000001000100111", -- A2 (4mA LVDS no termination enabled 2lanes 16bits) +-- "00000001000100000", -- A2 (4mA LVDS no termination enabled 2lanes 16bits) +-- "10000001000100000", -- A2 (4mA LVDS no termination enabled 2lanes 16bits) + "00000001100000000", -- A3 (no test pattern) + "10000001100000000", -- A3 (no test pattern) + "00000010000000000", -- A4 (test pattern) + "10000010000000000", -- A4 (test pattern) + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + + "00000000010000000", -- A0 (bit7=Reset) + "10000000010000000", -- A0 (bit7=Reset) + "00000000100000000", -- A1 (clock stabilize no random binary normal) + "10000000100000000", -- A1 (clock stabilize no random binary normal) + "00000001001000000", -- A2 (4.5mA LVDS no termination enabled 2lanes 16bits) + "10000001001000000", -- A2 (4.5mA LVDS no termination enabled 2lanes 16bits) + "00000001100000000", -- A3 (no test pattern) + "10000001100000000", -- A3 (no test pattern) + "00000010000000000", -- A4 (test pattern) + "10000010000000000", -- A4 (test pattern) + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + + "00000000010000000", -- A0 (bit7=Reset) + "10000000010000000", -- A0 (bit7=Reset) + "00000000100000000", -- A1 (clock stabilize no random binary normal) + "10000000100000000", -- A1 (clock stabilize no random binary normal) + "00000001010100000", -- A2 (2.5mA LVDS +termination enabled 2lanes 16bits) + "10000001010100000", -- A2 (2.5mA LVDS +termination enabled 2lanes 16bits) + "00000001100000000", -- A3 (no test pattern) + "10000001100000000", -- A3 (no test pattern) + "00000010000000000", -- A4 (test pattern) + "10000010000000000", -- A4 (test pattern) + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + + "00000000010000000", -- A0 (bit7=Reset) + "10000000010000000", -- A0 (bit7=Reset) + "00000000100000000", -- A1 (clock stabilize no random binary normal) + "10000000100000000", -- A1 (clock stabilize no random binary normal) + "00000001011000000", -- A2 (2.1mA LVDS +termination enabled 2lanes 16bits) + "10000001011000000", -- A2 (2.1mA LVDS +termination enabled 2lanes 16bits) + "00000001100000000", -- A3 (no test pattern) + "10000001100000000", -- A3 (no test pattern) + "00000010000000000", -- A4 (test pattern) + "10000010000000000", -- A4 (test pattern) + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + + "00000000010000000", -- A0 (bit7=Reset) + "10000000010000000", -- A0 (bit7=Reset) + "00000000100000000", -- A1 (clock stabilize no random binary normal) + "10000000100000000", -- A1 (clock stabilize no random binary normal) + "00000001011100000", -- A2 (1.75mA LVDS +termination enabled 2lanes 16bits) + "10000001011100000", -- A2 (1.75mA LVDS +termination enabled 2lanes 16bits) + "00000001100000000", -- A3 (no test pattern) + "10000001100000000", -- A3 (no test pattern) + "00000010000000000", -- A4 (test pattern) + "10000010000000000", -- A4 (test pattern) + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + + "00000000010000000", -- A0 (bit7=Reset) + "10000000010000000", -- A0 (bit7=Reset) + "00000000100000000", -- A1 (clock stabilize no random binary normal) + "10000000100000000", -- A1 (clock stabilize no random binary normal) + "00000001000000000", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits) + "10000001000000000", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits) + "00000001100000000", -- A3 (no test pattern) + "10000001100000000", -- A3 (no test pattern) + "00000010000000000", -- A4 (test pattern) + "10000010000000000", -- A4 (test pattern) + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000", -- dummy + "00000000000000000" -- dummy + + ); + + +type stage_type is (waiting,cs_high,cs_low,sdo_set,clk_rise,clk_high,clk_fall); +signal stage_S : stage_type := waiting; + +--type adcdata_type is array(0 to 31) of std_logic_vector(13 downto 0); +type AdcDataOut_type is array(0 to 3) of std_logic_vector(127 downto 0); +type adcdataserial_type is array(0 to 3) of std_logic_vector(7 downto 0); +signal bitcount_S : integer range 0 to 15; +signal regcount_S : integer range 0 to NROFREGS-1; +signal clock_out_S : std_logic; +signal data_out_S : std_logic; +signal chipnselectA_S : std_logic; +signal chipnselectB_S : std_logic; +signal REGS_out_S : std_logic_vector(16 downto 0); + +begin + +process (clock) +begin + if (clock'event and clock = '1') then + REGS_out_S <= REGS(conv_integer(selREGS)*16+regcount_S); + end if; +end process; + + + +clock_out <= clock_out_S; +data_out <= data_out_S; +chipnselectA <= chipnselectA_S & chipnselectA_S & chipnselectA_S & chipnselectA_S; +chipnselectB <= chipnselectB_S & chipnselectB_S & chipnselectB_S & chipnselectB_S; + +process(clock) +begin + if rising_edge(clock) then + if reset='1' then + chipnselectA_S <= '1'; + chipnselectB_S <= '1'; + clock_out_S <= '0'; + stage_S <= waiting; + else + case stage_S is + when waiting => + bitcount_S <= 15; + regcount_S <= 0; + chipnselectA_S <= '1'; + chipnselectB_S <= '1'; + clock_out_S <= '0'; + if init='1' then + stage_S <= cs_high; + end if; + when cs_high => + clock_out_S <= '0'; + chipnselectA_S <= '1'; + chipnselectB_S <= '1'; + stage_S <= cs_low; + when cs_low => + clock_out_S <= '0'; + chipnselectA_S <= REGS_out_S(16); + chipnselectB_S <= not REGS_out_S(16); + stage_S <= sdo_set; + when sdo_set => + data_out_S <= REGS_out_S(bitcount_S); + clock_out_S <= '0'; + stage_S <= clk_rise; + when clk_rise => + clock_out_S <= '1'; + stage_S <= clk_high; + when clk_high => + clock_out_S <= '1'; + stage_S <= clk_fall; + when clk_fall => + clock_out_S <= '0'; + if bitcount_S=0 then + bitcount_S <= 15; + if regcount_S=NROFREGS-1 then + regcount_S <= 0; + stage_S <= waiting; + else + regcount_S <= regcount_S+1; + stage_S <= cs_high; + end if; + else + bitcount_S <= bitcount_S-1; + stage_S <= sdo_set; + end if; + when others => + chipnselectA_S <= '1'; + chipnselectB_S <= '1'; + clock_out_S <= '0'; + stage_S <= waiting; + end case; + end if; + end if; +end process; + + +end Behavioral; diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcToplevel.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcToplevel.vhd new file mode 100644 index 0000000..0911450 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcToplevel.vhd @@ -0,0 +1,492 @@ +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.STD_LOGIC_ARITH.ALL; + use IEEE.std_logic_UNSIGNED.all; + use IEEE.std_logic_textio.all; + use std.textio.all; +library UNISIM; + use UNISIM.VCOMPONENTS.all; + + +entity AdcToplevel is + generic ( + C_BufioLoc : string := "BUFIO_X0Y6"; + C_BufrLoc : string := "BUFR_X0Y6"; + C_IserdesLoc : string := "BUFR_X0Y17"; + C_StatTaps : integer := 16; + C_AdcUseIdlyCtrl : integer := 1; -- 0 = No, 1 = Yes + C_AdcIdlyCtrlLoc : string := "IDELAYCTRL_X0Y1" + ); + port ( + DCLK_p : in std_logic; + DCLK_n : in std_logic; -- Not used. + FCLK_p : in std_logic; + FCLK_n : in std_logic; + DATA_p : in std_logic_vector(7 downto 0); + DATA_n : in std_logic_vector(7 downto 0); + SysRefClk : in std_logic; -- 200 MHz for IODELAYCTRL from application + clockAsync : in std_logic; + AdcIntrfcRst : in std_logic; + AdcIntrfcEna : in std_logic; + AdcBitClkDone : out std_logic; + AdcIdlyCtrlRdy : out std_logic; + AdcClkDiv : out std_logic; + AdcDataClk : in std_logic; + AdcDataOut : out std_logic_vector(127 downto 0); + ADCs_ready : out std_logic + ); +end AdcToplevel; + +----------------------------------------------------------------------------------------------- +-- Arcitecture section +----------------------------------------------------------------------------------------------- +architecture AdcToplevel_struct of AdcToplevel is +----------------------------------------------------------------------------------------------- +-- Component Instantiation +----------------------------------------------------------------------------------------------- +component AdcFrame is + port ( + FrmClk_n : in std_logic; -- input n from IBUFDS_DIFF_OUT + FrmClk_p : in std_logic; -- input p from IBUFDS_DIFF_OUT + FrmClkRst : in std_logic; + FrmClkEna : in std_logic; + FrmClk : in std_logic; + FrmClkDiv : in std_logic; + FrmClkDone : in std_logic; -- Input from clock syncronisation. + Frame_out : out std_logic; + Frame_OK : out std_logic + ); +end component; +component AdcClock is + generic ( + C_BufioLoc : string := C_BufioLoc; + C_BufrLoc : string := C_BufrLoc; + C_IserdesLoc : string := C_IserdesLoc; + C_StatTaps : integer := C_StatTaps + ); + port ( + BitClk : in std_logic; + BitClkRst : in std_logic; + BitClkEna : in std_logic; + BitClkReSync : in std_logic; + BitClk_MonClkOut : out std_logic; -- CLK output + BitClk_MonClkIn : in std_logic; -- ISERDES.CLK input + BitClk_RefClkOut : out std_logic; -- CLKDIV & logic output + BitClk_RefClkIn : in std_logic; -- CLKDIV & logic input + BitClkAlignWarn : out std_logic; + BitClkInvrtd : out std_logic; + BitClkDone : out std_logic + ); +end component; +component AdcData is + port ( + DatD0_n : in std_logic; + DatD0_p : in std_logic; + DatD1_n : in std_logic; + DatD1_p : in std_logic; + DatClk : in std_logic; + DatClkDiv : in std_logic; + DatRst : in std_logic; + DatEna : in std_logic; + DatDone : in std_logic; + DatOut : out std_logic_vector(31 downto 0) + ); +end component; + +component posedge_to_pulse is + port ( + clock_in : in std_logic; + clock_out : in std_logic; + en_clk : in std_logic; + signal_in : in std_logic; + pulse : out std_logic + ); +end component; + + +----------------------------------------------------------------------------------------------- +-- Constants, Signals and Attributes Declarations +----------------------------------------------------------------------------------------------- + +-- Signals +signal IntRst : std_logic; +signal IntEna_d : std_logic; +signal IntEna : std_logic; +-- +signal IntBitClkDone : std_logic; +signal IntClk : std_logic; +signal IntClkDiv : std_logic; +signal IntDataOut : std_logic_vector(127 downto 0); +----------------------------------------------------------------------------------------------- +-- + +signal AdcBitClkAlgnWrn_S : std_logic := '0'; +signal AdcBitClkInvrtd_S : std_logic := '0'; +signal AdcIdlyCtrlRdy_S : std_logic := '0'; +signal Frame_OK_S : std_logic := '0'; +signal ADCs_ready_S : std_logic := '0'; +signal IntBitClkDone_S : std_logic := '0'; +signal IntBitClkDone0_S : std_logic := '0'; + +signal slipcounter_S : integer range 0 to 63 := 0; +signal ClockResync_S : std_logic := '0'; +signal ClockResync0_S : std_logic := '0'; +signal ClockResync1_S : std_logic := '0'; +signal ClockResync2_S : std_logic := '0'; +signal ClockReset_S : std_logic := '0'; + +signal IntEna_S : std_logic := '0'; +signal IntRst_S : std_logic := '0'; +signal IntEna0_S : std_logic := '0'; +signal IntRst0_S : std_logic := '0'; +signal frame_S : std_logic := '0'; +signal reset_S : std_logic := '0'; + + +signal AdcData_negedge : std_logic_vector(127 downto 0); +signal AdcDataOut_S : std_logic_vector(127 downto 0); + +signal AdcIntrfcRst_IdlyCtrl_S : std_logic := '1'; +signal AdcIntrfcRst_IntClkDiv_S : std_logic := '1'; +signal AdcIntrfcRst_clockAsync_S : std_logic := '1'; + +-- Attributes +attribute keep : string; +attribute LOC : string; +attribute KEEP_HIERARCHY : string; +attribute keep of IntClk : signal is "TRUE"; +attribute keep of IntClkDiv : signal is "TRUE"; +attribute keep of IntRst_S : signal is "TRUE"; +attribute keep of IntEna_S : signal is "TRUE"; +attribute keep of IntBitClkDone_S : signal is "TRUE"; + +attribute mark_debug : string; +-- attribute mark_debug of IntDataOut : signal is "true"; +-- attribute mark_debug of AdcBitClkAlgnWrn_S : signal is "true"; +-- attribute mark_debug of AdcBitClkInvrtd_S : signal is "true"; +-- attribute mark_debug of IntBitClkDone : signal is "true"; +-- attribute mark_debug of ClockReset_S : signal is "true"; +-- attribute mark_debug of ClockResync_S : signal is "true"; +-- attribute mark_debug of IntEna_S : signal is "true"; +-- attribute mark_debug of IntRst_S : signal is "true"; +-- attribute mark_debug of IntBitClkDone_S : signal is "true"; +-- attribute mark_debug of AdcIdlyCtrlRdy_S : signal is "true"; +-- attribute mark_debug of Frame_OK_S : signal is "true"; +-- attribute mark_debug of ADCs_ready_S : signal is "true"; +-- attribute mark_debug of AdcIntrfcRst : signal is "true"; + + + +attribute KEEP_HIERARCHY of AdcToplevel_struct : architecture is "YES"; +----------------------------------------------------------------------------------------------- +-- +begin + + +AdcClkDiv <= IntClkDiv; +ADCs_ready <= ADCs_ready_S; +AdcBitClkDone <= IntBitClkDone_S; + +process(IntClkDiv) +begin + if falling_edge(IntClkDiv) then -- falling_edge + AdcData_negedge <= IntDataOut; + end if; +end process; + +process(AdcDataClk) +begin + if rising_edge(AdcDataClk) then + AdcDataOut <= AdcData_negedge; + end if; +end process; +--AdcDataOut <= IntDataOut; + +----------------------------------------------------------------------------------------------- +-- IDELAYCTRL +-- An IDELAYCTRL component must be used per IO-bank. Normally a ADC port fits a whole +-- IO-Bank. The number of IDELAYCTRL components should thus fit with the number of ADC port. +-- In case of this test design, two ADC ports fit into one IO-Bank, thus only one IDLEAYCTRL +-- component is needed. +-- Don not forget to hook the outputs of the IDELAYCTRL components correctly to the reset and +-- enable for each ADC block. +-- Don not forget to LOC the IDELAYCTRL components down. +----------------------------------------------------------------------------------------------- +Gen_0 : if C_AdcUseIdlyCtrl = 0 generate + AdcIdlyCtrlRdy_S <= '1'; +end generate Gen_0; +Gen_1 : if C_AdcUseIdlyCtrl = 1 generate + attribute LOC of AdcToplevel_I_IdlyCtrl_0 : label is C_AdcIdlyCtrlLoc; +begin + AdcToplevel_I_IdlyCtrl_0 : IDELAYCTRL +--// port map (REFCLK => SysRefClk, RST => ClockResync_S, RDY => AdcIdlyCtrlRdy); --AdcIntrfcRst + port map (REFCLK => SysRefClk, RST => AdcIntrfcRst_IdlyCtrl_S, RDY => AdcIdlyCtrlRdy_S); -- +end generate Gen_1; +AdcIdlyCtrlRdy <= AdcIdlyCtrlRdy_S; + +process(SysRefClk) +begin + if (rising_edge(SysRefClk)) then + AdcIntrfcRst_IdlyCtrl_S <= AdcIntrfcRst; + end if; +end process; +process(IntClkDiv,AdcIntrfcRst) +begin + if AdcIntrfcRst='1' then + AdcIntrfcRst_IntClkDiv_S <= '1'; + elsif (rising_edge(IntClkDiv)) then + AdcIntrfcRst_IntClkDiv_S <= AdcIntrfcRst; + end if; +end process; +process(clockAsync,AdcIntrfcRst) +begin + if AdcIntrfcRst='1' then + AdcIntrfcRst_clockAsync_S <= '1'; + elsif (rising_edge(clockAsync)) then + AdcIntrfcRst_clockAsync_S <= AdcIntrfcRst; + end if; +end process; + + +-- IntRst and IntEna are the reset and enable signals to be used in the interafce. +-- they are generated from the incomming system enable and reset. +AdcToplevel_I_Fdpe_Rst : FDPE + generic map (INIT => '1') + port map (C => IntClkDiv, CE => '1', PRE => AdcIntrfcRst_IntClkDiv_S, D => '0', Q => IntRst); --AdcIntrfcRst +AdcToplevel_I_Fdce_Ena_0 : FDCE + generic map (INIT => '0') + port map (C => IntClkDiv, CE => AdcIntrfcEna, CLR => IntRst, D => '1', Q => IntEna_d); +AdcToplevel_I_Fdce_Ena_1 : FDCE + generic map (INIT => '0') + port map (C => IntClkDiv, CE => '1', CLR => IntRst, D => IntEna_d, Q => IntEna); + +----------------------------------------------------------------------------------------------- +-- BIT CLOCK +-- IntClk and IntClkDiv are the clock to be used in the interface. +----------------------------------------------------------------------------------------------- +-- There is no IBUFGDS used on this level of the design. +-- The IBUFGDS can be found in the AdcIo level. +-- That is this the reason why the DCLK_n is not used here. +-- At the AdcIo level the DCLK_n output is connected to GND. +AdcToplevel_I_AdcClock : AdcClock +generic map ( + C_BufioLoc => C_BufioLoc, -- string + C_BufrLoc => C_BufrLoc, -- string + C_StatTaps => C_StatTaps -- integer + ) +port map ( + BitClk => DCLK_p, -- in + BitClkRst => IntRst, -- ClockReset_S, --//IntRst, -- IntRst, -- in + BitClkEna => IntEna, -- in + BitClkReSync => ClockResync_S, -- AdcReSync, -- in + BitClk_MonClkOut => IntClk, -- out -->--|---->---- + BitClk_MonClkIn => IntClk, -- in --<--| + BitClk_RefClkOut => IntClkDiv, -- out -->----|-->---- + BitClk_RefClkIn => IntClkDiv, -- in --<----| + BitClkAlignWarn => AdcBitClkAlgnWrn_S,-- out + BitClkInvrtd => AdcBitClkInvrtd_S, -- out + BitClkDone => IntBitClkDone -- out Enables the AdcFrame block. +); + + +AdcToplevel_I_AdcFrame : AdcFrame +port map ( + FrmClk_n => FCLK_n, -- in input n from IBUFDS_DIFF_OUT + FrmClk_p => FCLK_p, -- in input p from IBUFDS_DIFF_OUT + FrmClkRst => IntRst_S, -- in + FrmClkEna => IntEna_S, -- in + FrmClk => IntClk, -- in + FrmClkDiv => IntClkDiv, -- in + FrmClkDone => IntBitClkDone_S, -- in From AdcClock done. + Frame_out => frame_S, + Frame_OK => Frame_OK_S +); + +----------------------------------------------------------------------------------------------- +-- DATA INPUTS +-- Default the interface is set in BYTE and MSB first mode. +-- This is coded in the AdcData level and can be mnodified if wanted. +-- Enable the generics and all selection possibilities are available. +----------------------------------------------------------------------------------------------- +Gen_2 : for cw in 3 downto 0 generate + AdcToplevel_I_AdcData : AdcData + port map ( + DatD0_n => DATA_n(cw*2), -- in + DatD0_p => DATA_p(cw*2), -- in + DatD1_n => DATA_n((cw*2)+1), -- in + DatD1_p => DATA_p((cw*2)+1), -- in + DatClk => IntClk, -- in + DatClkDiv => IntClkDiv, -- in + DatRst => IntRst_S, -- in + DatEna => IntEna_S, -- in + DatDone => IntBitClkDone_S, -- in + DatOut => IntDataOut((32*(cw+1))-1 downto (32*(cw+1))-32) + ); +end generate Gen_2; + +--process(SysRefClk) +--begin +-- if (rising_edge(SysRefClk)) then +-- if (AdcIntrfcRst='1') then -- or (ClockResync0_S='1') then +-- reset_clockdiv0_S <= '1'; +-- elsif frame_S='1' then +-- reset_clockdiv0_S <= '0'; +-- end if; +-- end if; +--end process; + +--process(IntClkDiv,reset_clockdiv0_S) +--variable counter_V : integer range 0 to 3 := 0; +--begin +-- if reset_clockdiv0_S='1' then +-- ClockResync_S <= '0'; +-- counter_V := 0; +-- elsif (rising_edge(IntClkDiv)) then +-- if counter_V<3 then +-- counter_V := counter_V+1; +-- ClockResync_S <= '1'; +-- else +-- ClockResync_S <= '0'; +-- end if; +-- end if; +--end process; +--ClockResync_S <= ClockResync0_S; +--posedge_to_pulse1: posedge_to_pulse port map( +-- clock_in => IntClkDiv, +-- clock_out => clockAsync, +-- en_clk => '1', +-- signal_in => ClockResync1_S, +-- pulse => ClockResync_S +-- ); + +--process(clockAsync,AdcIntrfcRst) +--variable count_V : integer range 0 to 127 := 0; +--variable countsync_V : integer range 0 to 127 := 7; +--begin +-- if (AdcIntrfcRst='1') then +-- reset_S <= '1'; +-- ClockResync_S <= '1'; +-- count_V := 0; +-- elsif (rising_edge(clockAsync)) then +-- if count_V=0 then +-- if countsync_V>25 then +-- countsync_V := 7; +-- else +-- countsync_V := countsync_V+1; +-- end if; +-- end if; +-- ClockResync1_S <= ClockResync0_S; +-- ClockResync2_S <= ClockResync1_S; +-- if (ClockResync2_S='0') and (ClockResync1_S='1') then +-- reset_S <= '1'; +-- ClockResync_S <= '1'; +-- count_V := 0; +-- elsif (count_V '0') + port map (C => IntClkDiv, CE => '1', PRE => IntRst, D => IntRst0_S, Q => IntRst_S); +sync_IntEna : FDCE + generic map (INIT => '0') + port map (C => IntClkDiv, CE => '1', CLR => IntRst, D => IntEna0_S, Q => IntEna_S); +sync_IntBitClkDone : FDCE + generic map (INIT => '0') + port map (C => IntClkDiv, CE => '1', CLR => '0', D => IntBitClkDone0_S, Q => IntBitClkDone_S); + + +end AdcToplevel_struct; \ No newline at end of file diff --git a/FEE_ADC32board/modules/FEE_ADCinput_module.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/FEE_ADCinput_module.vhd similarity index 65% rename from FEE_ADC32board/modules/FEE_ADCinput_module.vhd rename to FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/FEE_ADCinput_module.vhd index 05c8721..9a99677 100644 --- a/FEE_ADC32board/modules/FEE_ADCinput_module.vhd +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/FEE_ADCinput_module.vhd @@ -26,7 +26,7 @@ use UNISIM.VComponents.all; -- -- Inputs: -- clock200MHz : 200MHz clock input for IODELAYCTRL --- reset : reset ADCs +-- reset : reset ADCs -- ADCs_enable : enable signal for ADCs -- AD*_P : serial data links from ADCs, LVDS positive -- AD*_N : serial data links from ADCs, LVDS negative @@ -47,6 +47,8 @@ use UNISIM.VComponents.all; entity FEE_ADCinput_module is port ( clock200MHz : in std_logic; + clock80MHz : in std_logic; + clockAsync : in std_logic; reset : in std_logic; ADCs_enable : in std_logic; ----ADC1--------------------------------------------- @@ -225,76 +227,69 @@ entity FEE_ADCinput_module is FRB4_P : in std_logic; FRB4_N : in std_logic; ADC_clk : out std_logic; - ADCs_ready : out std_logic; + ADCs_ready : out std_logic; adcdata : out array_adc_type ); end FEE_ADCinput_module; architecture Behavioral of FEE_ADCinput_module is - - +constant C_StatTaps : integer := 10;-- 10 = midden van 20 steps voor 80MHz/2 DDR component AdcToplevel is generic ( - C_AdcChnls : integer := 4; -- Number of ADC in a package - C_AdcWireInt : integer := 2; -- 2 = 2-wire, 1 = 1-wire interface - C_BufioLoc : string := "BUFIODQS_X1Y15"; - C_BufrLoc : string := "BUFR_X0Y6"; - C_AdcBits : integer := 16; - C_StatTaps : integer := 16; - C_AdcUseIdlyCtrl : integer := 1; -- 0 = No, 1 = Yes - C_AdcIdlyCtrlLoc : string := "IDELAYCTRL_X0Y3"; - C_FrmPattern : string := "0000000000001111" -- "0000000011110000" -- Read above text! + C_BufioLoc : string := "BUFIO_X0Y6"; + C_BufrLoc : string := "BUFR_X0Y6"; + C_IserdesLoc : string := "BUFR_X0Y17"; + C_StatTaps : integer := C_StatTaps; + C_AdcUseIdlyCtrl : integer := 1; -- 0 = No, 1 = Yes + C_AdcIdlyCtrlLoc : string := "IDELAYCTRL_X0Y1" ); port ( - DCLK_p : in std_logic; - DCLK_n : in std_logic; -- Not used. - FCLK_p : in std_logic; - FCLK_n : in std_logic; - DATA_p : in std_logic_vector((C_AdcChnls*C_AdcWireInt)-1 downto 0); - DATA_n : in std_logic_vector((C_AdcChnls*C_AdcWireInt)-1 downto 0); - -- application connections - SysRefClk : in std_logic; -- 200 MHz for IODELAYCTRL from application - AdcIntrfcRst : in std_logic; - AdcIntrfcEna : in std_logic; - AdcReSync : in std_logic; - AdcFrmSyncWrn : out std_logic; - AdcBitClkAlgnWrn : out std_logic; - AdcBitClkInvrtd : out std_logic; - AdcBitClkDone : out std_logic; - AdcIdlyCtrlRdy : out std_logic; - - AdcClkDiv : out std_logic; - AdcDataClk : in std_logic; - AdcDataClkNot : in std_logic; - AdcDataOut : out std_logic_vector((32*((C_AdcChnls/2)*C_AdcWireInt))-1 downto 0); - ADCs_ready : out std_logic; - testOK : out std_logic; - testword0 : out std_logic_vector(35 downto 0) + DCLK_p : in std_logic; + DCLK_n : in std_logic; -- Not used. + FCLK_p : in std_logic; + FCLK_n : in std_logic; + DATA_p : in std_logic_vector(7 downto 0); + DATA_n : in std_logic_vector(7 downto 0); + SysRefClk : in std_logic; -- 200 MHz for IODELAYCTRL from application + clockAsync : in std_logic; + AdcIntrfcRst : in std_logic; + AdcIntrfcEna : in std_logic; + AdcBitClkDone : out std_logic; + AdcIdlyCtrlRdy : out std_logic; + AdcClkDiv : out std_logic; + AdcDataClk : in std_logic; + AdcDataOut : out std_logic_vector(127 downto 0); + ADCs_ready : out std_logic ); -end component; - -component FEE_clockbuf80MHz - port( - CLK_IN1 : in std_logic; - CLK_OUT1 : out std_logic; - CLK_OUT2 : out std_logic - ); -end component; - -function TermOrNot (Term : integer) return boolean is -begin - if (Term = 0) then - return FALSE; - else - return TRUE; - end if; -end TermOrNot; - -constant C_OnChipLvdsTerm : integer := 1; +end component; + +component FEE_clockbuf80MHz + port( + CLK_IN1 : in std_logic; + CLK_OUT1 : out std_logic; + CLK_OUT2 : out std_logic + ); +end component; + +--COMPONENT async_fifo_512x128 +-- PORT ( +-- rst : IN STD_LOGIC; +-- wr_clk : IN STD_LOGIC; +-- rd_clk : IN STD_LOGIC; +-- din : IN STD_LOGIC_VECTOR(127 DOWNTO 0); +-- wr_en : IN STD_LOGIC; +-- rd_en : IN STD_LOGIC; +-- dout : OUT STD_LOGIC_VECTOR(127 DOWNTO 0); +-- full : OUT STD_LOGIC; +-- empty : OUT STD_LOGIC +-- ); +--END COMPONENT; + +constant C_OnChipLvdsTerm : boolean := true; --type adcdata_type is array(0 to 31) of std_logic_vector(13 downto 0); -type AdcDataOut_type is array(0 to 3) of std_logic_vector((32*((4/2)*2))-1 downto 0); +type AdcDataOut_type is array(0 to 3) of std_logic_vector(127 downto 0); type adcdataserial_type is array(0 to 3) of std_logic_vector(7 downto 0); signal adcdata1458_P : adcdataserial_type; @@ -353,299 +348,313 @@ signal AdcIdlyCtrlRdyB_S : std_logic_vector(0 to 3); signal AdcBitClkInvrtdB_S : std_logic_vector(0 to 3); signal adcclockB_S : std_logic_vector(0 to 3); signal AdcDataOutB_S : AdcDataOut_type; - + +signal ADCs_ready0_S : std_logic_vector(0 to 7); +signal ADCs_ready1_S : std_logic_vector(0 to 7); signal ADCs_ready_S : std_logic_vector(0 to 7); signal adcdata0_S : array_adc_type; signal adcdata1_S : array_adc_type; -signal ADC_clk_S : std_logic; -signal ADC_clknot_S : std_logic; +signal ADC_clk_S : std_logic; + +attribute keep : string; +attribute DONT_TOUCH : string; +attribute keep of ADC_clk_S : signal is "TRUE"; +attribute DONT_TOUCH of ADC_clk_S : signal is "TRUE"; + +signal sync_AdcDataOutA_S : AdcDataOut_type; +signal sync_AdcDataOutB_S : AdcDataOut_type; -attribute keep : string; -attribute keep of ADC_clk_S : signal is "TRUE"; -attribute keep of ADC_clknot_S: signal is "TRUE"; +attribute mark_debug : string; +--attribute mark_debug of ADCs_ready1_S : signal is "true"; begin ADC_clk <= ADC_clk_S; -ADCs_ready <= '1' when (ADCs_ready_S=x"ff") and (reset='0') else '0'; - +ADCs_ready <= '1' when (ADCs_ready1_S=x"ff") and (reset='0') else '0'; + +process(clock80MHz) -- synchronise to 1 clock +begin + if (rising_edge(clock80MHz)) then + ADCs_ready0_S <= ADCs_ready_S; + ADCs_ready1_S <= ADCs_ready0_S; + end if; +end process; -- ADC inputs ---------------------------------------------------------------------- ---- B and A swopped !!! adcdata1458_0B0 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD11B_P, IB => AD11B_N, O => adcdata1458_P(0)(0), OB => adcdata1458_N(0)(0)); adcdata1458_0A0 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD11A_P, IB => AD11A_N, O => adcdata1458_P(0)(1), OB => adcdata1458_N(0)(1)); adcdata1458_0B1 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD14B_P, IB => AD14B_N, O => adcdata1458_P(0)(2), OB => adcdata1458_N(0)(2)); adcdata1458_0A1 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD14A_P, IB => AD14A_N, O => adcdata1458_P(0)(3), OB => adcdata1458_N(0)(3)); adcdata1458_0B2 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD15B_P, IB => AD15B_N, O => adcdata1458_P(0)(4), OB => adcdata1458_N(0)(4)); adcdata1458_0A2 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD15A_P, IB => AD15A_N, O => adcdata1458_P(0)(5), OB => adcdata1458_N(0)(5)); adcdata1458_0B3 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD18B_P, IB => AD18B_N, O => adcdata1458_P(0)(6), OB => adcdata1458_N(0)(6)); adcdata1458_0A3 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD18A_P, IB => AD18A_N, O => adcdata1458_P(0)(7), OB => adcdata1458_N(0)(7)); adcdata2367_0B0 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD12B_P, IB => AD12B_N, O => adcdata2367_P(0)(0), OB => adcdata2367_N(0)(0)); adcdata2367_0A0 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD12A_P, IB => AD12A_N, O => adcdata2367_P(0)(1), OB => adcdata2367_N(0)(1)); adcdata2367_0B1 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD13B_P, IB => AD13B_N, O => adcdata2367_P(0)(2), OB => adcdata2367_N(0)(2)); adcdata2367_0A1 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD13A_P, IB => AD13A_N, O => adcdata2367_P(0)(3), OB => adcdata2367_N(0)(3)); adcdata2367_0B2 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD16B_P, IB => AD16B_N, O => adcdata2367_P(0)(4), OB => adcdata2367_N(0)(4)); adcdata2367_0A2 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD16A_P, IB => AD16A_N, O => adcdata2367_P(0)(5), OB => adcdata2367_N(0)(5)); adcdata2367_0B3 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD17B_P, IB => AD17B_N, O => adcdata2367_P(0)(6), OB => adcdata2367_N(0)(6)); adcdata2367_0A3 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD17A_P, IB => AD17A_N, O => adcdata2367_P(0)(7), OB => adcdata2367_N(0)(7)); adcdata1458_1B0 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD21B_P, IB => AD21B_N, O => adcdata1458_P(1)(0), OB => adcdata1458_N(1)(0)); adcdata1458_1A0 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD21A_P, IB => AD21A_N, O => adcdata1458_P(1)(1), OB => adcdata1458_N(1)(1)); adcdata1458_1B1 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD24B_P, IB => AD24B_N, O => adcdata1458_P(1)(2), OB => adcdata1458_N(1)(2)); adcdata1458_1A1 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD24A_P, IB => AD24A_N, O => adcdata1458_P(1)(3), OB => adcdata1458_N(1)(3)); adcdata1458_1B2 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD25B_P, IB => AD25B_N, O => adcdata1458_P(1)(4), OB => adcdata1458_N(1)(4)); adcdata1458_1A2 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD25A_P, IB => AD25A_N, O => adcdata1458_P(1)(5), OB => adcdata1458_N(1)(5)); adcdata1458_1B3 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD28B_P, IB => AD28B_N, O => adcdata1458_P(1)(6), OB => adcdata1458_N(1)(6)); adcdata1458_1A3 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD28A_P, IB => AD28A_N, O => adcdata1458_P(1)(7), OB => adcdata1458_N(1)(7)); adcdata2367_1B0 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD22B_P, IB => AD22B_N, O => adcdata2367_P(1)(0), OB => adcdata2367_N(1)(0)); adcdata2367_1A0 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD22A_P, IB => AD22A_N, O => adcdata2367_P(1)(1), OB => adcdata2367_N(1)(1)); adcdata2367_1B1 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD23B_P, IB => AD23B_N, O => adcdata2367_P(1)(2), OB => adcdata2367_N(1)(2)); adcdata2367_1A1 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD23A_P, IB => AD23A_N, O => adcdata2367_P(1)(3), OB => adcdata2367_N(1)(3)); adcdata2367_1B2 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD26B_P, IB => AD26B_N, O => adcdata2367_P(1)(4), OB => adcdata2367_N(1)(4)); adcdata2367_1A2 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD26A_P, IB => AD26A_N, O => adcdata2367_P(1)(5), OB => adcdata2367_N(1)(5)); adcdata2367_1B3 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD27B_P, IB => AD27B_N, O => adcdata2367_P(1)(6), OB => adcdata2367_N(1)(6)); adcdata2367_1A3 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD27A_P, IB => AD27A_N, O => adcdata2367_P(1)(7), OB => adcdata2367_N(1)(7)); adcdata1458_2B0 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD31B_P, IB => AD31B_N, O => adcdata1458_P(2)(0), OB => adcdata1458_N(2)(0)); adcdata1458_2A0 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD31A_P, IB => AD31A_N, O => adcdata1458_P(2)(1), OB => adcdata1458_N(2)(1)); adcdata1458_2B1 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD34B_P, IB => AD34B_N, O => adcdata1458_P(2)(2), OB => adcdata1458_N(2)(2)); adcdata1458_2A1 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD34A_P, IB => AD34A_N, O => adcdata1458_P(2)(3), OB => adcdata1458_N(2)(3)); adcdata1458_2B2 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD35B_P, IB => AD35B_N, O => adcdata1458_P(2)(4), OB => adcdata1458_N(2)(4)); adcdata1458_2A2 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD35A_P, IB => AD35A_N, O => adcdata1458_P(2)(5), OB => adcdata1458_N(2)(5)); adcdata1458_2B3 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD38B_P, IB => AD38B_N, O => adcdata1458_P(2)(6), OB => adcdata1458_N(2)(6)); adcdata1458_2A3 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD38A_P, IB => AD38A_N, O => adcdata1458_P(2)(7), OB => adcdata1458_N(2)(7)); adcdata2367_2B0 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD32B_P, IB => AD32B_N, O => adcdata2367_P(2)(0), OB => adcdata2367_N(2)(0)); adcdata2367_2A0 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD32A_P, IB => AD32A_N, O => adcdata2367_P(2)(1), OB => adcdata2367_N(2)(1)); adcdata2367_2B1 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD33B_P, IB => AD33B_N, O => adcdata2367_P(2)(2), OB => adcdata2367_N(2)(2)); adcdata2367_2A1 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD33A_P, IB => AD33A_N, O => adcdata2367_P(2)(3), OB => adcdata2367_N(2)(3)); adcdata2367_2B2 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD36B_P, IB => AD36B_N, O => adcdata2367_P(2)(4), OB => adcdata2367_N(2)(4)); adcdata2367_2A2 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD36A_P, IB => AD36A_N, O => adcdata2367_P(2)(5), OB => adcdata2367_N(2)(5)); adcdata2367_2B3 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD37B_P, IB => AD37B_N, O => adcdata2367_P(2)(6), OB => adcdata2367_N(2)(6)); adcdata2367_2A3 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD37A_P, IB => AD37A_N, O => adcdata2367_P(2)(7), OB => adcdata2367_N(2)(7)); adcdata1458_3B0 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD41B_P, IB => AD41B_N, O => adcdata1458_P(3)(0), OB => adcdata1458_N(3)(0)); adcdata1458_3A0 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD41A_P, IB => AD41A_N, O => adcdata1458_P(3)(1), OB => adcdata1458_N(3)(1)); adcdata1458_3B1 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD44B_P, IB => AD44B_N, O => adcdata1458_P(3)(2), OB => adcdata1458_N(3)(2)); adcdata1458_3A1 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD44A_P, IB => AD44A_N, O => adcdata1458_P(3)(3), OB => adcdata1458_N(3)(3)); adcdata1458_3B2 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD45B_P, IB => AD45B_N, O => adcdata1458_P(3)(4), OB => adcdata1458_N(3)(4)); adcdata1458_3A2 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD45A_P, IB => AD45A_N, O => adcdata1458_P(3)(5), OB => adcdata1458_N(3)(5)); adcdata1458_3B3 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD48B_P, IB => AD48B_N, O => adcdata1458_P(3)(6), OB => adcdata1458_N(3)(6)); adcdata1458_3A3 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD48A_P, IB => AD48A_N, O => adcdata1458_P(3)(7), OB => adcdata1458_N(3)(7)); adcdata2367_3B0 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD42B_P, IB => AD42B_N, O => adcdata2367_P(3)(0), OB => adcdata2367_N(3)(0)); adcdata2367_3A0 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD42A_P, IB => AD42A_N, O => adcdata2367_P(3)(1), OB => adcdata2367_N(3)(1)); adcdata2367_3B1 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD43B_P, IB => AD43B_N, O => adcdata2367_P(3)(2), OB => adcdata2367_N(3)(2)); adcdata2367_3A1 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD43A_P, IB => AD43A_N, O => adcdata2367_P(3)(3), OB => adcdata2367_N(3)(3)); adcdata2367_3B2 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD46B_P, IB => AD46B_N, O => adcdata2367_P(3)(4), OB => adcdata2367_N(3)(4)); adcdata2367_3A2 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD46A_P, IB => AD46A_N, O => adcdata2367_P(3)(5), OB => adcdata2367_N(3)(5)); adcdata2367_3B3 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD47B_P, IB => AD47B_N, O => adcdata2367_P(3)(6), OB => adcdata2367_N(3)(6)); adcdata2367_3A3 : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => AD47A_P, IB => AD47A_N, O => adcdata2367_P(3)(7), OB => adcdata2367_N(3)(7)); + + DCOA1_buf : IBUFGDS - generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25") + generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm) port map (I => DCOA1_P, IB => DCOA1_N, O => DCOA1_P_S); DCOA1_N_S <= '0'; DCOA2_buf : IBUFGDS - generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25") + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => DCOA2_P, IB => DCOA2_N, O => DCOA2_P_S); DCOA2_N_S <= '0'; DCOA3_buf : IBUFGDS - generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25") + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => DCOA3_P, IB => DCOA3_N, O => DCOA3_P_S); DCOA3_N_S <= '0'; DCOA4_buf : IBUFGDS - generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25") + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => DCOA4_P, IB => DCOA4_N, O => DCOA4_P_S); DCOA4_N_S <= '0'; DCOB1_buf : IBUFGDS - generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25") + generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm) port map (I => DCOB1_P, IB => DCOB1_N, O => DCOB1_P_S); DCOB1_N_S <= '0'; DCOB2_buf : IBUFGDS - generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25") + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => DCOB2_P, IB => DCOB2_N, O => DCOB2_P_S); DCOB2_N_S <= '0'; DCOB3_buf : IBUFGDS - generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25") + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => DCOB3_P, IB => DCOB3_N, O => DCOB3_P_S); DCOB3_N_S <= '0'; DCOB4_buf : IBUFGDS - generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25") + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => DCOB4_P, IB => DCOB4_N, O => DCOB4_P_S); DCOB4_N_S <= '0'; FRA1_buf : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm) port map (I => FRA1_P, IB => FRA1_N, O => FRA1_P_S, OB => FRA1_N_S); FRA2_buf : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => FRA2_P, IB => FRA2_N, O => FRA2_P_S, OB => FRA2_N_S); FRA3_buf : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => FRA3_P, IB => FRA3_N, O => FRA3_P_S, OB => FRA3_N_S); FRA4_buf : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => FRA4_P, IB => FRA4_N, O => FRA4_P_S, OB => FRA4_N_S); - FRB1_buf : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS", DIFF_TERM => C_OnChipLvdsTerm) port map (I => FRB1_P, IB => FRB1_N, O => FRB1_P_S, OB => FRB1_N_S); FRB2_buf : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => FRB2_P, IB => FRB2_N, O => FRB2_P_S, OB => FRB2_N_S); FRB3_buf : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => FRB3_P, IB => FRB3_N, O => FRB3_P_S, OB => FRB3_N_S); FRB4_buf : IBUFDS_DIFF_OUT - generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm)) + generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => C_OnChipLvdsTerm) port map (I => FRB4_P, IB => FRB4_N, O => FRB4_P_S, OB => FRB4_N_S); AdcToplevel1458_1: AdcToplevel generic map( - C_AdcChnls => 4, - C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface - C_BufioLoc => "BUFIODQS_X1Y14", - C_BufrLoc => "BUFR_X1Y7", - C_AdcBits => 16, --- C_StatTaps => 16, + C_BufioLoc => "BUFIO_X1Y5", + C_BufrLoc => "BUFR_X1Y4", + C_IserdesLoc => "ILOGIC_X1Y74", + C_StatTaps => C_StatTaps, -- 8 C_AdcUseIdlyCtrl => 1, -- 0 = No, 1 = Yes - C_AdcIdlyCtrlLoc => "IDELAYCTRL_X1Y3" --IDELAYCTRL_X2Y3 + C_AdcIdlyCtrlLoc => "IDELAYCTRL_X1Y1" ) port map( DCLK_p => DCOA1_P_S, @@ -656,32 +665,25 @@ FRB4_buf : IBUFDS_DIFF_OUT DATA_n => adcdata1458_n(0), -- application connections SysRefClk => clock200MHz, + clockAsync => clockAsync, AdcIntrfcRst => reset, AdcIntrfcEna => ADCs_enable, - AdcReSync => '0', - AdcFrmSyncWrn => AdcFrmSyncWrnA_S(0), - AdcBitClkAlgnWrn => AdcBitClkAlgnWrnA_S(0), - AdcBitClkInvrtd => AdcBitClkInvrtdA_S(0), AdcBitClkDone => AdcBitClkDoneA_S(0), AdcIdlyCtrlRdy => AdcIdlyCtrlRdyA_S(0), AdcClkDiv => adcclockA_S(0), - adcdataclk => ADC_clk_S, - adcdataclknot => ADC_clknot_S, + AdcDataClk => ADC_clk_S, AdcDataOut => AdcDataOutA_S(0), - ADCs_ready => ADCs_ready_S(0), - testOK => open, - testword0 => open); + ADCs_ready => ADCs_ready_S(0) + ); AdcToplevel2356_1: AdcToplevel generic map( - C_AdcChnls => 4, - C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface - C_BufioLoc => "BUFIODQS_X1Y13", - C_BufrLoc => "BUFR_X1Y6", - C_AdcBits => 16, --- C_StatTaps => 16, + C_BufioLoc => "BUFIO_X1Y6", + C_BufrLoc => "BUFR_X1Y7", + C_IserdesLoc => "ILOGIC_X1Y76", + C_StatTaps => C_StatTaps, -- 8 C_AdcUseIdlyCtrl => 0, -- 0 = No, 1 = Yes - C_AdcIdlyCtrlLoc => "IDELAYCTRL_X1Y3" + C_AdcIdlyCtrlLoc => "IDELAYCTRL_X1Y1" ) port map( DCLK_p => DCOB1_P_S, @@ -692,33 +694,26 @@ FRB4_buf : IBUFDS_DIFF_OUT DATA_n => adcdata2367_N(0), -- application connections SysRefClk => clock200MHz, + clockAsync => clockAsync, AdcIntrfcRst => reset, AdcIntrfcEna => ADCs_enable, - AdcReSync => '0', - AdcFrmSyncWrn => AdcFrmSyncWrnB_S(0), - AdcBitClkAlgnWrn => AdcBitClkAlgnWrnB_S(0), - AdcBitClkInvrtd => AdcBitClkInvrtdB_S(0), AdcBitClkDone => AdcBitClkDoneB_S(0), AdcIdlyCtrlRdy => AdcIdlyCtrlRdyB_S(0), AdcClkDiv => adcclockB_S(0), - adcdataclk => ADC_clk_S, - adcdataclknot => ADC_clknot_S, + AdcDataClk => ADC_clk_S, AdcDataOut => AdcDataOutB_S(0), - ADCs_ready => ADCs_ready_S(1), - testOK => open, - testword0 => open); + ADCs_ready => ADCs_ready_S(1) + ); AdcToplevel1458_2: AdcToplevel generic map( - C_AdcChnls => 4, - C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface - C_BufioLoc => "BUFIODQS_X0Y13", - C_BufrLoc => "BUFR_X0Y6", - C_AdcBits => 16, --- C_StatTaps => 16, + C_BufioLoc => "BUFIO_X0Y6", + C_BufrLoc => "BUFR_X0Y7", + C_IserdesLoc => "ILOGIC_X0Y76", + C_StatTaps => C_StatTaps, -- 8 C_AdcUseIdlyCtrl => 1, -- 0 = No, 1 = Yes - C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y3" --IDELAYCTRL_X2Y3 + C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y1" ) port map( DCLK_p => DCOA2_P_S, @@ -729,32 +724,25 @@ FRB4_buf : IBUFDS_DIFF_OUT DATA_n => adcdata1458_n(1), -- application connections SysRefClk => clock200MHz, + clockAsync => clockAsync, AdcIntrfcRst => reset, AdcIntrfcEna => ADCs_enable, - AdcReSync => '0', - AdcFrmSyncWrn => AdcFrmSyncWrnA_S(1), - AdcBitClkAlgnWrn => AdcBitClkAlgnWrnA_S(1), - AdcBitClkInvrtd => AdcBitClkInvrtdA_S(1), AdcBitClkDone => AdcBitClkDoneA_S(1), AdcIdlyCtrlRdy => AdcIdlyCtrlRdyA_S(1), AdcClkDiv => adcclockA_S(1), - adcdataclk => ADC_clk_S, - adcdataclknot => ADC_clknot_S, + AdcDataClk => ADC_clk_S, AdcDataOut => AdcDataOutA_S(1), - ADCs_ready => ADCs_ready_S(2), - testOK => open, - testword0 => open); + ADCs_ready => ADCs_ready_S(2) + ); AdcToplevel2356_2: AdcToplevel generic map( - C_AdcChnls => 4, - C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface - C_BufioLoc => "BUFIODQS_X0Y14", - C_BufrLoc => "BUFR_X0Y7", - C_AdcBits => 16, --- C_StatTaps => 16, + C_BufioLoc => "BUFIO_X0Y5", + C_BufrLoc => "BUFR_X0Y4", + C_IserdesLoc => "ILOGIC_X0Y74", + C_StatTaps => C_StatTaps, -- 8 C_AdcUseIdlyCtrl => 0, -- 0 = No, 1 = Yes - C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y3" + C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y1" ) port map( DCLK_p => DCOB2_P_S, @@ -765,33 +753,26 @@ FRB4_buf : IBUFDS_DIFF_OUT DATA_n => adcdata2367_N(1), -- application connections SysRefClk => clock200MHz, + clockAsync => clockAsync, AdcIntrfcRst => reset, AdcIntrfcEna => ADCs_enable, - AdcReSync => '0', - AdcFrmSyncWrn => AdcFrmSyncWrnB_S(1), - AdcBitClkAlgnWrn => AdcBitClkAlgnWrnB_S(1), - AdcBitClkInvrtd => AdcBitClkInvrtdB_S(1), AdcBitClkDone => AdcBitClkDoneB_S(1), AdcIdlyCtrlRdy => AdcIdlyCtrlRdyB_S(1), AdcClkDiv => adcclockB_S(1), - adcdataclk => ADC_clk_S, - adcdataclknot => ADC_clknot_S, + AdcDataClk => ADC_clk_S, AdcDataOut => AdcDataOutB_S(1), - ADCs_ready => ADCs_ready_S(3), - testOK => open, - testword0 => open); + ADCs_ready => ADCs_ready_S(3) + ); AdcToplevel1458_3: AdcToplevel generic map( - C_AdcChnls => 4, - C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface - C_BufioLoc => "BUFIODQS_X0Y10", - C_BufrLoc => "BUFR_X0Y5", - C_AdcBits => 16, --- C_StatTaps => 16, + C_BufioLoc => "BUFIO_X0Y10", + C_BufrLoc => "BUFR_X0Y11", + C_IserdesLoc => "ILOGIC_X0Y126", + C_StatTaps => C_StatTaps, -- 8 C_AdcUseIdlyCtrl => 1, -- 0 = No, 1 = Yes - C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y2" --IDELAYCTRL_X2Y3 + C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y2" ) port map( DCLK_p => DCOA3_P_S, @@ -802,30 +783,23 @@ FRB4_buf : IBUFDS_DIFF_OUT DATA_n => adcdata1458_n(2), -- application connections SysRefClk => clock200MHz, + clockAsync => clockAsync, AdcIntrfcRst => reset, AdcIntrfcEna => ADCs_enable, - AdcReSync => '0', - AdcFrmSyncWrn => AdcFrmSyncWrnA_S(2), - AdcBitClkAlgnWrn => AdcBitClkAlgnWrnA_S(2), - AdcBitClkInvrtd => AdcBitClkInvrtdA_S(2), AdcBitClkDone => AdcBitClkDoneA_S(2), AdcIdlyCtrlRdy => AdcIdlyCtrlRdyA_S(2), AdcClkDiv => adcclockA_S(2), - adcdataclk => ADC_clk_S, - adcdataclknot => ADC_clknot_S, + AdcDataClk => ADC_clk_S, AdcDataOut => AdcDataOutA_S(2), - ADCs_ready => ADCs_ready_S(4), - testOK => open, - testword0 => open); + ADCs_ready => ADCs_ready_S(4) + ); AdcToplevel2356_3: AdcToplevel generic map( - C_AdcChnls => 4, - C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface - C_BufioLoc => "BUFIODQS_X0Y9", - C_BufrLoc => "BUFR_X0Y4", - C_AdcBits => 16, --- C_StatTaps => 16, + C_BufioLoc => "BUFIO_X0Y9", + C_BufrLoc => "BUFR_X0Y8", + C_IserdesLoc => "ILOGIC_X0Y124", + C_StatTaps => C_StatTaps, -- 8 C_AdcUseIdlyCtrl => 0, -- 0 = No, 1 = Yes C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y2" ) @@ -838,33 +812,26 @@ FRB4_buf : IBUFDS_DIFF_OUT DATA_n => adcdata2367_N(2), -- application connections SysRefClk => clock200MHz, + clockAsync => clockAsync, AdcIntrfcRst => reset, AdcIntrfcEna => ADCs_enable, - AdcReSync => '0', - AdcFrmSyncWrn => AdcFrmSyncWrnB_S(2), - AdcBitClkAlgnWrn => AdcBitClkAlgnWrnB_S(2), - AdcBitClkInvrtd => AdcBitClkInvrtdB_S(2), AdcBitClkDone => AdcBitClkDoneB_S(2), AdcIdlyCtrlRdy => AdcIdlyCtrlRdyB_S(2), AdcClkDiv => adcclockB_S(2), - adcdataclk => ADC_clk_S, - adcdataclknot => ADC_clknot_S, + AdcDataClk => ADC_clk_S, AdcDataOut => AdcDataOutB_S(2), - ADCs_ready => ADCs_ready_S(5), - testOK => open, - testword0 => open); + ADCs_ready => ADCs_ready_S(5) + ); AdcToplevel1458_4: AdcToplevel generic map( - C_AdcChnls => 4, - C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface - C_BufioLoc => "BUFIODQS_X2Y9", - C_BufrLoc => "BUFR_X2Y4", - C_AdcBits => 16, --- C_StatTaps => 16, + C_BufioLoc => "BUFIO_X0Y14", + C_BufrLoc => "BUFR_X0Y15", + C_IserdesLoc => "ILOGIC_X0Y176", + C_StatTaps => C_StatTaps, -- 8 C_AdcUseIdlyCtrl => 1, -- 0 = No, 1 = Yes - C_AdcIdlyCtrlLoc => "IDELAYCTRL_X2Y2" --IDELAYCTRL_X2Y3 + C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y3" ) port map( DCLK_p => DCOA4_P_S, @@ -875,32 +842,25 @@ FRB4_buf : IBUFDS_DIFF_OUT DATA_n => adcdata1458_n(3), -- application connections SysRefClk => clock200MHz, + clockAsync => clockAsync, AdcIntrfcRst => reset, AdcIntrfcEna => ADCs_enable, - AdcReSync => '0', - AdcFrmSyncWrn => AdcFrmSyncWrnA_S(3), - AdcBitClkAlgnWrn => AdcBitClkAlgnWrnA_S(3), - AdcBitClkInvrtd => AdcBitClkInvrtdA_S(3), AdcBitClkDone => AdcBitClkDoneA_S(3), AdcIdlyCtrlRdy => AdcIdlyCtrlRdyA_S(3), AdcClkDiv => adcclockA_S(3), - adcdataclk => ADC_clk_S, - adcdataclknot => ADC_clknot_S, + AdcDataClk => ADC_clk_S, AdcDataOut => AdcDataOutA_S(3), - ADCs_ready => ADCs_ready_S(6), - testOK => open, - testword0 => open); + ADCs_ready => ADCs_ready_S(6) + ); AdcToplevel2356_4: AdcToplevel generic map( - C_AdcChnls => 4, - C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface - C_BufioLoc => "BUFIODQS_X2Y10", - C_BufrLoc => "BUFR_X2Y5", - C_AdcBits => 16, --- C_StatTaps => 16, + C_BufioLoc => "BUFIO_X0Y13", + C_BufrLoc => "BUFR_X0Y12", + C_IserdesLoc => "ILOGIC_X0Y174", + C_StatTaps => C_StatTaps, -- 8 C_AdcUseIdlyCtrl => 0, -- 0 = No, 1 = Yes - C_AdcIdlyCtrlLoc => "IDELAYCTRL_X2Y2" + C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y3" ) port map( DCLK_p => DCOB4_P_S, @@ -911,51 +871,55 @@ FRB4_buf : IBUFDS_DIFF_OUT DATA_n => adcdata2367_N(3), -- application connections SysRefClk => clock200MHz, + clockAsync => clockAsync, AdcIntrfcRst => reset, AdcIntrfcEna => ADCs_enable, - AdcReSync => '0', - AdcFrmSyncWrn => AdcFrmSyncWrnB_S(3), - AdcBitClkAlgnWrn => AdcBitClkAlgnWrnB_S(3), - AdcBitClkInvrtd => AdcBitClkInvrtdB_S(3), AdcBitClkDone => AdcBitClkDoneB_S(3), AdcIdlyCtrlRdy => AdcIdlyCtrlRdyB_S(3), AdcClkDiv => adcclockB_S(3), - adcdataclk => ADC_clk_S, - adcdataclknot => ADC_clknot_S, + AdcDataClk => ADC_clk_S, AdcDataOut => AdcDataOutB_S(3), - ADCs_ready => ADCs_ready_S(7), - testOK => open, - testword0 => open); - ---ADCclkbuf : BUFG port map ( --- O => ADC_clk_S, --- I => adcclockB_S(0)); - -FEE_clockbuf80MHz1: FEE_clockbuf80MHz port map( - CLK_IN1 => adcclockA_S(0), - CLK_OUT1 => ADC_clk_S, - CLK_OUT2 => ADC_clknot_S); - -gen_adcpar1: for chipnr in 0 to 3 generate + ADCs_ready => ADCs_ready_S(7) + ); + + -adcdata0_S((3-chipnr)*8+1) <= AdcDataOutA_S(chipnr)(0*32+7 downto 0*32+0) & AdcDataOutA_S(chipnr)(0*32+15 downto 0*32+10); -adcdata0_S((3-chipnr)*8+2) <= not (AdcDataOutA_S(chipnr)(1*32+7 downto 1*32+0) & AdcDataOutA_S(chipnr)(1*32+15 downto 1*32+10)); -adcdata0_S((3-chipnr)*8+5) <= AdcDataOutA_S(chipnr)(2*32+7 downto 2*32+0) & AdcDataOutA_S(chipnr)(2*32+15 downto 2*32+10); -adcdata0_S((3-chipnr)*8+6) <= not (AdcDataOutA_S(chipnr)(3*32+7 downto 3*32+0) & AdcDataOutA_S(chipnr)(3*32+15 downto 3*32+10)); +ADCclkbuf : BUFG port map ( + O => ADC_clk_S, + I => adcclockA_S(0)); -adcdata0_S((3-chipnr)*8+0) <= not (AdcDataOutB_S(chipnr)(0*32+7 downto 0*32+0) & AdcDataOutB_S(chipnr)(0*32+15 downto 0*32+10)); -adcdata0_S((3-chipnr)*8+3) <= AdcDataOutB_S(chipnr)(1*32+7 downto 1*32+0) & AdcDataOutB_S(chipnr)(1*32+15 downto 1*32+10); -adcdata0_S((3-chipnr)*8+4) <= not (AdcDataOutB_S(chipnr)(2*32+7 downto 2*32+0) & AdcDataOutB_S(chipnr)(2*32+15 downto 2*32+10)); -adcdata0_S((3-chipnr)*8+7) <= AdcDataOutB_S(chipnr)(3*32+7 downto 3*32+0) & AdcDataOutB_S(chipnr)(3*32+15 downto 3*32+10); +gen_adcpar1: for chipnr in 0 to 3 generate + +--process(ADC_clk_S) -- synchronise to 1 clock +--begin +-- if (rising_edge(ADC_clk_S)) then +adcdata0_S((chipnr)*8+1) <= (sync_AdcDataOutA_S(chipnr)(0*32+7 downto 0*32+0) & sync_AdcDataOutA_S(chipnr)(0*32+15 downto 0*32+10)); +adcdata0_S((chipnr)*8+2) <= (sync_AdcDataOutA_S(chipnr)(1*32+7 downto 1*32+0) & sync_AdcDataOutA_S(chipnr)(1*32+15 downto 1*32+10)); +adcdata0_S((chipnr)*8+5) <= (sync_AdcDataOutA_S(chipnr)(2*32+7 downto 2*32+0) & sync_AdcDataOutA_S(chipnr)(2*32+15 downto 2*32+10)); +adcdata0_S((chipnr)*8+6) <= (sync_AdcDataOutA_S(chipnr)(3*32+7 downto 3*32+0) & sync_AdcDataOutA_S(chipnr)(3*32+15 downto 3*32+10)); + +adcdata0_S((chipnr)*8+0) <= (sync_AdcDataOutB_S(chipnr)(0*32+7 downto 0*32+0) & sync_AdcDataOutB_S(chipnr)(0*32+15 downto 0*32+10)); +adcdata0_S((chipnr)*8+3) <= (sync_AdcDataOutB_S(chipnr)(1*32+7 downto 1*32+0) & sync_AdcDataOutB_S(chipnr)(1*32+15 downto 1*32+10)); +adcdata0_S((chipnr)*8+4) <= (sync_AdcDataOutB_S(chipnr)(2*32+7 downto 2*32+0) & sync_AdcDataOutB_S(chipnr)(2*32+15 downto 2*32+10)); +adcdata0_S((chipnr)*8+7) <= (sync_AdcDataOutB_S(chipnr)(3*32+7 downto 3*32+0) & sync_AdcDataOutB_S(chipnr)(3*32+15 downto 3*32+10)); +-- end if; +--end process; end generate; -process(ADC_clk_S) -- synchronise to 1 clock -begin - if (rising_edge(ADC_clk_S)) then - adcdata1_S <= adcdata0_S; - adcdata <= adcdata1_S; - end if; -end process; +adcdata <= adcdata0_S; + +sync_AdcDataOutA_S <= AdcDataOutA_S; +sync_AdcDataOutB_S <= AdcDataOutB_S; + +--0 <- B0 =1 +--1 <- A0 =0 +--2 <- A1 =2 +--3 <- B1 =3 +--4 <- B2 =5 +--5 <- A2 =4 +--6 <- A3 =6 +--7 <- B3 =7 + end Behavioral; diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/FEE_Kintex_ADCboard.ucf b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/FEE_Kintex_ADCboard.ucf new file mode 100644 index 0000000..b51c4dd --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/FEE_Kintex_ADCboard.ucf @@ -0,0 +1,1153 @@ +NET "AD11A_N" DIFF_TERM = "TRUE"; +NET "AD11A_N" IOSTANDARD = LVDS; +NET "AD11A_N" LOC = AB7; +NET "AD11A_P" DIFF_TERM = "TRUE"; +NET "AD11A_P" IOSTANDARD = LVDS; +NET "AD11A_P" LOC = AB8; +NET "AD21A_N" DIFF_TERM = "TRUE"; +NET "AD21A_N" IOSTANDARD = LVDS_25; +NET "AD21A_N" LOC = AB22; +NET "AD21A_P" DIFF_TERM = "TRUE"; +NET "AD21A_P" IOSTANDARD = LVDS_25; +NET "AD21A_P" LOC = AA21; +NET "AD31A_N" DIFF_TERM = "TRUE"; +NET "AD31A_N" IOSTANDARD = LVDS_25; +NET "AD31A_N" LOC = N17; +NET "AD31A_P" DIFF_TERM = "TRUE"; +NET "AD31A_P" IOSTANDARD = LVDS_25; +NET "AD31A_P" LOC = P16; +NET "AD41A_N" DIFF_TERM = "TRUE"; +NET "AD41A_N" IOSTANDARD = LVDS_25; +NET "AD41A_N" LOC = A19; +NET "AD41A_P" DIFF_TERM = "TRUE"; +NET "AD41A_P" IOSTANDARD = LVDS_25; +NET "AD41A_P" LOC = B18; +NET "AD11B_N" DIFF_TERM = "TRUE"; +NET "AD11B_N" IOSTANDARD = LVDS; +NET "AD11B_N" LOC = AB6; +NET "AD11B_P" DIFF_TERM = "TRUE"; +NET "AD11B_P" IOSTANDARD = LVDS; +NET "AD11B_P" LOC = AA6; +NET "AD21B_N" DIFF_TERM = "TRUE"; +NET "AD21B_N" IOSTANDARD = LVDS_25; +NET "AD21B_N" LOC = Y17; +NET "AD21B_P" DIFF_TERM = "TRUE"; +NET "AD21B_P" IOSTANDARD = LVDS_25; +NET "AD21B_P" LOC = W17; +NET "AD31B_N" DIFF_TERM = "TRUE"; +NET "AD31B_N" IOSTANDARD = LVDS_25; +NET "AD31B_N" LOC = P22; +NET "AD31B_P" DIFF_TERM = "TRUE"; +NET "AD31B_P" IOSTANDARD = LVDS_25; +NET "AD31B_P" LOC = P21; +NET "AD41B_N" DIFF_TERM = "TRUE"; +NET "AD41B_N" IOSTANDARD = LVDS_25; +NET "AD41B_N" LOC = C20; +NET "AD41B_P" DIFF_TERM = "TRUE"; +NET "AD41B_P" IOSTANDARD = LVDS_25; +NET "AD41B_P" LOC = C19; +NET "AD12A_N" DIFF_TERM = "TRUE"; +NET "AD12A_N" IOSTANDARD = LVDS; +NET "AD12A_N" LOC = U6; +NET "AD12A_P" DIFF_TERM = "TRUE"; +NET "AD12A_P" IOSTANDARD = LVDS; +NET "AD12A_P" LOC = U7; +NET "AD22A_N" DIFF_TERM = "TRUE"; +NET "AD22A_N" IOSTANDARD = LVDS_25; +NET "AD22A_N" LOC = Y16; +NET "AD22A_P" DIFF_TERM = "TRUE"; +NET "AD22A_P" IOSTANDARD = LVDS_25; +NET "AD22A_P" LOC = W16; +NET "AD32A_N" DIFF_TERM = "TRUE"; +NET "AD32A_N" IOSTANDARD = LVDS_25; +NET "AD32A_N" LOC = R19; +NET "AD32A_P" DIFF_TERM = "TRUE"; +NET "AD32A_P" IOSTANDARD = LVDS_25; +NET "AD32A_P" LOC = R18; +NET "AD42A_N" DIFF_TERM = "TRUE"; +NET "AD42A_N" IOSTANDARD = LVDS_25; +NET "AD42A_N" LOC = B22; +NET "AD42A_P" DIFF_TERM = "TRUE"; +NET "AD42A_P" IOSTANDARD = LVDS_25; +NET "AD42A_P" LOC = C22; +NET "AD12B_N" DIFF_TERM = "TRUE"; +NET "AD12B_N" IOSTANDARD = LVDS; +NET "AD12B_N" LOC = AB5; +NET "AD12B_P" DIFF_TERM = "TRUE"; +NET "AD12B_P" IOSTANDARD = LVDS; +NET "AD12B_P" LOC = AA5; +NET "AD22B_N" DIFF_TERM = "TRUE"; +NET "AD22B_N" IOSTANDARD = LVDS_25; +NET "AD22B_N" LOC = AB17; +NET "AD22B_P" DIFF_TERM = "TRUE"; +NET "AD22B_P" IOSTANDARD = LVDS_25; +NET "AD22B_P" LOC = AA16; +NET "AD32B_N" DIFF_TERM = "TRUE"; +NET "AD32B_N" IOSTANDARD = LVDS_25; +NET "AD32B_N" LOC = R22; +NET "AD32B_P" DIFF_TERM = "TRUE"; +NET "AD32B_P" IOSTANDARD = LVDS_25; +NET "AD32B_P" LOC = R21; +NET "AD42B_N" DIFF_TERM = "TRUE"; +NET "AD42B_N" IOSTANDARD = LVDS_25; +NET "AD42B_N" LOC = A21; +NET "AD42B_P" DIFF_TERM = "TRUE"; +NET "AD42B_P" IOSTANDARD = LVDS_25; +NET "AD42B_P" LOC = A20; +NET "AD13A_N" DIFF_TERM = "TRUE"; +NET "AD13A_N" IOSTANDARD = LVDS; +NET "AD13A_N" LOC = W7; +NET "AD13A_P" DIFF_TERM = "TRUE"; +NET "AD13A_P" IOSTANDARD = LVDS; +NET "AD13A_P" LOC = V7; +NET "AD23A_N" DIFF_TERM = "TRUE"; +NET "AD23A_N" IOSTANDARD = LVDS_25; +NET "AD23A_N" LOC = AB16; +NET "AD23A_P" DIFF_TERM = "TRUE"; +NET "AD23A_P" IOSTANDARD = LVDS_25; +NET "AD23A_P" LOC = AB15; +NET "AD33A_N" DIFF_TERM = "TRUE"; +NET "AD33A_N" IOSTANDARD = LVDS_25; +NET "AD33A_N" LOC = P17; +NET "AD33A_P" DIFF_TERM = "TRUE"; +NET "AD33A_P" IOSTANDARD = LVDS_25; +NET "AD33A_P" LOC = R17; +NET "AD43A_N" DIFF_TERM = "TRUE"; +NET "AD43A_N" IOSTANDARD = LVDS_25; +NET "AD43A_N" LOC = B21; +NET "AD43A_P" DIFF_TERM = "TRUE"; +NET "AD43A_P" IOSTANDARD = LVDS_25; +NET "AD43A_P" LOC = B20; +NET "AD13B_N" DIFF_TERM = "TRUE"; +NET "AD13B_N" IOSTANDARD = LVDS; +NET "AD13B_N" LOC = AA8; +NET "AD13B_P" DIFF_TERM = "TRUE"; +NET "AD13B_P" IOSTANDARD = LVDS; +NET "AD13B_P" LOC = AA9; +NET "AD23B_N" DIFF_TERM = "TRUE"; +NET "AD23B_N" IOSTANDARD = LVDS_25; +NET "AD23B_N" LOC = V18; +NET "AD23B_P" DIFF_TERM = "TRUE"; +NET "AD23B_P" IOSTANDARD = LVDS_25; +NET "AD23B_P" LOC = U17; +NET "AD33B_N" DIFF_TERM = "TRUE"; +NET "AD33B_N" IOSTANDARD = LVDS_25; +NET "AD33B_N" LOC = M22; +NET "AD33B_P" DIFF_TERM = "TRUE"; +NET "AD33B_P" IOSTANDARD = LVDS_25; +NET "AD33B_P" LOC = N22; +NET "AD43B_N" DIFF_TERM = "TRUE"; +NET "AD43B_N" IOSTANDARD = LVDS_25; +NET "AD43B_N" LOC = A18; +NET "AD43B_P" DIFF_TERM = "TRUE"; +NET "AD43B_P" IOSTANDARD = LVDS_25; +NET "AD43B_P" LOC = B17; +NET "AD14A_N" DIFF_TERM = "TRUE"; +NET "AD14A_N" IOSTANDARD = LVDS; +NET "AD14A_N" LOC = Y6; +NET "AD14A_P" DIFF_TERM = "TRUE"; +NET "AD14A_P" IOSTANDARD = LVDS; +NET "AD14A_P" LOC = W6; +NET "AD24A_N" DIFF_TERM = "TRUE"; +NET "AD24A_N" IOSTANDARD = LVDS_25; +NET "AD24A_N" LOC = AA15; +NET "AD24A_P" DIFF_TERM = "TRUE"; +NET "AD24A_P" IOSTANDARD = LVDS_25; +NET "AD24A_P" LOC = AA14; +NET "AD34A_N" DIFF_TERM = "TRUE"; +NET "AD34A_N" IOSTANDARD = LVDS_25; +NET "AD34A_N" LOC = P20; +NET "AD34A_P" DIFF_TERM = "TRUE"; +NET "AD34A_P" IOSTANDARD = LVDS_25; +NET "AD34A_P" LOC = P19; +NET "AD44A_N" DIFF_TERM = "TRUE"; +NET "AD44A_N" IOSTANDARD = LVDS_25; +NET "AD44A_N" LOC = D22; +NET "AD44A_P" DIFF_TERM = "TRUE"; +NET "AD44A_P" IOSTANDARD = LVDS_25; +NET "AD44A_P" LOC = D21; +NET "AD14B_N" DIFF_TERM = "TRUE"; +NET "AD14B_N" IOSTANDARD = LVDS; +NET "AD14B_N" LOC = V8; +NET "AD14B_P" DIFF_TERM = "TRUE"; +NET "AD14B_P" IOSTANDARD = LVDS; +NET "AD14B_P" LOC = U8; +NET "AD24B_N" DIFF_TERM = "TRUE"; +NET "AD24B_N" IOSTANDARD = LVDS_25; +NET "AD24B_N" LOC = AB21; +NET "AD24B_P" DIFF_TERM = "TRUE"; +NET "AD24B_P" IOSTANDARD = LVDS_25; +NET "AD24B_P" LOC = AA20; +NET "AD34B_N" DIFF_TERM = "TRUE"; +NET "AD34B_N" IOSTANDARD = LVDS_25; +NET "AD34B_N" LOC = K22; +NET "AD34B_P" DIFF_TERM = "TRUE"; +NET "AD34B_P" IOSTANDARD = LVDS_25; +NET "AD34B_P" LOC = K21; +NET "AD44B_N" DIFF_TERM = "TRUE"; +NET "AD44B_N" IOSTANDARD = LVDS_25; +NET "AD44B_N" LOC = D20; +NET "AD44B_P" DIFF_TERM = "TRUE"; +NET "AD44B_P" IOSTANDARD = LVDS_25; +NET "AD44B_P" LOC = D19; +NET "AD15A_N" DIFF_TERM = "TRUE"; +NET "AD15A_N" IOSTANDARD = LVDS; +NET "AD15A_N" LOC = W10; +NET "AD15A_P" DIFF_TERM = "TRUE"; +NET "AD15A_P" IOSTANDARD = LVDS; +NET "AD15A_P" LOC = V10; +NET "AD25A_N" DIFF_TERM = "TRUE"; +NET "AD25A_N" IOSTANDARD = LVDS_25; +NET "AD25A_N" LOC = W22; +NET "AD25A_P" DIFF_TERM = "TRUE"; +NET "AD25A_P" IOSTANDARD = LVDS_25; +NET "AD25A_P" LOC = W21; +NET "AD35A_N" DIFF_TERM = "TRUE"; +NET "AD35A_N" IOSTANDARD = LVDS_25; +NET "AD35A_N" LOC = L21; +NET "AD35A_P" DIFF_TERM = "TRUE"; +NET "AD35A_P" IOSTANDARD = LVDS_25; +NET "AD35A_P" LOC = M20; +NET "AD45A_N" DIFF_TERM = "TRUE"; +NET "AD45A_N" IOSTANDARD = LVDS_25; +NET "AD45A_N" LOC = A15; +NET "AD45A_P" DIFF_TERM = "TRUE"; +NET "AD45A_P" IOSTANDARD = LVDS_25; +NET "AD45A_P" LOC = B15; +NET "AD15B_N" DIFF_TERM = "TRUE"; +NET "AD15B_N" IOSTANDARD = LVDS; +NET "AD15B_N" LOC = Y11; +NET "AD15B_P" DIFF_TERM = "TRUE"; +NET "AD15B_P" IOSTANDARD = LVDS; +NET "AD15B_P" LOC = W11; +NET "AD25B_N" DIFF_TERM = "TRUE"; +NET "AD25B_N" IOSTANDARD = LVDS_25; +NET "AD25B_N" LOC = W20; +NET "AD25B_P" DIFF_TERM = "TRUE"; +NET "AD25B_P" IOSTANDARD = LVDS_25; +NET "AD25B_P" LOC = V20; +NET "AD35B_N" DIFF_TERM = "TRUE"; +NET "AD35B_N" IOSTANDARD = LVDS_25; +NET "AD35B_N" LOC = M18; +NET "AD35B_P" DIFF_TERM = "TRUE"; +NET "AD35B_P" IOSTANDARD = LVDS_25; +NET "AD35B_P" LOC = M17; +NET "AD45B_N" DIFF_TERM = "TRUE"; +NET "AD45B_N" IOSTANDARD = LVDS_25; +NET "AD45B_N" LOC = C15; +NET "AD45B_P" DIFF_TERM = "TRUE"; +NET "AD45B_P" IOSTANDARD = LVDS_25; +NET "AD45B_P" LOC = C14; +NET "AD16A_N" DIFF_TERM = "TRUE"; +NET "AD16A_N" IOSTANDARD = LVDS; +NET "AD16A_N" LOC = AB11; +NET "AD16A_P" DIFF_TERM = "TRUE"; +NET "AD16A_P" IOSTANDARD = LVDS; +NET "AD16A_P" LOC = AA11; +NET "AD26A_N" DIFF_TERM = "TRUE"; +NET "AD26A_N" IOSTANDARD = LVDS_25; +NET "AD26A_N" LOC = Y22; +NET "AD26A_P" DIFF_TERM = "TRUE"; +NET "AD26A_P" IOSTANDARD = LVDS_25; +NET "AD26A_P" LOC = Y21; +NET "AD36A_N" DIFF_TERM = "TRUE"; +NET "AD36A_N" IOSTANDARD = LVDS_25; +NET "AD36A_N" LOC = G22; +NET "AD36A_P" DIFF_TERM = "TRUE"; +NET "AD36A_P" IOSTANDARD = LVDS_25; +NET "AD36A_P" LOC = H22; +NET "AD46A_N" DIFF_TERM = "TRUE"; +NET "AD46A_N" IOSTANDARD = LVDS_25; +NET "AD46A_N" LOC = D16; +NET "AD46A_P" DIFF_TERM = "TRUE"; +NET "AD46A_P" IOSTANDARD = LVDS_25; +NET "AD46A_P" LOC = D15; +NET "AD16B_N" DIFF_TERM = "TRUE"; +NET "AD16B_N" IOSTANDARD = LVDS; +NET "AD16B_N" LOC = AB12; +NET "AD16B_P" DIFF_TERM = "TRUE"; +NET "AD16B_P" IOSTANDARD = LVDS; +NET "AD16B_P" LOC = AB13; +NET "AD26B_N" DIFF_TERM = "TRUE"; +NET "AD26B_N" IOSTANDARD = LVDS_25; +NET "AD26B_N" LOC = V17; +NET "AD26B_P" DIFF_TERM = "TRUE"; +NET "AD26B_P" IOSTANDARD = LVDS_25; +NET "AD26B_P" LOC = U16; +NET "AD36B_N" DIFF_TERM = "TRUE"; +NET "AD36B_N" IOSTANDARD = LVDS_25; +NET "AD36B_N" LOC = H20; +NET "AD36B_P" DIFF_TERM = "TRUE"; +NET "AD36B_P" IOSTANDARD = LVDS_25; +NET "AD36B_P" LOC = J20; +NET "AD46B_N" DIFF_TERM = "TRUE"; +NET "AD46B_N" IOSTANDARD = LVDS_25; +NET "AD46B_N" LOC = F16; +NET "AD46B_P" DIFF_TERM = "TRUE"; +NET "AD46B_P" IOSTANDARD = LVDS_25; +NET "AD46B_P" LOC = F15; +NET "AD17A_N" DIFF_TERM = "TRUE"; +NET "AD17A_N" IOSTANDARD = LVDS; +NET "AD17A_N" LOC = V12; +NET "AD17A_P" DIFF_TERM = "TRUE"; +NET "AD17A_P" IOSTANDARD = LVDS; +NET "AD17A_P" LOC = V13; +NET "AD27A_N" DIFF_TERM = "TRUE"; +NET "AD27A_N" IOSTANDARD = LVDS_25; +NET "AD27A_N" LOC = U21; +NET "AD27A_P" DIFF_TERM = "TRUE"; +NET "AD27A_P" IOSTANDARD = LVDS_25; +NET "AD27A_P" LOC = T21; +NET "AD37A_N" DIFF_TERM = "TRUE"; +NET "AD37A_N" IOSTANDARD = LVDS_25; +NET "AD37A_N" LOC = F20; +NET "AD37A_P" DIFF_TERM = "TRUE"; +NET "AD37A_P" IOSTANDARD = LVDS_25; +NET "AD37A_P" LOC = G20; +NET "AD47A_N" DIFF_TERM = "TRUE"; +NET "AD47A_N" IOSTANDARD = LVDS_25; +NET "AD47A_N" LOC = B13; +NET "AD47A_P" DIFF_TERM = "TRUE"; +NET "AD47A_P" IOSTANDARD = LVDS_25; +NET "AD47A_P" LOC = C13; +NET "AD17B_N" DIFF_TERM = "TRUE"; +NET "AD17B_N" IOSTANDARD = LVDS; +NET "AD17B_N" LOC = U13; +NET "AD17B_P" DIFF_TERM = "TRUE"; +NET "AD17B_P" IOSTANDARD = LVDS; +NET "AD17B_P" LOC = T13; +NET "AD27B_N" DIFF_TERM = "TRUE"; +NET "AD27B_N" IOSTANDARD = LVDS_25; +NET "AD27B_N" LOC = U18; +NET "AD27B_P" DIFF_TERM = "TRUE"; +NET "AD27B_P" IOSTANDARD = LVDS_25; +NET "AD27B_P" LOC = T18; +NET "AD37B_N" DIFF_TERM = "TRUE"; +NET "AD37B_N" IOSTANDARD = LVDS_25; +NET "AD37B_N" LOC = F21; +NET "AD37B_P" DIFF_TERM = "TRUE"; +NET "AD37B_P" IOSTANDARD = LVDS_25; +NET "AD37B_P" LOC = G21; +NET "AD47B_N" DIFF_TERM = "TRUE"; +NET "AD47B_N" IOSTANDARD = LVDS_25; +NET "AD47B_N" LOC = B12; +NET "AD47B_P" DIFF_TERM = "TRUE"; +NET "AD47B_P" IOSTANDARD = LVDS_25; +NET "AD47B_P" LOC = C12; +NET "AD18A_N" DIFF_TERM = "TRUE"; +NET "AD18A_N" IOSTANDARD = LVDS; +NET "AD18A_N" LOC = Y12; +NET "AD18A_P" DIFF_TERM = "TRUE"; +NET "AD18A_P" IOSTANDARD = LVDS; +NET "AD18A_P" LOC = W12; +NET "AD28A_N" DIFF_TERM = "TRUE"; +NET "AD28A_N" IOSTANDARD = LVDS_25; +NET "AD28A_N" LOC = V22; +NET "AD28A_P" DIFF_TERM = "TRUE"; +NET "AD28A_P" IOSTANDARD = LVDS_25; +NET "AD28A_P" LOC = U22; +NET "AD38A_N" DIFF_TERM = "TRUE"; +NET "AD38A_N" IOSTANDARD = LVDS_25; +NET "AD38A_N" LOC = K19; +NET "AD38A_P" DIFF_TERM = "TRUE"; +NET "AD38A_P" IOSTANDARD = LVDS_25; +NET "AD38A_P" LOC = L18; +NET "AD48A_N" DIFF_TERM = "TRUE"; +NET "AD48A_N" IOSTANDARD = LVDS_25; +NET "AD48A_N" LOC = A14; +NET "AD48A_P" DIFF_TERM = "TRUE"; +NET "AD48A_P" IOSTANDARD = LVDS_25; +NET "AD48A_P" LOC = A13; +NET "AD18B_N" DIFF_TERM = "TRUE"; +NET "AD18B_N" IOSTANDARD = LVDS; +NET "AD18B_N" LOC = AA13; +NET "AD18B_P" DIFF_TERM = "TRUE"; +NET "AD18B_P" IOSTANDARD = LVDS; +NET "AD18B_P" LOC = Y13; +NET "AD28B_N" DIFF_TERM = "TRUE"; +NET "AD28B_N" IOSTANDARD = LVDS_25; +NET "AD28B_N" LOC = U20; +NET "AD28B_P" DIFF_TERM = "TRUE"; +NET "AD28B_P" IOSTANDARD = LVDS_25; +NET "AD28B_P" LOC = T20; +NET "AD38B_N" DIFF_TERM = "TRUE"; +NET "AD38B_N" IOSTANDARD = LVDS_25; +NET "AD38B_N" LOC = E22; +NET "AD38B_P" DIFF_TERM = "TRUE"; +NET "AD38B_P" IOSTANDARD = LVDS_25; +NET "AD38B_P" LOC = E21; +NET "AD48B_N" DIFF_TERM = "TRUE"; +NET "AD48B_N" IOSTANDARD = LVDS_25; +NET "AD48B_N" LOC = D14; +NET "AD48B_P" DIFF_TERM = "TRUE"; +NET "AD48B_P" IOSTANDARD = LVDS_25; +NET "AD48B_P" LOC = E14; +NET "DCOA1_N" DIFF_TERM = "TRUE"; +NET "DCOA1_N" IOSTANDARD = LVDS; +NET "DCOA1_N" LOC = Y9; +NET "DCOA1_P" DIFF_TERM = "TRUE"; +NET "DCOA1_P" IOSTANDARD = LVDS; +NET "DCOA1_P" LOC = W9; +NET "DCOB1_N" DIFF_TERM = "TRUE"; +NET "DCOB1_N" IOSTANDARD = LVDS; +NET "DCOB1_N" LOC = Y7; +NET "DCOB1_P" DIFF_TERM = "TRUE"; +NET "DCOB1_P" IOSTANDARD = LVDS; +NET "DCOB1_P" LOC = Y8; +NET "FRA1_N" DIFF_TERM = "TRUE"; +NET "FRA1_N" IOSTANDARD = LVDS; +NET "FRA1_N" LOC = V9; +NET "FRA1_P" DIFF_TERM = "TRUE"; +NET "FRA1_P" IOSTANDARD = LVDS; +NET "FRA1_P" LOC = U10; +NET "FRB1_N" DIFF_TERM = "TRUE"; +NET "FRB1_N" IOSTANDARD = LVDS; +NET "FRB1_N" LOC = AB10; +NET "FRB1_P" DIFF_TERM = "TRUE"; +NET "FRB1_P" IOSTANDARD = LVDS; +NET "FRB1_P" LOC = AA10; +NET "DCOA2_N" DIFF_TERM = "TRUE"; +NET "DCOA2_N" IOSTANDARD = LVDS_25; +NET "DCOA2_N" LOC = W19; +NET "DCOA2_P" DIFF_TERM = "TRUE"; +NET "DCOA2_P" IOSTANDARD = LVDS_25; +NET "DCOA2_P" LOC = V19; +NET "DCOB2_N" DIFF_TERM = "TRUE"; +NET "DCOB2_N" IOSTANDARD = LVDS_25; +NET "DCOB2_N" LOC = Y19; +NET "DCOB2_P" DIFF_TERM = "TRUE"; +NET "DCOB2_P" IOSTANDARD = LVDS_25; +NET "DCOB2_P" LOC = Y18; +NET "FRA2_N" DIFF_TERM = "TRUE"; +NET "FRA2_N" IOSTANDARD = LVDS_25; +NET "FRA2_N" LOC = AB18; +NET "FRA2_P" DIFF_TERM = "TRUE"; +NET "FRA2_P" IOSTANDARD = LVDS_25; +NET "FRA2_P" LOC = AA18; +NET "FRB2_N" DIFF_TERM = "TRUE"; +NET "FRB2_N" IOSTANDARD = LVDS_25; +NET "FRB2_N" LOC = AB20; +NET "FRB2_P" DIFF_TERM = "TRUE"; +NET "FRB2_P" IOSTANDARD = LVDS_25; +NET "FRB2_P" LOC = AA19; +NET "DCOA3_N" DIFF_TERM = "TRUE"; +NET "DCOA3_N" IOSTANDARD = LVDS_25; +NET "DCOA3_N" LOC = L20; +NET "DCOA3_P" DIFF_TERM = "TRUE"; +NET "DCOA3_P" IOSTANDARD = LVDS_25; +NET "DCOA3_P" LOC = L19; +NET "DCOB3_N" DIFF_TERM = "TRUE"; +NET "DCOB3_N" IOSTANDARD = LVDS_25; +NET "DCOB3_N" LOC = N19; +NET "DCOB3_P" DIFF_TERM = "TRUE"; +NET "DCOB3_P" IOSTANDARD = LVDS_25; +NET "DCOB3_P" LOC = N18; +NET "FRA3_N" DIFF_TERM = "TRUE"; +NET "FRA3_N" IOSTANDARD = LVDS_25; +NET "FRA3_N" LOC = M21; +NET "FRA3_P" DIFF_TERM = "TRUE"; +NET "FRA3_P" IOSTANDARD = LVDS_25; +NET "FRA3_P" LOC = N20; +NET "FRB3_N" DIFF_TERM = "TRUE"; +NET "FRB3_N" IOSTANDARD = LVDS_25; +NET "FRB3_N" LOC = J22; +NET "FRB3_P" DIFF_TERM = "TRUE"; +NET "FRB3_P" IOSTANDARD = LVDS_25; +NET "FRB3_P" LOC = J21; +NET "DCOA4_N" DIFF_TERM = "TRUE"; +NET "DCOA4_N" IOSTANDARD = LVDS_25; +NET "DCOA4_N" LOC = C18; +NET "DCOA4_P" DIFF_TERM = "TRUE"; +NET "DCOA4_P" IOSTANDARD = LVDS_25; +NET "DCOA4_P" LOC = C17; +NET "DCOB4_N" DIFF_TERM = "TRUE"; +NET "DCOB4_N" IOSTANDARD = LVDS_25; +NET "DCOB4_N" LOC = E18; +NET "DCOB4_P" DIFF_TERM = "TRUE"; +NET "DCOB4_P" IOSTANDARD = LVDS_25; +NET "DCOB4_P" LOC = E17; +NET "FRA4_N" DIFF_TERM = "TRUE"; +NET "FRA4_N" IOSTANDARD = LVDS_25; +NET "FRA4_N" LOC = A16; +NET "FRA4_P" DIFF_TERM = "TRUE"; +NET "FRA4_P" IOSTANDARD = LVDS_25; +NET "FRA4_P" LOC = B16; +NET "FRB4_N" DIFF_TERM = "TRUE"; +NET "FRB4_N" IOSTANDARD = LVDS_25; +NET "FRB4_N" LOC = D17; +NET "FRB4_P" DIFF_TERM = "TRUE"; +NET "FRB4_P" IOSTANDARD = LVDS_25; +NET "FRB4_P" LOC = E16; + +NET "CSA[1]" LOC = W15; +NET "CSA[1]" IOSTANDARD = LVCMOS25; +NET "CSB[1]" LOC = V15; +NET "CSB[1]" IOSTANDARD = LVCMOS25; +NET "SCK" LOC = U12; +NET "SCK" IOSTANDARD = LVCMOS18; +NET "SDI" LOC = U11; +NET "SDI" IOSTANDARD = LVCMOS18; +NET "SDOA[1]" LOC = W14; +NET "SDOA[1]" IOSTANDARD = LVCMOS25; +NET "SDOB[1]" LOC = Y14; +NET "SDOB[1]" IOSTANDARD = LVCMOS25; +NET "CSA[2]" LOC = T16; +NET "CSA[2]" IOSTANDARD = LVCMOS25; +NET "CSB[2]" LOC = R16; +NET "CSB[2]" IOSTANDARD = LVCMOS25; +NET "SDOA[2]" LOC = T15; +NET "SDOA[2]" IOSTANDARD = LVCMOS25; +NET "SDOB[2]" LOC = U15; +NET "SDOB[2]" IOSTANDARD = LVCMOS25; +NET "CSA[3]" LOC = H17; +NET "CSA[3]" IOSTANDARD = LVCMOS25; +NET "CSB[3]" LOC = G17; +NET "CSB[3]" IOSTANDARD = LVCMOS25; +NET "SDOA[3]" LOC = J16; +NET "SDOA[3]" IOSTANDARD = LVCMOS25; +NET "SDOB[3]" LOC = J17; +NET "SDOB[3]" IOSTANDARD = LVCMOS25; +NET "CSA[4]" LOC = F18; +NET "CSA[4]" IOSTANDARD = LVCMOS25; +NET "CSB[4]" LOC = E19; +NET "CSB[4]" IOSTANDARD = LVCMOS25; +NET "SDOA[4]" LOC = G15; +NET "SDOA[4]" IOSTANDARD = LVCMOS25; +NET "SDOB[4]" LOC = G16; +NET "SDOB[4]" IOSTANDARD = LVCMOS25; + +NET "GCLK_N" DIFF_TERM = "TRUE"; +NET "GCLK_N" IOSTANDARD = LVDS; +NET "GCLK_N" LOC = T3; +NET "GCLK_P" DIFF_TERM = "TRUE"; +NET "GCLK_P" IOSTANDARD = LVDS; +NET "GCLK_P" LOC = R3; +#NET "GCLK_P" IOSTANDARD = LVCMOS18; +#NET "GCLK_N" IOSTANDARD = LVCMOS18; +#NET "GCLK_N" CLOCK_DEDICATED_ROUTE = FALSE; + + +NET "GEO" LOC = K17; +NET "GEO" IOSTANDARD = LVCMOS25; +NET "GEO" SLEW = SLOW; +NET "GEO" PULLUP; +NET "GEO" TIG; + +#Bank 16 = 2.5V +NET "SYS_CLK" LOC = H12; +NET "SYS_CLK" IOSTANDARD = LVCMOS25; + +NET "INTCOMC1_N" LOC = D11; +NET "INTCOMC1_P" LOC = E11; +NET "INTCOMC2_N" LOC = G10; +NET "INTCOMC2_P" LOC = G11; +NET "INTCOM0_N" LOC = E9; +NET "INTCOM0_P" LOC = F9; +NET "INTCOM1_N" LOC = H8; +NET "INTCOM1_P" LOC = H9; +NET "INTCOM2_N" LOC = F8; +NET "INTCOM2_P" LOC = G8; +NET "INTCOM3_N" LOC = C9; +NET "INTCOM3_P" LOC = D9; +NET "INTCOM4_N" LOC = B10; +NET "INTCOM4_P" LOC = B11; +NET "INTCOM5_N" LOC = A8; +NET "INTCOM5_P" LOC = A9; +NET "INTCOM6_N" LOC = B8; +NET "INTCOM6_P" LOC = C8; +NET "INTCOM7_N" LOC = A10; +NET "INTCOM7_P" LOC = A11; + +NET "INTCOMC1_N" IOSTANDARD = LVCMOS25; +NET "INTCOMC1_P" IOSTANDARD = LVCMOS25; +NET "INTCOMC2_N" IOSTANDARD = LVCMOS25; +NET "INTCOMC2_P" IOSTANDARD = LVCMOS25; +NET "INTCOM0_N" IOSTANDARD = LVCMOS25; +NET "INTCOM0_P" IOSTANDARD = LVCMOS25; +NET "INTCOM1_N" IOSTANDARD = LVCMOS25; +NET "INTCOM1_P" IOSTANDARD = LVCMOS25; +NET "INTCOM2_N" IOSTANDARD = LVCMOS25; +NET "INTCOM2_P" IOSTANDARD = LVCMOS25; +NET "INTCOM3_N" IOSTANDARD = LVCMOS25; +NET "INTCOM3_P" IOSTANDARD = LVCMOS25; +NET "INTCOM4_N" IOSTANDARD = LVCMOS25; +NET "INTCOM4_P" IOSTANDARD = LVCMOS25; +NET "INTCOM5_N" IOSTANDARD = LVCMOS25; +NET "INTCOM5_P" IOSTANDARD = LVCMOS25; +NET "INTCOM6_N" IOSTANDARD = LVCMOS25; +NET "INTCOM6_P" IOSTANDARD = LVCMOS25; +NET "INTCOM7_N" IOSTANDARD = LVCMOS25; +NET "INTCOM7_P" IOSTANDARD = LVCMOS25; + + +NET "INTCOMC1_P" SLEW = FAST; +NET "INTCOMC1_N" SLEW = FAST; +NET "INTCOMC2_P" SLEW = FAST; +NET "INTCOMC2_N" SLEW = FAST; +NET "INTCOM0_P" SLEW = FAST; +NET "INTCOM0_N" SLEW = FAST; +NET "INTCOM1_P" SLEW = FAST; +NET "INTCOM1_N" SLEW = FAST; +NET "INTCOM2_P" SLEW = FAST; +NET "INTCOM2_N" SLEW = FAST; +NET "INTCOM3_P" SLEW = FAST; +NET "INTCOM3_N" SLEW = FAST; +NET "INTCOM4_P" SLEW = FAST; +NET "INTCOM4_N" SLEW = FAST; +NET "INTCOM5_P" SLEW = FAST; +NET "INTCOM5_N" SLEW = FAST; +NET "INTCOM6_P" SLEW = FAST; +NET "INTCOM6_N" SLEW = FAST; +NET "INTCOM7_P" SLEW = FAST; +NET "INTCOM7_N" SLEW = FAST; + + +NET "INTCOMC1_P" DRIVE = 4; +NET "INTCOMC1_N" DRIVE = 4; +NET "INTCOMC2_P" DRIVE = 4; +NET "INTCOMC2_N" DRIVE = 4; +NET "INTCOM0_P" DRIVE = 4; +NET "INTCOM0_N" DRIVE = 4; +NET "INTCOM1_P" DRIVE = 4; +NET "INTCOM1_N" DRIVE = 4; +NET "INTCOM2_P" DRIVE = 4; +NET "INTCOM2_N" DRIVE = 4; +NET "INTCOM3_P" DRIVE = 4; +NET "INTCOM3_N" DRIVE = 4; +NET "INTCOM4_P" DRIVE = 4; +NET "INTCOM4_N" DRIVE = 4; +NET "INTCOM5_P" DRIVE = 4; +NET "INTCOM5_N" DRIVE = 4; +NET "INTCOM6_P" DRIVE = 4; +NET "INTCOM6_N" DRIVE = 4; +NET "INTCOM7_P" DRIVE = 4; +NET "INTCOM7_N" DRIVE = 4; + + + +NET "RCV_CLK_N" LOC = F10; +NET "RCV_CLK_N" DIFF_TERM = "TRUE"; +NET "RCV_CLK_N" IOSTANDARD = LVDS_25; +NET "RCV_CLK_P" LOC = F11; +NET "RCV_CLK_P" DIFF_TERM = "TRUE"; +NET "RCV_CLK_P" IOSTANDARD = LVDS_25; + +NET "S_CTRL" LOC = E12; +NET "S_CTRL" IOSTANDARD = LVCMOS25; +NET "T_CTRL" LOC = E13; +NET "T_CTRL" IOSTANDARD = LVCMOS25; + +#bank 34: 3.3V +NET "SYNC" LOC = W5; +NET "SYNC" IOSTANDARD = LVCMOS18; +NET "CLKu" LOC = AA4; +NET "CLKu" IOSTANDARD = LVCMOS18; +NET "DATAu" LOC = AA3; +NET "DATAu" IOSTANDARD = LVCMOS18; +NET "LEu" LOC = Y4; +NET "LEu" IOSTANDARD = LVCMOS18; +NET "RDu" LOC = AB3; +NET "RDu" IOSTANDARD = LVCMOS18; +NET "RDu" CLOCK_DEDICATED_ROUTE = FALSE; + +NET "ST_CLK_N" LOC = U3; +#NET "ST_CLK_N" DIFF_TERM = "TRUE"; +#NET "ST_CLK_N" IOSTANDARD = LVDS; +NET "ST_CLK_N" IOSTANDARD = LVCMOS18; + +NET "ST_CLK_P" LOC = T4; +#NET "ST_CLK_P" DIFF_TERM = "TRUE"; +#NET "ST_CLK_P" IOSTANDARD = LVDS; +NET "ST_CLK_P" IOSTANDARD = LVCMOS18; +#NET "ST_CLK_N" CLOCK_DEDICATED_ROUTE = FALSE; + +NET "MGTREFCLK_N" LOC = D5; +NET "MGTREFCLK_N" DIFF_TERM = "TRUE"; +NET "MGTREFCLK_N" IOSTANDARD = LVDS; +NET "MGTREFCLK_P" LOC = D6; +NET "MGTREFCLK_P" DIFF_TERM = "TRUE"; +NET "MGTREFCLK_P" IOSTANDARD = LVDS; +NET "RX_N" LOC = G3; +NET "RX_N" DIFF_TERM = "TRUE"; +NET "RX_N" IOSTANDARD = LVDS; +NET "RX_P" LOC = G4; +NET "RX_P" DIFF_TERM = "TRUE"; +NET "RX_P" IOSTANDARD = LVDS; +NET "TX_N" LOC = F1; +NET "TX_N" DIFF_TERM = "TRUE"; +NET "TX_N" IOSTANDARD = LVDS; +NET "TX_P" LOC = F2; +NET "TX_P" DIFF_TERM = "TRUE"; +NET "TX_P" IOSTANDARD = LVDS; +NET "LOS" LOC = K1; +NET "LOS" IOSTANDARD = LVCMOS18; +NET "TX_DIS" LOC = L1; +NET "TX_DIS" IOSTANDARD = LVCMOS18; +NET "MOD_DEF[0]" LOC = M2; +NET "MOD_DEF[0]" IOSTANDARD = LVCMOS18; +NET "MOD_DEF[1]" LOC = M1; +NET "MOD_DEF[1]" IOSTANDARD = LVCMOS18; +NET "MOD_DEF[2]" LOC = K3; +NET "MOD_DEF[2]" IOSTANDARD = LVCMOS18; + +NET "MON1_N" LOC = Y1; +NET "MON1_N" IOSTANDARD = LVCMOS18; +NET "MON1_P" LOC = W1; +NET "MON1_P" IOSTANDARD = LVCMOS18; +NET "MON2_N" LOC = Y2; +NET "MON2_N" IOSTANDARD = LVCMOS18; +NET "MON2_P" LOC = Y3; +NET "MON2_P" IOSTANDARD = LVCMOS18; + +NET "TEMP_OUT" LOC = T10; +NET "TEMP_OUT" IOSTANDARD = LVCMOS18; +NET "TEMP_IN" LOC = T11; +NET "TEMP_IN" IOSTANDARD = LVCMOS18; + +#NET "GT_A2B_0_N" LOC = D1; +#NET "GT_A2B_0_P" LOC = D2; +#NET "GT_A2B_1_N" LOC = B1; +#NET "GT_A2B_1_P" LOC = B2; +#NET "GT_B2A_0_N" LOC = E3; +#NET "GT_B2A_0_P" LOC = E4; +#NET "GT_B2A_1_N" LOC = C3; +#NET "GT_B2A_1_P" LOC = C4; +#NET "DONE_P1" LOC = P6; +#NET "CF_D0_I1" LOC = H18; +#NET "CF_D1_I1" LOC = H19; +#NET "CF_D2_I1" LOC = G18; +#NET "CF_D3_I1" LOC = F19; +#NET "CF_EMCL_I1" LOC = H12; +#NET "CF_EMCL_I1" LOC = J19; +#NET "CF_FCS_I1" LOC = L16; +#NET "CF_PUDC_I1" LOC = K18; +#NET "CCLK1_P1" LOC = G7; +#NET "JTAG_IN1_TCK" LOC = K7; +#NET "JTAG_IN1_TDI" LOC = K6; +#NET "JTAG_IN1_TDO" LOC = J6; +#NET "JTAG_IN1_TMS" LOC = L6; +NET "JTAG_OUT1_TCK_F" LOC = G13; +NET "JTAG_OUT1_TCK_F" IOSTANDARD = LVCMOS25; +NET "JTAG_OUT1_TDI_F" LOC = H14; +NET "JTAG_OUT1_TDI_F" IOSTANDARD = LVCMOS25; +NET "JTAG_OUT1_TDO_F" LOC = H13; +NET "JTAG_OUT1_TDO_F" IOSTANDARD = LVCMOS25; +NET "JTAG_OUT1_TMS_F" LOC = F13; +NET "JTAG_OUT1_TMS_F" IOSTANDARD = LVCMOS25; + + +########################################################################################## +# timing clock inputs: +NET "SYS_CLK" TNM_NET = "SYS_CLK"; +TIMESPEC TS_SYS_CLK = PERIOD "SYS_CLK" 10 ns HIGH 50 %; + +NET "ST_CLK_P" TNM_NET = "ST_CLK_P"; +TIMESPEC TS_ST_CLK_P = PERIOD "ST_CLK_P" 6.43 ns HIGH 50 %; +NET "ST_CLK_N" TNM_NET = "ST_CLK_N"; +TIMESPEC TS_ST_CLK_N = PERIOD "ST_CLK_N" 6.43 ns HIGH 50 %; + +NET "GCLK_P" TNM_NET = "GCLK_P"; +TIMESPEC TS_GCLK_P = PERIOD "GCLK_P" 12.5 ns HIGH 50 %; +NET "GCLK_N" TNM_NET = "GCLK_N"; +TIMESPEC TS_GCLK_N = PERIOD "GCLK_N" 12.5 ns HIGH 50 %; + +########################################################################################## +# derived clocks +NET "async_clock_S" TNM_NET = "async_clock_S"; +TIMESPEC TS_async_clock_S = PERIOD "async_clock_S" 15.8333 ns HIGH 50 %; + +NET "clock100MHz_S" TNM_NET = "clock100MHz_S"; +TIMESPEC TS_clock100MHz_S = PERIOD "clock100MHz_S" 10 ns HIGH 50 %; + +NET "clock_S" TNM_NET = "clock_S"; +TIMESPEC TS_clock_S = PERIOD "clock_S" 12.5 ns HIGH 50 %; + +#NET "ST_CLK_S" TNM_NET = "ST_CLK_S"; +#TIMESPEC TS_ST_CLK_S = PERIOD "ST_CLK_S" 6.43 ns HIGH 50 %; + +NET "rxSodaClk_S" TNM_NET = "rxSodaClk_S"; +TIMESPEC TS_rxSodaClk_S = PERIOD "rxSodaClk_S" 5 ns HIGH 50 %; + +########################################################################################## +# between clocks +TIMESPEC TS_asyn_to_clock = FROM "async_clock_S" TO "clock_S" TIG ; +TIMESPEC TS_clock_to_async = FROM "clock_S" TO "async_clock_S" TIG ; + +#TIMESPEC TS_G_to_ST = FROM "GCLK_P" TO "ST_CLK_S" TIG; +#TIMESPEC TS_SODA_to_ST = FROM "rxSodaClk_S" TO "ST_CLK_S_net" TIG; +TIMESPEC TS_SODA_to_G = FROM "rxSodaClk_S" TO "GCLK_P" TIG ; + + +################################################################################################################################ +# GTX +#NET "MGTREFCLK_P" TNM_NET = "MGTREFCLK_P"; +#TIMESPEC TS_MGTREFCLK_P = PERIOD "MGTREFCLK_P" 12.5 ns HIGH 50 %; +#NET "MGTREFCLK_N" TNM_NET = "MGTREFCLK_N"; +#TIMESPEC TS_MGTREFCLK_N = PERIOD "MGTREFCLK_N" 12.5 ns HIGH 50 %; + +NET "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/rxRecClk_S" TNM_NET = "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/rxRecClk_S"; +TIMESPEC TS_FEE_gtxModule1_FEE_gtxWrapper_Kintex7_1_rxRecClk_S = PERIOD "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/rxRecClk_S" 10 ns HIGH 50 %; +NET "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txOutClk_S" TNM_NET = "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txOutClk_S"; +TIMESPEC TS_FEE_gtxModule1_FEE_gtxWrapper_Kintex7_1_txOutClk_S = PERIOD "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txOutClk_S" 12.5 ns HIGH 50 %; + + +### ???????????????? : +NET "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClk_buf_S" TNM_NET = "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClk_buf_S"; +TIMESPEC TS_FEE_gtxModule1_FEE_gtxWrapper_Kintex7_1_txUsrClk_buf_S = PERIOD "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClk_buf_S" 10 ns HIGH 50 %; + +NET "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClkx2_S" TNM_NET = "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClkx2_S"; +TIMESPEC TS_FEE_gtxModule1_FEE_gtxWrapper_Kintex7_1_txUsrClkx2_S = PERIOD "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClkx2_S" 5 ns HIGH 50 %; + + +TIMESPEC TS_FEE_gtxModule1_tx = FROM "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClkx2_S" TO "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClk_buf_S" 2 ns; +TIMESPEC TS_FEE_gtxModule1_tx = FROM "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClkx2_S" TO "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClk_buf_S" 2 ns; + +INST "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/gtx_i/gtxKintex7FEE80_i/gt0_gtxKintex7FEE80_i/gtxe2_i" LOC = GTXE2_CHANNEL_X0Y0; + +################################################################################################################################ +# ADC +NET "ADC_clk_S" TNM_NET = "ADC_clk_S"; +TIMESPEC TS_ADC_clk_S = PERIOD "ADC_clk_S" 12.5 ns HIGH 50 %; +NET "ADC_clk_S" MAXDELAY = 3 ns; +NET "ADC_clk_S" MAXSKEW = 1 ns; + + +################################################################################################################################ +# ADC placement +INST "FEE_ADCinput_module1/AdcToplevel1458_1" AREA_GROUP = "pblock_adc_1"; +INST "FEE_ADCinput_module1/AdcToplevel2356_1" AREA_GROUP = "pblock_adc_1"; +AREA_GROUP "pblock_adc_1" RANGE=SLICE_X106Y50:SLICE_X109Y99; +#AREA_GROUP "pblock_adc_1" RANGE=SLICE_X104Y99:SLICE_X108Y50; +INST "FEE_ADCinput_module1/AdcToplevel1458_2" AREA_GROUP = "pblock_adc_2"; +INST "FEE_ADCinput_module1/AdcToplevel2356_2" AREA_GROUP = "pblock_adc_2"; +AREA_GROUP "pblock_adc_2" RANGE=SLICE_X0Y50:SLICE_X3Y99; +#AREA_GROUP "pblock_adc_2" RANGE=SLICE_X1Y99:SLICE_X2Y50; +#AREA_GROUP "pblock_adc_2" RANGE=SLICE_X0Y99:SLICE_X2Y50; +INST "FEE_ADCinput_module1/AdcToplevel1458_3" AREA_GROUP = "pblock_adc_3"; +INST "FEE_ADCinput_module1/AdcToplevel2356_3" AREA_GROUP = "pblock_adc_3"; +AREA_GROUP "pblock_adc_3" RANGE=SLICE_X0Y100:SLICE_X3Y149; +#AREA_GROUP "pblock_adc_3" RANGE=SLICE_X1Y149:SLICE_X2Y100; +INST "FEE_ADCinput_module1/AdcToplevel1458_4" AREA_GROUP = "pblock_adc_4"; +INST "FEE_ADCinput_module1/AdcToplevel2356_4" AREA_GROUP = "pblock_adc_4"; +AREA_GROUP "pblock_adc_4" RANGE=SLICE_X0Y151:SLICE_X3Y199; + + +############################################################################################# +# Timing constraints +############################################################################################# +# The DCLK input clock, bit clock from the ADC, doesn't need a timespec. +# This clock passes from the IOB through the BUFIO and to the .CLK input of all used ISERDES. +# This path is made from dedicated routing. +# From the IOB to the BUFIO.I is a dedicated connection only availabel with Clock Capable_IO. +# This connection takes for all IO-banks in a FPGA and from all FPGAs of the familly an +# average value of 220 ps. +# The connection from the BUFIO.O to all ISERDES.CLK is also a dedicated connection, it +# takes on average 330 ps. +# The BUFIO average delay is: 869 ps and an LVDS IOB is average: 1094 ps. +# A MAXSKEW constraint is used to detect the skew on the CLK net. +#-->NET "*AdcClock/BitClk_MonClkOut" MAXSKEW = 100 ps; +NET "FEE_ADCinput_module1/AdcToplevel1458_1/IntClk" MAXSKEW = 100 ps; +NET "FEE_ADCinput_module1/AdcToplevel1458_2/IntClk" MAXSKEW = 100 ps; +NET "FEE_ADCinput_module1/AdcToplevel1458_3/IntClk" MAXSKEW = 100 ps; +NET "FEE_ADCinput_module1/AdcToplevel1458_4/IntClk" MAXSKEW = 100 ps; +NET "FEE_ADCinput_module1/AdcToplevel2356_1/IntClk" MAXSKEW = 100 ps; +NET "FEE_ADCinput_module1/AdcToplevel2356_2/IntClk" MAXSKEW = 100 ps; +NET "FEE_ADCinput_module1/AdcToplevel2356_3/IntClk" MAXSKEW = 100 ps; +NET "FEE_ADCinput_module1/AdcToplevel2356_4/IntClk" MAXSKEW = 100 ps; + +NET "FEE_ADCinput_module1/AdcToplevel1458_1/IntClk" MAXDELAY = 400 ps; +NET "FEE_ADCinput_module1/AdcToplevel1458_2/IntClk" MAXDELAY = 400 ps; +NET "FEE_ADCinput_module1/AdcToplevel1458_3/IntClk" MAXDELAY = 400 ps; +NET "FEE_ADCinput_module1/AdcToplevel1458_4/IntClk" MAXDELAY = 400 ps; +NET "FEE_ADCinput_module1/AdcToplevel2356_1/IntClk" MAXDELAY = 400 ps; +NET "FEE_ADCinput_module1/AdcToplevel2356_2/IntClk" MAXDELAY = 400 ps; +NET "FEE_ADCinput_module1/AdcToplevel2356_3/IntClk" MAXDELAY = 400 ps; +NET "FEE_ADCinput_module1/AdcToplevel2356_4/IntClk" MAXDELAY = 400 ps; + +NET "FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcClock/BitClk_inv" MAXDELAY = 400 ps; +NET "FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcClock/BitClk_inv" MAXDELAY = 400 ps; +NET "FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcClock/BitClk_inv" MAXDELAY = 400 ps; +NET "FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcClock/BitClk_inv" MAXDELAY = 400 ps; +NET "FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcClock/BitClk_inv" MAXDELAY = 400 ps; +NET "FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcClock/BitClk_inv" MAXDELAY = 400 ps; +NET "FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcClock/BitClk_inv" MAXDELAY = 400 ps; +NET "FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcClock/BitClk_inv" MAXDELAY = 400 ps; + +# +# The connection from the BUFR.O to the ISERDES.CLKDIV inputs runs over normal clock nets. +# Oposite to the BUFIO.O - ISERDES.CLK routing, the BUFR.O net not only connects to the +# ISERDES.CLKDIV pins of the I/O SERDES in the IO-bank the BUFR is located in but to all +# clocked elements (FFs, BRAM, DSP, ..) in that clock area. +# It also connects to the adjacent upper and lower clock areas. +# Therefore it is necessary to put timing constraints on this clock. +# A MAXSKEW constraint to keep the skew as low as possible. makes sure the ISERDES are clocked +# at the same time so that early-late data cannot appear at the outputs of the ISERDES. +#-->NET "*AdcClock/BitClk_RefClkOut" MAXSKEW = 300 ps; +NET "FEE_ADCinput_module1/AdcToplevel1458_1/IntClkDiv" MAXSKEW = 400 ps; +NET "FEE_ADCinput_module1/AdcToplevel1458_2/IntClkDiv" MAXSKEW = 400 ps; +NET "FEE_ADCinput_module1/AdcToplevel1458_3/IntClkDiv" MAXSKEW = 400 ps; +NET "FEE_ADCinput_module1/AdcToplevel1458_4/IntClkDiv" MAXSKEW = 400 ps; +NET "FEE_ADCinput_module1/AdcToplevel2356_1/IntClkDiv" MAXSKEW = 400 ps; +NET "FEE_ADCinput_module1/AdcToplevel2356_2/IntClkDiv" MAXSKEW = 400 ps; +NET "FEE_ADCinput_module1/AdcToplevel2356_3/IntClkDiv" MAXSKEW = 400 ps; +NET "FEE_ADCinput_module1/AdcToplevel2356_4/IntClkDiv" MAXSKEW = 400 ps; + + +NET "FEE_ADCinput_module1/AdcToplevel1458_1/IntRst_S" MAXDELAY = 1.5 ns; +NET "FEE_ADCinput_module1/AdcToplevel1458_2/IntRst_S" MAXDELAY = 1.5 ns; +NET "FEE_ADCinput_module1/AdcToplevel1458_3/IntRst_S" MAXDELAY = 1.5 ns; +NET "FEE_ADCinput_module1/AdcToplevel1458_4/IntRst_S" MAXDELAY = 1.5 ns; +NET "FEE_ADCinput_module1/AdcToplevel2356_1/IntRst_S" MAXDELAY = 1.5 ns; +NET "FEE_ADCinput_module1/AdcToplevel2356_2/IntRst_S" MAXDELAY = 1.5 ns; +NET "FEE_ADCinput_module1/AdcToplevel2356_3/IntRst_S" MAXDELAY = 1.5 ns; +NET "FEE_ADCinput_module1/AdcToplevel2356_4/IntRst_S" MAXDELAY = 1.5 ns; + +NET "FEE_ADCinput_module1/AdcToplevel1458_1/IntEna_S" MAXDELAY = 1.5 ns; +NET "FEE_ADCinput_module1/AdcToplevel1458_2/IntEna_S" MAXDELAY = 1.5 ns; +NET "FEE_ADCinput_module1/AdcToplevel1458_3/IntEna_S" MAXDELAY = 1.5 ns; +NET "FEE_ADCinput_module1/AdcToplevel1458_4/IntEna_S" MAXDELAY = 1.5 ns; +NET "FEE_ADCinput_module1/AdcToplevel2356_1/IntEna_S" MAXDELAY = 1.5 ns; +NET "FEE_ADCinput_module1/AdcToplevel2356_2/IntEna_S" MAXDELAY = 1.5 ns; +NET "FEE_ADCinput_module1/AdcToplevel2356_3/IntEna_S" MAXDELAY = 1.5 ns; +NET "FEE_ADCinput_module1/AdcToplevel2356_4/IntEna_S" MAXDELAY = 1.5 ns; + +NET "FEE_ADCinput_module1/AdcToplevel1458_1/IntBitClkDone_S" MAXDELAY = 1.5 ns; +NET "FEE_ADCinput_module1/AdcToplevel1458_2/IntBitClkDone_S" MAXDELAY = 1.5 ns; +NET "FEE_ADCinput_module1/AdcToplevel1458_3/IntBitClkDone_S" MAXDELAY = 1.5 ns; +NET "FEE_ADCinput_module1/AdcToplevel1458_4/IntBitClkDone_S" MAXDELAY = 1.5 ns; +NET "FEE_ADCinput_module1/AdcToplevel2356_1/IntBitClkDone_S" MAXDELAY = 1.5 ns; +NET "FEE_ADCinput_module1/AdcToplevel2356_2/IntBitClkDone_S" MAXDELAY = 1.5 ns; +NET "FEE_ADCinput_module1/AdcToplevel2356_3/IntBitClkDone_S" MAXDELAY = 1.5 ns; +NET "FEE_ADCinput_module1/AdcToplevel2356_4/IntBitClkDone_S" MAXDELAY = 1.5 ns; + +# A period constraint at the BUFR will make sure the correct timing is applied on clock net. +#-->NET "*AdcClock/BitClk_RefClkOut" TNM_NET = "BitClkRefClk"; +#-->TIMESPEC TS_ClkDiv = PERIOD "BitClkRefClk" 3.4 ns HIGH 50 %; + +NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk"; +TIMESPEC TS_AdcToplevel1458_1_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk" 3 ns HIGH 50 %; +NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk"; +TIMESPEC TS_AdcToplevel2356_1_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk" 3 ns HIGH 50 %; + +NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk"; +TIMESPEC TS_AdcToplevel1458_2_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk" 3 ns HIGH 50 %; +NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk"; +TIMESPEC TS_AdcToplevel2356_2_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk" 3 ns HIGH 50 %; + +NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk"; +TIMESPEC TS_AdcToplevel1458_3_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk" 3 ns HIGH 50 %; +NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk"; +TIMESPEC TS_AdcToplevel2356_3_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk" 3 ns HIGH 50 %; + +NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk"; +TIMESPEC TS_AdcToplevel1458_4_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk" 3 ns HIGH 50 %; +NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk"; +TIMESPEC TS_AdcToplevel2356_4_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk" 3 ns HIGH 50 %; + + + + + + + +################################################################################ +# Grouping of components. +################################################################################ +# The logic of the interface is timing constraint with FROM-TO constraints. +# The logic is first grouped per functionality and the constraints are applied. +#-->INST "*AdcClock/AdcClock_I_Isrds_*" TNM = FFS "AdcClk_Isrds"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_1/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*" TNM = FFS "AdcClk_Isrds1A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_1/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*" TNM = FFS "AdcClk_Isrds1B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_2/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*" TNM = FFS "AdcClk_Isrds2A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_2/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*" TNM = FFS "AdcClk_Isrds2B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_3/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*" TNM = FFS "AdcClk_Isrds3A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_3/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*" TNM = FFS "AdcClk_Isrds3B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_4/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*" TNM = FFS "AdcClk_Isrds4A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_4/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*" TNM = FFS "AdcClk_Isrds4B"; +#-->INST "*AdcClock/*" TNM = FFS "AdcClk_Ffs"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_1/AdcToplevel_I_AdcClock/*" TNM = FFS "AdcClk_Ffs1A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_1/AdcToplevel_I_AdcClock/*" TNM = FFS "AdcClk_Ffs1B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_2/AdcToplevel_I_AdcClock/*" TNM = FFS "AdcClk_Ffs2A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_2/AdcToplevel_I_AdcClock/*" TNM = FFS "AdcClk_Ffs2B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_3/AdcToplevel_I_AdcClock/*" TNM = FFS "AdcClk_Ffs3A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_3/AdcToplevel_I_AdcClock/*" TNM = FFS "AdcClk_Ffs3B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_4/AdcToplevel_I_AdcClock/*" TNM = FFS "AdcClk_Ffs4A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_4/AdcToplevel_I_AdcClock/*" TNM = FFS "AdcClk_Ffs4B"; + +#-->INST "*AdcFrame/AdcFrame_I_Isrds_*" TNM = FFS "AdcFrm_Isrds"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_1/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*" TNM = FFS "AdcFrame_Isrds1A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_1/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*" TNM = FFS "AdcFrame_Isrds1B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_2/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*" TNM = FFS "AdcFrame_Isrds2A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_2/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*" TNM = FFS "AdcFrame_Isrds2B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_3/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*" TNM = FFS "AdcFrame_Isrds3A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_3/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*" TNM = FFS "AdcFrame_Isrds3B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_4/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*" TNM = FFS "AdcFrame_Isrds4A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_4/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*" TNM = FFS "AdcFrame_Isrds4B"; +#-->INST "*AdcFrame/*" TNM = FFS "AdcFrm_Ffs"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_1/AdcToplevel_I_AdcFrame/*" TNM = FFS "AdcFrame_Ffs1A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_1/AdcToplevel_I_AdcFrame/*" TNM = FFS "AdcFrame_Ffs1B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_2/AdcToplevel_I_AdcFrame/*" TNM = FFS "AdcFrame_Ffs2A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_2/AdcToplevel_I_AdcFrame/*" TNM = FFS "AdcFrame_Ffs2B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_3/AdcToplevel_I_AdcFrame/*" TNM = FFS "AdcFrame_Ffs3A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_3/AdcToplevel_I_AdcFrame/*" TNM = FFS "AdcFrame_Ffs3B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_4/AdcToplevel_I_AdcFrame/*" TNM = FFS "AdcFrame_Ffs4A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_4/AdcToplevel_I_AdcFrame/*" TNM = FFS "AdcFrame_Ffs4B"; + +#-->INST "*AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_1/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds1A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_1/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds1B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_2/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds2A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_2/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds2B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_3/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds3A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_3/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds3B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_4/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds4A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_4/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds4B"; + +INST "FEE_ADCinput_module1/AdcTopleveL1458_1/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds1A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_1/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds1B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_2/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds2A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_2/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds2B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_3/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds3A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_3/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds3B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_4/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds4A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_4/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds4B"; + +INST "FEE_ADCinput_module1/AdcTopleveL1458_1/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds1A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_1/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds1B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_2/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds2A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_2/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds2B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_3/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds3A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_3/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds3B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_4/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds4A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_4/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds4B"; + +INST "FEE_ADCinput_module1/AdcTopleveL1458_1/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds1A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_1/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds1B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_2/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds2A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_2/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds2B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_3/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds3A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_3/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds3B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_4/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds4A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_4/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcData_Isrds4B"; + +#-->INST "*AdcData/*" TNM = FFS "AdcData_Ffs"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_1/Gen_2[0].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs1A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_1/Gen_2[0].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs1B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_2/Gen_2[0].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs2A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_2/Gen_2[0].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs2B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_3/Gen_2[0].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs3A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_3/Gen_2[0].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs3B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_4/Gen_2[0].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs4A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_4/Gen_2[0].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs4B"; + +INST "FEE_ADCinput_module1/AdcTopleveL1458_1/Gen_2[1].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs1A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_1/Gen_2[1].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs1B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_2/Gen_2[1].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs2A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_2/Gen_2[1].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs2B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_3/Gen_2[1].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs3A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_3/Gen_2[1].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs3B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_4/Gen_2[1].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs4A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_4/Gen_2[1].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs4B"; + +INST "FEE_ADCinput_module1/AdcTopleveL1458_1/Gen_2[2].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs1A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_1/Gen_2[2].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs1B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_2/Gen_2[2].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs2A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_2/Gen_2[2].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs2B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_3/Gen_2[2].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs3A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_3/Gen_2[2].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs3B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_4/Gen_2[2].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs4A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_4/Gen_2[2].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs4B"; + +INST "FEE_ADCinput_module1/AdcTopleveL1458_1/Gen_2[3].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs1A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_1/Gen_2[3].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs1B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_2/Gen_2[3].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs2A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_2/Gen_2[3].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs2B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_3/Gen_2[3].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs3A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_3/Gen_2[3].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs3B"; +INST "FEE_ADCinput_module1/AdcTopleveL1458_4/Gen_2[3].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs4A"; +INST "FEE_ADCinput_module1/AdcTopleveL2356_4/Gen_2[3].AdcToplevel_I_AdcData/*" TNM = FFS "AdcData_Ffs4B"; + +################################################################################ +# Timespec between groups +################################################################################ +#-->TIMESPEC TS_ClkIsrds_ClkFfs = FROM "AdcClk_Isrds" TO "AdcClk_Ffs" 3 ns; +TIMESPEC TS_ClkIsrds_ClkFfs1A = FROM "AdcClk_Isrds1A" TO "AdcClk_Ffs1A" 2.2 ns; +TIMESPEC TS_ClkIsrds_ClkFfs1B = FROM "AdcClk_Isrds1B" TO "AdcClk_Ffs1B" 2.2 ns; +TIMESPEC TS_ClkIsrds_ClkFfs2A = FROM "AdcClk_Isrds2A" TO "AdcClk_Ffs2A" 2.2 ns; +TIMESPEC TS_ClkIsrds_ClkFfs2B = FROM "AdcClk_Isrds2B" TO "AdcClk_Ffs2B" 2.2 ns; +TIMESPEC TS_ClkIsrds_ClkFfs3A = FROM "AdcClk_Isrds3A" TO "AdcClk_Ffs3A" 2.2 ns; +TIMESPEC TS_ClkIsrds_ClkFfs3B = FROM "AdcClk_Isrds3B" TO "AdcClk_Ffs3B" 2.2 ns; +TIMESPEC TS_ClkIsrds_ClkFfs4A = FROM "AdcClk_Isrds4A" TO "AdcClk_Ffs4A" 2.2 ns; +TIMESPEC TS_ClkIsrds_ClkFfs4B = FROM "AdcClk_Isrds4B" TO "AdcClk_Ffs4B" 2.2 ns; +#-->TIMESPEC TS_FrmIsrds_FrmFfs = FROM "AdcFrm_Isrds" TO "AdcFrm_Ffs" 3 ns; +TIMESPEC TS_FrameIsrds_FrameFfs1A = FROM "AdcFrame_Isrds1A" TO "AdcFrame_Ffs1A" 2.2 ns; +TIMESPEC TS_FrameIsrds_FrameFfs1B = FROM "AdcFrame_Isrds1B" TO "AdcFrame_Ffs1B" 2.2 ns; +TIMESPEC TS_FrameIsrds_FrameFfs2A = FROM "AdcFrame_Isrds2A" TO "AdcFrame_Ffs2A" 2.2 ns; +TIMESPEC TS_FrameIsrds_FrameFfs2B = FROM "AdcFrame_Isrds2B" TO "AdcFrame_Ffs2B" 2.2 ns; +TIMESPEC TS_FrameIsrds_FrameFfs3A = FROM "AdcFrame_Isrds3A" TO "AdcFrame_Ffs3A" 2.2 ns; +TIMESPEC TS_FrameIsrds_FrameFfs3B = FROM "AdcFrame_Isrds3B" TO "AdcFrame_Ffs3B" 2.2 ns; +TIMESPEC TS_FrameIsrds_FrameFfs4A = FROM "AdcFrame_Isrds4A" TO "AdcFrame_Ffs4A" 2.2 ns; +TIMESPEC TS_FrameIsrds_FrameFfs4B = FROM "AdcFrame_Isrds4B" TO "AdcFrame_Ffs4B" 2.2 ns; +#-->TIMESPEC TS_DatIsrds_DatFfs = FROM "AdcDat_Isrds" TO "AdcDat_Ffs" 3 ns; +TIMESPEC TS_DataIsrds_DataFfs1A = FROM "AdcData_Isrds1A" TO "AdcData_Ffs1A" 2.2 ns; +TIMESPEC TS_DataIsrds_DataFfs1B = FROM "AdcData_Isrds1B" TO "AdcData_Ffs1B" 2.2 ns; +TIMESPEC TS_DataIsrds_DataFfs2A = FROM "AdcData_Isrds2A" TO "AdcData_Ffs2A" 2.2 ns; +TIMESPEC TS_DataIsrds_DataFfs2B = FROM "AdcData_Isrds2B" TO "AdcData_Ffs2B" 2.2 ns; +TIMESPEC TS_DataIsrds_DataFfs3A = FROM "AdcData_Isrds3A" TO "AdcData_Ffs3A" 2.2 ns; +TIMESPEC TS_DataIsrds_DataFfs3B = FROM "AdcData_Isrds3B" TO "AdcData_Ffs3B" 2.2 ns; +TIMESPEC TS_DataIsrds_DataFfs4A = FROM "AdcData_Isrds4A" TO "AdcData_Ffs4A" 2.2 ns; +TIMESPEC TS_DataIsrds_DataFfs4B = FROM "AdcData_Isrds4B" TO "AdcData_Ffs4B" 2.2 ns; + + +NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" TNM_NET = "IntClkDiv1"; +NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" TNM_NET = "IntClkDiv2"; +NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" TNM_NET = "IntClkDiv3"; +NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" TNM_NET = "IntClkDiv4"; +NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" TNM_NET = "IntClkDiv5"; +NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" TNM_NET = "IntClkDiv6"; +NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" TNM_NET = "IntClkDiv7"; +NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" TNM_NET = "IntClkDiv8"; + +NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk" TNM_NET = "IntClk1"; +NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk" TNM_NET = "IntClk2"; +NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk" TNM_NET = "IntClk3"; +NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk" TNM_NET = "IntClk4"; +NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk" TNM_NET = "IntClk5"; +NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk" TNM_NET = "IntClk6"; +NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk" TNM_NET = "IntClk7"; +NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk" TNM_NET = "IntClk8"; + + +TIMESPEC TS_IntClkDiv_IntClk1 = FROM "IntClkDiv1" TO "IntClk1" 2 ns; +TIMESPEC TS_IntClkDiv_IntClk2 = FROM "IntClkDiv2" TO "IntClk2" 2 ns; +TIMESPEC TS_IntClkDiv_IntClk3 = FROM "IntClkDiv3" TO "IntClk3" 2 ns; +TIMESPEC TS_IntClkDiv_IntClk4 = FROM "IntClkDiv4" TO "IntClk4" 2 ns; +TIMESPEC TS_IntClkDiv_IntClk5 = FROM "IntClkDiv5" TO "IntClk5" 2 ns; +TIMESPEC TS_IntClkDiv_IntClk6 = FROM "IntClkDiv6" TO "IntClk6" 2 ns; +TIMESPEC TS_IntClkDiv_IntClk7 = FROM "IntClkDiv7" TO "IntClk7" 2 ns; +TIMESPEC TS_IntClkDiv_IntClk8 = FROM "IntClkDiv8" TO "IntClk8" 2 ns; + +#TIMESPEC TS_IntClk_IntClkDiv1 = FROM "IntClk1" TO "IntClkDiv1" 2 ns; +#TIMESPEC TS_IntClk_IntClkDiv2 = FROM "IntClk2" TO "IntClkDiv2" 2 ns; +#TIMESPEC TS_IntClk_IntClkDiv3 = FROM "IntClk3" TO "IntClkDiv3" 2 ns; +#TIMESPEC TS_IntClk_IntClkDiv4 = FROM "IntClk4" TO "IntClkDiv4" 2 ns; +#TIMESPEC TS_IntClk_IntClkDiv5 = FROM "IntClk5" TO "IntClkDiv5" 2 ns; +#TIMESPEC TS_IntClk_IntClkDiv6 = FROM "IntClk6" TO "IntClkDiv6" 2 ns; +#TIMESPEC TS_IntClk_IntClkDiv7 = FROM "IntClk7" TO "IntClkDiv7" 2 ns; +#TIMESPEC TS_IntClk_IntClkDiv8 = FROM "IntClk8" TO "IntClkDiv8" 2 ns; + + +############################################################################################### + +#TIMESPEC TS_Data_ADCclk1A = FROM "AdcData_Ffs1A" TO "ADC_clk_S" 1 ns; +#TIMESPEC TS_Data_ADCclk2A = FROM "AdcData_Ffs2A" TO "ADC_clk_S" 1 ns; +#TIMESPEC TS_Data_ADCclk2B = FROM "AdcData_Ffs2B" TO "ADC_clk_S 1 ns; +#TIMESPEC TS_Data_ADCclk3A = FROM "AdcData_Ffs3A" TO "ADC_clk_S" 1 ns; +#TIMESPEC TS_Data_ADCclk3B = FROM "AdcData_Ffs3B" TO "ADC_clk_S" 1 ns; +#TIMESPEC TS_Data_ADCclk4A = FROM "AdcData_Ffs4A" TO "ADC_clk_S" 1 ns; +#TIMESPEC TS_Data_ADCclk4B = FROM "AdcData_Ffs4B" TO "ADC_clk_S" 1 ns; + + +# sys_clk not +NET "SYS_CLK" CLOCK_DEDICATED_ROUTE = BACKBONE; +PIN "clockmodule100Mto80Ma/mmcm_adv_inst.CLKIN1" CLOCK_DEDICATED_ROUTE = BACKBONE; diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_SODAfrequencydiv5.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_SODAfrequencydiv5.vhd new file mode 100644 index 0000000..16a0c4c --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_SODAfrequencydiv5.vhd @@ -0,0 +1,190 @@ +---------------------------------------------------------------------------------- +-- Company: KVI/RUG/Groningen University +-- Engineer: Peter Schakel +-- Create Date: 18-11-2014 +-- Module Name: FEE_SODAfrequencydiv5 +-- Description: Converts 200MHz from GTX to 40 MHz SODA +-- Modifications: +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all ; +USE ieee.std_logic_arith.all ; +library UNISIM; +use UNISIM.VComponents.all; + +---------------------------------------------------------------------------------- +-- FEE_SODAfrequencydiv5 +-- Measures the number of pulses in one second +-- +-- Library +-- +-- Generics: +-- +-- Inputs: +-- clock : recovered clock +-- data : data from GTX +-- kchar : k-character signal from GTX +-- +-- Outputs: +-- clockdiv5 : input clock divided by 5 and synchronous to SODA +-- error : error in incoming data or phase +-- +-- Components: +-- +---------------------------------------------------------------------------------- + +entity FEE_SODAfrequencydiv5 is + port ( + clock : in std_logic; + data : in std_logic_vector(7 downto 0); + kchar : in std_logic; + clockdiv5 : out std_logic; + error : out std_logic + ); +end FEE_SODAfrequencydiv5; + +architecture Behavioral of FEE_SODAfrequencydiv5 is +constant KCHARSODA : std_logic_vector(7 downto 0) := x"DC"; + +signal clockdiv5_S : std_logic; +signal div5count0_S : std_logic; +signal clock5div2_S : std_logic := '0'; +signal prev_clock5div2_S : std_logic := '0'; +signal clockdiv5_reset_S : std_logic; +signal SODA_kchar_S : std_logic; +signal disable_SODAcheck_S : std_logic := '0'; +signal disable_clock5check_S : std_logic := '0'; +signal SODA40_signal_S : std_logic; +signal div5count_S : std_logic_vector(2 downto 0) := (others => '0'); +signal SODA_count_S : std_logic_vector(3 downto 0) := (others => '0'); +signal SODAerror_S : std_logic; +signal clockdiv5error_S : std_logic; +signal clockbiterror_S : std_logic; + +begin + +error <= '1' when (SODAerror_S='1') or (clockdiv5error_S='1') or (clockbiterror_S='1') else '0'; +--clockdiv5 <= clockdiv5_S; +clockdiv5buf : BUFG + port map ( + I => clockdiv5_S, + O => clockdiv5); + +rxrecclk_bufrdiv5_i : BUFR + generic map ( BUFR_DIVIDE => "5" ) + port map ( + CE => '1', + CLR => clockdiv5_reset_S, + I => clock, + O => clockdiv5_S); + +process_checkSODA: process(clock) +variable disable_count_V : std_logic_vector(1 downto 0) := (others => '0'); +begin + if (rising_edge(clock)) then + div5count0_S <= '0'; + clockbiterror_S <= '0'; + if div5count_S/="100" then + if (disable_SODAcheck_S='0') and (SODA40_signal_S='1') then -- wrong phase + div5count_S <= "000"; + disable_SODAcheck_S <= '1'; + disable_count_V := (others => '0'); + clockbiterror_S <= '1'; + else + div5count_S <= div5count_S+1; + end if; + else + div5count_S <= "000"; + div5count0_S <= '1'; + if disable_count_V(disable_count_V'left)='0' then + disable_count_V := disable_count_V+1; + else + disable_SODAcheck_S <= '0'; + end if; + end if; + prev_clock5div2_S <= clock5div2_S; + end if; +end process; + + + +process_checkdiv5: process(clock) +variable disable_count_V : std_logic_vector(3 downto 0) := (others => '0'); +begin + if (rising_edge(clock)) then + clockdiv5_reset_S <= '0'; + clockdiv5error_S <= '0'; + if (disable_SODAcheck_S='0') and (disable_clock5check_S='0') then + if (clock5div2_S/=prev_clock5div2_S) and div5count0_S='0' then -- div5 clock wrong phase : reset + clockdiv5_reset_S <= '1'; + disable_clock5check_S <= '1'; + disable_count_V := (others => '0'); + clockdiv5error_S <= '1'; + end if; + else + if disable_count_V(disable_count_V'left)='0' then + disable_count_V := disable_count_V+1; + else + disable_clock5check_S <= '0'; + end if; + end if; + end if; +end process; + +process_SODAchar: process(clock) +variable count_V : std_logic_vector(2 downto 0) := (others => '0'); +variable count_rotate_V : std_logic_vector(2 downto 0) := (others => '0'); +begin + if (rising_edge(clock)) then + if (kchar='1') and (data=KCHARSODA) then + SODA_kchar_S <= '1'; + else + SODA_kchar_S <= '0'; + end if; + end if; +end process; + +process_SODAstart: process(clock) +variable count_V : std_logic_vector(2 downto 0) := (others => '0'); +variable count_rotate_V : std_logic_vector(2 downto 0) := (others => '0'); +begin + if (rising_edge(clock)) then + SODA40_signal_S <= '0'; + SODAerror_S <= '0'; + if (SODA_count_S="0000") and (SODA_kchar_S='1') then + SODA40_signal_S <= '1'; + SODA_count_S <= SODA_count_S+1; + elsif SODA_count_S(0)='1' then -- SODA data + if SODA_kchar_S='1' then -- error + SODA_count_S <= "0000"; + SODAerror_S <= '1'; + else + SODA_count_S <= SODA_count_S+1; + end if; + elsif (SODA_count_S(2 downto 1)/="00") then -- SODA k-char + if SODA_kchar_S='0' then -- error + SODA_count_S <= "0000"; + SODAerror_S <= '1'; + else + SODA_count_S <= SODA_count_S+1; + end if; + elsif (SODA_count_S(3)='1') then -- end SODA packet + SODA_count_S <= "0000"; + if SODA_kchar_S='1' then -- error + SODAerror_S <= '1'; + end if; + end if; + end if; +end process; + +process_clock5div2: process(clockdiv5_S) +begin + if (rising_edge(clockdiv5_S)) then + clock5div2_S <= not clock5div2_S; + end if; +end process; + + +end Behavioral; diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_data16to8.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_data16to8.vhd new file mode 100644 index 0000000..f211884 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_data16to8.vhd @@ -0,0 +1,109 @@ +---------------------------------------------------------------------------------- +-- Company: KVI/RUG/Groningen University +-- Engineer: Peter Schakel +-- Create Date: 04-02-2015 +-- Module Name: FEE_data16to8 +-- Description: Converts 16 bits data at 100MHz to 8 bits data at 200MHz +-- Modifications: +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all ; +USE ieee.std_logic_arith.all ; +library UNISIM; +use UNISIM.VComponents.all; + +---------------------------------------------------------------------------------- +-- FEE_data16to8 +-- Converts 16 bits data at 100MHz to 8 bits data at 200MHz +-- +-- Library +-- +-- Generics: +-- +-- Inputs: +-- clock_in : input clock at single +-- data_in : 16 bits input data +-- kchar_in : corresponding k-character (one for each input byte) +-- +-- Outputs: +-- clock_out : output clock at double speed +-- data_out : 8 bits output data at double speed +-- kchar_out : corresponding k-character +-- +-- Components: +-- clock100to200 : clock doubler : 100MHz -> 200MHz +-- +---------------------------------------------------------------------------------- + +entity FEE_data16to8 is + port ( + clock_in : in std_logic; + data_in : in std_logic_vector(15 downto 0); + kchar_in : in std_logic_vector(1 downto 0); + notintable_in : in std_logic_vector(1 downto 0); + clock_out : out std_logic; + data_out : out std_logic_vector(7 downto 0); + kchar_out : out std_logic; + notintable_out : out std_logic + ); +end FEE_data16to8; + +architecture Behavioral of FEE_data16to8 is + +component clock100to200 is + port + ( + clk_in1 : in std_logic; + clk_out1 : out std_logic; + clk_out2 : out std_logic + ); +end component; + +signal clock_out_S : std_logic; +signal phase_S : std_logic; +signal kchar_in_S : std_logic_vector(1 downto 0); + +begin + +clock100to200_1: clock100to200 port map( + clk_in1 => clock_in, + clk_out1 => open, + clk_out2 => clock_out_S); +clock_out <= clock_out_S; + +process(clock_out_S) +begin + if (rising_edge(clock_out_S)) then + kchar_in_S <= kchar_in; + end if; +end process; + +process(clock_out_S) +begin + if (rising_edge(clock_out_S)) then + if kchar_in_S/=kchar_in then + phase_S <= '0'; + else + phase_S <= not phase_S; + end if; + end if; +end process; + +process(clock_out_S) +begin + if (rising_edge(clock_out_S)) then + if phase_S='1' then + data_out <= data_in(7 downto 0); + kchar_out <= kchar_in(0); + notintable_out <= notintable_in(0); + else + data_out <= data_in(15 downto 8); + kchar_out <= kchar_in(1); + notintable_out <= notintable_in(1); + end if; + end if; +end process; + +end Behavioral; diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_data8to16.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_data8to16.vhd new file mode 100644 index 0000000..9322aa2 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_data8to16.vhd @@ -0,0 +1,100 @@ +---------------------------------------------------------------------------------- +-- Company: KVI/RUG/Groningen University +-- Engineer: Peter Schakel +-- Create Date: 06-02-2015 +-- Module Name: FEE_data8to16 +-- Description: Converts 8 bits data at 200MHz to 16 bits data at 100MHz +-- Modifications: +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all ; +USE ieee.std_logic_arith.all ; +library UNISIM; +use UNISIM.VComponents.all; + +---------------------------------------------------------------------------------- +-- FEE_data8to16 +-- Converts 8 bits data at 200MHz to 16 bits data at 100MHz +-- +-- Library +-- +-- Generics: +-- +-- Inputs: +-- clock_in : input clock +-- data_in : 8 bits input data +-- kchar_in : corresponding k-character +-- +-- Outputs: +-- clock_out : output clock at half speed +-- data_out : 16 bits output data at half speed +-- kchar_out : corresponding k-character (one for each byte) +-- +-- Components: +-- clock100to200 : clock doubler : 100MHz -> 200MHz +-- +---------------------------------------------------------------------------------- + +entity FEE_data8to16 is + port ( + clock_in : in std_logic; + data_in : in std_logic_vector(7 downto 0); + kchar_in : in std_logic; + clock_out : in std_logic; + data_out : out std_logic_vector(15 downto 0); + kchar_out : out std_logic_vector(1 downto 0) + ); +end FEE_data8to16; + +architecture Behavioral of FEE_data8to16 is + +component clock100to200 is + port + ( + clk_in1 : in std_logic; + clk_out1 : out std_logic; + clk_out2 : out std_logic + ); +end component; + +signal clock_in_S : std_logic; +signal data_in0_S : std_logic_vector(7 downto 0); +signal kchar_in0_S : std_logic; +signal data_in1_S : std_logic_vector(7 downto 0); +signal kchar_in1_S : std_logic; +signal data_out_S : std_logic_vector(15 downto 0); +signal kchar_out_S : std_logic_vector(1 downto 0); + +begin + +--clock100to200_1: clock100to200 port map( +-- clk_in1 => clock_out, +-- clk_out1 => open, +-- clk_out2 => clock_in_S); +--clock_in <= clock_in_S; +clock_in_S <= clock_in; + + +process(clock_in_S) +begin + if (rising_edge(clock_in_S)) then + data_in0_S <= data_in; + kchar_in0_S <= kchar_in; + data_in1_S <= data_in0_S; + kchar_in1_S <= kchar_in0_S; + end if; +end process; + +process(clock_out) +begin + if (rising_edge(clock_out)) then + data_out_S <= data_in0_S & data_in1_S; + kchar_out_S <= kchar_in0_S & kchar_in1_S; + data_out <= data_out_S; + kchar_out <= kchar_out_S; + end if; +end process; + +end Behavioral; diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_gtxModule.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_gtxModule.vhd new file mode 100644 index 0000000..12ece92 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_gtxModule.vhd @@ -0,0 +1,413 @@ +---------------------------------------------------------------------------------- +-- Company: KVI/RUG/Groningen University +-- Engineer: Peter Schakel +-- Create Date: 26-08-2013 +-- Module Name: FEE_gtxModule +-- Description: GTP/GTX/serdes tranceiver for PANDA Front End Electronics with clock synchronization +-- Modifications: +-- 19-11-2014 Name changed from gtpBufLayerFee to FEE_gtxModule +-- 07-02-2015 Version for Kintex7 +-- 25-01-2017 First/last signals added +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +Library UNISIM; +use UNISIM.vcomponents.all; +library work; +use work.panda_package.all; + +---------------------------------------------------------------------------------- +-- FEE_gtxModule +-- GTP/GTX tranceiver for PANDA Front End Electronics and Multiplexer with clock synchronization: +-- +-- Receiver generates synchronous clock on incomming serial data (SODA) and detects synchronous +-- data packages (SODA-commands) with fixed delay. +-- Receives also asynchronous data from fibre and outputs it as 32 bits. +-- SODA packages use the DLM i/o. Data is send along with K27.7 character (0xFB) +-- Idle's consists of K28.1 & K28.5 characters (0x3c,0xBC) +-- All other valid (non K) characters is treated as data and combined to 32-bits +-- +-- Transmitter sends data (asynchronous to SODA). The data is organised as 32-bits words. +-- If no data is available then idle's are sent (0x3CBC) +-- +-- Only one channel of the dual GTP or GTX is used. +-- +-- Library +-- work.gtpBufLayer : for GTP/GTX constants +-- +-- Generics: +-- +-- Inputs: +-- gtpClk_P,gtpClk_N : Reference clock for GTP/GTX, frequency must match expected SODA frequency (finally probably 155.52 MHz) +-- sysClk : stable clock (80MHz) +-- asyncclk : stable clock at different clock speed (not used) +-- reset : reset GTP/GTX +-- disable_GTX_reset : disable reset of GTX (during clock switching) +-- TX_DLM : transmit SODA character +-- TX_DLM_WORD : SODA character to be transmitted +-- rxAsyncClk : Clock for the asynchronous (32-bits) data (used for slow-control in FEE) +-- txAsyncData : asynchronous 32-bits data to be transmitted +-- txAsyncDataWrite : write signal for asynchronous 32-bits data to be transmitted +-- txAsyncFirstData : First asynchronous 32-bits word of the data packet to be transmitted +-- txAsyncLastData : Last asynchronous 32-bits word of the data packet to be transmitted, used for separating packets on the fiber +-- txAsyncClk : clock for the asynchronous 32-bits data to be transmitted +-- rxAsyncDataRead : read signal for the asynchronous data fifo +-- gtpRxP0,gtpRxN0 : differential GTP/GTX inputs +-- +-- Outputs: +-- RX_DLM : SODA character received +-- RX_DLM_WORD : SODA character +-- txAsyncFifoFull : fifo for 32-bits transmit data is full +-- txLocked : Transmitter PLL locked +-- rxAsyncData : asynchronous 32 bits data from the receiver fifo +-- rxError : invalid character or other receiver error +-- rxAsyncDataOverflow : overflow bit of the receiver asynchronous data fifo +-- rxAsyncDataPresent : Indicates if asynchronous data is available in the receiver fifo +-- rxSodaClk : Reconstructed clock, synchronous with original SODA clock but different frequency (200MHz) +-- rxSodaClk40 : Reconstructed SODA clock : 40MHz +-- rxLocked : Receiver locked +-- gtpTxP0,gtpTxN0 : differential transmit outputs of the GTP/GTX (not used at the moment) +-- +-- Components: +-- FEE_gtxWrapper_Kintex7 : module with the GTP/GTX interface +-- FEE_SODAfrequencydiv5 : make divide by 5 clock from recovered clock +-- FEE_fifo32to8_SODA : fifo for data to be transmitted, converts data from 32-bits to 16-bits +-- FEE_fifo8to32_SODA : fifo for received asynchronous data, converts data from 16-bits to 32-bits +-- sync_to_different_phase : synchronize to clock with same frequency but different phase +-- +---------------------------------------------------------------------------------- + +entity FEE_gtxModule is + Port ( + gtpClk_P : in std_logic; + gtpClk_N : in std_logic; + refclk_out : out std_logic; + sysClk : in std_logic; + asyncclk : in std_logic; + reset : in std_logic; + disable_GTX_reset : in std_logic; + + TX_DLM : in std_logic; + TX_DLM_WORD : in std_logic_vector(7 downto 0); + RX_DLM : out std_logic; + RX_DLM_WORD : out std_logic_vector(7 downto 0); + + txAsyncClk : in std_logic; + txAsyncData : in std_logic_vector(31 downto 0); + txAsyncDataWrite : in std_logic; + txAsyncFirstData : in std_logic; + txAsyncLastData : in std_logic; + txAsyncFifoFull : out std_logic; + txUsrClk : out std_logic; + txLocked : out std_logic; + + rxAsyncClk : in std_logic; + rxAsyncData : out std_logic_vector(31 downto 0); + rxAsyncFirstData : out std_logic; + rxAsyncLastData : out std_logic; + rxAsyncDataRead : in std_logic; + rxError : out std_logic; + rxAsyncDataOverflow : out std_logic; + rxAsyncDataPresent : out std_logic; + rxUsrClkdiv2 : out std_logic; + rxSodaClk : out std_logic; + rxSodaClk40 : out std_logic; + rxLocked : out std_logic; + + gtpTxP0 : out std_logic; + gtpTxN0 : out std_logic; + gtpRxP0 : in std_logic; + gtpRxN0 : in std_logic; + GT0_QPLLOUTCLK_IN : in std_logic; + GT0_QPLLOUTREFCLK_IN : in std_logic + ); +end FEE_gtxModule; + + +architecture Behavioral of FEE_gtxModule is + +component FEE_gtxWrapper_Kintex7 is + port ( + gtpClk_P : in std_logic; + gtpClk_N : in std_logic; + refclk_out : out std_logic; + sysClk : in std_logic; + gtpReset : in std_logic; + disable_GTX_reset : in std_logic; + + txData : in std_logic_vector (7 downto 0); + txCharIsK : in std_logic; + txP : out std_logic; + txN : out std_logic; + txUsrClk : out std_logic; + txLocked : out std_logic; + + rxData : out std_logic_vector (7 downto 0); + rxCharIsK : out std_logic; + rxNotInTable : out std_logic; + rxP : in std_logic; + rxN : in std_logic; + rxUsrClk : out std_logic; + rxUsrClkdiv2 : out std_logic; + rxLocked : out std_logic; + + resetDone : out std_logic; + GT0_QPLLOUTCLK_IN : in std_logic; + GT0_QPLLOUTREFCLK_IN : in std_logic + ); +end component; + +component FEE_SODAfrequencydiv5 is + port ( + clock : in std_logic; + data : in std_logic_vector(7 downto 0); + kchar : in std_logic; + clockdiv5 : out std_logic; + error : out std_logic + ); +end component; + +component FEE_fifo32to8_SODA is + port ( + write_clock : in std_logic; + read_clock : in std_logic; + reset : in std_logic; + data_in : in std_logic_vector(31 downto 0); + data_write : in std_logic; + full : out std_logic; + TX_DLM : in std_logic; + TX_DLM_WORD : in std_logic_vector(7 downto 0); + data_out : out std_logic_vector(7 downto 0); + char_is_k : out std_logic + ); +end component; + +component FEE_fifo8to32_SODA is + port ( + write_clock : in std_logic; + read_clock : in std_logic; + reset : in std_logic; + data_in : in std_logic_vector(7 downto 0); + char_is_k : in std_logic; + RX_DLM : out std_logic; + RX_DLM_WORD : out std_logic_vector(7 downto 0); + data_out : out std_logic_vector(31 downto 0); + data_read : in std_logic; + data_available : out std_logic; + overflow : out std_logic; + error : out std_logic + ); +end component; + +component sync_to_different_phase is + generic ( + WIDTH : natural := 18 + ); + port ( + clock1 : in std_logic; + clock2 : in std_logic; + data_in : in std_logic_vector(WIDTH-1 downto 0); + data_out : out std_logic_vector(WIDTH-1 downto 0) + ); +end component; + +component async_fifo_16x9 + port ( + rst : in std_logic; + wr_clk : in std_logic; + rd_clk : in std_logic; + din : in std_logic_vector(8 downto 0); + wr_en : in std_logic; + rd_en : in std_logic; + dout : out std_logic_vector(8 downto 0); + full : out std_logic; + empty : out std_logic); +end component; + +component asyncfifo is + generic ( + DATA_WIDTH : natural := 9; + ADDR_WIDTH : natural := 2 + ); + port ( + reset : in std_logic; + read_clock : in std_logic; + read_request : in std_logic; + data_in : in std_logic_vector(DATA_WIDTH-1 downto 0); + write_clock : in std_logic; + write_request : in std_logic; + data_out : out std_logic_vector(DATA_WIDTH-1 downto 0); + empty : out std_logic; + full : out std_logic; + valid : out std_logic + ); +end component; + +signal rxSodaClk40_S : std_logic := '0'; +signal rxNotInTable_S : std_logic := '0'; +signal rxLocked_S : std_logic := '0'; +signal txLocked_S : std_logic := '0'; +signal txreset_S : std_logic := '0'; +signal txCharIsK_S : std_logic := '0'; +signal txUsrClk_S : std_logic; +signal txData_S : std_logic_vector(7 downto 0); +signal rxCharIsK_S : std_logic; + +signal rxUsrClk_S : std_logic; +signal rxData_S : std_logic_vector(7 downto 0); +signal rxerror_s : std_logic; + +signal TX_DLM_S : std_logic; +signal TX_DLM_WORD_S : std_logic_vector(7 downto 0); +signal RX_DLM_S : std_logic; +signal RX_DLM_WORD_S : std_logic_vector(7 downto 0); + +signal fifo_dout_S : std_logic_vector(8 downto 0) := (others => '0'); +signal fifosync_write_S : std_logic; +signal fifosync_read_S : std_logic; +signal fifosync_empty_S : std_logic; +signal fifosync_full_S : std_logic; +signal fifosync_valid_S : std_logic; +signal rxphase_S : std_logic; +signal rxphaseError_S : std_logic; +signal rxAsyncData_S : std_logic_vector(31 downto 0); +signal rxAsyncDataRead_aftr1clk_S : std_logic; + +begin + +txUsrClk <= txUsrClk_S; +rxSodaClk <= rxUsrClk_S; +rxSodaClk40 <= rxSodaClk40_S; + +FEE_gtxWrapper_Kintex7_1 : FEE_gtxWrapper_Kintex7 + port map ( + gtpClk_P => gtpClk_P, + gtpClk_N => gtpClk_N, + refclk_out => refclk_out, + sysClk => sysClk, + gtpReset => reset, + disable_GTX_reset => disable_GTX_reset, + txData => txData_S, + txCharIsK => txCharIsK_S, + txP => gtpTxP0, + txN => gtpTxN0, + txUsrClk => txUsrClk_S, + txLocked => txLocked_S, + rxData => rxData_S, + rxCharIsK => rxCharIsK_S, + rxNotInTable => rxNotInTable_S, + rxP => gtpRxP0, + rxN => gtpRxN0, + rxUsrClk => rxUsrClk_S, + rxUsrClkdiv2 => rxUsrClkdiv2, + rxLocked => rxLocked_S, + resetDone => open, + GT0_QPLLOUTCLK_IN => GT0_QPLLOUTCLK_IN, + GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK_IN + ); + +FEE_SODAfrequencydiv51: FEE_SODAfrequencydiv5 port map( + clock => rxUsrClk_S, + data => rxData_S, + kchar => rxCharIsK_S, + clockdiv5 => rxSodaClk40_S, + error => open + ); + +-- synchronise SODA signals to txUsrClk_S. same frequency, differe4nt phase ----------------- +txreset_S <= '1' when (txLocked_S='0') or (reset='1') or (rxLocked_S='0') else '0'; +fifosync: async_fifo_16x9 port map( + rst => txreset_S, + wr_clk => rxUsrClk_S, + rd_clk => txUsrClk_S, + din(7 downto 0) => TX_DLM_WORD, + din(8) => TX_DLM, + wr_en => fifosync_write_S, + rd_en => fifosync_read_S, + dout => fifo_dout_S, + full => fifosync_full_S, + empty => fifosync_empty_S); +--fifosync: asyncfifo +-- generic map( +-- DATA_WIDTH => 9, +-- ADDR_WIDTH => 2 +-- ) +-- port map( +-- reset => txreset_S, +-- read_clock => txUsrClk_S, +-- read_request => fifosync_read_S, +-- data_in(7 downto 0) => TX_DLM_WORD, +-- data_in(8) => TX_DLM, +-- write_clock => rxUsrClk_S, +-- write_request => fifosync_write_S, +-- data_out => fifo_dout_S, +-- empty => fifosync_empty_S, +-- full => fifosync_full_S, +-- valid => fifosync_valid_S); +fifosync_read_S <= '1'; -- when fifosync_empty_S='0' else '0'; +fifosync_write_S <= '1' when fifosync_full_S='0' else '0'; + +TX_DLM_WORD_S <= fifo_dout_S(7 downto 0); +TX_DLM_S <= fifo_dout_S(8); -- when fifosync_valid_S='1' else '0'; + +FEE_fifo32to8_SODA1: FEE_fifo32to8_SODA port map( + write_clock => txAsyncClk, + read_clock => txUsrClk_S, + reset => '0', -- reset, + data_in => txAsyncData, + data_write => txAsyncDataWrite, + full => txAsyncFifoFull, + TX_DLM => TX_DLM_S, + TX_DLM_WORD => TX_DLM_WORD_S, + data_out => txData_S, + char_is_k => txCharIsK_S + ); + +FEE_fifo8to32_SODA1: FEE_fifo8to32_SODA port map( + write_clock => rxUsrClk_S, + read_clock => rxAsyncClk, + reset => '0', -- reset, + data_in => rxData_S, + char_is_k => rxCharIsK_S, + RX_DLM => RX_DLM_S, + RX_DLM_WORD => RX_DLM_WORD_S, + data_out => rxAsyncData_S, + data_read => rxAsyncDataRead, + data_available => rxAsyncDataPresent, + overflow => rxAsyncDataOverflow, + error => rxerror_S); +rxAsyncData <= rxAsyncData_S; +rxAsyncFirstData <= '1' when (rxAsyncDataRead_aftr1clk_S='1') and (rxphase_S='0') else '0'; +rxAsyncLastData <= '1' when (rxAsyncDataRead_aftr1clk_S='1') and (rxphase_S='1') else '0'; +process(rxAsyncClk) +begin + if (rising_edge(rxAsyncClk)) then + rxphaseError_S <= '0'; + if (rxAsyncDataRead_aftr1clk_S='1') then + if rxphase_S='0' then + if rxAsyncData_S(31 downto 24)=x"5C" then + rxphase_S <= '1'; + else + rxphaseError_S <= '1'; + end if; + else + rxphase_S <= '0'; + end if; + end if; + rxAsyncDataRead_aftr1clk_S <= rxAsyncDataRead; + end if; +end process; + +RX_DLM <= RX_DLM_S; +RX_DLM_WORD <= RX_DLM_WORD_S; + +txLocked <= txLocked_S; -- 1 => OK +rxLocked <= rxLocked_S; -- 1 => OK +rxError <= rxNotInTable_S or rxerror_S or rxphaseError_S; -- '1' => error + + +end Behavioral; + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_gtxWrapper_Kintex7.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_gtxWrapper_Kintex7.vhd new file mode 100644 index 0000000..e60f83e --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_gtxWrapper_Kintex7.vhd @@ -0,0 +1,549 @@ +---------------------------------------------------------------------------------- +-- Company: KVI/RUG/Groningen University +-- Engineer: Peter Schakel +-- Create Date: 05-02-2015 +-- Module Name: FEE_gtxWrapper_Kintex7 +-- Description: GTP/GTX tranceiver for PANDA Front End Electronics on Kintex7 with clock synchronization +-- Modifications: +-- 05-02-2015 Originally FEE_gtxWrapper_Virtex6 +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.std_logic_arith.all; +library work; +use work.panda_package.all; +library UNISIM; +use UNISIM.VComponents.all; + +---------------------------------------------------------------------------------- +-- FEE_gtxWrapper_Kintex7 +-- GTP/GTX tranceiver for PANDA Front End Electronics and Multiplexer with clock synchronization on a Virtex5. +-- +-- Receiver makes recovered synchronous clock on incomming serial data (SODA). +-- Data is 16-bits, synchronous to recovered clock. +-- Transmitter sends 16-bits data. +-- +-- Only one channel of the dual GTP or GTX is used. +-- +-- Library +-- work.gtpBufLayer : for GTP/GTX constants +-- +-- Generics: +-- +-- Inputs: +-- gtpClk_P,gtpClk_N : Reference clock for GTP/GTX, frequency must match expected SODA frequency +-- sysClk : stable clock (80MHz) +-- gtpReset : reset GTP/GTX +-- disable_GTX_reset : disable ressetting temporarely +-- txData : 16-bits input data to transmit +-- txCharIsK : data to transmit are K-characters +-- rxP,rxN : differential transmit inputs from the GTP/GTX +-- +-- Outputs: +-- txP,txN : differential transmit outputs of the GTP/GTX +-- txUsrClk : clock for transmit data +-- txLocked : transmitter locked +-- rxData : 16-bits received data +-- rxCharIsK : received 16-bits data (2 bytes) are K-characters +-- rxNotInTable : receiver data not valid +-- rxUsrClk : Recovered synchronous clock +-- rxLocked : receiver locked to incomming data +-- resetDone : resetting ready +-- +-- Components: +-- GTXVIRTEX5FEE : Xilinx module for GTP or GTX, generated with the IP core generator with a few adjustments +-- FEE_rxBitLock : Module for checking and resetting the GTP/GTX to lock the receiver clock at the right phase +-- Clock_62M5_doubler : Clock doubler with PLL +-- +---------------------------------------------------------------------------------- + +entity FEE_gtxWrapper_Kintex7 is + port ( + gtpClk_P : in std_logic; + gtpClk_N : in std_logic; + refclk_out : out std_logic; + sysClk : in std_logic; + gtpReset : in std_logic; + disable_GTX_reset : in std_logic; + + txData : in std_logic_vector (7 downto 0); + txCharIsK : in std_logic; + txP : out std_logic; + txN : out std_logic; + txUsrClk : out std_logic; + txLocked : out std_logic; + + rxData : out std_logic_vector (7 downto 0); + rxCharIsK : out std_logic; + rxNotInTable : out std_logic; + rxP : in std_logic; + rxN : in std_logic; + rxUsrClk : out std_logic; + rxUsrClkdiv2 : out std_logic; + rxLocked : out std_logic; + + resetDone : out std_logic; + GT0_QPLLOUTCLK_IN : in std_logic; + GT0_QPLLOUTREFCLK_IN : in std_logic + ); +end FEE_gtxWrapper_Kintex7; + +architecture Behavioral of FEE_gtxWrapper_Kintex7 is + +component gtxKintex7FEE80_support is +generic +( + EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model + STABLE_CLOCK_PERIOD : integer := 12 + +); +port +( + SOFT_RESET_TX_IN : in std_logic; + SOFT_RESET_RX_IN : in std_logic; + DONT_RESET_ON_DATA_ERROR_IN : in std_logic; + Q0_CLK0_GTREFCLK_PAD_N_IN : in std_logic; + Q0_CLK0_GTREFCLK_PAD_P_IN : in std_logic; + + GT0_TX_FSM_RESET_DONE_OUT : out std_logic; + GT0_RX_FSM_RESET_DONE_OUT : out std_logic; + GT0_DATA_VALID_IN : in std_logic; + GT0_TX_MMCM_LOCK_OUT : out std_logic; + + GT0_TXUSRCLK_OUT : out std_logic; + GT0_TXUSRCLK2_OUT : out std_logic; + GT0_TXUSRCLKX2_OUT : out std_logic; --// Modified + GT0_RXUSRCLK_OUT : out std_logic; + GT0_RXUSRCLK2_OUT : out std_logic; + + --_________________________________________________________________________ + --GT0 (X1Y0) + --____________________________CHANNEL PORTS________________________________ + --------------------------------- CPLL Ports ------------------------------- + gt0_cpllfbclklost_out : out std_logic; + gt0_cplllock_out : out std_logic; + gt0_cpllreset_in : in std_logic; + ---------------------------- Channel - DRP Ports -------------------------- + gt0_drpaddr_in : in std_logic_vector(8 downto 0); + gt0_drpdi_in : in std_logic_vector(15 downto 0); + gt0_drpdo_out : out std_logic_vector(15 downto 0); + gt0_drpen_in : in std_logic; + gt0_drprdy_out : out std_logic; + gt0_drpwe_in : in std_logic; + --------------------------- Digital Monitor Ports -------------------------- + gt0_dmonitorout_out : out std_logic_vector(7 downto 0); + --------------------- RX Initialization and Reset Ports -------------------- + gt0_eyescanreset_in : in std_logic; + gt0_rxuserrdy_in : in std_logic; + -------------------------- RX Margin Analysis Ports ------------------------ + gt0_eyescandataerror_out : out std_logic; + gt0_eyescantrigger_in : in std_logic; + ------------------------- Receive Ports - CDR Ports ------------------------ + GT0_RXCDRRESET_IN : in std_logic; --// Modified + GT0_RXCDRLOCK_OUT : out std_logic; --// Modified + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + gt0_rxdata_out : out std_logic_vector(15 downto 0); + ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- + gt0_rxdisperr_out : out std_logic_vector(1 downto 0); + gt0_rxnotintable_out : out std_logic_vector(1 downto 0); + --------------------------- Receive Ports - RX AFE ------------------------- + gt0_gtxrxp_in : in std_logic; + ------------------------ Receive Ports - RX AFE Ports ---------------------- + gt0_gtxrxn_in : in std_logic; + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + gt0_rxphmonitor_out : out std_logic_vector(4 downto 0); + gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0); + --------------------- Receive Ports - RX Equalizer Ports ------------------- + gt0_rxdfelpmreset_in : in std_logic; + gt0_rxmonitorout_out : out std_logic_vector(6 downto 0); + gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0); + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + gt0_gtrxreset_in : in std_logic; + gt0_rxpmareset_in : in std_logic; + ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- + gt0_rxcharisk_out : out std_logic_vector(1 downto 0); + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + gt0_rxresetdone_out : out std_logic; + --------------------- TX Initialization and Reset Ports -------------------- + gt0_gttxreset_in : in std_logic; + gt0_txuserrdy_in : in std_logic; + ------------------ Transmit Ports - TX Data Path interface ----------------- + gt0_txdata_in : in std_logic_vector(15 downto 0); + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + gt0_gtxtxn_out : out std_logic; + gt0_gtxtxp_out : out std_logic; + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + gt0_txoutclkfabric_out : out std_logic; + gt0_txoutclkpcs_out : out std_logic; + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + gt0_txcharisk_in : in std_logic_vector(1 downto 0); + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + gt0_txresetdone_out : out std_logic; + + --____________________________COMMON PORTS________________________________ + GT0_QPLLOUTCLK_IN : in std_logic; + GT0_QPLLOUTREFCLK_IN : in std_logic; + sysclk_in : in std_logic; + refclk_out : out std_logic --// Modified + +); + +end component; + +component FEE_rxBitLock is + port ( + clk : in std_logic; + reset : in std_logic; + resetDone : in std_logic; + lossOfSync : in std_logic; + rxPllLocked : in std_logic; + rxReset : out std_logic; + fsmStatus : out std_logic_vector (1 downto 0) + ); +end component; + +component FEE_data8to16 is + port ( + clock_in : in std_logic; + data_in : in std_logic_vector(7 downto 0); + kchar_in : in std_logic; + clock_out : in std_logic; + data_out : out std_logic_vector(15 downto 0); + kchar_out : out std_logic_vector(1 downto 0) + ); +end component; + +component FEE_data16to8 is + port ( + clock_in : in std_logic; + data_in : in std_logic_vector(15 downto 0); + kchar_in : in std_logic_vector(1 downto 0); + notintable_in : in std_logic_vector(1 downto 0); + clock_out : out std_logic; + data_out : out std_logic_vector(7 downto 0); + kchar_out : out std_logic; + notintable_out : out std_logic + ); +end component; + +component posedge_to_pulse is + port ( + clock_in : in std_logic; + clock_out : in std_logic; + en_clk : in std_logic; + signal_in : in std_logic; + pulse : out std_logic + ); +end component; + + +signal gtpReset_S : std_logic; +signal txResetdone_S : std_logic; +signal pllLkDet_S : std_logic :='0'; +signal rxResetDone_S : std_logic :='0'; +signal rxResetDone_sysclk_S: std_logic; +signal ff_txfullclk : std_logic; -- tx clock at double tx speed +signal ff_rxhalfclk : std_logic; +signal ff_txhalfclk : std_logic; + +signal txData16_S : std_logic_vector(15 downto 0); +signal txCharIsK16_S : std_logic_vector(1 downto 0); + +signal rxReset_S : std_logic :='0'; +signal rxData_S : std_logic_vector(7 downto 0); +signal rxCharIsK_S : std_logic; +signal rxNotInTable_S : std_logic; +signal rxData16_S : std_logic_vector(15 downto 0); +signal rxCharIsK16_S : std_logic_vector(1 downto 0); +signal rxNotInTable16_S : std_logic_vector(1 downto 0); +signal rxDispError16_S : std_logic_vector(1 downto 0); +signal rxLocked0_S : std_logic; +signal rxLocked1_S : std_logic; +signal rxLocked2_S : std_logic; +signal rxLossOfSync1_S : std_logic; +signal rxResetBitLock_S : std_logic :='0'; +signal sync_rxResetBitLock_S : std_logic :='0'; +signal prev_rxResetBitLock_S : std_logic :='0'; +signal fsmStatus_S : std_logic_vector(1 downto 0); +signal rxPLLwrapper_reset_S : std_logic :='0'; +signal rxResetBitLock_pulse_S : std_logic :='0'; + + +signal rxCDRlock_S : std_logic :='0'; +signal CDR_reset_S : std_logic :='0'; + +signal drpaddr_in_S : std_logic_vector(8 downto 0); +signal drpdi_in_S : std_logic_vector(15 downto 0); +signal drpdo_out_S : std_logic_vector(15 downto 0); +signal drpen_in_S : std_logic; +signal drprdy_out_S : std_logic; +signal drpwe_in_S : std_logic; + +signal comma_align_latency_S : std_logic_vector(6 downto 0); +signal comma_align_latency_valid_S : std_logic; + + +type drp_state_type is (initting, running, reading); +signal drp_state_S : drp_state_type := initting; + +-- attribute mark_debug : string; +-- attribute mark_debug of rxData16_S : signal is "true"; +-- attribute mark_debug of rxCharIsK16_S : signal is "true"; +-- attribute mark_debug of rxNotInTable16_S : signal is "true"; +-- attribute mark_debug of rxDispError16_S : signal is "true"; +-- attribute mark_debug of txData : signal is "true"; +-- attribute mark_debug of txCharIsK : signal is "true"; + +-- attribute mark_debug of gtpReset_S : signal is "true"; +-- attribute mark_debug of txResetdone_S : signal is "true"; +-- attribute mark_debug of rxResetDone_S : signal is "true"; +-- attribute mark_debug of pllLkDet_S : signal is "true"; +-- attribute mark_debug of rxReset_S : signal is "true"; +-- attribute mark_debug of rxLocked0_S : signal is "true"; +-- attribute mark_debug of rxLossOfSync1_S : signal is "true"; +-- attribute mark_debug of rxResetBitLock_S : signal is "true"; +-- attribute mark_debug of fsmStatus_S : signal is "true"; +-- attribute mark_debug of rxPLLwrapper_reset_S : signal is "true"; +-- attribute mark_debug of rxResetBitLock_pulse_S : signal is "true"; +-- attribute mark_debug of rxCDRlock_S : signal is "true"; +-- attribute mark_debug of CDR_reset_S : signal is "true"; +-- attribute mark_debug of disable_GTX_reset : signal is "true"; + + +begin + resetDone <= rxResetDone_sysclk_S; + rxLocked <= rxLocked2_S; + txLocked <= rxResetDone_sysclk_S; + rxUsrClkdiv2 <= ff_rxhalfclk; + txUsrClk <= ff_txfullclk; + +process(sysClk) +variable resetDone_V : std_logic; +begin + if rising_edge(sysClk) then + rxResetDone_sysclk_S <= resetDone_V; + resetDone_V := rxResetDone_S; + end if; +end process; + +FEE_data8to16_1: FEE_data8to16 + port map( + clock_in => ff_txfullclk, + data_in => txData, + kchar_in => txCharIsK, + clock_out => ff_txhalfclk, + data_out => txData16_S, + kchar_out => txCharIsK16_S + ); + +FEE_data16to8_1: FEE_data16to8 + port map( + clock_in => ff_rxhalfclk, + data_in => rxData16_S, + kchar_in => rxCharIsK16_S, + notintable_in => rxNotInTable16_S, + clock_out => rxUsrClk, + data_out => rxData_S, + kchar_out => rxCharIsK_S, + notintable_out => rxNotInTable_S + ); +rxData <= rxData_S; +rxCharIsK <= rxCharIsK_S; +rxNotInTable <= rxNotInTable_S; + +gtx_i : gtxKintex7FEE80_support + port map( + SOFT_RESET_TX_IN => gtpReset_S, + SOFT_RESET_RX_IN => gtpReset_S, + DONT_RESET_ON_DATA_ERROR_IN => '1', + Q0_CLK0_GTREFCLK_PAD_N_IN => gtpClk_N, + Q0_CLK0_GTREFCLK_PAD_P_IN => gtpClk_P, + + GT0_TX_FSM_RESET_DONE_OUT => open, + GT0_RX_FSM_RESET_DONE_OUT => open, + GT0_DATA_VALID_IN => '1', + GT0_TX_MMCM_LOCK_OUT => open, + + GT0_TXUSRCLK_OUT => open, + GT0_TXUSRCLK2_OUT => ff_txhalfclk, -- clock for tx_data (100MHz) + GT0_TXUSRCLKX2_OUT => ff_txfullclk, -- clock for 8 bits data (200MHz) + GT0_RXUSRCLK_OUT => open, + GT0_RXUSRCLK2_OUT => ff_rxhalfclk, -- clock for rx_data (100MHz) + --_________________________________________________________________________ + --GT0 (X1Y0) + --____________________________CHANNEL PORTS________________________________ + --------------------------------- CPLL Ports ------------------------------- + gt0_cpllfbclklost_out => open, + gt0_cplllock_out => pllLkDet_S, + gt0_cpllreset_in => '0', + ---------------------------- Channel - DRP Ports -------------------------- + gt0_drpaddr_in => drpaddr_in_S, + gt0_drpdi_in => drpdi_in_S, + gt0_drpdo_out => drpdo_out_S, + gt0_drpen_in => drpen_in_S, + gt0_drprdy_out => drprdy_out_S, + gt0_drpwe_in => drpwe_in_S, + --------------------------- Digital Monitor Ports -------------------------- + gt0_dmonitorout_out => open, + --------------------- RX Initialization and Reset Ports -------------------- + gt0_eyescanreset_in => '0', + gt0_rxuserrdy_in => '0', + -------------------------- RX Margin Analysis Ports ------------------------ + gt0_eyescandataerror_out => open, + gt0_eyescantrigger_in => '0', + ------------------------- Receive Ports - CDR Ports ------------------------ + GT0_RXCDRRESET_IN => CDR_reset_S, + GT0_RXCDRLOCK_OUT => rxCDRlock_S, + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + gt0_rxdata_out => rxData16_S, + ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- + gt0_rxdisperr_out => rxDispError16_S, + gt0_rxnotintable_out => rxNotInTable16_S, + --------------------------- Receive Ports - RX AFE ------------------------- + gt0_gtxrxp_in => rxP, + ------------------------ Receive Ports - RX AFE Ports ---------------------- + gt0_gtxrxn_in => rxN, + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + gt0_rxphmonitor_out => open, + gt0_rxphslipmonitor_out => open, + --------------------- Receive Ports - RX Equalizer Ports ------------------- + gt0_rxdfelpmreset_in => '0', + gt0_rxmonitorout_out => open, + gt0_rxmonitorsel_in => "00", + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + gt0_gtrxreset_in => rxReset_S, + gt0_rxpmareset_in => rxReset_S, + ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- + gt0_rxcharisk_out => rxCharIsK16_S, + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + gt0_rxresetdone_out => rxResetDone_S, + --------------------- TX Initialization and Reset Ports -------------------- + gt0_gttxreset_in => '0', + gt0_txuserrdy_in => '0', + ------------------ Transmit Ports - TX Data Path interface ----------------- + gt0_txdata_in => txData16_S, + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + gt0_gtxtxn_out => txN, + gt0_gtxtxp_out => txP, + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + gt0_txoutclkfabric_out => open, + gt0_txoutclkpcs_out => open, + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + gt0_txcharisk_in => txCharIsK16_S, + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + gt0_txresetdone_out => txResetdone_S, + --____________________________COMMON PORTS________________________________ + GT0_QPLLOUTCLK_IN => GT0_QPLLOUTCLK_IN, + GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK_IN, + sysclk_in => sysClk, + refclk_out => refclk_out --// Modified + ); + + +rxLossOfSync1_S <= '0' when (rxNotInTable16_S="00") or (disable_GTX_reset='1') else '1'; +FEE_rxBitLock1 : FEE_rxBitLock port map ( + clk => ff_rxhalfclk, + reset => gtpReset_S, + resetDone => rxResetDone_S, + lossOfSync => rxLossOfSync1_S, + rxPllLocked => PllLkDet_S, + rxReset => rxResetBitLock_S, + fsmStatus => fsmStatus_S + ); + + +process(sysClk,gtpReset) +variable counter_V : std_logic_vector(23 downto 0) := (others => '0'); +begin + if gtpReset='1' then + gtpReset_S <= '1'; + counter_V := (others => '0'); + elsif rising_edge(sysClk) then + gtpReset_S <= '0'; + if counter_V(counter_V'left)='1' then + if rxResetDone_S='0' then + counter_V := (others => '0'); + gtpReset_S <= '1'; + end if; + else + counter_V := counter_V+1; + end if; + end if; +end process; + +---- rxReset_S <= gtpReset; +rxReset_S <= '1' when ((rxPLLwrapper_reset_S='1') or (gtpReset_S='1') or (rxResetBitLock_pulse_S='1')) and (disable_GTX_reset='0') else '0'; +rxLocked0_S <= '1' when (rxResetDone_S='1') and (fsmStatus_S = "10") else '0'; + + +process(SYSCLK) +begin + if rising_edge(SYSCLK) then + if (sync_rxResetBitLock_S='1') and (prev_rxResetBitLock_S='0') then + rxResetBitLock_pulse_S <= '1'; + else + rxResetBitLock_pulse_S <= '0'; + end if; + sync_rxResetBitLock_S <= rxResetBitLock_S; + prev_rxResetBitLock_S <= sync_rxResetBitLock_S; + end if; +end process; + +process(sysClk) +variable counter_V : std_logic_vector(5 downto 0) := (others => '0'); +variable timoutcounter_V : std_logic_vector(7 downto 0) := (others => '0'); +begin + if rising_edge(sysClk) then + rxPLLwrapper_reset_S <= '0'; + CDR_reset_S <= '0'; + comma_align_latency_valid_S <= '0'; + drpen_in_S <= '0'; + drpwe_in_S <= '0'; + drpdi_in_S <= (others => '0'); + case drp_state_S is + when initting => + rxLocked2_S <= '0'; + counter_V := (others => '0'); + if rxResetDone_S='1' then + drp_state_S <= running; + end if; + when running => + if rxLocked1_S='0' then + drp_state_S <= initting; + else + if counter_V(counter_V'left) = '1' then + counter_V := (others => '0'); + timoutcounter_V := (others => '0'); + drpen_in_S <= '1'; + drpaddr_in_S <= "101001110"; -- x"14E"; + drp_state_S <= reading; + else + counter_V := counter_V+1; + end if; + end if; + when reading => + if drprdy_out_S='1' then + comma_align_latency_S <= drpdo_out_S(6 downto 0); -- COMMA_ALIGN_LATENCY + comma_align_latency_valid_S <= '1'; + if drpdo_out_S(6 downto 0)/="0000000" then + CDR_reset_S <= '1'; --// rxPLLwrapper_reset_S <= '1'; + rxLocked2_S <= '0'; + else + rxLocked2_S <= '1'; + end if; + drp_state_S <= running; + elsif timoutcounter_V(timoutcounter_V'left)='1' then + drp_state_S <= initting; + else + timoutcounter_V := timoutcounter_V+1; + end if; + when others => + drp_state_S <= initting; + end case; + rxLocked1_S <= rxLocked0_S; + end if; +end process; + + +end Behavioral; diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/gtx_common.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/gtx_common.vhd new file mode 100644 index 0000000..6e74759 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/gtx_common.vhd @@ -0,0 +1,251 @@ +--------------------------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 3.5 +-- \ \ Application : 7 Series FPGAs Transceivers Wizard +-- / / Filename : gtxkintex7fee80_common.vhd +-- /___/ /\ +-- \ \ / \ +-- \___\/\___\ +-- +-- +-- Module gtxKintex7FEE80_common +-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard +-- +-- +-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; + + + + +--***************************** Entity Declaration **************************** +entity gtx_common is +generic +( + -- Simulation attributes + WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "true" to speed up sim reset + SIM_QPLLREFCLK_SEL : bit_vector := "001" +); +port +( + QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0); + GTREFCLK1_IN : in std_logic; + GTREFCLK0_IN : in std_logic; + QPLLLOCK_OUT : out std_logic; + QPLLLOCKDETCLK_IN : in std_logic; + QPLLOUTCLK_OUT : out std_logic; + QPLLOUTREFCLK_OUT : out std_logic; + QPLLREFCLKLOST_OUT : out std_logic; + QPLLRESET_IN : in std_logic +); + +end gtx_common; + +architecture RTL of gtx_common is + + attribute CORE_GENERATION_INFO : string; + attribute CORE_GENERATION_INFO of RTL : architecture is "gtx_common,gtwizard_v3_5,{protocol_file=Start_from_scratch}"; + + + +--***********************************Parameter Declarations******************** + + constant DLY : time := 1 ns; + +--*************************Logic to set Attribute QPLL_FB_DIV***************************** + impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is + begin + if (qpllfbdiv_top = 16) then + return "0000100000"; + elsif (qpllfbdiv_top = 20) then + return "0000110000" ; + elsif (qpllfbdiv_top = 32) then + return "0001100000" ; + elsif (qpllfbdiv_top = 40) then + return "0010000000" ; + elsif (qpllfbdiv_top = 64) then + return "0011100000" ; + elsif (qpllfbdiv_top = 66) then + return "0101000000" ; + elsif (qpllfbdiv_top = 80) then + return "0100100000" ; + elsif (qpllfbdiv_top = 100) then + return "0101110000" ; + else + return "0000000000" ; + end if; + end function; + + impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is + begin + if (qpllfbdiv_top = 16) then + return '1'; + elsif (qpllfbdiv_top = 20) then + return '1' ; + elsif (qpllfbdiv_top = 32) then + return '1' ; + elsif (qpllfbdiv_top = 40) then + return '1' ; + elsif (qpllfbdiv_top = 64) then + return '1' ; + elsif (qpllfbdiv_top = 66) then + return '0' ; + elsif (qpllfbdiv_top = 80) then + return '1' ; + elsif (qpllfbdiv_top = 100) then + return '1' ; + else + return '1' ; + end if; + end function; + + constant QPLL_FBDIV_TOP : integer := 40; + constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP); + constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP); + + -- ground and tied_to_vcc_i signals + signal tied_to_ground_i : std_logic; + signal tied_to_ground_vec_i : std_logic_vector(63 downto 0); + signal tied_to_vcc_i : std_logic; + signal tied_to_vcc_vec_i : std_logic_vector(63 downto 0); + +begin + tied_to_ground_i <= '0'; + tied_to_ground_vec_i(63 downto 0) <= (others => '0'); + tied_to_vcc_i <= '1'; + tied_to_vcc_vec_i(63 downto 0) <= (others => '1'); + + --_________________________________________________________________________ + --_________________________________________________________________________ + --_________________________GTXE2_COMMON____________________________________ + + gtxe2_common_i : GTXE2_COMMON + generic map + ( + -- Simulation attributes + SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP, + SIM_QPLLREFCLK_SEL => (SIM_QPLLREFCLK_SEL), + SIM_VERSION => "4.0", + + + + ------------------COMMON BLOCK Attributes--------------- + BIAS_CFG => (x"0000040000001000"), + COMMON_CFG => (x"00000000"), + QPLL_CFG => (x"06801C1"), + QPLL_CLKOUT_CFG => ("0000"), + QPLL_COARSE_FREQ_OVRD => ("010000"), + QPLL_COARSE_FREQ_OVRD_EN => ('0'), + QPLL_CP => ("0000011111"), + QPLL_CP_MONITOR_EN => ('0'), + QPLL_DMONITOR_SEL => ('0'), + QPLL_FBDIV => (QPLL_FBDIV_IN), + QPLL_FBDIV_MONITOR_EN => ('0'), + QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO), + QPLL_INIT_CFG => (x"000006"), + QPLL_LOCK_CFG => (x"21E8"), + QPLL_LPF => ("1111"), + QPLL_REFCLK_DIV => (1) + + + ) + port map + ( + ------------- Common Block - Dynamic Reconfiguration Port (DRP) ----------- + DRPADDR => tied_to_ground_vec_i(7 downto 0), + DRPCLK => tied_to_ground_i, + DRPDI => tied_to_ground_vec_i(15 downto 0), + DRPDO => open, + DRPEN => tied_to_ground_i, + DRPRDY => open, + DRPWE => tied_to_ground_i, + ---------------------- Common Block - Ref Clock Ports --------------------- + GTGREFCLK => tied_to_ground_i, + GTNORTHREFCLK0 => tied_to_ground_i, + GTNORTHREFCLK1 => tied_to_ground_i, + GTREFCLK0 => GTREFCLK0_IN, + GTREFCLK1 => GTREFCLK1_IN, + GTSOUTHREFCLK0 => tied_to_ground_i, + GTSOUTHREFCLK1 => tied_to_ground_i, + ------------------------- Common Block - QPLL Ports ----------------------- + QPLLDMONITOR => open, + ----------------------- Common Block - Clocking Ports ---------------------- + QPLLOUTCLK => QPLLOUTCLK_OUT, + QPLLOUTREFCLK => QPLLOUTREFCLK_OUT, + REFCLKOUTMONITOR => open, + ------------------------- Common Block - QPLL Ports ------------------------ + QPLLFBCLKLOST => open, + QPLLLOCK => QPLLLOCK_OUT, + QPLLLOCKDETCLK => QPLLLOCKDETCLK_IN, + QPLLLOCKEN => tied_to_vcc_i, + QPLLOUTRESET => tied_to_ground_i, + QPLLPD => tied_to_vcc_i, + QPLLREFCLKLOST => QPLLREFCLKLOST_OUT, + QPLLREFCLKSEL => QPLLREFCLKSEL_IN, + QPLLRESET => QPLLRESET_IN, + QPLLRSVD1 => "0000000000000000", + QPLLRSVD2 => "11111", + --------------------------------- QPLL Ports ------------------------------- + BGBYPASSB => tied_to_vcc_i, + BGMONITORENB => tied_to_vcc_i, + BGPDB => tied_to_vcc_i, + BGRCALOVRD => "11111", + PMARSVD => "00000000", + RCALENB => tied_to_vcc_i + + ); + +end RTL; diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80.vhd new file mode 100644 index 0000000..a46be17 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80.vhd @@ -0,0 +1,584 @@ +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 2.6 +-- \ \ Application : 7 Series FPGAs Transceivers Wizard +-- / / Filename : gtxkintex7fee80.vhd +-- /___/ /\ +-- \ \ / \ +-- \___\/\___\ +-- +-- +-- Module gtxKintex7FEE80 (a GT Wrapper) +-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard +-- +-- +-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; + + +--***************************** Entity Declaration **************************** + +entity gtxKintex7FEE80 is +generic +( + QPLL_FBDIV_TOP : integer := 16; + + -- Simulation attributes + WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "true" to speed up sim reset + RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC"; + PMA_RSV_IN : bit_vector := x"00018480" + +); +port +( + --_________________________________________________________________________ + --_________________________________________________________________________ + --GT0 (X0Y0) + --____________________________CHANNEL PORTS________________________________ + --------------------------------- CPLL Ports ------------------------------- + GT0_CPLLFBCLKLOST_OUT : out std_logic; + GT0_CPLLLOCK_OUT : out std_logic; + GT0_CPLLLOCKDETCLK_IN : in std_logic; + GT0_CPLLREFCLKLOST_OUT : out std_logic; + GT0_CPLLRESET_IN : in std_logic; + -------------------------- Channel - Clocking Ports ------------------------ + GT0_GTREFCLK0_IN : in std_logic; + ---------------------------- Channel - DRP Ports -------------------------- + GT0_DRPADDR_IN : in std_logic_vector(8 downto 0); + GT0_DRPCLK_IN : in std_logic; + GT0_DRPDI_IN : in std_logic_vector(15 downto 0); + GT0_DRPDO_OUT : out std_logic_vector(15 downto 0); + GT0_DRPEN_IN : in std_logic; + GT0_DRPRDY_OUT : out std_logic; + GT0_DRPWE_IN : in std_logic; + --------------------- RX Initialization and Reset Ports -------------------- + GT0_RXUSERRDY_IN : in std_logic; + -------------------------- RX Margin Analysis Ports ------------------------ + GT0_EYESCANDATAERROR_OUT : out std_logic; + ------------------------- Receive Ports - CDR Ports ------------------------ + GT0_RXCDRRESET_IN : in std_logic; + GT0_RXCDRLOCK_OUT : out std_logic; + ------------------ Receive Ports - FPGA RX Interface Ports ----------------- + GT0_RXUSRCLK_IN : in std_logic; + GT0_RXUSRCLK2_IN : in std_logic; + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + GT0_RXDATA_OUT : out std_logic_vector(15 downto 0); + ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- + GT0_RXDISPERR_OUT : out std_logic_vector(1 downto 0); + GT0_RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0); + --------------------------- Receive Ports - RX AFE ------------------------- + GT0_GTXRXP_IN : in std_logic; + ------------------------ Receive Ports - RX AFE Ports ---------------------- + GT0_GTXRXN_IN : in std_logic; + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + GT0_RXDLYEN_IN : in std_logic; + GT0_RXDLYSRESET_IN : in std_logic; + GT0_RXDLYSRESETDONE_OUT : out std_logic; + GT0_RXPHALIGN_IN : in std_logic; + GT0_RXPHALIGNDONE_OUT : out std_logic; + GT0_RXPHALIGNEN_IN : in std_logic; + GT0_RXPHDLYRESET_IN : in std_logic; + GT0_RXPHMONITOR_OUT : out std_logic_vector(4 downto 0); + GT0_RXPHSLIPMONITOR_OUT : out std_logic_vector(4 downto 0); + -------------------- Receive Ports - RX Equailizer Ports ------------------- + GT0_RXLPMHFHOLD_IN : in std_logic; + GT0_RXLPMLFHOLD_IN : in std_logic; + --------------- Receive Ports - RX Fabric Output Control Ports ------------- + GT0_RXOUTCLK_OUT : out std_logic; + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + GT0_GTRXRESET_IN : in std_logic; + GT0_RXPCSRESET_IN : in std_logic; + GT0_RXPMARESET_IN : in std_logic; + ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- + GT0_RXCHARISK_OUT : out std_logic_vector(1 downto 0); + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + GT0_RXRESETDONE_OUT : out std_logic; + --------------------- TX Initialization and Reset Ports -------------------- + GT0_GTTXRESET_IN : in std_logic; + GT0_TXUSERRDY_IN : in std_logic; + ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- + GT0_TXUSRCLK_IN : in std_logic; + GT0_TXUSRCLK2_IN : in std_logic; + ------------------ Transmit Ports - TX Buffer Bypass Ports ----------------- + GT0_TXDLYEN_IN : in std_logic; + GT0_TXDLYSRESET_IN : in std_logic; + GT0_TXDLYSRESETDONE_OUT : out std_logic; + GT0_TXPHALIGN_IN : in std_logic; + GT0_TXPHALIGNDONE_OUT : out std_logic; + GT0_TXPHALIGNEN_IN : in std_logic; + GT0_TXPHDLYRESET_IN : in std_logic; + GT0_TXPHINIT_IN : in std_logic; + GT0_TXPHINITDONE_OUT : out std_logic; + ------------------ Transmit Ports - TX Data Path interface ----------------- + GT0_TXDATA_IN : in std_logic_vector(15 downto 0); + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + GT0_GTXTXN_OUT : out std_logic; + GT0_GTXTXP_OUT : out std_logic; + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + GT0_TXOUTCLK_OUT : out std_logic; + GT0_TXOUTCLKFABRIC_OUT : out std_logic; + GT0_TXOUTCLKPCS_OUT : out std_logic; + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + GT0_TXCHARISK_IN : in std_logic_vector(1 downto 0); + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + GT0_TXRESETDONE_OUT : out std_logic; + + + --____________________________COMMON PORTS________________________________ + ---------------------- Common Block - Ref Clock Ports --------------------- + GT0_GTREFCLK0_COMMON_IN : in std_logic; + ------------------------- Common Block - QPLL Ports ------------------------ + GT0_QPLLLOCK_OUT : out std_logic; + GT0_QPLLLOCKDETCLK_IN : in std_logic; + GT0_QPLLREFCLKLOST_OUT : out std_logic; + GT0_QPLLRESET_IN : in std_logic + + +); + + +end gtxKintex7FEE80; + +architecture RTL of gtxKintex7FEE80 is + + attribute CORE_GENERATION_INFO : string; + attribute CORE_GENERATION_INFO of RTL : architecture is "gtxKintex7FEE80,gtwizard_v2_6,{protocol_file=Start_from_scratch}"; + + +--***********************************Parameter Declarations******************** + + constant DLY : time := 1 ns; + +--***************************** Signal Declarations ***************************** + + -- ground and tied_to_vcc_i signals + signal tied_to_ground_i : std_logic; + signal tied_to_ground_vec_i : std_logic_vector(63 downto 0); + signal tied_to_vcc_i : std_logic; + signal gt0_qplloutclk_i : std_logic; + signal gt0_qplloutrefclk_i : std_logic; + + + signal gt0_mgtrefclktx_i : std_logic_vector(1 downto 0); + signal gt0_mgtrefclkrx_i : std_logic_vector(1 downto 0); + + + signal gt0_qpllclk_i : std_logic; + signal gt0_qpllrefclk_i : std_logic; + + +--*************************** Component Declarations ************************** +component gtxKintex7FEE80_GT +generic +( + -- Simulation attributes + GT_SIM_GTRESET_SPEEDUP : string := "FALSE"; + RX_DFE_KL_CFG2_IN : bit_vector := X"3010D90C"; + PMA_RSV_IN : bit_vector := X"00000000"; + PCS_RSVD_ATTR_IN : bit_vector := X"000000000000" +); +port +( + --------------------------------- CPLL Ports ------------------------------- + CPLLFBCLKLOST_OUT : out std_logic; + CPLLLOCK_OUT : out std_logic; + CPLLLOCKDETCLK_IN : in std_logic; + CPLLREFCLKLOST_OUT : out std_logic; + CPLLRESET_IN : in std_logic; + -------------------------- Channel - Clocking Ports ------------------------ + GTREFCLK0_IN : in std_logic; + ---------------------------- Channel - DRP Ports -------------------------- + DRPADDR_IN : in std_logic_vector(8 downto 0); + DRPCLK_IN : in std_logic; + DRPDI_IN : in std_logic_vector(15 downto 0); + DRPDO_OUT : out std_logic_vector(15 downto 0); + DRPEN_IN : in std_logic; + DRPRDY_OUT : out std_logic; + DRPWE_IN : in std_logic; + ------------------------------- Clocking Ports ----------------------------- + QPLLCLK_IN : in std_logic; + QPLLREFCLK_IN : in std_logic; + --------------------- RX Initialization and Reset Ports -------------------- + RXUSERRDY_IN : in std_logic; + -------------------------- RX Margin Analysis Ports ------------------------ + EYESCANDATAERROR_OUT : out std_logic; + ------------------------- Receive Ports - CDR Ports ------------------------ + RXCDRRESET_IN : in std_logic; + RXCDRLOCK_OUT : out std_logic; + ------------------ Receive Ports - FPGA RX Interface Ports ----------------- + RXUSRCLK_IN : in std_logic; + RXUSRCLK2_IN : in std_logic; + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + RXDATA_OUT : out std_logic_vector(15 downto 0); + ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- + RXDISPERR_OUT : out std_logic_vector(1 downto 0); + RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0); + --------------------------- Receive Ports - RX AFE ------------------------- + GTXRXP_IN : in std_logic; + ------------------------ Receive Ports - RX AFE Ports ---------------------- + GTXRXN_IN : in std_logic; + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + RXDLYEN_IN : in std_logic; + RXDLYSRESET_IN : in std_logic; + RXDLYSRESETDONE_OUT : out std_logic; + RXPHALIGN_IN : in std_logic; + RXPHALIGNDONE_OUT : out std_logic; + RXPHALIGNEN_IN : in std_logic; + RXPHDLYRESET_IN : in std_logic; + RXPHMONITOR_OUT : out std_logic_vector(4 downto 0); + RXPHSLIPMONITOR_OUT : out std_logic_vector(4 downto 0); + -------------------- Receive Ports - RX Equailizer Ports ------------------- + RXLPMHFHOLD_IN : in std_logic; + RXLPMLFHOLD_IN : in std_logic; + --------------- Receive Ports - RX Fabric Output Control Ports ------------- + RXOUTCLK_OUT : out std_logic; + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + GTRXRESET_IN : in std_logic; + RXPCSRESET_IN : in std_logic; + RXPMARESET_IN : in std_logic; + ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- + RXCHARISK_OUT : out std_logic_vector(1 downto 0); + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + RXRESETDONE_OUT : out std_logic; + --------------------- TX Initialization and Reset Ports -------------------- + GTTXRESET_IN : in std_logic; + TXUSERRDY_IN : in std_logic; + ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- + TXUSRCLK_IN : in std_logic; + TXUSRCLK2_IN : in std_logic; + ------------------ Transmit Ports - TX Buffer Bypass Ports ----------------- + TXDLYEN_IN : in std_logic; + TXDLYSRESET_IN : in std_logic; + TXDLYSRESETDONE_OUT : out std_logic; + TXPHALIGN_IN : in std_logic; + TXPHALIGNDONE_OUT : out std_logic; + TXPHALIGNEN_IN : in std_logic; + TXPHDLYRESET_IN : in std_logic; + TXPHINIT_IN : in std_logic; + TXPHINITDONE_OUT : out std_logic; + ------------------ Transmit Ports - TX Data Path interface ----------------- + TXDATA_IN : in std_logic_vector(15 downto 0); + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + GTXTXN_OUT : out std_logic; + GTXTXP_OUT : out std_logic; + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + TXOUTCLK_OUT : out std_logic; + TXOUTCLKFABRIC_OUT : out std_logic; + TXOUTCLKPCS_OUT : out std_logic; + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + TXCHARISK_IN : in std_logic_vector(1 downto 0); + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + TXRESETDONE_OUT : out std_logic + + +); +end component; + + + +--*************************Logic to set Attribute QPLL_FB_DIV***************************** + impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is + begin + if (qpllfbdiv_top = 16) then + return "0000100000"; + elsif (qpllfbdiv_top = 20) then + return "0000110000" ; + elsif (qpllfbdiv_top = 32) then + return "0001100000" ; + elsif (qpllfbdiv_top = 40) then + return "0010000000" ; + elsif (qpllfbdiv_top = 64) then + return "0011100000" ; + elsif (qpllfbdiv_top = 66) then + return "0101000000" ; + elsif (qpllfbdiv_top = 80) then + return "0100100000" ; + elsif (qpllfbdiv_top = 100) then + return "0101110000" ; + else + return "0000000000" ; + end if; + end function; + + impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is + begin + if (qpllfbdiv_top = 16) then + return '1'; + elsif (qpllfbdiv_top = 20) then + return '1' ; + elsif (qpllfbdiv_top = 32) then + return '1' ; + elsif (qpllfbdiv_top = 40) then + return '1' ; + elsif (qpllfbdiv_top = 64) then + return '1' ; + elsif (qpllfbdiv_top = 66) then + return '0' ; + elsif (qpllfbdiv_top = 80) then + return '1' ; + elsif (qpllfbdiv_top = 100) then + return '1' ; + else + return '1' ; + end if; + end function; + + constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP); + constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP); + +--********************************* Main Body of Code************************** + +begin + + tied_to_ground_i <= '0'; + tied_to_ground_vec_i(63 downto 0) <= (others => '0'); + tied_to_vcc_i <= '1'; + gt0_qpllclk_i <= gt0_qplloutclk_i; + gt0_qpllrefclk_i <= gt0_qplloutrefclk_i; + + + + --------------------------- GT Instances ------------------------------- + + --_________________________________________________________________________ + --_________________________________________________________________________ + --GT0 (X0Y0) + + gt0_gtxKintex7FEE80_i : gtxKintex7FEE80_GT + generic map + ( + -- Simulation attributes + GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP, + RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN, + PMA_RSV_IN => PMA_RSV_IN, + PCS_RSVD_ATTR_IN => X"000000000006" + ) + port map + ( + --------------------------------- CPLL Ports ------------------------------- + CPLLFBCLKLOST_OUT => GT0_CPLLFBCLKLOST_OUT, + CPLLLOCK_OUT => GT0_CPLLLOCK_OUT, + CPLLLOCKDETCLK_IN => GT0_CPLLLOCKDETCLK_IN, + CPLLREFCLKLOST_OUT => GT0_CPLLREFCLKLOST_OUT, + CPLLRESET_IN => GT0_CPLLRESET_IN, + -------------------------- Channel - Clocking Ports ------------------------ + GTREFCLK0_IN => GT0_GTREFCLK0_IN, + ---------------------------- Channel - DRP Ports -------------------------- + DRPADDR_IN => GT0_DRPADDR_IN, + DRPCLK_IN => GT0_DRPCLK_IN, + DRPDI_IN => GT0_DRPDI_IN, + DRPDO_OUT => GT0_DRPDO_OUT, + DRPEN_IN => GT0_DRPEN_IN, + DRPRDY_OUT => GT0_DRPRDY_OUT, + DRPWE_IN => GT0_DRPWE_IN, + ------------------------------- Clocking Ports ----------------------------- + QPLLCLK_IN => gt0_qpllclk_i, + QPLLREFCLK_IN => gt0_qpllrefclk_i, + --------------------- RX Initialization and Reset Ports -------------------- + RXUSERRDY_IN => GT0_RXUSERRDY_IN, + -------------------------- RX Margin Analysis Ports ------------------------ + EYESCANDATAERROR_OUT => GT0_EYESCANDATAERROR_OUT, + ------------------------- Receive Ports - CDR Ports ------------------------ + RXCDRRESET_IN => GT0_RXCDRRESET_IN, + RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT, + ------------------ Receive Ports - FPGA RX Interface Ports ----------------- + RXUSRCLK_IN => GT0_RXUSRCLK_IN, + RXUSRCLK2_IN => GT0_RXUSRCLK2_IN, + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + RXDATA_OUT => GT0_RXDATA_OUT, + ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- + RXDISPERR_OUT => GT0_RXDISPERR_OUT, + RXNOTINTABLE_OUT => GT0_RXNOTINTABLE_OUT, + --------------------------- Receive Ports - RX AFE ------------------------- + GTXRXP_IN => GT0_GTXRXP_IN, + ------------------------ Receive Ports - RX AFE Ports ---------------------- + GTXRXN_IN => GT0_GTXRXN_IN, + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + RXDLYEN_IN => GT0_RXDLYEN_IN, + RXDLYSRESET_IN => GT0_RXDLYSRESET_IN, + RXDLYSRESETDONE_OUT => GT0_RXDLYSRESETDONE_OUT, + RXPHALIGN_IN => GT0_RXPHALIGN_IN, + RXPHALIGNDONE_OUT => GT0_RXPHALIGNDONE_OUT, + RXPHALIGNEN_IN => GT0_RXPHALIGNEN_IN, + RXPHDLYRESET_IN => GT0_RXPHDLYRESET_IN, + RXPHMONITOR_OUT => GT0_RXPHMONITOR_OUT, + RXPHSLIPMONITOR_OUT => GT0_RXPHSLIPMONITOR_OUT, + -------------------- Receive Ports - RX Equailizer Ports ------------------- + RXLPMHFHOLD_IN => GT0_RXLPMHFHOLD_IN, + RXLPMLFHOLD_IN => GT0_RXLPMLFHOLD_IN, + --------------- Receive Ports - RX Fabric Output Control Ports ------------- + RXOUTCLK_OUT => GT0_RXOUTCLK_OUT, + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + GTRXRESET_IN => GT0_GTRXRESET_IN, + RXPCSRESET_IN => GT0_RXPCSRESET_IN, + RXPMARESET_IN => GT0_RXPMARESET_IN, + ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- + RXCHARISK_OUT => GT0_RXCHARISK_OUT, + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + RXRESETDONE_OUT => GT0_RXRESETDONE_OUT, + --------------------- TX Initialization and Reset Ports -------------------- + GTTXRESET_IN => GT0_GTTXRESET_IN, + TXUSERRDY_IN => GT0_TXUSERRDY_IN, + ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- + TXUSRCLK_IN => GT0_TXUSRCLK_IN, + TXUSRCLK2_IN => GT0_TXUSRCLK2_IN, + ------------------ Transmit Ports - TX Buffer Bypass Ports ----------------- + TXDLYEN_IN => GT0_TXDLYEN_IN, + TXDLYSRESET_IN => GT0_TXDLYSRESET_IN, + TXDLYSRESETDONE_OUT => GT0_TXDLYSRESETDONE_OUT, + TXPHALIGN_IN => GT0_TXPHALIGN_IN, + TXPHALIGNDONE_OUT => GT0_TXPHALIGNDONE_OUT, + TXPHALIGNEN_IN => GT0_TXPHALIGNEN_IN, + TXPHDLYRESET_IN => GT0_TXPHDLYRESET_IN, + TXPHINIT_IN => GT0_TXPHINIT_IN, + TXPHINITDONE_OUT => GT0_TXPHINITDONE_OUT, + ------------------ Transmit Ports - TX Data Path interface ----------------- + TXDATA_IN => GT0_TXDATA_IN, + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + GTXTXN_OUT => GT0_GTXTXN_OUT, + GTXTXP_OUT => GT0_GTXTXP_OUT, + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + TXOUTCLK_OUT => GT0_TXOUTCLK_OUT, + TXOUTCLKFABRIC_OUT => GT0_TXOUTCLKFABRIC_OUT, + TXOUTCLKPCS_OUT => GT0_TXOUTCLKPCS_OUT, + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + TXCHARISK_IN => GT0_TXCHARISK_IN, + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + TXRESETDONE_OUT => GT0_TXRESETDONE_OUT + + ); + + --_________________________________________________________________________ + --_________________________________________________________________________ + --_________________________GTXE2_COMMON____________________________________ + + gtxe2_common_0_i : GTXE2_COMMON + generic map + ( + -- Simulation attributes + SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP, + SIM_QPLLREFCLK_SEL => ("001"), + SIM_VERSION => "4.0", + + + ------------------COMMON BLOCK Attributes--------------- + BIAS_CFG => (x"0000040000001000"), + COMMON_CFG => (x"00000000"), + QPLL_CFG => (x"06801C1"), + QPLL_CLKOUT_CFG => ("0000"), + QPLL_COARSE_FREQ_OVRD => ("010000"), + QPLL_COARSE_FREQ_OVRD_EN => ('0'), + QPLL_CP => ("0000011111"), + QPLL_CP_MONITOR_EN => ('0'), + QPLL_DMONITOR_SEL => ('0'), + QPLL_FBDIV => (QPLL_FBDIV_IN), + QPLL_FBDIV_MONITOR_EN => ('0'), + QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO), + QPLL_INIT_CFG => (x"000006"), + QPLL_LOCK_CFG => (x"21E8"), + QPLL_LPF => ("1111"), + QPLL_REFCLK_DIV => (1) + + + ) + port map + ( + ------------- Common Block - Dynamic Reconfiguration Port (DRP) ----------- + DRPADDR => tied_to_ground_vec_i(7 downto 0), + DRPCLK => tied_to_ground_i, + DRPDI => tied_to_ground_vec_i(15 downto 0), + DRPDO => open, + DRPEN => tied_to_ground_i, + DRPRDY => open, + DRPWE => tied_to_ground_i, + ---------------------- Common Block - Ref Clock Ports --------------------- + GTGREFCLK => tied_to_ground_i, + GTNORTHREFCLK0 => tied_to_ground_i, + GTNORTHREFCLK1 => tied_to_ground_i, + GTREFCLK0 => GT0_GTREFCLK0_COMMON_IN, + GTREFCLK1 => tied_to_ground_i, + GTSOUTHREFCLK0 => tied_to_ground_i, + GTSOUTHREFCLK1 => tied_to_ground_i, + ------------------------- Common Block - QPLL Ports ----------------------- + QPLLDMONITOR => open, + ----------------------- Common Block - Clocking Ports ---------------------- + QPLLOUTCLK => gt0_qplloutclk_i, + QPLLOUTREFCLK => gt0_qplloutrefclk_i, + REFCLKOUTMONITOR => open, + ------------------------- Common Block - QPLL Ports ------------------------ + QPLLFBCLKLOST => open, + QPLLLOCK => GT0_QPLLLOCK_OUT, + QPLLLOCKDETCLK => GT0_QPLLLOCKDETCLK_IN, + QPLLLOCKEN => tied_to_vcc_i, + QPLLOUTRESET => tied_to_ground_i, + QPLLPD => tied_to_ground_i, + QPLLREFCLKLOST => GT0_QPLLREFCLKLOST_OUT, + QPLLREFCLKSEL => "001", + QPLLRESET => GT0_QPLLRESET_IN, + QPLLRSVD1 => "0000000000000000", + QPLLRSVD2 => "11111", + --------------------------------- QPLL Ports ------------------------------- + BGBYPASSB => tied_to_vcc_i, + BGMONITORENB => tied_to_vcc_i, + BGPDB => tied_to_vcc_i, + BGRCALOVRD => "00000", + PMARSVD => "00000000", + RCALENB => tied_to_vcc_i + + ); + + + +end RTL; diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_auto_phase_align.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_auto_phase_align.vhd new file mode 100644 index 0000000..1781690 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_auto_phase_align.vhd @@ -0,0 +1,202 @@ +--//////////////////////////////////////////////////////////////////////////////// +--// ____ ____ +--// / /\/ / +--// /___/ \ / Vendor: Xilinx +--// \ \ \/ Version : 2.6 +--// \ \ Application : 7 Series FPGAs Transceivers Wizard +--// / / Filename : gtxkintex7fee80_auto_phase_align.vhd +--// /___/ /\ +--// \ \ / \ +--// \___\/\___\ +--// +--// +-- Description : The logic below implements the procedure to do automatic phase-alignment +-- on the 7-series GTX as described in ug476pdf, version 1.3, +-- Chapters "Using the TX Phase Alignment to Bypass the TX Buffer" +-- and "Using the RX Phase Alignment to Bypass the RX Elastic Buffer" +-- Should the logic below differ from what is described in a later version +-- of the user-guide, you are using an auto-alignment block, which is +-- out of date and needs to be updated for safe operation. +-- +-- +-- +-- Module gtxKintex7FEE80_AUTO_PHASE_ALIGN +-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard +-- +-- +-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + + +--***************************************************************************** + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gtxKintex7FEE80_AUTO_PHASE_ALIGN is + Generic( + GT_TYPE : string := "GTX" + ); + + Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB + --or reference-clock present at startup. + RUN_PHALIGNMENT : in STD_LOGIC; --Signal from the main Reset-FSM to run the auto phase-alignment procedure + PHASE_ALIGNMENT_DONE : out STD_LOGIC := '0'; -- Auto phase-alignment performed sucessfully + PHALIGNDONE : in STD_LOGIC; --\ Phase-alignment signals from and to the + DLYSRESET : out STD_LOGIC; -- |transceiver. + DLYSRESETDONE : in STD_LOGIC; --/ + RECCLKSTABLE : in STD_LOGIC --/on the RX-side. + + ); +end gtxKintex7FEE80_AUTO_PHASE_ALIGN; + +architecture RTL of gtxKintex7FEE80_AUTO_PHASE_ALIGN is + + component gtxKintex7FEE80_sync_block + generic ( + INITIALISE : bit_vector(1 downto 0) := "00" + ); + port ( + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); + end component; + + type phase_align_auto_fsm is( + INIT, WAIT_PHRST_DONE, COUNT_PHALIGN_DONE, PHALIGN_DONE + ); + + signal phalign_state : phase_align_auto_fsm := INIT; + signal phaligndone_prev : std_logic := '0'; + signal phaligndone_ris_edge : std_logic; + + signal count_phalign_edges : integer range 0 to 3:= 0; + signal phaligndone_sync : std_logic := '0'; + signal dlysresetdone_sync : std_logic := '0'; + +begin + + sync_PHALIGNDONE : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => PHALIGNDONE, + data_out => phaligndone_sync + ); + + sync_DLYSRESETDONE : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => DLYSRESETDONE, + data_out => dlysresetdone_sync + ); + + + process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + phaligndone_prev <= phaligndone_sync; + end if; + end process; + phaligndone_ris_edge <= '1' when (phaligndone_prev = '0') and (phaligndone_sync = '1') else '0'; + + process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + if RUN_PHALIGNMENT = '0' or RECCLKSTABLE = '0' then + DLYSRESET <= '0'; + count_phalign_edges <= 0; + PHASE_ALIGNMENT_DONE <= '0'; + phalign_state <= INIT; + else + if phaligndone_ris_edge = '1' then + if count_phalign_edges < 3 then + count_phalign_edges <= count_phalign_edges + 1; + end if; + end if; + + DLYSRESET <= '0'; + + case phalign_state is + when INIT => + PHASE_ALIGNMENT_DONE <= '0'; + if RUN_PHALIGNMENT = '1' and RECCLKSTABLE = '1' then + --DLYSRESET is toggled to '1' + DLYSRESET <= '1'; + phalign_state <= WAIT_PHRST_DONE; + end if; + + when WAIT_PHRST_DONE => + if dlysresetdone_sync = '1' then + phalign_state <= COUNT_PHALIGN_DONE; + end if; + --No timeout-check here as that is done in the main FSM + + when COUNT_PHALIGN_DONE => + if ((GT_TYPE = "GTX" and count_phalign_edges = 2) or ((GT_TYPE = "GTH" or GT_TYPE = "GTP") and phaligndone_ris_edge = '1')) then + --For GTX: Only on the second edge of the PHALIGNDONE-signal the + -- phase-alignment is completed + --For GTH, GTP: TXSYNCDONE indicates the completion of Phase Alignment + + phalign_state <= PHALIGN_DONE; + end if; + + when PHALIGN_DONE => + PHASE_ALIGNMENT_DONE <= '1'; + + when OTHERS => + phalign_state <= INIT; + + end case; + end if; + end if; + end process; + +end RTL; + diff --git a/FEE_ADC32board/project/ipcore_dir/clockmodule80to80M.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_clock_module.vhd similarity index 73% rename from FEE_ADC32board/project/ipcore_dir/clockmodule80to80M.vhd rename to FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_clock_module.vhd index ccf25dc..e908bb5 100644 --- a/FEE_ADC32board/project/ipcore_dir/clockmodule80to80M.vhd +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_clock_module.vhd @@ -1,233 +1,242 @@ --- file: clockmodule80to80M.vhd --- --- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- ------------------------------------------------------------------------------- --- User entered comments ------------------------------------------------------------------------------- --- None --- ------------------------------------------------------------------------------- --- "Output Output Phase Duty Pk-to-Pk Phase" --- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" ------------------------------------------------------------------------------- --- CLK_OUT1____40.000______0.000______50.0______174.629____114.212 --- CLK_OUT2____80.000______0.000______50.0______151.652____114.212 --- CLK_OUT3___100.000______0.000______50.0______144.719____114.212 --- CLK_OUT4___200.000______0.000______50.0______126.455____114.212 --- ------------------------------------------------------------------------------- --- "Input Clock Freq (MHz) Input Jitter (UI)" ------------------------------------------------------------------------------- --- __primary_____________100____________0.010 - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; -use ieee.numeric_std.all; - -library unisim; -use unisim.vcomponents.all; - -entity clockmodule80to80M is -port - (-- Clock in ports - CLK_IN1 : in std_logic; - -- Clock out ports - CLK_OUT1 : out std_logic; - CLK_OUT2 : out std_logic; - CLK_OUT3 : out std_logic; - CLK_OUT4 : out std_logic; - -- Status and control signals - RESET : in std_logic; - LOCKED : out std_logic - ); -end clockmodule80to80M; - -architecture xilinx of clockmodule80to80M is - attribute CORE_GENERATION_INFO : string; - attribute CORE_GENERATION_INFO of xilinx : architecture is "clockmodule80to80M,clk_wiz_v3_6,{component_name=clockmodule80to80M,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=4,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}"; - -- Input clock buffering / unused connectors - signal clkin1 : std_logic; - -- Output clock buffering / unused connectors - signal clkfbout : std_logic; - signal clkfbout_buf : std_logic; - signal clkfboutb_unused : std_logic; - signal clkout0 : std_logic; - signal clkout0b_unused : std_logic; - signal clkout1 : std_logic; - signal clkout1b_unused : std_logic; - signal clkout2 : std_logic; - signal clkout2b_unused : std_logic; - signal clkout3 : std_logic; - signal clkout3b_unused : std_logic; - signal clkout4_unused : std_logic; - signal clkout5_unused : std_logic; - signal clkout6_unused : std_logic; - -- Dynamic programming unused signals - signal do_unused : std_logic_vector(15 downto 0); - signal drdy_unused : std_logic; - -- Dynamic phase shift unused signals - signal psdone_unused : std_logic; - -- Unused status signals - signal clkfbstopped_unused : std_logic; - signal clkinstopped_unused : std_logic; -begin - - - -- Input buffering - -------------------------------------- - clkin1 <= CLK_IN1; - - - -- Clocking primitive - -------------------------------------- - -- Instantiation of the MMCM primitive - -- * Unused inputs are tied off - -- * Unused outputs are labeled unused - mmcm_adv_inst : MMCM_ADV - generic map - (BANDWIDTH => "OPTIMIZED", - CLKOUT4_CASCADE => FALSE, - CLOCK_HOLD => FALSE, - COMPENSATION => "ZHOLD", - STARTUP_WAIT => FALSE, - DIVCLK_DIVIDE => 1, - CLKFBOUT_MULT_F => 8.000, - CLKFBOUT_PHASE => 0.000, - CLKFBOUT_USE_FINE_PS => FALSE, - CLKOUT0_DIVIDE_F => 20.000, - CLKOUT0_PHASE => 0.000, - CLKOUT0_DUTY_CYCLE => 0.500, - CLKOUT0_USE_FINE_PS => FALSE, - CLKOUT1_DIVIDE => 10, - CLKOUT1_PHASE => 0.000, - CLKOUT1_DUTY_CYCLE => 0.500, - CLKOUT1_USE_FINE_PS => FALSE, - CLKOUT2_DIVIDE => 8, - CLKOUT2_PHASE => 0.000, - CLKOUT2_DUTY_CYCLE => 0.500, - CLKOUT2_USE_FINE_PS => FALSE, - CLKOUT3_DIVIDE => 4, - CLKOUT3_PHASE => 0.000, - CLKOUT3_DUTY_CYCLE => 0.500, - CLKOUT3_USE_FINE_PS => FALSE, - CLKIN1_PERIOD => 10.000, - REF_JITTER1 => 0.010) - port map - -- Output clocks - (CLKFBOUT => clkfbout, - CLKFBOUTB => clkfboutb_unused, - CLKOUT0 => clkout0, - CLKOUT0B => clkout0b_unused, - CLKOUT1 => clkout1, - CLKOUT1B => clkout1b_unused, - CLKOUT2 => clkout2, - CLKOUT2B => clkout2b_unused, - CLKOUT3 => clkout3, - CLKOUT3B => clkout3b_unused, - CLKOUT4 => clkout4_unused, - CLKOUT5 => clkout5_unused, - CLKOUT6 => clkout6_unused, - -- Input clock control - CLKFBIN => clkfbout_buf, - CLKIN1 => clkin1, - CLKIN2 => '0', - -- Tied to always select the primary input clock - CLKINSEL => '1', - -- Ports for dynamic reconfiguration - DADDR => (others => '0'), - DCLK => '0', - DEN => '0', - DI => (others => '0'), - DO => do_unused, - DRDY => drdy_unused, - DWE => '0', - -- Ports for dynamic phase shift - PSCLK => '0', - PSEN => '0', - PSINCDEC => '0', - PSDONE => psdone_unused, - -- Other control and status signals - LOCKED => LOCKED, - CLKINSTOPPED => clkinstopped_unused, - CLKFBSTOPPED => clkfbstopped_unused, - PWRDWN => '0', - RST => RESET); - - -- Output buffering - ------------------------------------- - clkf_buf : BUFG - port map - (O => clkfbout_buf, - I => clkfbout); - - - clkout1_buf : BUFG - port map - (O => CLK_OUT1, - I => clkout0); - - - - clkout2_buf : BUFG - port map - (O => CLK_OUT2, - I => clkout1); - - clkout3_buf : BUFG - port map - (O => CLK_OUT3, - I => clkout2); - - clkout4_buf : BUFG - port map - (O => CLK_OUT4, - I => clkout3); - -end xilinx; +-- file: clk_wiz_v2_1.vhd +-- +-- (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +------------------------------------------------------------------------------ +-- User entered comments +------------------------------------------------------------------------------ +-- None +-- +------------------------------------------------------------------------------ +-- Output Output Phase Duty Cycle Pk-to-Pk Phase +-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +------------------------------------------------------------------------------ +-- CLK_OUT1 100.000 0.000 50.000 130.958 98.575 +-- CLK_OUT2 200.000 0.000 50.000 114.829 98.575 +-- +------------------------------------------------------------------------------ +-- Input Clock Input Freq (MHz) Input Jitter (UI) +------------------------------------------------------------------------------ +-- primary 100.000 0.010 + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; +use ieee.numeric_std.all; + +library unisim; +use unisim.vcomponents.all; + +entity GTXKINTEX7FEE80_CLOCK_MODULE is +generic +( + MULT : real := 2.0; + DIVIDE : integer := 2; + CLK_PERIOD : real := 6.4; + OUT0_DIVIDE : real := 2.0; + OUT1_DIVIDE : integer := 2; + OUT2_DIVIDE : integer := 2; + OUT3_DIVIDE : integer := 2 +); +port + (-- Clock in ports + CLK_IN : in std_logic; + -- Clock out ports + CLK0_OUT : out std_logic; + CLK1_OUT : out std_logic; + CLK2_OUT : out std_logic; + CLK3_OUT : out std_logic; + -- Status and control signals + MMCM_RESET_IN : in std_logic; + MMCM_LOCKED_OUT : out std_logic + ); +end GTXKINTEX7FEE80_CLOCK_MODULE; + +architecture xilinx of GTXKINTEX7FEE80_CLOCK_MODULE is + attribute CORE_GENERATION_INFO : string; + attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_v2_1,clk_wiz_v2_1,{component_name=clk_wiz_v2_1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}"; + -- Input clock buffering / unused connectors + signal clkin1 : std_logic; + -- Output clock buffering / unused connectors + signal clkfbout : std_logic; + signal clkfbout_buf : std_logic; + signal clkfboutb_unused : std_logic; + signal clkout0 : std_logic; + signal clkout0b_unused : std_logic; + signal clkout1 : std_logic; + signal clkout1b_unused : std_logic; + signal clkout2 : std_logic; + signal clkout2b_unused : std_logic; + signal clkout3 : std_logic; + signal clkout3b_unused : std_logic; + signal clkout4_unused : std_logic; + signal clkout5_unused : std_logic; + signal clkout6_unused : std_logic; + -- Dynamic programming unused signals + signal do_unused : std_logic_vector(15 downto 0); + signal drdy_unused : std_logic; + -- Dynamic phase shift unused signals + signal psdone_unused : std_logic; + -- Unused status signals + signal clkfbstopped_unused : std_logic; + signal clkinstopped_unused : std_logic; +begin + + + -- Input buffering + -------------------------------------- + clkin1_buf : BUFG + port map + (O => clkin1, + I => CLK_IN); + + -- Clocking primitive + -------------------------------------- + -- Instantiation of the MMCM primitive + -- * Unused inputs are tied off + -- * Unused outputs are labeled unused + + mmcm_adv_inst : MMCME2_ADV + generic map + (BANDWIDTH => "OPTIMIZED", + CLKOUT4_CASCADE => FALSE, + COMPENSATION => "ZHOLD", + STARTUP_WAIT => FALSE, + DIVCLK_DIVIDE => DIVIDE, + CLKFBOUT_MULT_F => MULT, + CLKFBOUT_PHASE => 0.000, + CLKFBOUT_USE_FINE_PS => FALSE, + CLKOUT0_DIVIDE_F => OUT0_DIVIDE, + CLKOUT0_PHASE => 0.000, + CLKOUT0_DUTY_CYCLE => 0.500, + CLKOUT0_USE_FINE_PS => FALSE, + CLKIN1_PERIOD => CLK_PERIOD, + CLKOUT1_DIVIDE => OUT1_DIVIDE, + CLKOUT1_PHASE => 0.000, + CLKOUT1_DUTY_CYCLE => 0.500, + CLKOUT1_USE_FINE_PS => FALSE, + CLKOUT2_DIVIDE => OUT2_DIVIDE, + CLKOUT2_PHASE => 0.000, + CLKOUT2_DUTY_CYCLE => 0.500, + CLKOUT2_USE_FINE_PS => FALSE, + CLKOUT3_DIVIDE => OUT3_DIVIDE, + CLKOUT3_PHASE => 0.000, + CLKOUT3_DUTY_CYCLE => 0.500, + CLKOUT3_USE_FINE_PS => FALSE, + REF_JITTER1 => 0.010) + port map + -- Output clocks + (CLKFBOUT => clkfbout, + CLKFBOUTB => clkfboutb_unused, + CLKOUT0 => clkout0, + CLKOUT0B => clkout0b_unused, + CLKOUT1 => clkout1, + CLKOUT1B => clkout1b_unused, + CLKOUT2 => clkout2, + CLKOUT2B => clkout2b_unused, + CLKOUT3 => clkout3, + CLKOUT3B => clkout3b_unused, + CLKOUT4 => clkout4_unused, + CLKOUT5 => clkout5_unused, + CLKOUT6 => clkout6_unused, + -- Input clock control + CLKFBIN => clkfbout, + CLKIN1 => clkin1, + CLKIN2 => '0', + -- Tied to always select the primary input clock + CLKINSEL => '1', + -- Ports for dynamic reconfiguration + DADDR => (others => '0'), + DCLK => '0', + DEN => '0', + DI => (others => '0'), + DO => do_unused, + DRDY => drdy_unused, + DWE => '0', + -- Ports for dynamic phase shift + PSCLK => '0', + PSEN => '0', + PSINCDEC => '0', + PSDONE => psdone_unused, + -- Other control and status signals + LOCKED => MMCM_LOCKED_OUT, + CLKINSTOPPED => clkinstopped_unused, + CLKFBSTOPPED => clkfbstopped_unused, + PWRDWN => '0', + RST => MMCM_RESET_IN); + + -- Output buffering + ------------------------------------- + --clkf_buf : BUFG + --port map + -- (O => clkfbout_buf, + -- I => clkfbout); + + + clkout0_buf : BUFG + port map + (O => CLK0_OUT, + I => clkout0); + + clkout1_buf : BUFG + port map + (O => CLK1_OUT, + I => clkout1); + + clkout2_buf : BUFG + port map + (O => CLK2_OUT, + I => clkout2); + + clkout3_buf : BUFG + port map + (O => CLK3_OUT, + I => clkout3); + +end xilinx; + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_gt.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_gt.vhd new file mode 100644 index 0000000..4eb81b8 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_gt.vhd @@ -0,0 +1,816 @@ +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 2.6 +-- \ \ Application : 7 Series FPGAs Transceivers Wizard +-- / / Filename : gtxkintex7fee80_gt.vhd +-- /___/ /\ +-- \ \ / \ +-- \___\/\___\ +-- +-- +-- Module gtxKintex7FEE80_GT (a GT Wrapper) +-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard +-- +-- +-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; + +--***************************** Entity Declaration **************************** + +entity gtxKintex7FEE80_GT is +generic +( + -- Simulation attributes + GT_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "true" to speed up sim reset + RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC"; + PMA_RSV_IN : bit_vector := x"00018480"; + PCS_RSVD_ATTR_IN : bit_vector := X"000000000000" +); +port +( + --------------------------------- CPLL Ports ------------------------------- + CPLLFBCLKLOST_OUT : out std_logic; + CPLLLOCK_OUT : out std_logic; + CPLLLOCKDETCLK_IN : in std_logic; + CPLLREFCLKLOST_OUT : out std_logic; + CPLLRESET_IN : in std_logic; + -------------------------- Channel - Clocking Ports ------------------------ + GTREFCLK0_IN : in std_logic; + ---------------------------- Channel - DRP Ports -------------------------- + DRPADDR_IN : in std_logic_vector(8 downto 0); + DRPCLK_IN : in std_logic; + DRPDI_IN : in std_logic_vector(15 downto 0); + DRPDO_OUT : out std_logic_vector(15 downto 0); + DRPEN_IN : in std_logic; + DRPRDY_OUT : out std_logic; + DRPWE_IN : in std_logic; + ------------------------------- Clocking Ports ----------------------------- + QPLLCLK_IN : in std_logic; + QPLLREFCLK_IN : in std_logic; + --------------------- RX Initialization and Reset Ports -------------------- + RXUSERRDY_IN : in std_logic; + -------------------------- RX Margin Analysis Ports ------------------------ + EYESCANDATAERROR_OUT : out std_logic; + ------------------------- Receive Ports - CDR Ports ------------------------ + RXCDRRESET_IN : in std_logic; + RXCDRLOCK_OUT : out std_logic; + ------------------ Receive Ports - FPGA RX Interface Ports ----------------- + RXUSRCLK_IN : in std_logic; + RXUSRCLK2_IN : in std_logic; + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + RXDATA_OUT : out std_logic_vector(15 downto 0); + ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- + RXDISPERR_OUT : out std_logic_vector(1 downto 0); + RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0); + --------------------------- Receive Ports - RX AFE ------------------------- + GTXRXP_IN : in std_logic; + ------------------------ Receive Ports - RX AFE Ports ---------------------- + GTXRXN_IN : in std_logic; + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + RXDLYEN_IN : in std_logic; + RXDLYSRESET_IN : in std_logic; + RXDLYSRESETDONE_OUT : out std_logic; + RXPHALIGN_IN : in std_logic; + RXPHALIGNDONE_OUT : out std_logic; + RXPHALIGNEN_IN : in std_logic; + RXPHDLYRESET_IN : in std_logic; + RXPHMONITOR_OUT : out std_logic_vector(4 downto 0); + RXPHSLIPMONITOR_OUT : out std_logic_vector(4 downto 0); + -------------------- Receive Ports - RX Equailizer Ports ------------------- + RXLPMHFHOLD_IN : in std_logic; + RXLPMLFHOLD_IN : in std_logic; + --------------- Receive Ports - RX Fabric Output Control Ports ------------- + RXOUTCLK_OUT : out std_logic; + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + GTRXRESET_IN : in std_logic; + RXPCSRESET_IN : in std_logic; + RXPMARESET_IN : in std_logic; + ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- + RXCHARISK_OUT : out std_logic_vector(1 downto 0); + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + RXRESETDONE_OUT : out std_logic; + --------------------- TX Initialization and Reset Ports -------------------- + GTTXRESET_IN : in std_logic; + TXUSERRDY_IN : in std_logic; + ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- + TXUSRCLK_IN : in std_logic; + TXUSRCLK2_IN : in std_logic; + ------------------ Transmit Ports - TX Buffer Bypass Ports ----------------- + TXDLYEN_IN : in std_logic; + TXDLYSRESET_IN : in std_logic; + TXDLYSRESETDONE_OUT : out std_logic; + TXPHALIGN_IN : in std_logic; + TXPHALIGNDONE_OUT : out std_logic; + TXPHALIGNEN_IN : in std_logic; + TXPHDLYRESET_IN : in std_logic; + TXPHINIT_IN : in std_logic; + TXPHINITDONE_OUT : out std_logic; + ------------------ Transmit Ports - TX Data Path interface ----------------- + TXDATA_IN : in std_logic_vector(15 downto 0); + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + GTXTXN_OUT : out std_logic; + GTXTXP_OUT : out std_logic; + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + TXOUTCLK_OUT : out std_logic; + TXOUTCLKFABRIC_OUT : out std_logic; + TXOUTCLKPCS_OUT : out std_logic; + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + TXCHARISK_IN : in std_logic_vector(1 downto 0); + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + TXRESETDONE_OUT : out std_logic + + +); + + +end gtxKintex7FEE80_GT; + +architecture RTL of gtxKintex7FEE80_GT is + +--**************************** Signal Declarations **************************** + + -- ground and tied_to_vcc_i signals + signal tied_to_ground_i : std_logic; + signal tied_to_ground_vec_i : std_logic_vector(63 downto 0); + signal tied_to_vcc_i : std_logic; + + + + -- RX Datapath signals + signal rxdata_i : std_logic_vector(63 downto 0); + signal rxchariscomma_float_i : std_logic_vector(5 downto 0); + signal rxcharisk_float_i : std_logic_vector(5 downto 0); + signal rxdisperr_float_i : std_logic_vector(5 downto 0); + signal rxnotintable_float_i : std_logic_vector(5 downto 0); + signal rxrundisp_float_i : std_logic_vector(5 downto 0); + + + + -- TX Datapath signals + signal txdata_i : std_logic_vector(63 downto 0); + signal txkerr_float_i : std_logic_vector(5 downto 0); + signal txrundisp_float_i : std_logic_vector(5 downto 0); + signal rxstartofseq_float_i : std_logic; + +--******************************** Main Body of Code*************************** + +begin + + --------------------------- Static signal Assignments --------------------- + + tied_to_ground_i <= '0'; + tied_to_ground_vec_i(63 downto 0) <= (others => '0'); + tied_to_vcc_i <= '1'; + + ------------------- GT Datapath byte mapping ----------------- + + RXDATA_OUT <= rxdata_i(15 downto 0); + + txdata_i <= (tied_to_ground_vec_i(47 downto 0) & TXDATA_IN); + + + + ----------------------------- GTXE2 Instance -------------------------- + + gtxe2_i :GTXE2_CHANNEL + generic map + ( + + --_______________________ Simulation-Only Attributes ___________________ + + SIM_RECEIVER_DETECT_PASS => ("TRUE"), + SIM_RESET_SPEEDUP => (GT_SIM_GTRESET_SPEEDUP), + SIM_TX_EIDLE_DRIVE_LEVEL => ("X"), + SIM_CPLLREFCLK_SEL => ("001"), + SIM_VERSION => ("4.0"), + + + ------------------RX Byte and Word Alignment Attributes--------------- + ALIGN_COMMA_DOUBLE => ("FALSE"), + ALIGN_COMMA_ENABLE => ("1111111111"), + ALIGN_COMMA_WORD => (1), + ALIGN_MCOMMA_DET => ("TRUE"), + ALIGN_MCOMMA_VALUE => ("1010000011"), + ALIGN_PCOMMA_DET => ("TRUE"), + ALIGN_PCOMMA_VALUE => ("0101111100"), + SHOW_REALIGN_COMMA => ("FALSE"), --//("TRUE"), + RXSLIDE_AUTO_WAIT => (7), + RXSLIDE_MODE => ("AUTO"),--//("PCS"), + RX_SIG_VALID_DLY => (10), + + ------------------RX 8B/10B Decoder Attributes--------------- + RX_DISPERR_SEQ_MATCH => ("TRUE"), + DEC_MCOMMA_DETECT => ("TRUE"), + DEC_PCOMMA_DETECT => ("TRUE"), + DEC_VALID_COMMA_ONLY => ("FALSE"), + + ------------------------RX Clock Correction Attributes---------------------- + CBCC_DATA_SOURCE_SEL => ("DECODED"), + CLK_COR_SEQ_2_USE => ("FALSE"), + CLK_COR_KEEP_IDLE => ("FALSE"), + CLK_COR_MAX_LAT => (9), + CLK_COR_MIN_LAT => (7), + CLK_COR_PRECEDENCE => ("TRUE"), + CLK_COR_REPEAT_WAIT => (0), + CLK_COR_SEQ_LEN => (1), + CLK_COR_SEQ_1_ENABLE => ("1111"), + CLK_COR_SEQ_1_1 => ("0100000000"), + CLK_COR_SEQ_1_2 => ("0000000000"), + CLK_COR_SEQ_1_3 => ("0000000000"), + CLK_COR_SEQ_1_4 => ("0000000000"), + CLK_CORRECT_USE => ("FALSE"), + CLK_COR_SEQ_2_ENABLE => ("1111"), + CLK_COR_SEQ_2_1 => ("0100000000"), + CLK_COR_SEQ_2_2 => ("0000000000"), + CLK_COR_SEQ_2_3 => ("0000000000"), + CLK_COR_SEQ_2_4 => ("0000000000"), + + ------------------------RX Channel Bonding Attributes---------------------- + CHAN_BOND_KEEP_ALIGN => ("FALSE"), + CHAN_BOND_MAX_SKEW => (1), + CHAN_BOND_SEQ_LEN => (1), + CHAN_BOND_SEQ_1_1 => ("0000000000"), + CHAN_BOND_SEQ_1_2 => ("0000000000"), + CHAN_BOND_SEQ_1_3 => ("0000000000"), + CHAN_BOND_SEQ_1_4 => ("0000000000"), + CHAN_BOND_SEQ_1_ENABLE => ("1111"), + CHAN_BOND_SEQ_2_1 => ("0000000000"), + CHAN_BOND_SEQ_2_2 => ("0000000000"), + CHAN_BOND_SEQ_2_3 => ("0000000000"), + CHAN_BOND_SEQ_2_4 => ("0000000000"), + CHAN_BOND_SEQ_2_ENABLE => ("1111"), + CHAN_BOND_SEQ_2_USE => ("FALSE"), + FTS_DESKEW_SEQ_ENABLE => ("1111"), + FTS_LANE_DESKEW_CFG => ("1111"), + FTS_LANE_DESKEW_EN => ("FALSE"), + + ---------------------------RX Margin Analysis Attributes---------------------------- + ES_CONTROL => ("000000"), + ES_ERRDET_EN => ("FALSE"), + ES_EYE_SCAN_EN => ("TRUE"), + ES_HORZ_OFFSET => (x"000"), + ES_PMA_CFG => ("0000000000"), + ES_PRESCALE => ("00000"), + ES_QUALIFIER => (x"00000000000000000000"), + ES_QUAL_MASK => (x"00000000000000000000"), + ES_SDATA_MASK => (x"00000000000000000000"), + ES_VERT_OFFSET => ("000000000"), + + -------------------------FPGA RX Interface Attributes------------------------- + RX_DATA_WIDTH => (20), + + ---------------------------PMA Attributes---------------------------- + OUTREFCLK_SEL_INV => ("11"), + PMA_RSV => (PMA_RSV_IN), + PMA_RSV2 => (x"2040"), + PMA_RSV3 => ("00"), + PMA_RSV4 => (x"00000000"), + RX_BIAS_CFG => ("000000000100"), + DMONITOR_CFG => (x"000A00"), + RX_CM_SEL => ("00"), + RX_CM_TRIM => ("000"), + RX_DEBUG_CFG => ("000000000000"), + RX_OS_CFG => ("0000010000000"), + TERM_RCAL_CFG => ("10000"), + TERM_RCAL_OVRD => ('0'), + TST_RSV => (x"00000000"), + RX_CLK25_DIV => (4), + TX_CLK25_DIV => (4), + UCODEER_CLR => ('0'), + + ---------------------------PCI Express Attributes---------------------------- + PCS_PCIE_EN => ("FALSE"), + + ---------------------------PCS Attributes---------------------------- + PCS_RSVD_ATTR => (PCS_RSVD_ATTR_IN), + + -------------RX Buffer Attributes------------ + RXBUF_ADDR_MODE => ("FAST"), + RXBUF_EIDLE_HI_CNT => ("1000"), + RXBUF_EIDLE_LO_CNT => ("0000"), + RXBUF_EN => ("FALSE"), + RX_BUFFER_CFG => ("000000"), + RXBUF_RESET_ON_CB_CHANGE => ("TRUE"), + RXBUF_RESET_ON_COMMAALIGN => ("FALSE"), + RXBUF_RESET_ON_EIDLE => ("FALSE"), + RXBUF_RESET_ON_RATE_CHANGE => ("TRUE"), + RXBUFRESET_TIME => ("00001"), + RXBUF_THRESH_OVFLW => (61), + RXBUF_THRESH_OVRD => ("FALSE"), + RXBUF_THRESH_UNDFLW => (4), + RXDLY_CFG => (x"001F"), + RXDLY_LCFG => (x"030"), + RXDLY_TAP_CFG => (x"0000"), + RXPH_CFG => (x"000000"), + RXPHDLY_CFG => (x"084020"), + RXPH_MONITOR_SEL => ("00000"), + RX_XCLK_SEL => ("RXUSR"), + RX_DDI_SEL => ("000000"), + RX_DEFER_RESET_BUF_EN => ("TRUE"), + + -----------------------CDR Attributes------------------------- + + --For GTX only: Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200008 + + --For GTX only: Display Port, HBR2 - set RXCDR_CFG=72'h038C008bff20200010 + RXCDR_CFG => (x"03000023ff10200020"), + + RXCDR_FR_RESET_ON_EIDLE => ('0'), + RXCDR_HOLD_DURING_EIDLE => ('0'), + RXCDR_PH_RESET_ON_EIDLE => ('0'), + RXCDR_LOCK_CFG => ("010101"), + + -------------------RX Initialization and Reset Attributes------------------- + RXCDRFREQRESET_TIME => ("00001"), + RXCDRPHRESET_TIME => ("00001"), + RXISCANRESET_TIME => ("00001"), + RXPCSRESET_TIME => ("00001"), + RXPMARESET_TIME => ("00011"), + + -------------------RX OOB Signaling Attributes------------------- + RXOOB_CFG => ("0000110"), + + -------------------------RX Gearbox Attributes--------------------------- + RXGEARBOX_EN => ("FALSE"), + GEARBOX_MODE => ("000"), + + -------------------------PRBS Detection Attribute----------------------- + RXPRBS_ERR_LOOPBACK => ('0'), + + -------------Power-Down Attributes---------- + PD_TRANS_TIME_FROM_P2 => (x"03c"), + PD_TRANS_TIME_NONE_P2 => (x"3c"), + PD_TRANS_TIME_TO_P2 => (x"64"), + + -------------RX OOB Signaling Attributes---------- + SAS_MAX_COM => (64), + SAS_MIN_COM => (36), + SATA_BURST_SEQ_LEN => ("1111"), + SATA_BURST_VAL => ("100"), + SATA_EIDLE_VAL => ("100"), + SATA_MAX_BURST => (8), + SATA_MAX_INIT => (21), + SATA_MAX_WAKE => (7), + SATA_MIN_BURST => (4), + SATA_MIN_INIT => (12), + SATA_MIN_WAKE => (4), + + -------------RX Fabric Clock Output Control Attributes---------- + TRANS_TIME_RATE => (x"0E"), + + --------------TX Buffer Attributes---------------- + TXBUF_EN => ("FALSE"), + TXBUF_RESET_ON_RATE_CHANGE => ("TRUE"), + TXDLY_CFG => (x"001F"), + TXDLY_LCFG => (x"030"), + TXDLY_TAP_CFG => (x"0000"), + TXPH_CFG => (x"0780"), + TXPHDLY_CFG => (x"084020"), + TXPH_MONITOR_SEL => ("00000"), + TX_XCLK_SEL => ("TXUSR"), + + -------------------------FPGA TX Interface Attributes------------------------- + TX_DATA_WIDTH => (20), + + -------------------------TX Configurable Driver Attributes------------------------- + TX_DEEMPH0 => ("00000"), + TX_DEEMPH1 => ("00000"), + TX_EIDLE_ASSERT_DELAY => ("110"), + TX_EIDLE_DEASSERT_DELAY => ("100"), + TX_LOOPBACK_DRIVE_HIZ => ("FALSE"), + TX_MAINCURSOR_SEL => ('0'), + TX_DRIVE_MODE => ("DIRECT"), + TX_MARGIN_FULL_0 => ("1001110"), + TX_MARGIN_FULL_1 => ("1001001"), + TX_MARGIN_FULL_2 => ("1000101"), + TX_MARGIN_FULL_3 => ("1000010"), + TX_MARGIN_FULL_4 => ("1000000"), + TX_MARGIN_LOW_0 => ("1000110"), + TX_MARGIN_LOW_1 => ("1000100"), + TX_MARGIN_LOW_2 => ("1000010"), + TX_MARGIN_LOW_3 => ("1000000"), + TX_MARGIN_LOW_4 => ("1000000"), + + -------------------------TX Gearbox Attributes-------------------------- + TXGEARBOX_EN => ("FALSE"), + + -------------------------TX Initialization and Reset Attributes-------------------------- + TXPCSRESET_TIME => ("00001"), + TXPMARESET_TIME => ("00001"), + + -------------------------TX Receiver Detection Attributes-------------------------- + TX_RXDETECT_CFG => (x"1832"), + TX_RXDETECT_REF => ("100"), + + ----------------------------CPLL Attributes---------------------------- + CPLL_CFG => (x"BC07DC"), + CPLL_FBDIV => (5), + CPLL_FBDIV_45 => (5), + CPLL_INIT_CFG => (x"00001E"), + CPLL_LOCK_CFG => (x"01E8"), + CPLL_REFCLK_DIV => (1), + RXOUT_DIV => (2), + TXOUT_DIV => (2), + SATA_CPLL_CFG => ("VCO_3000MHZ"), + + --------------RX Initialization and Reset Attributes------------- + RXDFELPMRESET_TIME => ("0001111"), + + --------------RX Equalizer Attributes------------- + RXLPM_HF_CFG => ("00000011110000"), + RXLPM_LF_CFG => ("00000011110000"), + RX_DFE_GAIN_CFG => (x"020FEA"), + RX_DFE_H2_CFG => ("000000000000"), + RX_DFE_H3_CFG => ("000001000000"), + RX_DFE_H4_CFG => ("00011110000"), + RX_DFE_H5_CFG => ("00011100000"), + RX_DFE_KL_CFG => ("0000011111110"), + RX_DFE_LPM_CFG => (x"0904"), + RX_DFE_LPM_HOLD_DURING_EIDLE => ('0'), + RX_DFE_UT_CFG => ("10001111000000000"), + RX_DFE_VP_CFG => ("00011111100000011"), + + -------------------------Power-Down Attributes------------------------- + RX_CLKMUX_PD => ('1'), + TX_CLKMUX_PD => ('1'), + + -------------------------FPGA RX Interface Attribute------------------------- + RX_INT_DATAWIDTH => (0), + + -------------------------FPGA TX Interface Attribute------------------------- + TX_INT_DATAWIDTH => (0), + + ------------------TX Configurable Driver Attributes--------------- + TX_QPI_STATUS_EN => ('0'), + + -------------------------RX Equalizer Attributes-------------------------- + RX_DFE_KL_CFG2 => (RX_DFE_KL_CFG2_IN), + RX_DFE_XYD_CFG => ("0000000000000"), + + -------------------------TX Configurable Driver Attributes-------------------------- + TX_PREDRIVER_MODE => ('0') + + + ) + port map + ( + --------------------------------- CPLL Ports ------------------------------- + CPLLFBCLKLOST => CPLLFBCLKLOST_OUT, + CPLLLOCK => CPLLLOCK_OUT, + CPLLLOCKDETCLK => CPLLLOCKDETCLK_IN, + CPLLLOCKEN => tied_to_vcc_i, + CPLLPD => tied_to_ground_i, + CPLLREFCLKLOST => CPLLREFCLKLOST_OUT, + CPLLREFCLKSEL => "001", + CPLLRESET => CPLLRESET_IN, + GTRSVD => "0000000000000000", + PCSRSVDIN => "0000000000000000", + PCSRSVDIN2 => "00000", + PMARSVDIN => "00000", + PMARSVDIN2 => "00000", + TSTIN => "11111111111111111111", + TSTOUT => open, + ---------------------------------- Channel --------------------------------- + CLKRSVD => "0000", + -------------------------- Channel - Clocking Ports ------------------------ + GTGREFCLK => tied_to_ground_i, + GTNORTHREFCLK0 => tied_to_ground_i, + GTNORTHREFCLK1 => tied_to_ground_i, + GTREFCLK0 => GTREFCLK0_IN, + GTREFCLK1 => tied_to_ground_i, + GTSOUTHREFCLK0 => tied_to_ground_i, + GTSOUTHREFCLK1 => tied_to_ground_i, + ---------------------------- Channel - DRP Ports -------------------------- + DRPADDR => DRPADDR_IN, + DRPCLK => DRPCLK_IN, + DRPDI => DRPDI_IN, + DRPDO => DRPDO_OUT, + DRPEN => DRPEN_IN, + DRPRDY => DRPRDY_OUT, + DRPWE => DRPWE_IN, + ------------------------------- Clocking Ports ----------------------------- + GTREFCLKMONITOR => open, + QPLLCLK => QPLLCLK_IN, + QPLLREFCLK => QPLLREFCLK_IN, + RXSYSCLKSEL => "00", + TXSYSCLKSEL => "00", + --------------------------- Digital Monitor Ports -------------------------- + DMONITOROUT => open, + ----------------- FPGA TX Interface Datapath Configuration ---------------- + TX8B10BEN => tied_to_vcc_i, + ------------------------------- Loopback Ports ----------------------------- + LOOPBACK => tied_to_ground_vec_i(2 downto 0), + ----------------------------- PCI Express Ports ---------------------------- + PHYSTATUS => open, + RXRATE => tied_to_ground_vec_i(2 downto 0), + RXVALID => open, + ------------------------------ Power-Down Ports ---------------------------- + RXPD => "00", + TXPD => "00", + -------------------------- RX 8B/10B Decoder Ports ------------------------- + SETERRSTATUS => tied_to_ground_i, + --------------------- RX Initialization and Reset Ports -------------------- + EYESCANRESET => tied_to_ground_i, + RXUSERRDY => RXUSERRDY_IN, + -------------------------- RX Margin Analysis Ports ------------------------ + EYESCANDATAERROR => EYESCANDATAERROR_OUT, + EYESCANMODE => tied_to_ground_i, + EYESCANTRIGGER => tied_to_ground_i, + ------------------------- Receive Ports - CDR Ports ------------------------ + RXCDRFREQRESET => tied_to_ground_i, + RXCDRHOLD => tied_to_ground_i, + RXCDRLOCK => RXCDRLOCK_OUT, + RXCDROVRDEN => tied_to_ground_i, + RXCDRRESET => RXCDRRESET_IN, --// tied_to_ground_i, + RXCDRRESETRSV => tied_to_ground_i, + ------------------- Receive Ports - Clock Correction Ports ----------------- + RXCLKCORCNT => open, + ---------- Receive Ports - FPGA RX Interface Datapath Configuration -------- + RX8B10BEN => tied_to_vcc_i, + ------------------ Receive Ports - FPGA RX Interface Ports ----------------- + RXUSRCLK => RXUSRCLK_IN, + RXUSRCLK2 => RXUSRCLK2_IN, + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + RXDATA => rxdata_i, + ------------------- Receive Ports - Pattern Checker Ports ------------------ + RXPRBSERR => open, + RXPRBSSEL => tied_to_ground_vec_i(2 downto 0), + ------------------- Receive Ports - Pattern Checker ports ------------------ + RXPRBSCNTRESET => tied_to_ground_i, + -------------------- Receive Ports - RX Equalizer Ports ------------------- + RXDFEXYDEN => tied_to_ground_i, + RXDFEXYDHOLD => tied_to_ground_i, + RXDFEXYDOVRDEN => tied_to_ground_i, + ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- + RXDISPERR(7 downto 2) => rxdisperr_float_i, + RXDISPERR(1 downto 0) => RXDISPERR_OUT, + RXNOTINTABLE(7 downto 2) => rxnotintable_float_i, + RXNOTINTABLE(1 downto 0) => RXNOTINTABLE_OUT, + --------------------------- Receive Ports - RX AFE ------------------------- + GTXRXP => GTXRXP_IN, + ------------------------ Receive Ports - RX AFE Ports ---------------------- + GTXRXN => GTXRXN_IN, + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + RXBUFRESET => tied_to_ground_i, + RXBUFSTATUS => open, + RXDDIEN => tied_to_vcc_i, + RXDLYBYPASS => tied_to_ground_i, + RXDLYEN => RXDLYEN_IN, + RXDLYOVRDEN => tied_to_ground_i, + RXDLYSRESET => RXDLYSRESET_IN, + RXDLYSRESETDONE => RXDLYSRESETDONE_OUT, + RXPHALIGN => RXPHALIGN_IN, + RXPHALIGNDONE => RXPHALIGNDONE_OUT, + RXPHALIGNEN => RXPHALIGNEN_IN, + RXPHDLYPD => tied_to_ground_i, + RXPHDLYRESET => RXPHDLYRESET_IN, + RXPHMONITOR => RXPHMONITOR_OUT, + RXPHOVRDEN => tied_to_ground_i, + RXPHSLIPMONITOR => RXPHSLIPMONITOR_OUT, + RXSTATUS => open, + -------------- Receive Ports - RX Byte and Word Alignment Ports ------------ + RXBYTEISALIGNED => open, + RXBYTEREALIGN => open, + RXCOMMADET => open, + RXCOMMADETEN => tied_to_vcc_i, + RXMCOMMAALIGNEN => tied_to_vcc_i, + RXPCOMMAALIGNEN => tied_to_vcc_i, + ------------------ Receive Ports - RX Channel Bonding Ports ---------------- + RXCHANBONDSEQ => open, + RXCHBONDEN => tied_to_ground_i, + RXCHBONDLEVEL => tied_to_ground_vec_i(2 downto 0), + RXCHBONDMASTER => tied_to_ground_i, + RXCHBONDO => open, + RXCHBONDSLAVE => tied_to_ground_i, + ----------------- Receive Ports - RX Channel Bonding Ports ---------------- + RXCHANISALIGNED => open, + RXCHANREALIGN => open, + -------------------- Receive Ports - RX Equailizer Ports ------------------- + RXLPMHFHOLD => RXLPMHFHOLD_IN, + RXLPMHFOVRDEN => tied_to_ground_i, + RXLPMLFHOLD => RXLPMLFHOLD_IN, + --------------------- Receive Ports - RX Equalizer Ports ------------------- + RXDFEAGCHOLD => tied_to_ground_i, + RXDFEAGCOVRDEN => tied_to_ground_i, + RXDFECM1EN => tied_to_ground_i, + RXDFELFHOLD => tied_to_ground_i, + RXDFELFOVRDEN => tied_to_ground_i, + RXDFELPMRESET => tied_to_ground_i, + RXDFETAP2HOLD => tied_to_ground_i, + RXDFETAP2OVRDEN => tied_to_ground_i, + RXDFETAP3HOLD => tied_to_ground_i, + RXDFETAP3OVRDEN => tied_to_ground_i, + RXDFETAP4HOLD => tied_to_ground_i, + RXDFETAP4OVRDEN => tied_to_ground_i, + RXDFETAP5HOLD => tied_to_ground_i, + RXDFETAP5OVRDEN => tied_to_ground_i, + RXDFEUTHOLD => tied_to_ground_i, + RXDFEUTOVRDEN => tied_to_ground_i, + RXDFEVPHOLD => tied_to_ground_i, + RXDFEVPOVRDEN => tied_to_ground_i, + RXDFEVSEN => tied_to_ground_i, + RXLPMLFKLOVRDEN => tied_to_ground_i, + RXMONITOROUT => open, + RXMONITORSEL => "00", + RXOSHOLD => tied_to_ground_i, + RXOSOVRDEN => tied_to_ground_i, + ------------ Receive Ports - RX Fabric ClocK Output Control Ports ---------- + RXRATEDONE => open, + --------------- Receive Ports - RX Fabric Output Control Ports ------------- + RXOUTCLK => RXOUTCLK_OUT, + RXOUTCLKFABRIC => open, + RXOUTCLKPCS => open, + RXOUTCLKSEL => "010", + ---------------------- Receive Ports - RX Gearbox Ports -------------------- + RXDATAVALID => open, + RXHEADER => open, + RXHEADERVALID => open, + RXSTARTOFSEQ => open, + --------------------- Receive Ports - RX Gearbox Ports -------------------- + RXGEARBOXSLIP => tied_to_ground_i, + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + GTRXRESET => GTRXRESET_IN, + RXOOBRESET => tied_to_ground_i, + RXPCSRESET => RXPCSRESET_IN, + RXPMARESET => RXPMARESET_IN, + ------------------ Receive Ports - RX Margin Analysis ports ---------------- + RXLPMEN => tied_to_vcc_i, + ------------------- Receive Ports - RX OOB Signaling ports ----------------- + RXCOMSASDET => open, + RXCOMWAKEDET => open, + ------------------ Receive Ports - RX OOB Signaling ports ----------------- + RXCOMINITDET => open, + ------------------ Receive Ports - RX OOB signalling Ports ----------------- + RXELECIDLE => open, + RXELECIDLEMODE => "11", + ----------------- Receive Ports - RX Polarity Control Ports ---------------- + RXPOLARITY => tied_to_ground_i, + ---------------------- Receive Ports - RX gearbox ports -------------------- + RXSLIDE => tied_to_ground_i, + ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- + RXCHARISCOMMA => open, + RXCHARISK(7 downto 2) => rxcharisk_float_i, + RXCHARISK(1 downto 0) => RXCHARISK_OUT, + ------------------ Receive Ports - Rx Channel Bonding Ports ---------------- + RXCHBONDI => "00000", + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + RXRESETDONE => RXRESETDONE_OUT, + -------------------------------- Rx AFE Ports ------------------------------ + RXQPIEN => tied_to_ground_i, + RXQPISENN => open, + RXQPISENP => open, + --------------------------- TX Buffer Bypass Ports ------------------------- + TXPHDLYTSTCLK => tied_to_ground_i, + ------------------------ TX Configurable Driver Ports ---------------------- + TXPOSTCURSOR => "00000", + TXPOSTCURSORINV => tied_to_ground_i, + TXPRECURSOR => tied_to_ground_vec_i(4 downto 0), + TXPRECURSORINV => tied_to_ground_i, + TXQPIBIASEN => tied_to_ground_i, + TXQPISTRONGPDOWN => tied_to_ground_i, + TXQPIWEAKPUP => tied_to_ground_i, + --------------------- TX Initialization and Reset Ports -------------------- + CFGRESET => tied_to_ground_i, + GTTXRESET => GTTXRESET_IN, + PCSRSVDOUT => open, + TXUSERRDY => TXUSERRDY_IN, + ---------------------- Transceiver Reset Mode Operation -------------------- + GTRESETSEL => tied_to_ground_i, + RESETOVRD => tied_to_ground_i, + ---------------- Transmit Ports - 8b10b Encoder Control Ports -------------- + TXCHARDISPMODE => tied_to_ground_vec_i(7 downto 0), + TXCHARDISPVAL => tied_to_ground_vec_i(7 downto 0), + ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- + TXUSRCLK => TXUSRCLK_IN, + TXUSRCLK2 => TXUSRCLK2_IN, + --------------------- Transmit Ports - PCI Express Ports ------------------- + TXELECIDLE => tied_to_ground_i, + TXMARGIN => tied_to_ground_vec_i(2 downto 0), + TXRATE => tied_to_ground_vec_i(2 downto 0), + TXSWING => tied_to_ground_i, + ------------------ Transmit Ports - Pattern Generator Ports ---------------- + TXPRBSFORCEERR => tied_to_ground_i, + ------------------ Transmit Ports - TX Buffer Bypass Ports ----------------- + TXDLYBYPASS => tied_to_ground_i, + TXDLYEN => TXDLYEN_IN, + TXDLYHOLD => tied_to_ground_i, + TXDLYOVRDEN => tied_to_ground_i, + TXDLYSRESET => TXDLYSRESET_IN, + TXDLYSRESETDONE => TXDLYSRESETDONE_OUT, + TXDLYUPDOWN => tied_to_ground_i, + TXPHALIGN => TXPHALIGN_IN, + TXPHALIGNDONE => TXPHALIGNDONE_OUT, + TXPHALIGNEN => TXPHALIGNEN_IN, + TXPHDLYPD => tied_to_ground_i, + TXPHDLYRESET => TXPHDLYRESET_IN, + TXPHINIT => TXPHINIT_IN, + TXPHINITDONE => TXPHINITDONE_OUT, + TXPHOVRDEN => tied_to_ground_i, + ---------------------- Transmit Ports - TX Buffer Ports -------------------- + TXBUFSTATUS => open, + --------------- Transmit Ports - TX Configurable Driver Ports -------------- + TXBUFDIFFCTRL => "100", + TXDEEMPH => tied_to_ground_i, + TXDIFFCTRL => "1000", + TXDIFFPD => tied_to_ground_i, + TXINHIBIT => tied_to_ground_i, + TXMAINCURSOR => "0000000", + TXPISOPD => tied_to_ground_i, + ------------------ Transmit Ports - TX Data Path interface ----------------- + TXDATA => txdata_i, + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + GTXTXN => GTXTXN_OUT, + GTXTXP => GTXTXP_OUT, + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + TXOUTCLK => TXOUTCLK_OUT, + TXOUTCLKFABRIC => TXOUTCLKFABRIC_OUT, + TXOUTCLKPCS => TXOUTCLKPCS_OUT, + TXOUTCLKSEL => "011", + TXRATEDONE => open, + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + TXCHARISK(7 downto 2) => tied_to_ground_vec_i(5 downto 0), + TXCHARISK(1 downto 0) => TXCHARISK_IN, + TXGEARBOXREADY => open, + TXHEADER => tied_to_ground_vec_i(2 downto 0), + TXSEQUENCE => tied_to_ground_vec_i(6 downto 0), + TXSTARTSEQ => tied_to_ground_i, + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + TXPCSRESET => tied_to_ground_i, + TXPMARESET => tied_to_ground_i, + TXRESETDONE => TXRESETDONE_OUT, + ------------------ Transmit Ports - TX OOB signalling Ports ---------------- + TXCOMFINISH => open, + TXCOMINIT => tied_to_ground_i, + TXCOMSAS => tied_to_ground_i, + TXCOMWAKE => tied_to_ground_i, + TXPDELECIDLEMODE => tied_to_ground_i, + ----------------- Transmit Ports - TX Polarity Control Ports --------------- + TXPOLARITY => tied_to_ground_i, + --------------- Transmit Ports - TX Receiver Detection Ports -------------- + TXDETECTRX => tied_to_ground_i, + ------------------ Transmit Ports - TX8b/10b Encoder Ports ----------------- + TX8B10BBYPASS => tied_to_ground_vec_i(7 downto 0), + ------------------ Transmit Ports - pattern Generator Ports ---------------- + TXPRBSSEL => tied_to_ground_vec_i(2 downto 0), + ----------------------- Tx Configurable Driver Ports ---------------------- + TXQPISENN => open, + TXQPISENP => open + + ); + + end RTL; + + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_rx_manual_phase_align.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_rx_manual_phase_align.vhd new file mode 100644 index 0000000..eb72828 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_rx_manual_phase_align.vhd @@ -0,0 +1,286 @@ +--//////////////////////////////////////////////////////////////////////////////// +--// ____ ____ +--// / /\/ / +--// /___/ \ / Vendor: Xilinx +--// \ \ \/ Version : 2.6 +--// \ \ Application : 7 Series FPGAs Transceivers Wizard +--// / / Filename : gtxkintex7fee80_rx_manual_phase_align.vhd +--// /___/ /\ +--// \ \ / \ +--// \___\/\___\ +--// +--// +-- Description : This module performs RX Buffer Phase Alignment in Manual Mode. +-- +-- +-- +-- Module gtxKintex7FEE80_rx_manual_phase_align +-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard +-- +-- +-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity gtxKintex7FEE80_RX_MANUAL_PHASE_ALIGN is + Generic( NUMBER_OF_LANES : integer range 1 to 32:= 4; -- Number of lanes that are controlled using this FSM. + MASTER_LANE_ID : integer range 0 to 31:= 0 -- Number of the lane which is considered the master in manual phase-alignment + ); + + Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB + --or reference-clock present at startup. + RESET_PHALIGNMENT : in STD_LOGIC; + RUN_PHALIGNMENT : in STD_LOGIC; + PHASE_ALIGNMENT_DONE : out STD_LOGIC := '0'; -- Manual phase-alignment performed sucessfully + RXDLYSRESET : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0'); + RXDLYSRESETDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0); + RXPHALIGN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0'); + RXPHALIGNDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0); + RXDLYEN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0') + ); +end gtxKintex7FEE80_RX_MANUAL_PHASE_ALIGN; + +architecture RTL of gtxKintex7FEE80_RX_MANUAL_PHASE_ALIGN is + + component gtxKintex7FEE80_sync_block + generic ( + INITIALISE : bit_vector(1 downto 0) := "00" + ); + port ( + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); + end component; + + constant VCC_VEC : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '1'); + constant GND_VEC : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0'); + + type rx_phase_align_manual_fsm is( + INIT, WAIT_DLYRST_DONE, M_PHALIGN, M_DLYEN, + S_PHALIGN, M_DLYEN2, PHALIGN_DONE + ); + signal rx_phalign_manual_state : rx_phase_align_manual_fsm := INIT; + signal rxphaligndone_prev : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0'); + signal rxphaligndone_ris_edge : std_logic_vector(NUMBER_OF_LANES-1 downto 0); + + signal rxdlysresetdone_store : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0'); + signal rxphaligndone_store : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0'); + signal rxdone_clear : std_logic := '0'; + + signal rxphaligndone_sync : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0'); + signal rxdlysresetdone_sync : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0'); + + +begin + + cdc: for i in 0 to NUMBER_OF_LANES-1 generate + sync_RXPHALIGNDONE : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => RXPHALIGNDONE(i), + data_out => rxphaligndone_sync(i) + ); + + sync_RXDLYSRESETDONE : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => RXDLYSRESETDONE(i), + data_out => rxdlysresetdone_sync(i) + ); + + end generate; + + + + process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + rxphaligndone_prev <= rxphaligndone_sync; + end if; + end process; + + edge_detect: for i in 0 to NUMBER_OF_LANES-1 generate + rxphaligndone_ris_edge(i) <= '1' when (rxphaligndone_prev(i) = '0') and (rxphaligndone_sync(i) = '1') else '0'; + end generate; + + process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + if rxdone_clear = '1' then + rxdlysresetdone_store <= (others=>'0'); + rxphaligndone_store <= (others=>'0'); + else + for i in 0 to NUMBER_OF_LANES-1 loop + if rxdlysresetdone_sync(i) = '1' then + rxdlysresetdone_store(i) <= '1'; + end if; + if rxphaligndone_ris_edge(i) = '1' then + rxphaligndone_store(i) <= '1'; + end if; + end loop; + end if; + end if; + end process; + + + + + process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + if RESET_PHALIGNMENT = '1' then + PHASE_ALIGNMENT_DONE <= '0'; + RXDLYSRESET <= (others => '0'); + RXPHALIGN <= (others => '0'); + RXDLYEN <= (others => '0'); + rx_phalign_manual_state <= INIT; + rxdone_clear <= '1'; + else + case rx_phalign_manual_state is + when INIT => + PHASE_ALIGNMENT_DONE <= '0'; + rxdone_clear <= '1'; + + if RUN_PHALIGNMENT = '1' then + --Assert RXDLYSRESET for all lanes. + rxdone_clear <= '0'; + RXDLYSRESET <= (others => '1'); + rx_phalign_manual_state <= WAIT_DLYRST_DONE; + end if; + + when WAIT_DLYRST_DONE => + for i in 0 to NUMBER_OF_LANES - 1 loop + --if RXDLYSRESETDONE(i) = '1' then + if rxdlysresetdone_store(i) = '1' then + --Hold RXDLYSRESET High until RXDLYSRESETDONE of the + --respective lane is asserted. + --Deassert RXDLYSRESET for the lane in which the + --RXDLYSRESETDONE is asserted. + RXDLYSRESET(i) <= '0'; + end if; + end loop; + if rxdlysresetdone_store = VCC_VEC then + rx_phalign_manual_state <= M_PHALIGN; + end if; + + when M_PHALIGN => + --When RXDLYSRESET of all lanes are deasserted, assert + --RXPHALIGN for the master lane. + RXPHALIGN(MASTER_LANE_ID) <= '1'; + if rxphaligndone_ris_edge(MASTER_LANE_ID) = '1' then + --Hold this signal High until a rising edge on RXPHALIGNDONE + --of the master lane is detected, then deassert RXPHALIGN for + --the master lane. + RXPHALIGN(MASTER_LANE_ID) <= '0'; + rx_phalign_manual_state <= M_DLYEN; + end if; + + when M_DLYEN => + --Assert RXDLYEN for the master lane. This causes RXPHALIGNDONE + --to be deasserted. + RXDLYEN(MASTER_LANE_ID) <= '1'; + if rxphaligndone_ris_edge(MASTER_LANE_ID) = '1' then + --Hold RXDLYEN for the master lane High until a rising edge on + --RXPHALIGNDONE of the master lane is detected, then deassert + --RXDLYEN for the master lane. + RXDLYEN(MASTER_LANE_ID) <= '0'; + rx_phalign_manual_state <= S_PHALIGN; + end if; + + when S_PHALIGN => + --Assert RXPHALIGN for all slave lane(s). Hold this signal High until + --a rising edge on RXPHALIGNDONE of the respective slave lane is detected. + RXPHALIGN <= (others=>'1');--\Assert only the PHALIGN signal of + RXPHALIGN(MASTER_LANE_ID) <= '0'; --/the slaves. + for i in 0 to NUMBER_OF_LANES - 1 loop + if rxphaligndone_store(i) = '1' then + --When a rising edge on the respective lane is detected, RXPHALIGN + --of that lane is deasserted. + RXPHALIGN(i) <= '0'; + end if; + end loop; + --The reason for checking of the occurance of at least one rising edge + --is to avoid the potential direct move where RXPHALIGNDONE might not + --be going low fast enough. + --if rxphaligndone_store = VCC_VEC and rxphaligndone_ris_edge /= GND_VEC then + if rxphaligndone_store = VCC_VEC then + rx_phalign_manual_state <= M_DLYEN2; + end if; + + when M_DLYEN2 => + --When RXPHALIGN for all slave lane(s) are deasserted, assert RXDLYEN + --for the master lane. This causes RXPHALIGNDONE of the master lane + --to be deasserted. + RXDLYEN(MASTER_LANE_ID) <= '1'; + if rxphaligndone_ris_edge(MASTER_LANE_ID) = '1' then + --Wait until RXPHALIGNDONE of the master lane reasserts. Phase and + --delay alignment for the multilane interface is complete. + rx_phalign_manual_state <= PHALIGN_DONE; + end if; + + when PHALIGN_DONE => + --Continue to hold RXDLYEN for the master lane High to adjust RXUSRCLK + --to compensate for temperature and voltage variations. + RXDLYEN(MASTER_LANE_ID) <= '1'; + PHASE_ALIGNMENT_DONE <= '1'; + + when OTHERS => + rx_phalign_manual_state <= INIT; + + end case; + end if; + end if; + end process; + +end RTL; + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_rx_startup_fsm.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_rx_startup_fsm.vhd new file mode 100644 index 0000000..65592aa --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_rx_startup_fsm.vhd @@ -0,0 +1,738 @@ +--//////////////////////////////////////////////////////////////////////////////// +--// ____ ____ +--// / /\/ / +--// /___/ \ / Vendor: Xilinx +--// \ \ \/ Version : 2.6 +--// \ \ Application : 7 Series FPGAs Transceivers Wizard +--// / / Filename : gtxkintex7fee80_rx_startup_fsm.vhd +--// /___/ /\ +--// \ \ / \ +--// \___\/\___\ +--// +--// +-- Description : This module performs RX reset and initialization. +-- +-- +-- +-- Module gtxKintex7FEE80_rx_startup_fsm +-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard +-- +-- +-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + + +--***************************************************************************** + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gtxKintex7FEE80_RX_STARTUP_FSM is + Generic( EXAMPLE_SIMULATION : integer := 0; + GT_TYPE : string := "GTX"; + EQ_MODE : string := "DFE"; --RX Equalisation Mode; set to DFE or LPM + STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns] + RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8; + TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must + RX_QPLL_USED : boolean := False; -- share these two generic values + PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic + -- is enough. For single-lane applications the automatic alignment is + -- sufficient + ); + Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB + --or reference-clock present at startup. + RXUSERCLK : in STD_LOGIC; --RXUSERCLK as used in the design + SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time + QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost + CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost + QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT + CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT + RXRESETDONE : in STD_LOGIC; + MMCM_LOCK : in STD_LOGIC; + RECCLK_STABLE : in STD_LOGIC; + RECCLK_MONITOR_RESTART : in STD_LOGIC:='0'; + DATA_VALID : in STD_LOGIC; + TXUSERRDY : in STD_LOGIC; --TXUSERRDY from GT + DONT_RESET_ON_DATA_ERROR : in STD_LOGIC; --Used to control the Auto-Reset of FSM when Data Error is detected + GTRXRESET : out STD_LOGIC:='0'; + MMCM_RESET : out STD_LOGIC:='1'; + QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL (only if RX uses QPLL) + CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL (only if RX uses CPLL) + RX_FSM_RESET_DONE : out STD_LOGIC; --Reset-sequence has sucessfully been finished. + RXUSERRDY : out STD_LOGIC:='0'; + RUN_PHALIGNMENT : out STD_LOGIC; + PHALIGNMENT_DONE : in STD_LOGIC; + RESET_PHALIGNMENT : out STD_LOGIC:='0'; + RXDFEAGCHOLD : out STD_LOGIC; + RXDFELFHOLD : out STD_LOGIC; + RXLPMLFHOLD : out STD_LOGIC; + RXLPMHFHOLD : out STD_LOGIC; + RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of + -- Retries it took to get the transceiver up and running + ); +end gtxKintex7FEE80_RX_STARTUP_FSM; + +--Interdependencies: +-- * Timing depends on the frequency of the stable clock. Hence counters-sizes +-- are calculated at design-time based on the Generics +-- +-- * if either of the PLLs is reset during TX-startup, it does not need to be reset again by RX +-- => signal which PLL has been reset +-- * + + + +architecture RTL of gtxKintex7FEE80_RX_STARTUP_FSM is + + component gtxKintex7FEE80_sync_block + generic ( + INITIALISE : bit_vector(1 downto 0) := "00" + ); + port ( + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); + end component; + + + type rx_rst_fsm_type is( + INIT, ASSERT_ALL_RESETS, RELEASE_PLL_RESET, VERIFY_RECCLK_STABLE, + RELEASE_MMCM_RESET, WAIT_RESET_DONE, DO_PHASE_ALIGNMENT, + MONITOR_DATA_VALID, FSM_DONE); + + signal rx_state : rx_rst_fsm_type := INIT; + + constant MMCM_LOCK_CNT_MAX : integer := 1024; + constant STARTUP_DELAY : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration + constant WAIT_CYCLES : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration + constant WAIT_MAX : integer := WAIT_CYCLES + 10; -- 500 ns plus some additional margin + + constant WAIT_TIMEOUT_2ms : integer := 2000000 / STABLE_CLOCK_PERIOD;-- 2 ms time-out + constant WAIT_TLOCK_MAX : integer := 100000 / STABLE_CLOCK_PERIOD;--100 us time-out + constant WAIT_TIMEOUT_500us : integer := 500000 / STABLE_CLOCK_PERIOD;--500 us time-out + constant WAIT_TIMEOUT_1us : integer := 1000 / STABLE_CLOCK_PERIOD; --1 us time-out + constant WAIT_TIMEOUT_100us : integer := 100000 / STABLE_CLOCK_PERIOD; --100 us time-out + constant WAIT_TIME_ADAPT : integer := (37000000 /integer(2))/STABLE_CLOCK_PERIOD; + + signal init_wait_count : integer range 0 to WAIT_MAX:=0; + signal init_wait_done : std_logic := '0'; + signal pll_reset_asserted : std_logic := '0'; + signal rx_fsm_reset_done_int : std_logic := '0'; + signal rx_fsm_reset_done_int_s2 : std_logic := '0'; + signal rx_fsm_reset_done_int_s3 : std_logic := '0'; + + signal rxresetdone_s2 : std_logic := '0'; + signal rxresetdone_s3 : std_logic := '0'; + + constant MAX_RETRIES : integer := 2**RETRY_COUNTER_BITWIDTH-1; + signal retry_counter_int : integer range 0 to MAX_RETRIES := 0; + signal time_out_counter : integer range 0 to WAIT_TIMEOUT_2ms := 0; + signal recclk_mon_restart_count : integer range 0 to 3:= 0; + signal recclk_mon_count_reset : std_logic := '0'; + + signal reset_time_out : std_logic := '0'; + signal time_out_2ms : std_logic := '0';--\Flags that the various time-out points + signal time_tlock_max : std_logic := '0';--|have been reached. + signal time_out_500us : std_logic := '0';--| + signal time_out_1us : std_logic := '0';--/ + signal time_out_100us : std_logic := '0';--/ + signal check_tlock_max : std_logic := '0'; + + signal mmcm_lock_count : integer range 0 to MMCM_LOCK_CNT_MAX-1:=0; + signal mmcm_lock_int : std_logic := '0'; + signal mmcm_lock_reclocked : std_logic := '0'; + + signal run_phase_alignment_int: std_logic := '0'; + signal run_phase_alignment_int_s2 : std_logic := '0'; + signal run_phase_alignment_int_s3 : std_logic := '0'; + + constant MAX_WAIT_BYPASS : integer := 5000;--5000 RXUSRCLK cycles is the max time for Multi lanes designs + signal wait_bypass_count : integer range 0 to MAX_WAIT_BYPASS-1; + signal time_out_wait_bypass : std_logic := '0'; + signal time_out_wait_bypass_s2 : std_logic := '0'; + signal time_out_wait_bypass_s3 : std_logic := '0'; + + signal refclk_lost : std_logic; + + signal time_out_adapt : std_logic := '0'; + signal adapt_count_reset : std_logic := '0'; + signal adapt_count : integer range 0 to WAIT_TIME_ADAPT-1; + + signal data_valid_sync: std_logic := '0'; + + signal cplllock_sync: std_logic := '0'; + signal qplllock_sync: std_logic := '0'; + signal cplllock_prev: std_logic := '0'; + signal qplllock_prev: std_logic := '0'; + signal cplllock_ris_edge: std_logic := '0'; + signal qplllock_ris_edge: std_logic := '0'; + +begin + --Alias section, signals used within this module mapped to output ports: + RETRY_COUNTER <= STD_LOGIC_VECTOR(TO_UNSIGNED(retry_counter_int,RETRY_COUNTER_BITWIDTH)); + RUN_PHALIGNMENT <= run_phase_alignment_int; + RX_FSM_RESET_DONE <= rx_fsm_reset_done_int; + + process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + -- The counter starts running when configuration has finished and + -- the clock is stable. When its maximum count-value has been reached, + -- the 500 ns from Answer Record 43482 have been passed. + if init_wait_count = WAIT_MAX then + init_wait_done <= '1'; + else + init_wait_count <= init_wait_count + 1; + end if; + end if; + end process; + + + adapt_wait_sim:if(EXAMPLE_SIMULATION = 1) generate + time_out_adapt <= '1'; + end generate; + + adapt_wait_hw:if(EXAMPLE_SIMULATION = 0) generate + process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + if(adapt_count_reset = '1') then + adapt_count <= 0; + time_out_adapt <= '0'; + elsif(adapt_count = WAIT_TIME_ADAPT -1) then + time_out_adapt <= '1'; + else + adapt_count <= adapt_count + 1; + end if; + end if; + end process; + end generate; + + retries_recclk_monitor:process(STABLE_CLOCK) + begin + --This counter monitors, how many retries the RECCLK monitor + --runs. If during startup too many retries are necessary, the whole + --initialisation-process of the transceivers gets restarted. + if rising_edge(STABLE_CLOCK) then + if recclk_mon_count_reset = '1' then + recclk_mon_restart_count <= 0; + elsif RECCLK_MONITOR_RESTART = '1' then + if recclk_mon_restart_count = 3 then + recclk_mon_restart_count <= 0; + else + recclk_mon_restart_count <= recclk_mon_restart_count + 1; + end if; + end if; + end if; + end process; + + timeouts:process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + -- One common large counter for generating three time-out signals. + -- Intermediate time-outs are derived from calculated values, based + -- on the period of the provided clock. + if reset_time_out = '1' then + time_out_counter <= 0; + time_out_2ms <= '0'; + time_tlock_max <= '0'; + time_out_500us <= '0'; + time_out_1us <= '0'; + time_out_100us <= '0'; + else + if time_out_counter = WAIT_TIMEOUT_2ms then + time_out_2ms <= '1'; + else + time_out_counter <= time_out_counter + 1; + end if; + + if (time_out_counter > WAIT_TLOCK_MAX) and (check_tlock_max='1') then + time_tlock_max <= '1'; + end if; + + if time_out_counter = WAIT_TIMEOUT_500us then + time_out_500us <= '1'; + end if; + + if time_out_counter = WAIT_TIMEOUT_1us then + time_out_1us <= '1'; + end if; + + if time_out_counter = WAIT_TIMEOUT_100us then + time_out_100us <= '1'; + end if; + + end if; + end if; + end process; + + + mmcm_lock_wait:process(RXUSERCLK) + begin + --The lock-signal from the MMCM is not immediately used but + --enabling a counter. Only when the counter hits its maximum, + --the MMCM is considered as "really" locked. + --The counter avoids that the FSM already starts on only a + --coarse lock of the MMCM (=toggling of the LOCK-signal). + if rising_edge(RXUSERCLK) then + if MMCM_LOCK = '0' then + mmcm_lock_count <= 0; + mmcm_lock_int <= '0'; + else + if mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1 then + mmcm_lock_count <= mmcm_lock_count + 1; + else + mmcm_lock_int <= '1'; + end if; + end if; + end if; + end process; + + + -- Clock Domain Crossing + + sync_run_phase_alignment_int : gtxKintex7FEE80_sync_block + port map + ( + clk => RXUSERCLK, + data_in => run_phase_alignment_int, + data_out => run_phase_alignment_int_s2 + ); + + sync_rx_fsm_reset_done_int : gtxKintex7FEE80_sync_block + port map + ( + clk => RXUSERCLK, + data_in => rx_fsm_reset_done_int, + data_out => rx_fsm_reset_done_int_s2 + ); + + process(RXUSERCLK) + begin + if rising_edge(RXUSERCLK) then + run_phase_alignment_int_s3 <= run_phase_alignment_int_s2; + + rx_fsm_reset_done_int_s3 <= rx_fsm_reset_done_int_s2; + end if; + end process; + + sync_RXRESETDONE : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => RXRESETDONE, + data_out => rxresetdone_s2 + ); + + sync_time_out_wait_bypass : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => time_out_wait_bypass, + data_out => time_out_wait_bypass_s2 + ); + + sync_mmcm_lock_reclocked : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => mmcm_lock_int, + data_out => mmcm_lock_reclocked + ); + + sync_data_valid : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => DATA_VALID, + data_out => data_valid_sync + ); + + + process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + rxresetdone_s3 <= rxresetdone_s2; + + time_out_wait_bypass_s3 <= time_out_wait_bypass_s2; + cplllock_prev <= cplllock_sync; + qplllock_prev <= qplllock_sync; + end if; + end process; + + sync_CPLLLOCK : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => CPLLLOCK, + data_out => cplllock_sync + ); + + sync_QPLLLOCK : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => QPLLLOCK, + data_out => qplllock_sync + ); + + + process (STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + if(SOFT_RESET = '1' ) then + cplllock_ris_edge <= '0'; + elsif((cplllock_prev = '0') and (cplllock_sync = '1')) then + cplllock_ris_edge <= '1'; + elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then + cplllock_ris_edge <= cplllock_ris_edge; + else + cplllock_ris_edge <= '0'; + end if; + end if; + end process; + + process (STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + if(SOFT_RESET = '1' ) then + qplllock_ris_edge <= '0'; + elsif((qplllock_prev = '0') and (qplllock_sync = '1')) then + qplllock_ris_edge <= '1'; + elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then + qplllock_ris_edge <= qplllock_ris_edge; + else + qplllock_ris_edge <= '0'; + end if; + end if; + end process; + + + + timeout_buffer_bypass:process(RXUSERCLK) + begin + if rising_edge(RXUSERCLK) then + if run_phase_alignment_int_s3 = '0' then + wait_bypass_count <= 0; + time_out_wait_bypass <= '0'; + elsif (run_phase_alignment_int_s3 = '1') and (rx_fsm_reset_done_int_s3 = '0') then + if wait_bypass_count = MAX_WAIT_BYPASS - 1 then + time_out_wait_bypass <= '1'; + else + wait_bypass_count <= wait_bypass_count + 1; + end if; + end if; + end if; + end process; + + refclk_lost <= '1' when ((RX_QPLL_USED and QPLLREFCLKLOST='1') or (not RX_QPLL_USED and CPLLREFCLKLOST='1')) else '0'; + + + + --FSM for resetting the GTX/GTH/GTP in the 7-series. + --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + -- + -- Following steps are performed: + -- 1) After configuration wait for approximately 500 ns as specified in + -- answer-record 43482 + -- 2) Assert all resets on the GT and on an MMCM potentially connected. + -- After that wait until a reference-clock has been detected. + -- 3) Release the reset to the GT and wait until the GT-PLL has locked. + -- 4) Release the MMCM-reset and wait until the MMCM has signalled lock. + -- Also get info from the TX-side which PLL has been reset. + -- 5) Wait for the RESET_DONE-signal from the GT. + -- 6) Signal to start the phase-alignment procedure and wait for it to + -- finish. + -- 7) Reset-sequence has successfully run through. Signal this to the + -- rest of the design by asserting RX_FSM_RESET_DONE. + + reset_fsm:process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + if (SOFT_RESET = '1' or (not(rx_state = INIT) and not(rx_state = ASSERT_ALL_RESETS) and refclk_lost = '1')) then + rx_state <= INIT; + RXUSERRDY <= '0'; + GTRXRESET <= '0'; + MMCM_RESET <= '1'; + rx_fsm_reset_done_int <= '0'; + QPLL_RESET <= '0'; + CPLL_RESET <= '0'; + pll_reset_asserted <= '0'; + reset_time_out <= '1'; + retry_counter_int <= 0; + run_phase_alignment_int <= '0'; + check_tlock_max <= '0'; + RESET_PHALIGNMENT <= '1'; + recclk_mon_count_reset <= '1'; + adapt_count_reset <= '1'; + RXDFEAGCHOLD <= '0'; + RXDFELFHOLD <= '0'; + RXLPMLFHOLD <= '0'; + RXLPMHFHOLD <= '0'; + + else + + case rx_state is + when INIT => + --Initial state after configuration. This state will be left after + --approx. 500 ns and not be re-entered. + if init_wait_done = '1' then + rx_state <= ASSERT_ALL_RESETS; + end if; + + when ASSERT_ALL_RESETS => + --This is the state into which the FSM will always jump back if any + --time-outs will occur. + --The number of retries is reported on the output RETRY_COUNTER. In + --case the transceiver never comes up for some reason, this machine + --will still continue its best and rerun until the FPGA is turned off + --or the transceivers come up correctly. + if RX_QPLL_USED and not TX_QPLL_USED then + if pll_reset_asserted = '0' then + QPLL_RESET <= '1'; + pll_reset_asserted <= '1'; + else + QPLL_RESET <= '0'; + end if; + elsif not RX_QPLL_USED and TX_QPLL_USED then + if pll_reset_asserted = '0' then + CPLL_RESET <= '1'; + pll_reset_asserted <= '1'; + else + CPLL_RESET <= '0'; + end if; + end if; + + RXUSERRDY <= '0'; + GTRXRESET <= '1'; + MMCM_RESET <= '1'; + run_phase_alignment_int <= '0'; + RESET_PHALIGNMENT <= '1'; + check_tlock_max <= '0'; + recclk_mon_count_reset <= '1'; + adapt_count_reset <= '1'; + + + if (RX_QPLL_USED and not TX_QPLL_USED and (QPLLREFCLKLOST = '0') and pll_reset_asserted = '1') or + (not RX_QPLL_USED and TX_QPLL_USED and (CPLLREFCLKLOST = '0') and pll_reset_asserted = '1') or + (not RX_QPLL_USED and not TX_QPLL_USED and (CPLLREFCLKLOST = '0') ) or + (RX_QPLL_USED and TX_QPLL_USED and (QPLLREFCLKLOST = '0') ) then + rx_state <= RELEASE_PLL_RESET; + reset_time_out <= '1'; + end if; + + when RELEASE_PLL_RESET => + --PLL-Reset of the GTX gets released and the time-out counter + --starts running. + pll_reset_asserted <= '0'; + reset_time_out <= '0'; + + + if (RX_QPLL_USED and not TX_QPLL_USED and (qplllock_ris_edge = '1')) or + (not RX_QPLL_USED and TX_QPLL_USED and (cplllock_ris_edge = '1')) then + rx_state <= VERIFY_RECCLK_STABLE; + reset_time_out <= '1'; + recclk_mon_count_reset <= '0'; + adapt_count_reset <= '0'; + + elsif (RX_QPLL_USED and (qplllock_sync = '1')) or + (not RX_QPLL_USED and (cplllock_sync = '1')) then + rx_state <= VERIFY_RECCLK_STABLE; + reset_time_out <= '1'; + recclk_mon_count_reset <= '0'; + adapt_count_reset <= '0'; + end if; + + if time_out_2ms = '1' then + if retry_counter_int = MAX_RETRIES then + -- If too many retries are performed compared to what is specified in + -- the generic, the counter simply wraps around. + retry_counter_int <= 0; + else + retry_counter_int <= retry_counter_int + 1; + end if; + rx_state <= ASSERT_ALL_RESETS; + end if; + + when VERIFY_RECCLK_STABLE => + --reset_time_out <= '0'; + --Time-out counter is not released in this state as here the FSM + --does not wait for a certain period of time but checks on the number + --of retries in the RECCLK monitor + GTRXRESET <= '0'; + if RECCLK_STABLE = '1' then + rx_state <= RELEASE_MMCM_RESET; + reset_time_out <= '1'; + + end if; + + if recclk_mon_restart_count = 2 then + --If two retries are performed in the RECCLK monitor + --the whole initialisation-sequence gets restarted. + if retry_counter_int = MAX_RETRIES then + -- If too many retries are performed compared to what is specified in + -- the generic, the counter simply wraps around. + retry_counter_int <= 0; + else + retry_counter_int <= retry_counter_int + 1; + end if; + rx_state <= ASSERT_ALL_RESETS; + end if; + + when RELEASE_MMCM_RESET => + --Release of the MMCM-reset. Waiting for the MMCM to lock. + reset_time_out <= '0'; + check_tlock_max <= '1'; + + MMCM_RESET <= '0'; + if mmcm_lock_reclocked = '1' then + rx_state <= WAIT_RESET_DONE; + reset_time_out <= '1'; + end if; + + if time_tlock_max = '1' then + if retry_counter_int = MAX_RETRIES then + -- If too many retries are performed compared to what is specified in + -- the generic, the counter simply wraps around. + retry_counter_int <= 0; + else + retry_counter_int <= retry_counter_int + 1; + end if; + rx_state <= ASSERT_ALL_RESETS; + end if; + + when WAIT_RESET_DONE => + --When TXOUTCLK is the source for RXUSRCLK, RXUSERRDY depends on TXUSERRDY + --If RXOUTCLK is the source for RXUSRCLK, TXUSERRDY can be tied to '1' + if TXUSERRDY = '1' then + RXUSERRDY <= '1'; + end if; + reset_time_out <= '0'; + if rxresetdone_s3 = '1' then + rx_state <= DO_PHASE_ALIGNMENT; + reset_time_out <= '1'; + end if; + + if time_out_2ms = '1' then + if retry_counter_int = MAX_RETRIES then + -- If too many retries are performed compared to what is specified in + -- the generic, the counter simply wraps around. + retry_counter_int <= 0; + else + retry_counter_int <= retry_counter_int + 1; + end if; + rx_state <= ASSERT_ALL_RESETS; + end if; + + when DO_PHASE_ALIGNMENT => + --The direct handling of the signals for the Phase Alignment is done outside + --this state-machine. + RESET_PHALIGNMENT <= '0'; + run_phase_alignment_int <= '1'; + reset_time_out <= '0'; + + if PHALIGNMENT_DONE = '1' then + rx_state <= MONITOR_DATA_VALID; + reset_time_out <= '1'; + end if; + + if time_out_wait_bypass_s3 = '1' then + if retry_counter_int = MAX_RETRIES then + -- If too many retries are performed compared to what is specified in + -- the generic, the counter simply wraps around. + retry_counter_int <= 0; + else + retry_counter_int <= retry_counter_int + 1; + end if; + rx_state <= ASSERT_ALL_RESETS; + end if; + + when MONITOR_DATA_VALID => + reset_time_out <= '0'; + + if(time_out_100us = '1' and data_valid_sync ='0' and DONT_RESET_ON_DATA_ERROR = '0') then + rx_state <= ASSERT_ALL_RESETS; + rx_fsm_reset_done_int <= '0'; + elsif (data_valid_sync = '1') then + rx_state <= FSM_DONE; + rx_fsm_reset_done_int <= '0'; + reset_time_out <= '1'; + end if; + + when FSM_DONE => + reset_time_out <= '0'; + if data_valid_sync = '0' then + rx_fsm_reset_done_int <= '0'; + reset_time_out <= '1'; + rx_state <= MONITOR_DATA_VALID; + elsif(time_out_1us = '1') then + rx_fsm_reset_done_int <= '1'; + end if; + + if(time_out_adapt = '1') then + if((GT_TYPE = "GTX" ) and EQ_MODE = "DFE") then + RXDFEAGCHOLD <= '1'; + RXDFELFHOLD <= '1'; + else + RXDFEAGCHOLD <= '0'; + RXDFELFHOLD <= '0'; + RXLPMHFHOLD <= '0'; + RXLPMLFHOLD <= '0'; + end if; + end if; + + when OTHERS => + rx_state <= INIT; + end case; + end if; + end if; + end process; + +end RTL; + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_sync_block.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_sync_block.vhd new file mode 100644 index 0000000..eb749bc --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_sync_block.vhd @@ -0,0 +1,144 @@ +--//////////////////////////////////////////////////////////////////////////////// +--// ____ ____ +--// / /\/ / +--// /___/ \ / Vendor: Xilinx +--// \ \ \/ Version : 2.6 +--// \ \ Application : 7 Series FPGAs Transceivers Wizard +--// / / Filename :gtxkintex7fee80_sync_block.vhd +--// /___/ /\ +--// \ \ / \ +--// \___\/\___\ +--// +--// +-- +-- Description: Used on signals crossing from one clock domain to +-- another, this is a flip-flop pair, with both flops +-- placed together with RLOCs into the same slice. Thus +-- the routing delay between the two is minimum to safe- +-- guard against metastability issues. +-- +-- +-- Module gtxKintex7FEE80_sync_block +-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard +-- +-- +-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + + + + + +library ieee; +use ieee.std_logic_1164.all; + +library unisim; +use unisim.vcomponents.all; + +entity gtxkintex7fee80_sync_block is + generic ( + INITIALISE : bit_vector(1 downto 0) := "00" + ); + port ( + clk : in std_logic; -- clock to be sync'ed to + data_in : in std_logic; -- Data to be 'synced' + data_out : out std_logic -- synced data + ); + +end gtxkintex7fee80_sync_block; + + +architecture structural of gtxkintex7fee80_sync_block is + + + -- Internal Signals + signal data_sync1 : std_logic; + + -- These attributes will stop Vivado translating the desired flip-flops into an + -- SRL based shift register. + attribute ASYNC_REG : string; + attribute ASYNC_REG of data_sync : label is "TRUE"; + attribute ASYNC_REG of data_sync_reg : label is "TRUE"; + + -- These attributes will stop timing errors being reported on the target flip-flop during back annotated SDF simulation. + attribute MSGON : string; + attribute MSGON of data_sync : label is "FALSE"; + attribute MSGON of data_sync_reg : label is "FALSE"; + + -- These attributes will stop XST translating the desired flip-flops into an + -- SRL based shift register. + attribute shreg_extract : string; + attribute shreg_extract of data_sync : label is "no"; + attribute shreg_extract of data_sync_reg : label is "no"; + + +begin + + data_sync : FD + generic map ( + INIT => INITIALISE(0) + ) + port map ( + C => clk, + D => data_in, + Q => data_sync1 + ); + + + data_sync_reg : FD + generic map ( + INIT => INITIALISE(1) + ) + port map ( + C => clk, + D => data_sync1, + Q => data_out + ); + + +end structural; + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_sync_pulse.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_sync_pulse.vhd new file mode 100644 index 0000000..c9ede59 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_sync_pulse.vhd @@ -0,0 +1,157 @@ +--//////////////////////////////////////////////////////////////////////////////// +--// ____ ____ +--// / /\/ / +--// /___/ \ / Vendor: Xilinx +--// \ \ \/ Version : 2.6 +--// \ \ Application : 7 Series FPGAs Transceivers Wizard +--// / / Filename :gtxkintex7fee80_sync_pulse.vhd +--// /___/ /\ +--// \ \ / \ +--// \___\/\___\ +--// +--// +-- +-- Description: Used on signals crossing from faster clock domain +-- +-- +-- Module gtxKintex7FEE80_sync_pulse +-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard +-- +-- +-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + + + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gtxkintex7fee80_sync_pulse is + Generic( + C_NUM_SRETCH_REGS : integer := 3; + C_NUM_SYNC_REGS : integer := 3 + ); + + Port ( + -- Clock and Reset + CLK : in STD_LOGIC; + -- User Interface + USER_DONE : out STD_LOGIC := '0'; + -- GT Interface + GT_DONE : in STD_LOGIC + + ); +end gtxkintex7fee80_sync_pulse; + +architecture RTL of gtxkintex7fee80_sync_pulse is + +-- --------------------------------------------------------------------------- +-- Wire and Register Declaration +-- --------------------------------------------------------------------------- +signal stretch_r : std_logic_vector (C_NUM_SRETCH_REGS-1 downto 0):= (others=>'0'); +signal sync1_r : std_logic_vector (C_NUM_SYNC_REGS-1 downto 0):= (others=>'0'); +signal sync2_r : std_logic_vector (C_NUM_SYNC_REGS-1 downto 0):= (others=>'0'); + + -- These attributes will stop Vivado translating the desired flip-flops into an + -- SRL based shift register. + attribute ASYNC_REG : string; + attribute ASYNC_REG of sync1_r : signal is "TRUE"; + attribute ASYNC_REG of sync2_r : signal is "TRUE"; + + -- These attributes will stop XST translating the desired flip-flops into an + -- SRL based shift register. + attribute shreg_extract : string; + attribute shreg_extract of sync1_r : signal is "no"; + attribute shreg_extract of sync2_r : signal is "no"; + + +begin +------------------------------------------------------------------------------ +-- Stretch GT_DONE Signal +------------------------------------------------------------------------------ + process (CLK,GT_DONE) + begin + if (GT_DONE = '0') then + stretch_r <= (others=>'0'); + elsif (CLK'event and CLK = '1') then + stretch_r <= ('1' & stretch_r(C_NUM_SRETCH_REGS-1 downto 1)); + end if; + end process; + +------------------------------------------------------------------------------ +-- Synchronizers +------------------------------------------------------------------------------ + process (CLK) + begin + if (CLK'event and CLK = '1') then + sync1_r <= (stretch_r(0) & sync1_r(C_NUM_SYNC_REGS-1 downto 1)); + end if; + end process; + + process (CLK) + begin + if (CLK'event and CLK = '1') then + sync2_r <= (GT_DONE & sync2_r(C_NUM_SYNC_REGS-1 downto 1)); + end if; + end process; + +------------------------------------------------------------------------------ +-- Final Flop Stage with AND of both synchronizers - keeps USER_DONE low +-- when input is low for many cycles... +------------------------------------------------------------------------------ + process (CLK) + begin + if (CLK'event and CLK = '1') then + USER_DONE <= sync1_r(0) and sync2_r(0); + end if; + end process; + +end RTL; + + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_top.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_top.vhd new file mode 100644 index 0000000..b6dcc22 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_top.vhd @@ -0,0 +1,929 @@ +------------------------------------------------------------------------------ +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 2.6 +-- \ \ Application : 7 Series FPGAs Transceivers Wizard +-- / / Filename : gtxkintex7fee80_init.vhd +-- /___/ /\ +-- \ \ / \ +-- \___\/\___\ +-- +-- Description : This module instantiates the modules required for +-- reset and initialisation of the Transceiver +-- +-- Module gtxKintex7FEE80_init +-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard +-- +-- +-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; + +--***********************************Entity Declaration************************ + +entity gtxKintex7FEE80_top is +generic +( + EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model + EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation + STABLE_CLOCK_PERIOD : integer := 12; --Period of the stable clock driving this state-machine, unit is [ns] + EXAMPLE_USE_CHIPSCOPE : integer := 0 -- Set to 1 to use Chipscope to drive resets + +); +port +( + SYSCLK_IN : in std_logic; + SOFT_RESET_IN : in std_logic; + DONT_RESET_ON_DATA_ERROR_IN : in std_logic; + GT0_TX_FSM_RESET_DONE_OUT : out std_logic; + GT0_RX_FSM_RESET_DONE_OUT : out std_logic; + GT0_DATA_VALID_IN : in std_logic; + GT0_TX_MMCM_LOCK_IN : in std_logic; + GT0_TX_MMCM_RESET_OUT : out std_logic; + + --_________________________________________________________________________ + --GT0 (X1Y0) + --____________________________CHANNEL PORTS________________________________ + --------------------------------- CPLL Ports ------------------------------- + GT0_CPLLFBCLKLOST_OUT : out std_logic; + GT0_CPLLLOCK_OUT : out std_logic; + GT0_CPLLLOCKDETCLK_IN : in std_logic; + GT0_CPLLRESET_IN : in std_logic; + -------------------------- Channel - Clocking Ports ------------------------ + GT0_GTREFCLK0_IN : in std_logic; + ---------------------------- Channel - DRP Ports -------------------------- + GT0_DRPADDR_IN : in std_logic_vector(8 downto 0); + GT0_DRPCLK_IN : in std_logic; + GT0_DRPDI_IN : in std_logic_vector(15 downto 0); + GT0_DRPDO_OUT : out std_logic_vector(15 downto 0); + GT0_DRPEN_IN : in std_logic; + GT0_DRPRDY_OUT : out std_logic; + GT0_DRPWE_IN : in std_logic; + --------------------- RX Initialization and Reset Ports -------------------- + GT0_RXUSERRDY_IN : in std_logic; + -------------------------- RX Margin Analysis Ports ------------------------ + GT0_EYESCANDATAERROR_OUT : out std_logic; + ------------------------- Receive Ports - CDR Ports ------------------------ + GT0_RXCDRRESET_IN : in std_logic; + GT0_RXCDRLOCK_OUT : out std_logic; + ------------------ Receive Ports - FPGA RX Interface Ports ----------------- + GT0_RXUSRCLK_IN : in std_logic; + GT0_RXUSRCLK2_IN : in std_logic; + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + GT0_RXDATA_OUT : out std_logic_vector(15 downto 0); + ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- + GT0_RXDISPERR_OUT : out std_logic_vector(1 downto 0); + GT0_RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0); + --------------------------- Receive Ports - RX AFE ------------------------- + GT0_GTXRXP_IN : in std_logic; + ------------------------ Receive Ports - RX AFE Ports ---------------------- + GT0_GTXRXN_IN : in std_logic; + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + GT0_RXPHMONITOR_OUT : out std_logic_vector(4 downto 0); + GT0_RXPHSLIPMONITOR_OUT : out std_logic_vector(4 downto 0); + --------------- Receive Ports - RX Fabric Output Control Ports ------------- + GT0_RXOUTCLK_OUT : out std_logic; + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + GT0_GTRXRESET_IN : in std_logic; + GT0_RXPMARESET_IN : in std_logic; + ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- + GT0_RXCHARISK_OUT : out std_logic_vector(1 downto 0); + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + GT0_RXRESETDONE_OUT : out std_logic; + --------------------- TX Initialization and Reset Ports -------------------- + GT0_GTTXRESET_IN : in std_logic; + GT0_TXUSERRDY_IN : in std_logic; + ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- + GT0_TXUSRCLK_IN : in std_logic; + GT0_TXUSRCLK2_IN : in std_logic; + ------------------ Transmit Ports - TX Data Path interface ----------------- + GT0_TXDATA_IN : in std_logic_vector(15 downto 0); + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + GT0_GTXTXN_OUT : out std_logic; + GT0_GTXTXP_OUT : out std_logic; + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + GT0_TXOUTCLK_OUT : out std_logic; + GT0_TXOUTCLKFABRIC_OUT : out std_logic; + GT0_TXOUTCLKPCS_OUT : out std_logic; + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + GT0_TXCHARISK_IN : in std_logic_vector(1 downto 0); + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + GT0_TXRESETDONE_OUT : out std_logic; + + + --____________________________COMMON PORTS________________________________ + ---------------------- Common Block - Ref Clock Ports --------------------- + GT0_GTREFCLK0_COMMON_IN : in std_logic; + ------------------------- Common Block - QPLL Ports ------------------------ + GT0_QPLLLOCK_OUT : out std_logic; + GT0_QPLLLOCKDETCLK_IN : in std_logic; + GT0_QPLLRESET_IN : in std_logic; + testword0 : out std_logic_vector(35 downto 0) := (others => '0') + + +); + +end gtxKintex7FEE80_top; + +architecture RTL of gtxKintex7FEE80_top is + +--**************************Component Declarations***************************** + + +component gtxKintex7FEE80 +generic +( + -- Simulation attributes + WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" -- Set to 1 to speed up sim reset + +); +port +( + + --_________________________________________________________________________ + --_________________________________________________________________________ + --GT0 (X1Y0) + --____________________________CHANNEL PORTS________________________________ + --------------------------------- CPLL Ports ------------------------------- + GT0_CPLLFBCLKLOST_OUT : out std_logic; + GT0_CPLLLOCK_OUT : out std_logic; + GT0_CPLLLOCKDETCLK_IN : in std_logic; + GT0_CPLLREFCLKLOST_OUT : out std_logic; + GT0_CPLLRESET_IN : in std_logic; + -------------------------- Channel - Clocking Ports ------------------------ + GT0_GTREFCLK0_IN : in std_logic; + ---------------------------- Channel - DRP Ports -------------------------- + GT0_DRPADDR_IN : in std_logic_vector(8 downto 0); + GT0_DRPCLK_IN : in std_logic; + GT0_DRPDI_IN : in std_logic_vector(15 downto 0); + GT0_DRPDO_OUT : out std_logic_vector(15 downto 0); + GT0_DRPEN_IN : in std_logic; + GT0_DRPRDY_OUT : out std_logic; + GT0_DRPWE_IN : in std_logic; + --------------------- RX Initialization and Reset Ports -------------------- + GT0_RXUSERRDY_IN : in std_logic; + -------------------------- RX Margin Analysis Ports ------------------------ + GT0_EYESCANDATAERROR_OUT : out std_logic; + ------------------------- Receive Ports - CDR Ports ------------------------ + GT0_RXCDRRESET_IN : in std_logic; + GT0_RXCDRLOCK_OUT : out std_logic; + ------------------ Receive Ports - FPGA RX Interface Ports ----------------- + GT0_RXUSRCLK_IN : in std_logic; + GT0_RXUSRCLK2_IN : in std_logic; + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + GT0_RXDATA_OUT : out std_logic_vector(15 downto 0); + ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- + GT0_RXDISPERR_OUT : out std_logic_vector(1 downto 0); + GT0_RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0); + --------------------------- Receive Ports - RX AFE ------------------------- + GT0_GTXRXP_IN : in std_logic; + ------------------------ Receive Ports - RX AFE Ports ---------------------- + GT0_GTXRXN_IN : in std_logic; + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + GT0_RXDLYEN_IN : in std_logic; + GT0_RXDLYSRESET_IN : in std_logic; + GT0_RXDLYSRESETDONE_OUT : out std_logic; + GT0_RXPHALIGN_IN : in std_logic; + GT0_RXPHALIGNDONE_OUT : out std_logic; + GT0_RXPHALIGNEN_IN : in std_logic; + GT0_RXPHDLYRESET_IN : in std_logic; + GT0_RXPHMONITOR_OUT : out std_logic_vector(4 downto 0); + GT0_RXPHSLIPMONITOR_OUT : out std_logic_vector(4 downto 0); + -------------------- Receive Ports - RX Equailizer Ports ------------------- + GT0_RXLPMHFHOLD_IN : in std_logic; + GT0_RXLPMLFHOLD_IN : in std_logic; + --------------- Receive Ports - RX Fabric Output Control Ports ------------- + GT0_RXOUTCLK_OUT : out std_logic; + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + GT0_GTRXRESET_IN : in std_logic; + GT0_RXPCSRESET_IN : in std_logic; + GT0_RXPMARESET_IN : in std_logic; + ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- + GT0_RXCHARISK_OUT : out std_logic_vector(1 downto 0); + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + GT0_RXRESETDONE_OUT : out std_logic; + --------------------- TX Initialization and Reset Ports -------------------- + GT0_GTTXRESET_IN : in std_logic; + GT0_TXUSERRDY_IN : in std_logic; + ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- + GT0_TXUSRCLK_IN : in std_logic; + GT0_TXUSRCLK2_IN : in std_logic; + ------------------ Transmit Ports - TX Buffer Bypass Ports ----------------- + GT0_TXDLYEN_IN : in std_logic; + GT0_TXDLYSRESET_IN : in std_logic; + GT0_TXDLYSRESETDONE_OUT : out std_logic; + GT0_TXPHALIGN_IN : in std_logic; + GT0_TXPHALIGNDONE_OUT : out std_logic; + GT0_TXPHALIGNEN_IN : in std_logic; + GT0_TXPHDLYRESET_IN : in std_logic; + GT0_TXPHINIT_IN : in std_logic; + GT0_TXPHINITDONE_OUT : out std_logic; + ------------------ Transmit Ports - TX Data Path interface ----------------- + GT0_TXDATA_IN : in std_logic_vector(15 downto 0); + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + GT0_GTXTXN_OUT : out std_logic; + GT0_GTXTXP_OUT : out std_logic; + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + GT0_TXOUTCLK_OUT : out std_logic; + GT0_TXOUTCLKFABRIC_OUT : out std_logic; + GT0_TXOUTCLKPCS_OUT : out std_logic; + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + GT0_TXCHARISK_IN : in std_logic_vector(1 downto 0); + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + GT0_TXRESETDONE_OUT : out std_logic; + + + --____________________________COMMON PORTS________________________________ + ---------------------- Common Block - Ref Clock Ports --------------------- + GT0_GTREFCLK0_COMMON_IN : in std_logic; + ------------------------- Common Block - QPLL Ports ------------------------ + GT0_QPLLLOCK_OUT : out std_logic; + GT0_QPLLLOCKDETCLK_IN : in std_logic; + GT0_QPLLREFCLKLOST_OUT : out std_logic; + GT0_QPLLRESET_IN : in std_logic + +); +end component; + +component gtxKintex7FEE80_TX_STARTUP_FSM + Generic( + GT_TYPE : string := "GTX"; + STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns] + RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8; + TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must + RX_QPLL_USED : boolean := False; -- share these two generic values + PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic + -- is enough. For single-lane applications the automatic alignment is + -- sufficient + ); + Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB + --or reference-clock present at startup. + TXUSERCLK : in STD_LOGIC; --TXUSERCLK as used in the design + SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time + QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost + CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost + QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT + CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT + TXRESETDONE : in STD_LOGIC; + MMCM_LOCK : in STD_LOGIC; + GTTXRESET : out STD_LOGIC:='0'; + MMCM_RESET : out STD_LOGIC:='0'; + QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL + CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL + TX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished. + TXUSERRDY : out STD_LOGIC:='0'; + RUN_PHALIGNMENT : out STD_LOGIC:='0'; + RESET_PHALIGNMENT : out STD_LOGIC:='0'; + PHALIGNMENT_DONE : in STD_LOGIC; + + RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of + -- Retries it took to get the transceiver up and running + ); +end component; + +component gtxKintex7FEE80_RX_STARTUP_FSM + Generic( + EXAMPLE_SIMULATION : integer := 0; + EQ_MODE : string := "DFE"; + GT_TYPE : string := "GTX"; + STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns] + RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8; + TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must + RX_QPLL_USED : boolean := False; -- share these two generic values + PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic + -- is enough. For single-lane applications the automatic alignment is + -- sufficient + ); + Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB + --or reference-clock present at startup. + RXUSERCLK : in STD_LOGIC; --RXUSERCLK as used in the design + SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time + QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost + CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost + QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT + CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT + RXRESETDONE : in STD_LOGIC; + MMCM_LOCK : in STD_LOGIC; + RECCLK_STABLE : in STD_LOGIC; + RECCLK_MONITOR_RESTART : in STD_LOGIC; + DATA_VALID : in STD_LOGIC; + TXUSERRDY : in STD_LOGIC; --TXUSERRDY from GT + DONT_RESET_ON_DATA_ERROR : in STD_LOGIC; + GTRXRESET : out STD_LOGIC:='0'; + MMCM_RESET : out STD_LOGIC:='0'; + QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL (only if RX uses QPLL) + CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL (only if RX uses CPLL) + RX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished. + RXUSERRDY : out STD_LOGIC:='0'; + RUN_PHALIGNMENT : out STD_LOGIC; + PHALIGNMENT_DONE : in STD_LOGIC; + RESET_PHALIGNMENT : out STD_LOGIC:='0'; + RXDFEAGCHOLD : out STD_LOGIC; + RXDFELFHOLD : out STD_LOGIC; + RXLPMLFHOLD : out STD_LOGIC; + RXLPMHFHOLD : out STD_LOGIC; + RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of + -- Retries it took to get the transceiver up and running + ); +end component; + + + + +component gtxKintex7FEE80_AUTO_PHASE_ALIGN + Generic( + GT_TYPE : string := "GTX" + ); + port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB + --or reference-clock present at startup. + RUN_PHALIGNMENT : in STD_LOGIC; --Signal from the main Reset-FSM to run the auto phase-alignment procedure + PHASE_ALIGNMENT_DONE : out STD_LOGIC; -- Auto phase-alignment performed sucessfully + PHALIGNDONE : in STD_LOGIC; --\ Phase-alignment signals from and to the + DLYSRESET : out STD_LOGIC; -- |transceiver. + DLYSRESETDONE : in STD_LOGIC; --/ + RECCLKSTABLE : in STD_LOGIC --/on the RX-side. + + ); +end component; + + +component gtxKintex7FEE80_TX_MANUAL_PHASE_ALIGN + Generic( NUMBER_OF_LANES : integer range 1 to 32:= 4; -- Number of lanes that are controlled using this FSM. + MASTER_LANE_ID : integer range 0 to 31:= 0 -- Number of the lane which is considered the master in manual phase-alignment + ); + + Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB + --or reference-clock present at startup. + RESET_PHALIGNMENT : in STD_LOGIC; + RUN_PHALIGNMENT : in STD_LOGIC; + PHASE_ALIGNMENT_DONE : out STD_LOGIC := '0'; -- Manual phase-alignment performed sucessfully + TXDLYSRESET : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0'); + TXDLYSRESETDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0); + TXPHINIT : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0'); + TXPHINITDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0); + TXPHALIGN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0'); + TXPHALIGNDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0); + TXDLYEN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0') + ); +end component; + +component gtxKintex7FEE80_RX_MANUAL_PHASE_ALIGN + Generic( NUMBER_OF_LANES : integer range 1 to 32:= 4; -- Number of lanes that are controlled using this FSM. + MASTER_LANE_ID : integer range 0 to 31:= 0 -- Number of the lane which is considered the master in manual phase-alignment + ); + + Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB + --or reference-clock present at startup. + RESET_PHALIGNMENT : in STD_LOGIC; + RUN_PHALIGNMENT : in STD_LOGIC; + PHASE_ALIGNMENT_DONE : out STD_LOGIC := '0'; -- Manual phase-alignment performed sucessfully + RXDLYSRESET : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0'); + RXDLYSRESETDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0); + RXPHALIGN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0'); + RXPHALIGNDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0); + RXDLYEN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0') + ); +end component; + + function get_cdrlock_time(is_sim : in integer) return integer is + variable lock_time: integer; + begin + if (is_sim = 1) then + lock_time := 1000; + else + lock_time := 50000 / integer(2); --Typical CDR lock time is 50,000UI as per DS183 + end if; + return lock_time; + end function; + + +--***********************************Parameter Declarations******************** + + constant DLY : time := 1 ns; + constant RX_CDRLOCK_TIME : integer := get_cdrlock_time(EXAMPLE_SIMULATION); -- 200us + constant WAIT_TIME_CDRLOCK : integer := RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD; -- 200 us time-out + + -------------------------- GT Wrapper Wires ------------------------------ + signal gt0_cpllreset_i : std_logic; + signal gt0_cpllreset_t : std_logic; + signal gt0_cpllrefclklost_i : std_logic; + signal gt0_cplllock_i : std_logic; + signal gt0_txresetdone_i : std_logic; + signal gt0_rxresetdone_i : std_logic; + signal gt0_gttxreset_i : std_logic; + signal gt0_gttxreset_t : std_logic; + signal gt0_gtrxreset_i : std_logic; + signal gt0_gtrxreset_t : std_logic; + signal gt0_rxpcsreset_i : std_logic; + signal gt0_rxdfelpmreset_i : std_logic; + signal gt0_txuserrdy_i : std_logic; + signal gt0_txuserrdy_t : std_logic; + signal gt0_rxuserrdy_i : std_logic; + signal gt0_rxuserrdy_t : std_logic; + + signal gt0_rxdfeagchold_i : std_logic; + signal gt0_rxdfelfhold_i : std_logic; + signal gt0_rxlpmlfhold_i : std_logic; + signal gt0_rxlpmhfhold_i : std_logic; + + + + signal gt0_qpllreset_i : std_logic; + signal gt0_qpllreset_t : std_logic; + signal gt0_qpllrefclklost_i : std_logic; + signal gt0_qplllock_i : std_logic; + + + ------------------------------- Global Signals ----------------------------- + signal tied_to_ground_i : std_logic; + signal tied_to_vcc_i : std_logic; + signal gt0_txphaligndone_i : std_logic; + signal gt0_txdlysreset_i : std_logic; + signal gt0_txdlysresetdone_i : std_logic; + signal gt0_txphdlyreset_i : std_logic; + signal gt0_txphalignen_i : std_logic; + signal gt0_txdlyen_i : std_logic; + signal gt0_txphalign_i : std_logic; + signal gt0_txphinit_i : std_logic; + signal gt0_txphinitdone_i : std_logic; + signal gt0_run_tx_phalignment_i : std_logic; + signal gt0_rst_tx_phalignment_i : std_logic; + signal gt0_tx_phalignment_done_i : std_logic; + + signal gt0_rxoutclk_i : std_logic; + signal gt0_recclk_stable_i : std_logic; + signal gt0_rxphaligndone_i : std_logic; + signal gt0_rxdlysreset_i : std_logic; + signal gt0_rxdlysresetdone_i : std_logic; + signal gt0_rxphdlyreset_i : std_logic; + signal gt0_rxphalignen_i : std_logic; + signal gt0_rxdlyen_i : std_logic; + signal gt0_rxphalign_i : std_logic; + signal gt0_run_rx_phalignment_i : std_logic; + signal gt0_rst_rx_phalignment_i : std_logic; + signal gt0_rx_phalignment_done_i : std_logic; + + + + --------------------------- TX Buffer Bypass Signals -------------------- + signal mstr0_txsyncallin_i : std_logic; + signal U0_TXDLYEN : std_logic_vector(0 downto 0); + signal U0_TXDLYSRESET : std_logic_vector(0 downto 0); + signal U0_TXDLYSRESETDONE : std_logic_vector(0 downto 0); + signal U0_TXPHINIT : std_logic_vector(0 downto 0); + signal U0_TXPHINITDONE : std_logic_vector(0 downto 0); + signal U0_TXPHALIGN : std_logic_vector(0 downto 0); + signal U0_TXPHALIGNDONE : std_logic_vector(0 downto 0); + signal U0_run_tx_phalignment_i : std_logic; + signal U0_rst_tx_phalignment_i : std_logic; + + + --------------------------- RX Buffer Bypass Signals -------------------- + signal rxmstr0_rxsyncallin_i : std_logic; + + + signal rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ; + signal rx_cdrlocked : std_logic; + + + signal testword0_S : std_logic_vector(35 downto 0) := (others => '0'); + + + +--**************************** Main Body of Code ******************************* +begin + -- Static signal Assigments + tied_to_ground_i <= '0'; + tied_to_vcc_i <= '1'; + + ----------------------------- The GT Wrapper ----------------------------- + + -- Use the instantiation template in the example directory to add the GT wrapper to your design. + -- In this example, the wrapper is wired up for basic operation with a frame generator and frame + -- checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is + -- enabled, bonding should occur after alignment. + + + gtxKintex7FEE80_i : gtxKintex7FEE80 + generic map + ( + WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP + ) + port map + ( + + --_____________________________________________________________________ + --_____________________________________________________________________ + --GT0 (X1Y0) + + --------------------------------- CPLL Ports ------------------------------- + GT0_CPLLFBCLKLOST_OUT => GT0_CPLLFBCLKLOST_OUT, + GT0_CPLLLOCK_OUT => gt0_cplllock_i, + GT0_CPLLLOCKDETCLK_IN => GT0_CPLLLOCKDETCLK_IN, + GT0_CPLLREFCLKLOST_OUT => gt0_cpllrefclklost_i, + GT0_CPLLRESET_IN => gt0_cpllreset_i, + -------------------------- Channel - Clocking Ports ------------------------ + GT0_GTREFCLK0_IN => GT0_GTREFCLK0_IN, + ---------------------------- Channel - DRP Ports -------------------------- + GT0_DRPADDR_IN => GT0_DRPADDR_IN, + GT0_DRPCLK_IN => GT0_DRPCLK_IN, + GT0_DRPDI_IN => GT0_DRPDI_IN, + GT0_DRPDO_OUT => GT0_DRPDO_OUT, + GT0_DRPEN_IN => GT0_DRPEN_IN, + GT0_DRPRDY_OUT => GT0_DRPRDY_OUT, + GT0_DRPWE_IN => GT0_DRPWE_IN, + --------------------- RX Initialization and Reset Ports -------------------- + GT0_RXUSERRDY_IN => gt0_rxuserrdy_i, + -------------------------- RX Margin Analysis Ports ------------------------ + GT0_EYESCANDATAERROR_OUT => GT0_EYESCANDATAERROR_OUT, + ------------------------- Receive Ports - CDR Ports ------------------------ + GT0_RXCDRRESET_IN => GT0_RXCDRRESET_IN, + GT0_RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT, + ------------------ Receive Ports - FPGA RX Interface Ports ----------------- + GT0_RXUSRCLK_IN => GT0_RXUSRCLK_IN, + GT0_RXUSRCLK2_IN => GT0_RXUSRCLK2_IN, + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + GT0_RXDATA_OUT => GT0_RXDATA_OUT, + ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- + GT0_RXDISPERR_OUT => GT0_RXDISPERR_OUT, + GT0_RXNOTINTABLE_OUT => GT0_RXNOTINTABLE_OUT, + --------------------------- Receive Ports - RX AFE ------------------------- + GT0_GTXRXP_IN => GT0_GTXRXP_IN, + ------------------------ Receive Ports - RX AFE Ports ---------------------- + GT0_GTXRXN_IN => GT0_GTXRXN_IN, + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + GT0_RXDLYEN_IN => '0', -- gt0_rxdlyen_i, + GT0_RXDLYSRESET_IN => '1', -- gt0_rxdlysreset_i, + GT0_RXDLYSRESETDONE_OUT => gt0_rxdlysresetdone_i, + GT0_RXPHALIGN_IN => '0', -- gt0_rxphalign_i, + GT0_RXPHALIGNDONE_OUT => gt0_rxphaligndone_i, + GT0_RXPHALIGNEN_IN => '1', -- gt0_rxphalignen_i, + GT0_RXPHDLYRESET_IN => '1', -- gt0_rxphdlyreset_i, + GT0_RXPHMONITOR_OUT => GT0_RXPHMONITOR_OUT, + GT0_RXPHSLIPMONITOR_OUT => GT0_RXPHSLIPMONITOR_OUT, + -------------------- Receive Ports - RX Equailizer Ports ------------------- + GT0_RXLPMHFHOLD_IN => gt0_rxlpmhfhold_i, + GT0_RXLPMLFHOLD_IN => gt0_rxlpmlfhold_i, + --------------- Receive Ports - RX Fabric Output Control Ports ------------- + GT0_RXOUTCLK_OUT => gt0_rxoutclk_i, + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + GT0_GTRXRESET_IN => gt0_gtrxreset_i, + GT0_RXPCSRESET_IN => gt0_rxpcsreset_i, + GT0_RXPMARESET_IN => GT0_RXPMARESET_IN, + ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- + GT0_RXCHARISK_OUT => GT0_RXCHARISK_OUT, + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + GT0_RXRESETDONE_OUT => gt0_rxresetdone_i, + --------------------- TX Initialization and Reset Ports -------------------- + GT0_GTTXRESET_IN => gt0_gttxreset_i, + GT0_TXUSERRDY_IN => gt0_txuserrdy_i, + ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- + GT0_TXUSRCLK_IN => GT0_TXUSRCLK_IN, + GT0_TXUSRCLK2_IN => GT0_TXUSRCLK2_IN, + ------------------ Transmit Ports - TX Buffer Bypass Ports ----------------- + GT0_TXDLYEN_IN => gt0_txdlyen_i, + GT0_TXDLYSRESET_IN => gt0_txdlysreset_i, + GT0_TXDLYSRESETDONE_OUT => gt0_txdlysresetdone_i, + GT0_TXPHALIGN_IN => gt0_txphalign_i, + GT0_TXPHALIGNDONE_OUT => gt0_txphaligndone_i, + GT0_TXPHALIGNEN_IN => gt0_txphalignen_i, + GT0_TXPHDLYRESET_IN => gt0_txphdlyreset_i, + GT0_TXPHINIT_IN => gt0_txphinit_i, + GT0_TXPHINITDONE_OUT => gt0_txphinitdone_i, + ------------------ Transmit Ports - TX Data Path interface ----------------- + GT0_TXDATA_IN => GT0_TXDATA_IN, + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + GT0_GTXTXN_OUT => GT0_GTXTXN_OUT, + GT0_GTXTXP_OUT => GT0_GTXTXP_OUT, + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + GT0_TXOUTCLK_OUT => GT0_TXOUTCLK_OUT, + GT0_TXOUTCLKFABRIC_OUT => GT0_TXOUTCLKFABRIC_OUT, + GT0_TXOUTCLKPCS_OUT => GT0_TXOUTCLKPCS_OUT, + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + GT0_TXCHARISK_IN => GT0_TXCHARISK_IN, + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + GT0_TXRESETDONE_OUT => gt0_txresetdone_i, + + + + + --____________________________COMMON PORTS________________________________ + ---------------------- Common Block - Ref Clock Ports --------------------- + GT0_GTREFCLK0_COMMON_IN => GT0_GTREFCLK0_COMMON_IN, + ------------------------- Common Block - QPLL Ports ------------------------ + GT0_QPLLLOCK_OUT => gt0_qplllock_i, + GT0_QPLLLOCKDETCLK_IN => GT0_QPLLLOCKDETCLK_IN, + GT0_QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i, + GT0_QPLLRESET_IN => gt0_qpllreset_i + + ); + + gt0_rxpcsreset_i <= tied_to_ground_i; + + gt0_rxdfelpmreset_i <= tied_to_ground_i; + + + + + GT0_CPLLLOCK_OUT <= gt0_cplllock_i; + GT0_TXRESETDONE_OUT <= gt0_txresetdone_i; + GT0_RXRESETDONE_OUT <= gt0_rxresetdone_i; + GT0_RXOUTCLK_OUT <= gt0_rxoutclk_i; + GT0_QPLLLOCK_OUT <= gt0_qplllock_i; + +chipscope : if EXAMPLE_USE_CHIPSCOPE = 1 generate + gt0_cpllreset_i <= GT0_CPLLRESET_IN or gt0_cpllreset_t; + gt0_gttxreset_i <= GT0_GTTXRESET_IN or gt0_gttxreset_t; + gt0_gtrxreset_i <= GT0_GTRXRESET_IN or gt0_gtrxreset_t; + gt0_txuserrdy_i <= GT0_TXUSERRDY_IN or gt0_txuserrdy_t; + gt0_rxuserrdy_i <= GT0_RXUSERRDY_IN or gt0_rxuserrdy_t; + gt0_qpllreset_i <= GT0_QPLLRESET_IN or gt0_qpllreset_t; +end generate chipscope; + +no_chipscope : if EXAMPLE_USE_CHIPSCOPE = 0 generate + gt0_cpllreset_i <= gt0_cpllreset_t; + gt0_gttxreset_i <= gt0_gttxreset_t; + gt0_gtrxreset_i <= gt0_gtrxreset_t; + gt0_txuserrdy_i <= gt0_txuserrdy_t; + gt0_rxuserrdy_i <= gt0_rxuserrdy_t; + gt0_qpllreset_i <= gt0_qpllreset_t; +end generate no_chipscope; + + +gt0_txresetfsm_i: gtxKintex7FEE80_TX_STARTUP_FSM + + generic map( + GT_TYPE => "GTX", --GTX or GTH or GTP + STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns] + RETRY_COUNTER_BITWIDTH => 8, + TX_QPLL_USED => FALSE , -- the TX and RX Reset FSMs must + RX_QPLL_USED => FALSE, -- share these two generic values + PHASE_ALIGNMENT_MANUAL => TRUE -- Decision if a manual phase-alignment is necessary or the automatic + -- is enough. For single-lane applications the automatic alignment is + -- sufficient + ) + port map ( + STABLE_CLOCK => SYSCLK_IN, + TXUSERCLK => GT0_TXUSRCLK_IN, + SOFT_RESET => SOFT_RESET_IN, + QPLLREFCLKLOST => tied_to_ground_i, + CPLLREFCLKLOST => gt0_cpllrefclklost_i, + QPLLLOCK => tied_to_vcc_i, + CPLLLOCK => gt0_cplllock_i, + TXRESETDONE => gt0_txresetdone_i, + MMCM_LOCK => GT0_TX_MMCM_LOCK_IN, + GTTXRESET => gt0_gttxreset_t, + MMCM_RESET => GT0_TX_MMCM_RESET_OUT, + QPLL_RESET => open, + CPLL_RESET => gt0_cpllreset_t, + TX_FSM_RESET_DONE => GT0_TX_FSM_RESET_DONE_OUT, + TXUSERRDY => gt0_txuserrdy_t, + RUN_PHALIGNMENT => gt0_run_tx_phalignment_i, + RESET_PHALIGNMENT => gt0_rst_tx_phalignment_i, + PHALIGNMENT_DONE => gt0_tx_phalignment_done_i, + RETRY_COUNTER => open + ); + + + + + + +gt0_rxresetfsm_i: gtxKintex7FEE80_RX_STARTUP_FSM + + generic map( + EXAMPLE_SIMULATION => EXAMPLE_SIMULATION, + GT_TYPE => "GTX", --GTX or GTH or GTP + EQ_MODE => "LPM", --Rx Equalization Mode - Set to DFE or LPM + STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns] + RETRY_COUNTER_BITWIDTH => 8, + TX_QPLL_USED => FALSE , -- the TX and RX Reset FSMs must + RX_QPLL_USED => FALSE, -- share these two generic values + PHASE_ALIGNMENT_MANUAL => TRUE -- Decision if a manual phase-alignment is necessary or the automatic + -- is enough. For single-lane applications the automatic alignment is + -- sufficient + ) + port map ( + STABLE_CLOCK => SYSCLK_IN, + RXUSERCLK => GT0_RXUSRCLK_IN, + SOFT_RESET => SOFT_RESET_IN, + DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN, + QPLLREFCLKLOST => tied_to_ground_i, + CPLLREFCLKLOST => gt0_cpllrefclklost_i, + QPLLLOCK => tied_to_vcc_i, + CPLLLOCK => gt0_cplllock_i, + RXRESETDONE => gt0_rxresetdone_i, + MMCM_LOCK => tied_to_vcc_i, + RECCLK_STABLE => gt0_recclk_stable_i, + RECCLK_MONITOR_RESTART => tied_to_ground_i, + DATA_VALID => GT0_DATA_VALID_IN, + TXUSERRDY => tied_to_vcc_i, + GTRXRESET => gt0_gtrxreset_t, + MMCM_RESET => open, + QPLL_RESET => open, + CPLL_RESET => open, + RX_FSM_RESET_DONE => GT0_RX_FSM_RESET_DONE_OUT, + RXUSERRDY => gt0_rxuserrdy_t, + RUN_PHALIGNMENT => gt0_run_rx_phalignment_i, + RESET_PHALIGNMENT => gt0_rst_rx_phalignment_i, + PHALIGNMENT_DONE => gt0_rx_phalignment_done_i, + RXDFEAGCHOLD => gt0_rxdfeagchold_i, + RXDFELFHOLD => gt0_rxdfelfhold_i, + RXLPMLFHOLD => gt0_rxlpmlfhold_i, + RXLPMHFHOLD => gt0_rxlpmhfhold_i, + RETRY_COUNTER => open + ); + + + + cdrlock_timeout:process(SYSCLK_IN) + begin + if rising_edge(SYSCLK_IN) then + if(gt0_gtrxreset_i = '1') then + rx_cdrlocked <= '0'; + rx_cdrlock_counter <= 0 after DLY; + elsif (rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then + rx_cdrlocked <= '1'; + rx_cdrlock_counter <= rx_cdrlock_counter after DLY; + else + rx_cdrlock_counter <= rx_cdrlock_counter + 1 after DLY; + end if; + end if; + end process; + +gt0_recclk_stable_i <= rx_cdrlocked; + + + + --------------------------- TX Buffer Bypass Logic -------------------- + -- The TX SYNC Module drives the ports needed to Bypass the TX Buffer. + -- Include the TX SYNC module in your own design if TX Buffer is bypassed. + +--Manual + gt0_tx_manual_phase_i : gtxKintex7FEE80_TX_MANUAL_PHASE_ALIGN + generic map + ( NUMBER_OF_LANES => 1, + MASTER_LANE_ID => 0 + ) + port map + ( + STABLE_CLOCK => SYSCLK_IN, + RESET_PHALIGNMENT => U0_rst_tx_phalignment_i, --TODO + RUN_PHALIGNMENT => U0_run_tx_phalignment_i, --TODO + PHASE_ALIGNMENT_DONE => gt0_tx_phalignment_done_i, + TXDLYSRESET => U0_TXDLYSRESET, + TXDLYSRESETDONE => U0_TXDLYSRESETDONE, + TXPHINIT => U0_TXPHINIT, + TXPHINITDONE => U0_TXPHINITDONE, + TXPHALIGN => U0_TXPHALIGN, + TXPHALIGNDONE => U0_TXPHALIGNDONE, + TXDLYEN => U0_TXDLYEN + ); + + gt0_txphdlyreset_i <= tied_to_ground_i; + gt0_txphalignen_i <= tied_to_vcc_i; + gt0_txdlysreset_i <= U0_TXDLYSRESET(0); + gt0_txphinit_i <= U0_TXPHINIT(0); + gt0_txphalign_i <= U0_TXPHALIGN(0); + gt0_txdlyen_i <= U0_TXDLYEN(0); + U0_TXDLYSRESETDONE(0) <= gt0_txdlysresetdone_i; + U0_TXPHINITDONE(0) <= gt0_txphinitdone_i; + U0_TXPHALIGNDONE(0) <= gt0_txphaligndone_i; + + + + U0_run_tx_phalignment_i <= gt0_run_tx_phalignment_i + ; + + U0_rst_tx_phalignment_i <= gt0_rst_tx_phalignment_i + ; + + + + --------------------------- RX Buffer Bypass Logic -------------------- +-- The RX SYNC Module drives the ports needed to Bypass the RX Buffer. +-- Include the RX SYNC module in your own design if RX Buffer is bypassed. + + +--Auto + +gt0_rxphdlyreset_i <= tied_to_ground_i; --// '1'; --// +gt0_rxphalignen_i <= tied_to_ground_i; --//'1'; --// +gt0_rxdlyen_i <= tied_to_ground_i; +gt0_rxphalign_i <= tied_to_ground_i; + +gt0_rx_phalignment_done_i <= '1'; +gt0_rxdlysreset_i <= '1'; --// + + + +--gt0_rx_auto_phase_align_i : gtxKintex7FEE80_AUTO_PHASE_ALIGN +-- generic map( +-- GT_TYPE => "GTX" --GTX or GTH or GTP +-- ) +-- port map ( +-- STABLE_CLOCK => SYSCLK_IN, +-- RUN_PHALIGNMENT => gt0_run_rx_phalignment_i, +-- PHASE_ALIGNMENT_DONE => gt0_rx_phalignment_done_i, +-- PHALIGNDONE => gt0_rxphaligndone_i, +-- DLYSRESET => gt0_rxdlysreset_i, +-- DLYSRESETDONE => gt0_rxdlysresetdone_i, +-- RECCLKSTABLE => gt0_recclk_stable_i +-- ); + + + + + +--testword0(22) <= gt0_cplllock_i; +--testword0(23) <= gt0_cpllrefclklost_i; +--testword0(24) <= gt0_cpllreset_i; + + +--testword0(35 downto 22) <= testword0_S(35 downto 22); + +--testword0(22) <= SOFT_RESET_IN; +--testword0(23) <= gt0_cplllock_i; +--testword0(24) <= gt0_recclk_stable_i; +-- +--testword0(25) <= gt0_rxuserrdy_i; +--testword0(26) <= gt0_rxdlysreset_i; +--testword0(27) <= gt0_rxdlysresetdone_i; +--testword0(28) <= gt0_rxphaligndone_i; +--testword0(29) <= gt0_rxphdlyreset_i; +--testword0(30) <= gt0_gtrxreset_i; +-- +--testword0(31) <= gt0_rxpcsreset_i; +--testword0(32) <= gt0_rxresetdone_i; +-- +-- +--testword0(33) <= gt0_run_rx_phalignment_i; +--testword0(34) <= gt0_rst_rx_phalignment_i; +--testword0(35) <= gt0_rx_phalignment_done_i; + +--testword0(33) <= gt0_txresetdone_i; +--testword0(34) <= gt0_qpllrefclklost_i; +--testword0(35) <= gt0_qpllreset_i; + +--gt0_gttxreset_i +--gt0_txuserrdy_i +--gt0_txphaligndone_i +--gt0_txphdlyreset_i + + + + +end RTL; + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_tx_manual_phase_align.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_tx_manual_phase_align.vhd new file mode 100644 index 0000000..1db8669 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_tx_manual_phase_align.vhd @@ -0,0 +1,380 @@ +--//////////////////////////////////////////////////////////////////////////////// +--// ____ ____ +--// / /\/ / +--// /___/ \ / Vendor: Xilinx +--// \ \ \/ Version : 2.6 +--// \ \ Application : 7 Series FPGAs Transceivers Wizard +--// / / Filename : gtxkintex7fee80_tx_manual_phase_align.vhd +--// /___/ /\ +--// \ \ / \ +--// \___\/\___\ +--// +--// +-- Description : This module performs TX Buffer Phase Alignment in Manual Mode. +-- +-- +-- +-- Module gtxKintex7FEE80_tx_manual_phase_align +-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard +-- +-- +-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + + +--***************************************************************************** + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity gtxKintex7FEE80_TX_MANUAL_PHASE_ALIGN is + Generic( NUMBER_OF_LANES : integer range 1 to 32:= 4; -- Number of lanes that are controlled using this FSM. + MASTER_LANE_ID : integer range 0 to 31:= 0 -- Number of the lane which is considered the master in manual phase-alignment + ); + + Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB + --or reference-clock present at startup. + RESET_PHALIGNMENT : in STD_LOGIC; + RUN_PHALIGNMENT : in STD_LOGIC; + PHASE_ALIGNMENT_DONE : out STD_LOGIC := '0'; -- Manual phase-alignment performed sucessfully + TXDLYSRESET : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0'); + TXDLYSRESETDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0); + TXPHINIT : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0'); + TXPHINITDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0); + TXPHALIGN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0'); + TXPHALIGNDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0); + TXDLYEN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0') + ); +end gtxKintex7FEE80_TX_MANUAL_PHASE_ALIGN; + +architecture RTL of gtxKintex7FEE80_TX_MANUAL_PHASE_ALIGN is + + component gtxKintex7FEE80_sync_block + generic ( + INITIALISE : bit_vector(1 downto 0) := "00" + ); + port ( + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); + end component; + + component gtxkintex7fee80_sync_pulse + generic( + C_NUM_SRETCH_REGS : integer := 3; + C_NUM_SYNC_REGS : integer := 3 + ); + + port ( + CLK : in STD_LOGIC; + USER_DONE : out STD_LOGIC := '0'; + GT_DONE : in STD_LOGIC + + ); +end component; + + constant VCC_VEC : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '1'); + constant GND_VEC : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0'); + + signal txphaligndone_prev : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0'); + signal txphaligndone_ris_edge : std_logic_vector(NUMBER_OF_LANES-1 downto 0); + signal txphinitdone_prev : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0'); + signal txphinitdone_ris_edge : std_logic_vector(NUMBER_OF_LANES-1 downto 0); + signal txphinitdone_store_edge : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0'); + signal txphinitdone_clear_slave : std_logic:='0'; + signal txdlysresetdone_store : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0'); + signal txphaligndone_store : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0'); + signal txdone_clear : std_logic:='0'; + + + signal count_phalign_edges : integer range 0 to 3:= 0; + + + signal txphaligndone_sync : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0'); + signal txphinitdone_sync : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0'); + signal txdlysresetdone_sync : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0'); + + type tx_phase_align_manual_fsm is( + INIT, WAIT_PHRST_DONE, M_PHINIT, M_PHALIGN, M_DLYEN, + S_PHINIT, S_PHALIGN, M_DLYEN2, PHALIGN_DONE + ); + signal tx_phalign_manual_state : tx_phase_align_manual_fsm := INIT; + +begin + + cdc: for i in 0 to NUMBER_OF_LANES-1 generate + sync_TXPHALIGNDONE : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => TXPHALIGNDONE(i), + data_out => txphaligndone_sync(i) + ); + + sync_TXDLYSRESETDONE : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => TXDLYSRESETDONE(i), + data_out => txdlysresetdone_sync(i) + ); + + sync_TXPHINITDONE : gtxKintex7FEE80_sync_pulse + port map + ( + CLK => STABLE_CLOCK, + GT_DONE => TXPHINITDONE(i), + USER_DONE => txphinitdone_sync(i) + ); + end generate; + + process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + txphaligndone_prev <= txphaligndone_sync; + txphinitdone_prev <= txphinitdone_sync; + end if; + end process; + + + rising_edge_detect: for i in 0 to NUMBER_OF_LANES-1 generate + txphaligndone_ris_edge(i) <= '1' when (txphaligndone_prev(i) = '0') and (txphaligndone_sync(i) = '1') else '0'; + txphinitdone_ris_edge(i) <= '1' when (txphinitdone_prev(i) = '0') and (txphinitdone_sync(i) = '1') else '0'; + end generate; + + process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + if txdone_clear = '1' then + txdlysresetdone_store <= (others=>'0'); + txphaligndone_store <= (others=>'0'); + else + for i in 0 to NUMBER_OF_LANES-1 loop + if txdlysresetdone_sync(i) = '1' then + txdlysresetdone_store(i) <= '1'; + end if; + if txphaligndone_ris_edge(i) = '1' then + txphaligndone_store(i) <= '1'; + end if; + end loop; + end if; + end if; + end process; + + + + process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + if txphinitdone_clear_slave = '1' then + --Only clear the TXPHINITDONE-storage from the slaves. + txphinitdone_store_edge <= (others=>'0'); + --The information stored on the MASTER_LANE_ID is used differently. The way txphinitdone_store_edge + --is coded, it will be optimised away afterwards. It is only for simplicity of the code on the checks + --that the master-lane is "recorded" too. + txphinitdone_store_edge(MASTER_LANE_ID) <= '1'; + else + for i in 0 to NUMBER_OF_LANES-1 loop + if txphinitdone_ris_edge(i) = '1' then + txphinitdone_store_edge(i) <= '1'; + end if; + end loop; + end if; + end if; + end process; + + + + + process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + if RESET_PHALIGNMENT = '1' then + PHASE_ALIGNMENT_DONE <= '0'; + TXDLYSRESET <= (others=> '0'); + TXPHINIT <= (others=> '0'); + TXPHALIGN <= (others=> '0'); + TXDLYEN <= (others=> '0'); + tx_phalign_manual_state <= INIT; + txphinitdone_clear_slave <= '1'; + txdone_clear <= '1'; + else + case tx_phalign_manual_state is + when INIT => + PHASE_ALIGNMENT_DONE <= '0'; + txphinitdone_clear_slave <= '1'; + txdone_clear <= '1'; + if RUN_PHALIGNMENT = '1' then + --TXDLYSRESET is toggled to '1' + TXDLYSRESET <= (others=> '1'); + txphinitdone_clear_slave <= '0'; + txdone_clear <= '0'; + tx_phalign_manual_state <= WAIT_PHRST_DONE; + end if; + + when WAIT_PHRST_DONE => + --Assert TXDLYSRESET for all lanes, hold high until + --TXDLYSRESETDONE of the respective lane is asserted. + for i in 0 to NUMBER_OF_LANES - 1 loop + if txdlysresetdone_store(i) = '1' then + --Deassert TXDLYSRESET for the lane in which + --the TXDLYSRESETDONE is asserted: + TXDLYSRESET(i) <= '0'; + end if; + end loop; + if txdlysresetdone_store = VCC_VEC then + --When all TXDLYSRESETDONE-signals are asserted, move + --to the next state. + tx_phalign_manual_state <= M_PHINIT; + end if; + + when M_PHINIT => + --Assert TXPHINIT on the master and hold high until a + --rising edge on TXPHINITDONE is detected: + TXPHINIT(MASTER_LANE_ID) <= '1'; + if txphinitdone_ris_edge(MASTER_LANE_ID) = '1' then + --Then deassert TXPHINIT and move to the next state. + TXPHINIT(MASTER_LANE_ID) <= '0'; + tx_phalign_manual_state <= M_PHALIGN; + end if; + + when M_PHALIGN => + --Assert TXPHALIGN on the master and hold high until a + --rising edge on TXPHALIGNDONE is detected: + TXPHALIGN(MASTER_LANE_ID) <= '1'; + if txphaligndone_ris_edge(MASTER_LANE_ID) = '1' then + --Then dassert TXPHALIGN and move to the next state. + TXPHALIGN(MASTER_LANE_ID) <= '0'; + tx_phalign_manual_state <= M_DLYEN; + end if; + + when M_DLYEN => + --Assert TXDLYEN on the master and hold high until a + --rising edge on TXPHALIGNDONE is detected. + TXDLYEN(MASTER_LANE_ID) <= '1'; + if txphaligndone_ris_edge(MASTER_LANE_ID) = '1' then + --Then deassert TXDLYEN and move to the next state. + if(NUMBER_OF_LANES > 1) then + TXDLYEN(MASTER_LANE_ID) <= '0'; + tx_phalign_manual_state <= S_PHINIT; + else + tx_phalign_manual_state <= PHALIGN_DONE; + end if; + end if; + when S_PHINIT => + --Assert TXPHINIT for all slave lane(s). Hold this + --signal High until TXPHINITDONE of the respective + --slave lane is asserted. + TXPHINIT <= (others=>'1');--\Assert only the PHINIT-signal of + TXPHINIT(MASTER_LANE_ID) <= '0'; --/the slaves. + + for i in 0 to NUMBER_OF_LANES - 1 loop + if txphinitdone_store_edge(i) = '1' then + --Deassert TXPHINIT for the slave lane in which + --the TXPHINITDONE is asserted. + TXPHINIT(i) <= '0'; + end if; + end loop; + --if txphinitdone_store_edge = VCC_VEC and txphinitdone_ris_edge /= GND_VEC then + if txphinitdone_store_edge = VCC_VEC then + --When all TXPHINITDONE-signals are high and at least one rising edge + --has been detected, move to the next state. + --The reason for checking of the occurance of at least one rising edge + --is to avoid the potential direct move where TXPHINITDONE might not + --be going low fast enough. + tx_phalign_manual_state <= S_PHALIGN; + end if; + + when S_PHALIGN => + --Assert TXPHALIGN for all slave lane(s). Hold this signal High + --until TXPHALIGNDONE of the respective slave lane is asserted. + TXPHALIGN <= (others=>'1');--again only assertion for slave + TXPHALIGN(MASTER_LANE_ID) <= '0'; --but not for master + + for i in 0 to NUMBER_OF_LANES - 1 loop + --if txphaligndone_ris_edge(i) = '1' then + if txphaligndone_store(i) = '1' then + --Deassert TXPHALIGN for the slave lane in which the + --TXPHALIGNDONE is asserted. + TXPHALIGN(i) <= '0'; + end if; + end loop; + --if txphaligndone_store = VCC_VEC and txphaligndone_ris_edge /= GND_VEC then + if txphaligndone_store = VCC_VEC then + --When all TXPHALIGNDONE-signals are asserted high, move to the next + --state. + tx_phalign_manual_state <= M_DLYEN2; + end if; + + when M_DLYEN2 => + --Assert TXDLYEN for the master lane. This causes TXPHALIGNDONE of + --the master lane to be deasserted. + TXDLYEN(MASTER_LANE_ID) <= '1'; + if txphaligndone_ris_edge(MASTER_LANE_ID) = '1' then + --Wait until TXPHALIGNDONE of the master lane reasserts. Phase + --and delay alignment for the multilane interface is complete. + tx_phalign_manual_state <= PHALIGN_DONE; + end if; + + when PHALIGN_DONE => + --Continue to hold TXDLYEN for the master lane High to adjust + --TXUSRCLK to compensate for temperature and voltage variations. + TXDLYEN(MASTER_LANE_ID) <= '1'; + PHASE_ALIGNMENT_DONE <= '1'; + + when OTHERS => + tx_phalign_manual_state <= INIT; + + end case; + end if; + end if; + end process; + + +end RTL; + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_tx_startup_fsm.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_tx_startup_fsm.vhd new file mode 100644 index 0000000..7bd5f2d --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_tx_startup_fsm.vhd @@ -0,0 +1,562 @@ +--//////////////////////////////////////////////////////////////////////////////// +--// ____ ____ +--// / /\/ / +--// /___/ \ / Vendor: Xilinx +--// \ \ \/ Version : 2.6 +--// \ \ Application : 7 Series FPGAs Transceivers Wizard +--// / / Filename :gtxkintex7fee80_tx_startup_fsm.vhd +--// /___/ /\ +--// \ \ / \ +--// \___\/\___\ +--// +--// +-- Description : This module performs TX reset and initialization. +-- +-- +-- +-- Module gtxKintex7FEE80_tx_startup_fsm +-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard +-- +-- +-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + + +--***************************************************************************** + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gtxKintex7FEE80_TX_STARTUP_FSM is + Generic( GT_TYPE : string := "GTX"; + STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns] + RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8; + TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must + RX_QPLL_USED : boolean := False; -- share these two generic values + PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic + -- is enough. For single-lane applications the automatic alignment is + -- sufficient + ); + Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB + --or reference-clock present at startup. + TXUSERCLK : in STD_LOGIC; --TXUSERCLK as used in the design + SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time + QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost + CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost + QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT + CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT + TXRESETDONE : in STD_LOGIC; + MMCM_LOCK : in STD_LOGIC; + GTTXRESET : out STD_LOGIC:='0'; + MMCM_RESET : out STD_LOGIC:='1'; + QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL + CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL + TX_FSM_RESET_DONE : out STD_LOGIC; --Reset-sequence has sucessfully been finished. + TXUSERRDY : out STD_LOGIC:='0'; + RUN_PHALIGNMENT : out STD_LOGIC:='0'; + RESET_PHALIGNMENT : out STD_LOGIC:='0'; + PHALIGNMENT_DONE : in STD_LOGIC; + + RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of + -- Retries it took to get the transceiver up and running + ); +end gtxKintex7FEE80_TX_STARTUP_FSM; + +--Interdependencies: +-- * Timing depends on the frequency of the stable clock. Hence counters-sizes +-- are calculated at design-time based on the Generics +-- +-- * if either of PLLs is reset during TX-startup, it does not need to be reset again by RX +-- => signal which PLL has been reset +-- * + + + +architecture RTL of gtxKintex7FEE80_TX_STARTUP_FSM is + + component gtxKintex7FEE80_sync_block + generic ( + INITIALISE : bit_vector(1 downto 0) := "00" + ); + port ( + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); + end component; + + type tx_rst_fsm_type is( + INIT, ASSERT_ALL_RESETS, RELEASE_PLL_RESET, + RELEASE_MMCM_RESET, WAIT_RESET_DONE, DO_PHASE_ALIGNMENT, + RESET_FSM_DONE); + + signal tx_state : tx_rst_fsm_type := INIT; + + constant MMCM_LOCK_CNT_MAX : integer := 1024; + constant STARTUP_DELAY : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration + constant WAIT_CYCLES : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration + constant WAIT_MAX : integer := WAIT_CYCLES + 10; -- 500 ns plus some additional margin + + constant WAIT_TIMEOUT_2ms : integer := 2000000 / STABLE_CLOCK_PERIOD;-- 2 ms time-out + constant WAIT_TLOCK_MAX : integer := 100000 / STABLE_CLOCK_PERIOD;--100 us time-out + constant WAIT_TIMEOUT_500us : integer := 500000 / STABLE_CLOCK_PERIOD;--100 us time-out + + signal init_wait_count : integer range 0 to WAIT_MAX:=0; + signal init_wait_done : std_logic := '0'; + signal pll_reset_asserted : std_logic := '0'; + + signal tx_fsm_reset_done_int : std_logic := '0'; + signal tx_fsm_reset_done_int_s2 : std_logic := '0'; + signal tx_fsm_reset_done_int_s3 : std_logic := '0'; + + signal txresetdone_s2 : std_logic := '0'; + signal txresetdone_s3 : std_logic := '0'; + + constant MAX_RETRIES : integer := 2**RETRY_COUNTER_BITWIDTH-1; + signal retry_counter_int : integer range 0 to MAX_RETRIES; + signal time_out_counter : integer range 0 to WAIT_TIMEOUT_2ms := 0; + + signal reset_time_out : std_logic := '0'; + signal time_out_2ms : std_logic := '0';--\Flags that the various time-out points + signal time_tlock_max : std_logic := '0';--|have been reached. + signal time_out_500us : std_logic := '0';--/ + + signal mmcm_lock_count : integer range 0 to MMCM_LOCK_CNT_MAX-1:=0; + signal mmcm_lock_int : std_logic := '0'; + signal mmcm_lock_reclocked : std_logic := '0'; + + signal run_phase_alignment_int : std_logic := '0'; + signal run_phase_alignment_int_s2 : std_logic := '0'; + signal run_phase_alignment_int_s3 : std_logic := '0'; + + constant MAX_WAIT_BYPASS : integer := 110000; --110000 TXUSRCLK cycles is the max time for Multi lane designs + signal wait_bypass_count : integer range 0 to MAX_WAIT_BYPASS-1; + signal time_out_wait_bypass : std_logic := '0'; + signal time_out_wait_bypass_s2 : std_logic := '0'; + signal time_out_wait_bypass_s3 : std_logic := '0'; + signal refclk_lost : std_logic; + + signal cplllock_sync: std_logic := '0'; + signal qplllock_sync: std_logic := '0'; + signal cplllock_prev: std_logic := '0'; + signal qplllock_prev: std_logic := '0'; + signal cplllock_ris_edge: std_logic := '0'; + signal qplllock_ris_edge: std_logic := '0'; + +begin + --Alias section, signals used within this module mapped to output ports: + RETRY_COUNTER <= STD_LOGIC_VECTOR(TO_UNSIGNED(retry_counter_int,RETRY_COUNTER_BITWIDTH)); + RUN_PHALIGNMENT <= run_phase_alignment_int; + TX_FSM_RESET_DONE <= tx_fsm_reset_done_int; + + process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + -- The counter starts running when configuration has finished and + -- the clock is stable. When its maximum count-value has been reached, + -- the 500 ns from Answer Record 43482 have been passed. + if init_wait_count = WAIT_MAX then + init_wait_done <= '1'; + else + init_wait_count <= init_wait_count + 1; + end if; + end if; + end process; + + + timeouts:process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + -- One common large counter for generating three time-out signals. + -- Intermediate time-outs are derived from calculated values, based + -- on the period of the provided clock. + if reset_time_out = '1' then + time_out_counter <= 0; + time_out_2ms <= '0'; + time_tlock_max <= '0'; + time_out_500us <= '0'; + else + if time_out_counter = WAIT_TIMEOUT_2ms then + time_out_2ms <= '1'; + else + time_out_counter <= time_out_counter + 1; + end if; + + if time_out_counter = WAIT_TLOCK_MAX then + time_tlock_max <= '1'; + end if; + + if time_out_counter = WAIT_TIMEOUT_500us then + time_out_500us <= '1'; + end if; + end if; + end if; + end process; + + mmcm_lock_wait:process(TXUSERCLK) + begin + if rising_edge(TXUSERCLK) then + if MMCM_LOCK = '0' then + mmcm_lock_count <= 0; + mmcm_lock_int <= '0'; + else + if mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1 then + mmcm_lock_count <= mmcm_lock_count + 1; + else + mmcm_lock_int <= '1'; + end if; + end if; + end if; + end process; + + + + -- Clock Domain Crossing + + sync_run_phase_alignment_int : gtxKintex7FEE80_sync_block + port map + ( + clk => TXUSERCLK, + data_in => run_phase_alignment_int, + data_out => run_phase_alignment_int_s2 + ); + + sync_tx_fsm_reset_done_int : gtxKintex7FEE80_sync_block + port map + ( + clk => TXUSERCLK, + data_in => tx_fsm_reset_done_int, + data_out => tx_fsm_reset_done_int_s2 + ); + + process(TXUSERCLK) + begin + if rising_edge(TXUSERCLK) then + run_phase_alignment_int_s3 <= run_phase_alignment_int_s2; + + tx_fsm_reset_done_int_s3 <= tx_fsm_reset_done_int_s2; + end if; + end process; + + sync_TXRESETDONE : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => TXRESETDONE, + data_out => txresetdone_s2 + ); + + sync_time_out_wait_bypass : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => time_out_wait_bypass, + data_out => time_out_wait_bypass_s2 + ); + + sync_mmcm_lock_reclocked : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => mmcm_lock_int, + data_out => mmcm_lock_reclocked + ); + + process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + txresetdone_s3 <= txresetdone_s2; + + time_out_wait_bypass_s3 <= time_out_wait_bypass_s2; + cplllock_prev <= cplllock_sync; + qplllock_prev <= qplllock_sync; + end if; + end process; + + sync_CPLLLOCK : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => CPLLLOCK, + data_out => cplllock_sync + ); + + sync_QPLLLOCK : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => QPLLLOCK, + data_out => qplllock_sync + ); + + + process (STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + if(SOFT_RESET = '1' ) then + cplllock_ris_edge <= '0'; + elsif((cplllock_prev = '0') and (cplllock_sync = '1')) then + cplllock_ris_edge <= '1'; + elsif(tx_state = ASSERT_ALL_RESETS or tx_state = RELEASE_PLL_RESET) then + cplllock_ris_edge <= cplllock_ris_edge; + else + cplllock_ris_edge <= '0'; + end if; + end if; + end process; + + process (STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + if(SOFT_RESET = '1' ) then + qplllock_ris_edge <= '0'; + elsif((qplllock_prev = '0') and (qplllock_sync = '1')) then + qplllock_ris_edge <= '1'; + elsif(tx_state = ASSERT_ALL_RESETS or tx_state = RELEASE_PLL_RESET) then + qplllock_ris_edge <= qplllock_ris_edge; + else + qplllock_ris_edge <= '0'; + end if; + end if; + end process; + + + timeout_buffer_bypass:process(TXUSERCLK) + begin + if rising_edge(TXUSERCLK) then + if run_phase_alignment_int_s3 = '0' then + wait_bypass_count <= 0; + time_out_wait_bypass <= '0'; + elsif (run_phase_alignment_int_s3 = '1') and (tx_fsm_reset_done_int_s3 = '0') then + if wait_bypass_count = MAX_WAIT_BYPASS - 1 then + time_out_wait_bypass <= '1'; + else + wait_bypass_count <= wait_bypass_count + 1; + end if; + end if; + end if; + end process; + + refclk_lost <= '1' when ((TX_QPLL_USED and QPLLREFCLKLOST='1') or (not TX_QPLL_USED and CPLLREFCLKLOST='1')) else '0'; + + + --FSM for resetting the GTX/GTH/GTP in the 7-series. + --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + -- + -- Following steps are performed: + -- 1) Only for GTX - After configuration wait for approximately 500 ns as specified in + -- answer-record 43482 + -- 2) Assert all resets on the GT and on an MMCM potentially connected. + -- After that wait until a reference-clock has been detected. + -- 3) Release the reset to the GT and wait until the GT-PLL has locked. + -- 4) Release the MMCM-reset and wait until the MMCM has signalled lock. + -- Also signal to the RX-side which PLL has been reset. + -- 5) Wait for the RESET_DONE-signal from the GT. + -- 6) Signal to start the phase-alignment procedure and wait for it to + -- finish. + -- 7) Reset-sequence has successfully run through. Signal this to the + -- rest of the design by asserting TX_FSM_RESET_DONE. + + reset_fsm:process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + if(SOFT_RESET = '1' or (not(tx_state = INIT) and not(tx_state = ASSERT_ALL_RESETS) and refclk_lost = '1')) then + tx_state <= INIT; + TXUSERRDY <= '0'; + GTTXRESET <= '0'; + MMCM_RESET <= '1'; + tx_fsm_reset_done_int <= '0'; + QPLL_RESET <= '0'; + CPLL_RESET <= '0'; + pll_reset_asserted <= '0'; + reset_time_out <= '0'; + retry_counter_int <= 0; + run_phase_alignment_int <= '0'; + RESET_PHALIGNMENT <= '1'; + else + + case tx_state is + when INIT => + --Initial state after configuration. This state will be left after + --approx. 500 ns and not be re-entered. + if init_wait_done = '1' then + tx_state <= ASSERT_ALL_RESETS; + reset_time_out <= '1'; + end if; + + when ASSERT_ALL_RESETS => + --This is the state into which the FSM will always jump back if any + --time-outs will occur. + --The number of retries is reported on the output RETRY_COUNTER. In + --case the transceiver never comes up for some reason, this machine + --will still continue its best and rerun until the FPGA is turned off + --or the transceivers come up correctly. + if TX_QPLL_USED then + if pll_reset_asserted = '0' then + QPLL_RESET <= '1'; + pll_reset_asserted <= '1'; + else + QPLL_RESET <= '0'; + end if; + else + if pll_reset_asserted = '0' then + CPLL_RESET <= '1'; + pll_reset_asserted <= '1'; + else + CPLL_RESET <= '0'; + end if; + end if; + TXUSERRDY <= '0'; + GTTXRESET <= '1'; + MMCM_RESET <= '1'; + reset_time_out <= '0'; + run_phase_alignment_int <= '0'; + RESET_PHALIGNMENT <= '1'; + + if (TX_QPLL_USED and (QPLLREFCLKLOST = '0') and pll_reset_asserted = '1') or + (not TX_QPLL_USED and (CPLLREFCLKLOST = '0') and pll_reset_asserted = '1') then + tx_state <= RELEASE_PLL_RESET; + end if; + + when RELEASE_PLL_RESET => + --PLL-Reset of the GTX gets released and the time-out counter + --starts running. + pll_reset_asserted <= '0'; + + if (TX_QPLL_USED and (qplllock_ris_edge = '1')) or + (not TX_QPLL_USED and (cplllock_ris_edge = '1')) then + tx_state <= RELEASE_MMCM_RESET; + reset_time_out <= '1'; + end if; + + if time_out_2ms = '1' then + if retry_counter_int = MAX_RETRIES then + -- If too many retries are performed compared to what is specified in + -- the generic, the counter simply wraps around. + retry_counter_int <= 0; + else + retry_counter_int <= retry_counter_int + 1; + end if; + tx_state <= ASSERT_ALL_RESETS; + end if; + + when RELEASE_MMCM_RESET => + GTTXRESET <= '0'; + reset_time_out <= '0'; + --Release of the MMCM-reset. Waiting for the MMCM to lock. + MMCM_RESET <= '0'; + if mmcm_lock_reclocked = '1' then + tx_state <= WAIT_RESET_DONE; + reset_time_out <= '1'; + end if; + + if time_tlock_max = '1' and mmcm_lock_reclocked = '0' then + if retry_counter_int = MAX_RETRIES then + -- If too many retries are performed compared to what is specified in + -- the generic, the counter simply wraps around. + retry_counter_int <= 0; + else + retry_counter_int <= retry_counter_int + 1; + end if; + tx_state <= ASSERT_ALL_RESETS; + end if; + + when WAIT_RESET_DONE => + TXUSERRDY <= '1'; + reset_time_out <= '0'; + if txresetdone_s3 = '1' then + tx_state <= DO_PHASE_ALIGNMENT; + reset_time_out <= '1'; + end if; + + if time_out_500us = '1' then + if retry_counter_int = MAX_RETRIES then + -- If too many retries are performed compared to what is specified in + -- the generic, the counter simply wraps around. + retry_counter_int <= 0; + else + retry_counter_int <= retry_counter_int + 1; + end if; + tx_state <= ASSERT_ALL_RESETS; + end if; + + when DO_PHASE_ALIGNMENT => + --The direct handling of the signals for the Phase Alignment is done outside + --this state-machine. + RESET_PHALIGNMENT <= '0'; + run_phase_alignment_int <= '1'; + reset_time_out <= '0'; + + if PHALIGNMENT_DONE = '1' then + tx_state <= RESET_FSM_DONE; + end if; + + if time_out_wait_bypass_s3 = '1' then + if retry_counter_int = MAX_RETRIES then + -- If too many retries are performed compared to what is specified in + -- the generic, the counter simply wraps around. + retry_counter_int <= 0; + else + retry_counter_int <= retry_counter_int + 1; + end if; + tx_state <= ASSERT_ALL_RESETS; + end if; + + when RESET_FSM_DONE => + reset_time_out <= '1'; + tx_fsm_reset_done_int <= '1'; + + when OTHERS => + tx_state <= INIT; + + end case; + end if; + end if; + end process; + +end RTL; + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80.vhd new file mode 100644 index 0000000..ce90e86 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80.vhd @@ -0,0 +1,403 @@ +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 3.5 +-- \ \ Application : 7 Series FPGAs Transceivers Wizard +-- / / Filename : gtxkintex7fee80.vhd +-- /___/ /\ +-- \ \ / \ +-- \___\/\___\ +-- +-- +-- Module gtxKintex7FEE80 (a Core Top) +-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard +-- +-- +-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; + + +--***************************** Entity Declaration **************************** +entity gtxKintex7FEE80 is +port +( + SYSCLK_IN : in std_logic; + SOFT_RESET_TX_IN : in std_logic; + SOFT_RESET_RX_IN : in std_logic; + DONT_RESET_ON_DATA_ERROR_IN : in std_logic; + GT0_TX_FSM_RESET_DONE_OUT : out std_logic; + GT0_RX_FSM_RESET_DONE_OUT : out std_logic; + GT0_DATA_VALID_IN : in std_logic; + GT0_TX_MMCM_LOCK_IN : in std_logic; + GT0_TX_MMCM_RESET_OUT : out std_logic; + + --_________________________________________________________________________ + --GT0 (X1Y0) + --____________________________CHANNEL PORTS________________________________ + --------------------------------- CPLL Ports ------------------------------- + gt0_cpllfbclklost_out : out std_logic; + gt0_cplllock_out : out std_logic; + gt0_cplllockdetclk_in : in std_logic; + gt0_cpllreset_in : in std_logic; + -------------------------- Channel - Clocking Ports ------------------------ + gt0_gtrefclk0_in : in std_logic; + gt0_gtrefclk1_in : in std_logic; + ---------------------------- Channel - DRP Ports -------------------------- + gt0_drpaddr_in : in std_logic_vector(8 downto 0); + gt0_drpclk_in : in std_logic; + gt0_drpdi_in : in std_logic_vector(15 downto 0); + gt0_drpdo_out : out std_logic_vector(15 downto 0); + gt0_drpen_in : in std_logic; + gt0_drprdy_out : out std_logic; + gt0_drpwe_in : in std_logic; + --------------------------- Digital Monitor Ports -------------------------- + gt0_dmonitorout_out : out std_logic_vector(7 downto 0); + --------------------- RX Initialization and Reset Ports -------------------- + gt0_eyescanreset_in : in std_logic; + gt0_rxuserrdy_in : in std_logic; + -------------------------- RX Margin Analysis Ports ------------------------ + gt0_eyescandataerror_out : out std_logic; + gt0_eyescantrigger_in : in std_logic; + ------------------------- Receive Ports - CDR Ports ------------------------ + GT0_RXCDRRESET_IN : in std_logic; --// Modified + GT0_RXCDRLOCK_OUT : out std_logic; --// Modified + ------------------ Receive Ports - FPGA RX Interface Ports ----------------- + gt0_rxusrclk_in : in std_logic; + gt0_rxusrclk2_in : in std_logic; + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + gt0_rxdata_out : out std_logic_vector(15 downto 0); + ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- + gt0_rxdisperr_out : out std_logic_vector(1 downto 0); + gt0_rxnotintable_out : out std_logic_vector(1 downto 0); + --------------------------- Receive Ports - RX AFE ------------------------- + gt0_gtxrxp_in : in std_logic; + ------------------------ Receive Ports - RX AFE Ports ---------------------- + gt0_gtxrxn_in : in std_logic; + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + gt0_rxphmonitor_out : out std_logic_vector(4 downto 0); + gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0); + --------------------- Receive Ports - RX Equalizer Ports ------------------- + gt0_rxdfelpmreset_in : in std_logic; + gt0_rxmonitorout_out : out std_logic_vector(6 downto 0); + gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0); + --------------- Receive Ports - RX Fabric Output Control Ports ------------- + gt0_rxoutclk_out : out std_logic; + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + gt0_gtrxreset_in : in std_logic; + gt0_rxpmareset_in : in std_logic; + ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- + gt0_rxcharisk_out : out std_logic_vector(1 downto 0); + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + gt0_rxresetdone_out : out std_logic; + --------------------- TX Initialization and Reset Ports -------------------- + gt0_gttxreset_in : in std_logic; + gt0_txuserrdy_in : in std_logic; + ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- + gt0_txusrclk_in : in std_logic; + gt0_txusrclk2_in : in std_logic; + ------------------ Transmit Ports - TX Data Path interface ----------------- + gt0_txdata_in : in std_logic_vector(15 downto 0); + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + gt0_gtxtxn_out : out std_logic; + gt0_gtxtxp_out : out std_logic; + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + gt0_txoutclk_out : out std_logic; + gt0_txoutclkfabric_out : out std_logic; + gt0_txoutclkpcs_out : out std_logic; + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + gt0_txcharisk_in : in std_logic_vector(1 downto 0); + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + gt0_txresetdone_out : out std_logic; + + + --____________________________COMMON PORTS________________________________ + GT0_QPLLOUTCLK_IN : in std_logic; + GT0_QPLLOUTREFCLK_IN : in std_logic + +); +end gtxKintex7FEE80; + +architecture RTL of gtxKintex7FEE80 is + attribute DowngradeIPIdentifiedWarnings: string; + attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes"; + + attribute X_CORE_INFO : string; + attribute X_CORE_INFO of RTL : architecture is "gtxKintex7FEE80,gtwizard_v3_5,{protocol_file=Start_from_scratch}"; + attribute CORE_GENERATION_INFO : string; + attribute CORE_GENERATION_INFO of RTL : architecture is "gtxKintex7FEE80,gtwizard_v3_5,{protocol_file=Start_from_scratch}"; + +--**************************Component Declarations***************************** + +component gtxKintex7FEE80_init +generic +( + EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model + EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation + USE_BUFG : integer := 0; -- Set to 1 for bufg usage for cpll railing logic + + STABLE_CLOCK_PERIOD : integer := 12; + -- Set to 1 for simulation + EXAMPLE_USE_CHIPSCOPE : integer := 1 --// Modified -- Set to 1 to use Chipscope to drive resets + +); +port +( + SYSCLK_IN : in std_logic; + SOFT_RESET_TX_IN : in std_logic; + SOFT_RESET_RX_IN : in std_logic; + DONT_RESET_ON_DATA_ERROR_IN : in std_logic; + GT0_TX_FSM_RESET_DONE_OUT : out std_logic; + GT0_RX_FSM_RESET_DONE_OUT : out std_logic; + GT0_DATA_VALID_IN : in std_logic; + GT0_TX_MMCM_LOCK_IN : in std_logic; + GT0_TX_MMCM_RESET_OUT : out std_logic; + + --_________________________________________________________________________ + --GT0 (X1Y0) + --____________________________CHANNEL PORTS________________________________ + --------------------------------- CPLL Ports ------------------------------- + gt0_cpllfbclklost_out : out std_logic; + gt0_cplllock_out : out std_logic; + gt0_cplllockdetclk_in : in std_logic; + gt0_cpllreset_in : in std_logic; + -------------------------- Channel - Clocking Ports ------------------------ + gt0_gtrefclk0_in : in std_logic; + gt0_gtrefclk1_in : in std_logic; + ---------------------------- Channel - DRP Ports -------------------------- + gt0_drpaddr_in : in std_logic_vector(8 downto 0); + gt0_drpclk_in : in std_logic; + gt0_drpdi_in : in std_logic_vector(15 downto 0); + gt0_drpdo_out : out std_logic_vector(15 downto 0); + gt0_drpen_in : in std_logic; + gt0_drprdy_out : out std_logic; + gt0_drpwe_in : in std_logic; + --------------------------- Digital Monitor Ports -------------------------- + gt0_dmonitorout_out : out std_logic_vector(7 downto 0); + --------------------- RX Initialization and Reset Ports -------------------- + gt0_eyescanreset_in : in std_logic; + gt0_rxuserrdy_in : in std_logic; + -------------------------- RX Margin Analysis Ports ------------------------ + gt0_eyescandataerror_out : out std_logic; + gt0_eyescantrigger_in : in std_logic; + ------------------------- Receive Ports - CDR Ports ------------------------ + GT0_RXCDRRESET_IN : in std_logic; --// Modified + GT0_RXCDRLOCK_OUT : out std_logic; --// Modified + ------------------ Receive Ports - FPGA RX Interface Ports ----------------- + gt0_rxusrclk_in : in std_logic; + gt0_rxusrclk2_in : in std_logic; + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + gt0_rxdata_out : out std_logic_vector(15 downto 0); + ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- + gt0_rxdisperr_out : out std_logic_vector(1 downto 0); + gt0_rxnotintable_out : out std_logic_vector(1 downto 0); + --------------------------- Receive Ports - RX AFE ------------------------- + gt0_gtxrxp_in : in std_logic; + ------------------------ Receive Ports - RX AFE Ports ---------------------- + gt0_gtxrxn_in : in std_logic; + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + gt0_rxphmonitor_out : out std_logic_vector(4 downto 0); + gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0); + --------------------- Receive Ports - RX Equalizer Ports ------------------- + gt0_rxdfelpmreset_in : in std_logic; + gt0_rxmonitorout_out : out std_logic_vector(6 downto 0); + gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0); + --------------- Receive Ports - RX Fabric Output Control Ports ------------- + gt0_rxoutclk_out : out std_logic; + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + gt0_gtrxreset_in : in std_logic; + gt0_rxpmareset_in : in std_logic; + ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- + gt0_rxcharisk_out : out std_logic_vector(1 downto 0); + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + gt0_rxresetdone_out : out std_logic; + --------------------- TX Initialization and Reset Ports -------------------- + gt0_gttxreset_in : in std_logic; + gt0_txuserrdy_in : in std_logic; + ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- + gt0_txusrclk_in : in std_logic; + gt0_txusrclk2_in : in std_logic; + ------------------ Transmit Ports - TX Data Path interface ----------------- + gt0_txdata_in : in std_logic_vector(15 downto 0); + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + gt0_gtxtxn_out : out std_logic; + gt0_gtxtxp_out : out std_logic; + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + gt0_txoutclk_out : out std_logic; + gt0_txoutclkfabric_out : out std_logic; + gt0_txoutclkpcs_out : out std_logic; + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + gt0_txcharisk_in : in std_logic_vector(1 downto 0); + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + gt0_txresetdone_out : out std_logic; + + + --____________________________COMMON PORTS________________________________ + GT0_QPLLOUTCLK_IN : in std_logic; + GT0_QPLLOUTREFCLK_IN : in std_logic + +); +end component; + +--**************************** Main Body of Code ******************************* +begin + U0 : gtxKintex7FEE80_init + generic map +( + EXAMPLE_SIM_GTRESET_SPEEDUP => "TRUE", + EXAMPLE_SIMULATION => 0, + + USE_BUFG => 0, + + STABLE_CLOCK_PERIOD => 12, + EXAMPLE_USE_CHIPSCOPE => 1 --// Modified +) +port map +( + SYSCLK_IN => SYSCLK_IN, + SOFT_RESET_TX_IN => SOFT_RESET_TX_IN, + SOFT_RESET_RX_IN => SOFT_RESET_RX_IN, + DONT_RESET_ON_DATA_ERROR_IN => DONT_RESET_ON_DATA_ERROR_IN, + GT0_TX_FSM_RESET_DONE_OUT => GT0_TX_FSM_RESET_DONE_OUT, + GT0_RX_FSM_RESET_DONE_OUT => GT0_RX_FSM_RESET_DONE_OUT, + GT0_DATA_VALID_IN => GT0_DATA_VALID_IN, + GT0_TX_MMCM_LOCK_IN => GT0_TX_MMCM_LOCK_IN, + GT0_TX_MMCM_RESET_OUT => GT0_TX_MMCM_RESET_OUT, + + --_________________________________________________________________________ + --GT0 (X1Y0) + --____________________________CHANNEL PORTS________________________________ + --------------------------------- CPLL Ports ------------------------------- + gt0_cpllfbclklost_out => gt0_cpllfbclklost_out, + gt0_cplllock_out => gt0_cplllock_out, + gt0_cplllockdetclk_in => gt0_cplllockdetclk_in, + gt0_cpllreset_in => gt0_cpllreset_in, + -------------------------- Channel - Clocking Ports ------------------------ + gt0_gtrefclk0_in => gt0_gtrefclk0_in, + gt0_gtrefclk1_in => gt0_gtrefclk1_in, + ---------------------------- Channel - DRP Ports -------------------------- + gt0_drpaddr_in => gt0_drpaddr_in, + gt0_drpclk_in => gt0_drpclk_in, + gt0_drpdi_in => gt0_drpdi_in, + gt0_drpdo_out => gt0_drpdo_out, + gt0_drpen_in => gt0_drpen_in, + gt0_drprdy_out => gt0_drprdy_out, + gt0_drpwe_in => gt0_drpwe_in, + --------------------------- Digital Monitor Ports -------------------------- + gt0_dmonitorout_out => gt0_dmonitorout_out, + --------------------- RX Initialization and Reset Ports -------------------- + gt0_eyescanreset_in => gt0_eyescanreset_in, + gt0_rxuserrdy_in => gt0_rxuserrdy_in, + -------------------------- RX Margin Analysis Ports ------------------------ + gt0_eyescandataerror_out => gt0_eyescandataerror_out, + gt0_eyescantrigger_in => gt0_eyescantrigger_in, + ------------------------- Receive Ports - CDR Ports ------------------------ + GT0_RXCDRRESET_IN => GT0_RXCDRRESET_IN, --// Modified + GT0_RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT, --// Modified + ------------------ Receive Ports - FPGA RX Interface Ports ----------------- + gt0_rxusrclk_in => gt0_rxusrclk_in, + gt0_rxusrclk2_in => gt0_rxusrclk2_in, + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + gt0_rxdata_out => gt0_rxdata_out, + ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- + gt0_rxdisperr_out => gt0_rxdisperr_out, + gt0_rxnotintable_out => gt0_rxnotintable_out, + --------------------------- Receive Ports - RX AFE ------------------------- + gt0_gtxrxp_in => gt0_gtxrxp_in, + ------------------------ Receive Ports - RX AFE Ports ---------------------- + gt0_gtxrxn_in => gt0_gtxrxn_in, + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + gt0_rxphmonitor_out => gt0_rxphmonitor_out, + gt0_rxphslipmonitor_out => gt0_rxphslipmonitor_out, + --------------------- Receive Ports - RX Equalizer Ports ------------------- + gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in, + gt0_rxmonitorout_out => gt0_rxmonitorout_out, + gt0_rxmonitorsel_in => gt0_rxmonitorsel_in, + --------------- Receive Ports - RX Fabric Output Control Ports ------------- + gt0_rxoutclk_out => gt0_rxoutclk_out, + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + gt0_gtrxreset_in => gt0_gtrxreset_in, + gt0_rxpmareset_in => gt0_rxpmareset_in, + ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- + gt0_rxcharisk_out => gt0_rxcharisk_out, + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + gt0_rxresetdone_out => gt0_rxresetdone_out, + --------------------- TX Initialization and Reset Ports -------------------- + gt0_gttxreset_in => gt0_gttxreset_in, + gt0_txuserrdy_in => gt0_txuserrdy_in, + ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- + gt0_txusrclk_in => gt0_txusrclk_in, + gt0_txusrclk2_in => gt0_txusrclk2_in, + ------------------ Transmit Ports - TX Data Path interface ----------------- + gt0_txdata_in => gt0_txdata_in, + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + gt0_gtxtxn_out => gt0_gtxtxn_out, + gt0_gtxtxp_out => gt0_gtxtxp_out, + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + gt0_txoutclk_out => gt0_txoutclk_out, + gt0_txoutclkfabric_out => gt0_txoutclkfabric_out, + gt0_txoutclkpcs_out => gt0_txoutclkpcs_out, + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + gt0_txcharisk_in => gt0_txcharisk_in, + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + gt0_txresetdone_out => gt0_txresetdone_out, + + + --____________________________COMMON PORTS________________________________ + GT0_QPLLOUTCLK_IN => GT0_QPLLOUTCLK_IN, + GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK_IN + +); + +end RTL; + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_auto_phase_align.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_auto_phase_align.vhd new file mode 100644 index 0000000..e3a0db5 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_auto_phase_align.vhd @@ -0,0 +1,198 @@ +--////////////////////////////////////////////////////////////////////////////// +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 3.5 +-- \ \ Application : 7 Series FPGAs Transceivers Wizard +-- / / Filename : gtxkintex7fee80_auto_phase_align.vhd +-- /___/ /\ +-- \ \ / \ +-- \___\/\___\ +-- +-- +-- Description : The logic below implements the procedure to do automatic phase-alignment +-- on the 7-series GTX as described in ug476pdf, version 1.3, +-- Chapters "Using the TX Phase Alignment to Bypass the TX Buffer" +-- and "Using the RX Phase Alignment to Bypass the RX Elastic Buffer" +-- Should the logic below differ from what is described in a later version +-- of the user-guide, you are using an auto-alignment block, which is +-- out of date and needs to be updated for safe operation. +-- +-- +-- +-- Module gtxKintex7FEE80_AUTO_PHASE_ALIGN +-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard +-- +-- +-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + + +--***************************************************************************** + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gtxKintex7FEE80_AUTO_PHASE_ALIGN is + Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB + --or reference-clock present at startup. + RUN_PHALIGNMENT : in STD_LOGIC; --Signal from the main Reset-FSM to run the auto phase-alignment procedure + PHASE_ALIGNMENT_DONE : out STD_LOGIC := '0'; -- Auto phase-alignment performed sucessfully + PHALIGNDONE : in STD_LOGIC; --\ Phase-alignment signals from and to the + DLYSRESET : out STD_LOGIC; -- |transceiver. + DLYSRESETDONE : in STD_LOGIC; --/ + RECCLKSTABLE : in STD_LOGIC --/on the RX-side. + + ); +end gtxKintex7FEE80_AUTO_PHASE_ALIGN; + +architecture RTL of gtxKintex7FEE80_AUTO_PHASE_ALIGN is + + component gtxKintex7FEE80_sync_block + generic ( + INITIALISE : bit_vector(5 downto 0) := "000000" + ); + port ( + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); + end component; + + type phase_align_auto_fsm is( + INIT, WAIT_PHRST_DONE, COUNT_PHALIGN_DONE, PHALIGN_DONE + ); + + signal phalign_state : phase_align_auto_fsm := INIT; + signal phaligndone_prev : std_logic := '0'; + signal phaligndone_ris_edge : std_logic; + + signal count_phalign_edges : integer range 0 to 3:= 0; + signal phaligndone_sync : std_logic := '0'; + signal dlysresetdone_sync : std_logic := '0'; + +begin + + sync_PHALIGNDONE : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => PHALIGNDONE, + data_out => phaligndone_sync + ); + + sync_DLYSRESETDONE : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => DLYSRESETDONE, + data_out => dlysresetdone_sync + ); + + + process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + phaligndone_prev <= phaligndone_sync; + end if; + end process; + phaligndone_ris_edge <= '1' when (phaligndone_prev = '0') and (phaligndone_sync = '1') else '0'; + + process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + if RUN_PHALIGNMENT = '0' or RECCLKSTABLE = '0' then + DLYSRESET <= '0'; + count_phalign_edges <= 0; + PHASE_ALIGNMENT_DONE <= '0'; + phalign_state <= INIT; + else + if phaligndone_ris_edge = '1' then + if count_phalign_edges < 3 then + count_phalign_edges <= count_phalign_edges + 1; + end if; + end if; + + DLYSRESET <= '0'; + + case phalign_state is + when INIT => + PHASE_ALIGNMENT_DONE <= '0'; + if RUN_PHALIGNMENT = '1' and RECCLKSTABLE = '1' then + --DLYSRESET is toggled to '1' + DLYSRESET <= '1'; + phalign_state <= WAIT_PHRST_DONE; + end if; + + when WAIT_PHRST_DONE => + if dlysresetdone_sync = '1' then + phalign_state <= COUNT_PHALIGN_DONE; + end if; + --No timeout-check here as that is done in the main FSM + + when COUNT_PHALIGN_DONE => + if (count_phalign_edges = 2) then + + --For GTX: Only on the second edge of the PHALIGNDONE-signal the + -- phase-alignment is completed + --For GTH, GTP: TXSYNCDONE indicates the completion of Phase Alignment + + phalign_state <= PHALIGN_DONE; + end if; + + when PHALIGN_DONE => + PHASE_ALIGNMENT_DONE <= '1'; + + when OTHERS => + phalign_state <= INIT; + + end case; + end if; + end if; + end process; + +end RTL; diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_cpll_railing.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_cpll_railing.vhd new file mode 100644 index 0000000..8664c5d --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_cpll_railing.vhd @@ -0,0 +1,144 @@ +------------------------------------------------------------------------------ +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 3.5 +-- \ \ Application : 7 Series FPGAs Transceivers Wizard +-- / / Filename : gtxkintex7fee80_cpll_railing.vhd +-- /___/ /\ +-- \ \ / \ +-- \___\/\___\ +-- +-- Description : This module instantiates the modules required for +-- reset and initialisation of the Transceiver +-- +-- Module gtxKintex7FEE80_cpll_railing +-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard +-- +-- +-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; + +--***********************************Entity Declaration************************ + +entity gtxKintex7FEE80_cpll_railing is +generic( USE_BUFG : integer := 0 + ); + port ( + cpll_reset_out : out std_logic; + cpll_pd_out : out std_logic; + refclk_out : out std_logic; + + refclk_in : in std_logic + ); + end gtxKintex7FEE80_cpll_railing; + + +architecture RTL of gtxKintex7FEE80_cpll_railing is + +--**************************** Signal Declarations **************************** + + -- ground and tied_to_vcc_i signals + signal tied_to_ground_i : std_logic; + signal tied_to_ground_vec_i : std_logic_vector(63 downto 0); + signal tied_to_vcc_i : std_logic; + +attribute equivalent_register_removal: string; +signal cpllpd_wait : std_logic_vector(95 downto 0) := x"FFFFFFFFFFFFFFFFFFFFFFFF"; +signal cpllreset_wait : std_logic_vector(127 downto 0) := x"000000000000000000000000000000FF"; +attribute equivalent_register_removal of cpllpd_wait : signal is "no"; +attribute equivalent_register_removal of cpllreset_wait : signal is "no"; +signal gtrefclk0_i :std_logic ; +--******************************** Main Body of Code*************************** + +begin + + --------------------------- Static signal Assignments --------------------- + + tied_to_ground_i <= '0'; + tied_to_ground_vec_i(63 downto 0) <= (others => '0'); + tied_to_vcc_i <= '1'; + + use_bufg_cpll:if(USE_BUFG = 1) generate + refclk_buf : BUFG + port map + (O => gtrefclk0_i, + I => refclk_in); + + end generate; + + use_bufr_cpll:if(USE_BUFG = 0) generate + refclk_buf : BUFR + port map + (O => gtrefclk0_i, + CE => tied_to_vcc_i, + CLR => tied_to_ground_i, + I => refclk_in); + + end generate; + + process( gtrefclk0_i ) + begin + if(gtrefclk0_i'event and gtrefclk0_i = '1') then + cpllpd_wait <= cpllpd_wait(94 downto 0) & '0'; + cpllreset_wait <= cpllreset_wait(126 downto 0) & '0'; + end if; + end process; + +cpll_pd_out <= cpllpd_wait(95); +cpll_reset_out <= cpllreset_wait(127); +refclk_out <= gtrefclk0_i; + + + end RTL; diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_gt.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_gt.vhd new file mode 100644 index 0000000..8e82fbc --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_gt.vhd @@ -0,0 +1,834 @@ +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 3.5 +-- \ \ Application : 7 Series FPGAs Transceivers Wizard +-- / / Filename : gtxkintex7fee80_gt.vhd +-- /___/ /\ +-- \ \ / \ +-- \___\/\___\ +-- +-- +-- Module gtxKintex7FEE80_GT (a GT Wrapper) +-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard +-- +-- +-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; + +--***************************** Entity Declaration **************************** + +entity gtxKintex7FEE80_GT is +generic +( + -- Simulation attributes + GT_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "TRUE" to speed up sim reset + RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC"; + SIM_CPLLREFCLK_SEL : bit_vector := "001"; + PMA_RSV_IN : bit_vector := x"00018480"; + PCS_RSVD_ATTR_IN : bit_vector := X"000000000000" +); +port +( + cpllpd_in : in std_logic; + cpllrefclksel_in : in std_logic_vector(2 downto 0); + --------------------------------- CPLL Ports ------------------------------- + cpllfbclklost_out : out std_logic; + cplllock_out : out std_logic; + cplllockdetclk_in : in std_logic; + cpllrefclklost_out : out std_logic; + cpllreset_in : in std_logic; + -------------------------- Channel - Clocking Ports ------------------------ + gtrefclk0_in : in std_logic; + gtrefclk1_in : in std_logic; + ---------------------------- Channel - DRP Ports -------------------------- + drpaddr_in : in std_logic_vector(8 downto 0); + drpclk_in : in std_logic; + drpdi_in : in std_logic_vector(15 downto 0); + drpdo_out : out std_logic_vector(15 downto 0); + drpen_in : in std_logic; + drprdy_out : out std_logic; + drpwe_in : in std_logic; + ------------------------------- Clocking Ports ----------------------------- + qpllclk_in : in std_logic; + qpllrefclk_in : in std_logic; + --------------------------- Digital Monitor Ports -------------------------- + dmonitorout_out : out std_logic_vector(7 downto 0); + --------------------- RX Initialization and Reset Ports -------------------- + eyescanreset_in : in std_logic; + rxuserrdy_in : in std_logic; + -------------------------- RX Margin Analysis Ports ------------------------ + eyescandataerror_out : out std_logic; + eyescantrigger_in : in std_logic; + ------------------------- Receive Ports - CDR Ports ------------------------ + RXCDRRESET_IN : in std_logic; --// Modified + RXCDRLOCK_OUT : out std_logic; --// Modified + ------------------ Receive Ports - FPGA RX Interface Ports ----------------- + rxusrclk_in : in std_logic; + rxusrclk2_in : in std_logic; + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + rxdata_out : out std_logic_vector(15 downto 0); + ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- + rxdisperr_out : out std_logic_vector(1 downto 0); + rxnotintable_out : out std_logic_vector(1 downto 0); + --------------------------- Receive Ports - RX AFE ------------------------- + gtxrxp_in : in std_logic; + ------------------------ Receive Ports - RX AFE Ports ---------------------- + gtxrxn_in : in std_logic; + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + rxdlyen_in : in std_logic; + rxdlysreset_in : in std_logic; + rxdlysresetdone_out : out std_logic; + rxphalign_in : in std_logic; + rxphaligndone_out : out std_logic; + rxphalignen_in : in std_logic; + rxphdlyreset_in : in std_logic; + rxphmonitor_out : out std_logic_vector(4 downto 0); + rxphslipmonitor_out : out std_logic_vector(4 downto 0); + -------------------- Receive Ports - RX Equailizer Ports ------------------- + rxlpmhfhold_in : in std_logic; + rxlpmlfhold_in : in std_logic; + --------------------- Receive Ports - RX Equalizer Ports ------------------- + rxdfelpmreset_in : in std_logic; + rxmonitorout_out : out std_logic_vector(6 downto 0); + rxmonitorsel_in : in std_logic_vector(1 downto 0); + --------------- Receive Ports - RX Fabric Output Control Ports ------------- + rxoutclk_out : out std_logic; + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + gtrxreset_in : in std_logic; + rxpmareset_in : in std_logic; + ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- + rxcharisk_out : out std_logic_vector(1 downto 0); + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + rxresetdone_out : out std_logic; + --------------------- TX Initialization and Reset Ports -------------------- + gttxreset_in : in std_logic; + txuserrdy_in : in std_logic; + ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- + txusrclk_in : in std_logic; + txusrclk2_in : in std_logic; + ------------------ Transmit Ports - TX Buffer Bypass Ports ----------------- + txdlyen_in : in std_logic; + txdlysreset_in : in std_logic; + txdlysresetdone_out : out std_logic; + txphalign_in : in std_logic; + txphaligndone_out : out std_logic; + txphalignen_in : in std_logic; + txphdlyreset_in : in std_logic; + txphinit_in : in std_logic; + txphinitdone_out : out std_logic; + ------------------ Transmit Ports - TX Data Path interface ----------------- + txdata_in : in std_logic_vector(15 downto 0); + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + gtxtxn_out : out std_logic; + gtxtxp_out : out std_logic; + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + txoutclk_out : out std_logic; + txoutclkfabric_out : out std_logic; + txoutclkpcs_out : out std_logic; + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + txcharisk_in : in std_logic_vector(1 downto 0); + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + txresetdone_out : out std_logic + + +); + + +end gtxKintex7FEE80_GT; + +architecture RTL of gtxKintex7FEE80_GT is + +--**************************** Signal Declarations **************************** + + -- ground and tied_to_vcc_i signals + signal tied_to_ground_i : std_logic; + signal tied_to_ground_vec_i : std_logic_vector(63 downto 0); + signal tied_to_vcc_i : std_logic; + + + + -- RX Datapath signals + signal rxdata_i : std_logic_vector(63 downto 0); + signal rxchariscomma_float_i : std_logic_vector(5 downto 0); + signal rxcharisk_float_i : std_logic_vector(5 downto 0); + signal rxdisperr_float_i : std_logic_vector(5 downto 0); + signal rxnotintable_float_i : std_logic_vector(5 downto 0); + signal rxrundisp_float_i : std_logic_vector(5 downto 0); + + + -- TX Datapath signals + signal txdata_i : std_logic_vector(63 downto 0); + signal txkerr_float_i : std_logic_vector(5 downto 0); + signal txrundisp_float_i : std_logic_vector(5 downto 0); + signal rxstartofseq_float_i : std_logic; +--******************************** Main Body of Code*************************** + +begin + + --------------------------- Static signal Assignments --------------------- + + tied_to_ground_i <= '0'; + tied_to_ground_vec_i(63 downto 0) <= (others => '0'); + tied_to_vcc_i <= '1'; + + ------------------- GT Datapath byte mapping ----------------- + RXDATA_OUT <= rxdata_i(15 downto 0); + + txdata_i <= (tied_to_ground_vec_i(47 downto 0) & TXDATA_IN); + + + + ----------------------------- GTXE2 Instance -------------------------- + + gtxe2_i :GTXE2_CHANNEL + generic map + ( + + --_______________________ Simulation-Only Attributes ___________________ + + SIM_RECEIVER_DETECT_PASS => ("TRUE"), + SIM_RESET_SPEEDUP => (GT_SIM_GTRESET_SPEEDUP), + SIM_TX_EIDLE_DRIVE_LEVEL => ("X"), + SIM_CPLLREFCLK_SEL => (SIM_CPLLREFCLK_SEL), + SIM_VERSION => ("4.0"), + + + ------------------RX Byte and Word Alignment Attributes--------------- + ALIGN_COMMA_DOUBLE => ("FALSE"), + ALIGN_COMMA_ENABLE => ("1111111111"), + ALIGN_COMMA_WORD => (1), + ALIGN_MCOMMA_DET => ("TRUE"), + ALIGN_MCOMMA_VALUE => ("1010000011"), + ALIGN_PCOMMA_DET => ("TRUE"), + ALIGN_PCOMMA_VALUE => ("0101111100"), + SHOW_REALIGN_COMMA => ("FALSE"), + RXSLIDE_AUTO_WAIT => (7), + RXSLIDE_MODE => ("AUTO"), --// ("PCS"), Modified + RX_SIG_VALID_DLY => (10), + + ------------------RX 8B/10B Decoder Attributes--------------- + RX_DISPERR_SEQ_MATCH => ("TRUE"), + DEC_MCOMMA_DETECT => ("TRUE"), + DEC_PCOMMA_DETECT => ("TRUE"), + DEC_VALID_COMMA_ONLY => ("FALSE"), + + ------------------------RX Clock Correction Attributes---------------------- + CBCC_DATA_SOURCE_SEL => ("DECODED"), + CLK_COR_SEQ_2_USE => ("FALSE"), + CLK_COR_KEEP_IDLE => ("FALSE"), + CLK_COR_MAX_LAT => (9), + CLK_COR_MIN_LAT => (7), + CLK_COR_PRECEDENCE => ("TRUE"), + CLK_COR_REPEAT_WAIT => (0), + CLK_COR_SEQ_LEN => (1), + CLK_COR_SEQ_1_ENABLE => ("1111"), + CLK_COR_SEQ_1_1 => ("0100000000"), + CLK_COR_SEQ_1_2 => ("0000000000"), + CLK_COR_SEQ_1_3 => ("0000000000"), + CLK_COR_SEQ_1_4 => ("0000000000"), + CLK_CORRECT_USE => ("FALSE"), + CLK_COR_SEQ_2_ENABLE => ("1111"), + CLK_COR_SEQ_2_1 => ("0100000000"), + CLK_COR_SEQ_2_2 => ("0000000000"), + CLK_COR_SEQ_2_3 => ("0000000000"), + CLK_COR_SEQ_2_4 => ("0000000000"), + + ------------------------RX Channel Bonding Attributes---------------------- + CHAN_BOND_KEEP_ALIGN => ("FALSE"), + CHAN_BOND_MAX_SKEW => (1), + CHAN_BOND_SEQ_LEN => (1), + CHAN_BOND_SEQ_1_1 => ("0000000000"), + CHAN_BOND_SEQ_1_2 => ("0000000000"), + CHAN_BOND_SEQ_1_3 => ("0000000000"), + CHAN_BOND_SEQ_1_4 => ("0000000000"), + CHAN_BOND_SEQ_1_ENABLE => ("1111"), + CHAN_BOND_SEQ_2_1 => ("0000000000"), + CHAN_BOND_SEQ_2_2 => ("0000000000"), + CHAN_BOND_SEQ_2_3 => ("0000000000"), + CHAN_BOND_SEQ_2_4 => ("0000000000"), + CHAN_BOND_SEQ_2_ENABLE => ("1111"), + CHAN_BOND_SEQ_2_USE => ("FALSE"), + FTS_DESKEW_SEQ_ENABLE => ("1111"), + FTS_LANE_DESKEW_CFG => ("1111"), + FTS_LANE_DESKEW_EN => ("FALSE"), + + ---------------------------RX Margin Analysis Attributes---------------------------- + ES_CONTROL => ("000000"), + ES_ERRDET_EN => ("FALSE"), + ES_EYE_SCAN_EN => ("TRUE"), + ES_HORZ_OFFSET => (x"000"), + ES_PMA_CFG => ("0000000000"), + ES_PRESCALE => ("00000"), + ES_QUALIFIER => (x"00000000000000000000"), + ES_QUAL_MASK => (x"00000000000000000000"), + ES_SDATA_MASK => (x"00000000000000000000"), + ES_VERT_OFFSET => ("000000000"), + + -------------------------FPGA RX Interface Attributes------------------------- + RX_DATA_WIDTH => (20), + + ---------------------------PMA Attributes---------------------------- + OUTREFCLK_SEL_INV => ("11"), + PMA_RSV => (PMA_RSV_IN), + PMA_RSV2 => (x"2040"), --// was 2050 + PMA_RSV3 => ("00"), + PMA_RSV4 => (x"00000000"), + RX_BIAS_CFG => ("000000000100"), + DMONITOR_CFG => (x"000A00"), + RX_CM_SEL => ("00"), + RX_CM_TRIM => ("000"), --// was 010 + RX_DEBUG_CFG => ("000000000000"), + RX_OS_CFG => ("0000010000000"), + TERM_RCAL_CFG => ("10000"), + TERM_RCAL_OVRD => ('0'), + TST_RSV => (x"00000000"), + RX_CLK25_DIV => (4), + TX_CLK25_DIV => (4), + UCODEER_CLR => ('0'), + + ---------------------------PCI Express Attributes---------------------------- + PCS_PCIE_EN => ("FALSE"), + + ---------------------------PCS Attributes---------------------------- + PCS_RSVD_ATTR => (PCS_RSVD_ATTR_IN), + + -------------RX Buffer Attributes------------ + RXBUF_ADDR_MODE => ("FAST"), + RXBUF_EIDLE_HI_CNT => ("1000"), + RXBUF_EIDLE_LO_CNT => ("0000"), + RXBUF_EN => ("FALSE"), + RX_BUFFER_CFG => ("000000"), + RXBUF_RESET_ON_CB_CHANGE => ("TRUE"), + RXBUF_RESET_ON_COMMAALIGN => ("FALSE"), + RXBUF_RESET_ON_EIDLE => ("FALSE"), + RXBUF_RESET_ON_RATE_CHANGE => ("TRUE"), + RXBUFRESET_TIME => ("00001"), + RXBUF_THRESH_OVFLW => (61), + RXBUF_THRESH_OVRD => ("FALSE"), + RXBUF_THRESH_UNDFLW => (4), + RXDLY_CFG => (x"001F"), + RXDLY_LCFG => (x"030"), + RXDLY_TAP_CFG => (x"0000"), + RXPH_CFG => (x"000000"), + RXPHDLY_CFG => (x"084020"), + RXPH_MONITOR_SEL => ("00000"), + RX_XCLK_SEL => ("RXUSR"), + RX_DDI_SEL => ("000000"), + RX_DEFER_RESET_BUF_EN => ("TRUE"), + + -----------------------CDR Attributes------------------------- + + --For Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200008 + + --For Display Port, HBR2 - set RXCDR_CFG=72'h038c008bff20200010 + + --For SATA Gen1 GTX- set RXCDR_CFG=72'h03_8000_8BFF_4010_0008 + + --For SATA Gen2 GTX- set RXCDR_CFG=72'h03_8800_8BFF_4020_0008 + + --For SATA Gen3 GTX- set RXCDR_CFG=72'h03_8000_8BFF_1020_0010 + + --For SATA Gen3 GTP- set RXCDR_CFG=83'h0_0000_87FE_2060_2444_1010 + + --For SATA Gen2 GTP- set RXCDR_CFG=83'h0_0000_47FE_2060_2448_1010 + + --For SATA Gen1 GTP- set RXCDR_CFG=83'h0_0000_47FE_1060_2448_1010 + RXCDR_CFG => (x"03000023ff10200020"), + RXCDR_FR_RESET_ON_EIDLE => ('0'), + RXCDR_HOLD_DURING_EIDLE => ('0'), + RXCDR_PH_RESET_ON_EIDLE => ('0'), + RXCDR_LOCK_CFG => ("010101"), + + -------------------RX Initialization and Reset Attributes------------------- + RXCDRFREQRESET_TIME => ("00001"), + RXCDRPHRESET_TIME => ("00001"), + RXISCANRESET_TIME => ("00001"), + RXPCSRESET_TIME => ("00001"), + RXPMARESET_TIME => ("00011"), + + -------------------RX OOB Signaling Attributes------------------- + RXOOB_CFG => ("0000110"), + + -------------------------RX Gearbox Attributes--------------------------- + RXGEARBOX_EN => ("FALSE"), + GEARBOX_MODE => ("000"), + + -------------------------PRBS Detection Attribute----------------------- + RXPRBS_ERR_LOOPBACK => ('0'), + + -------------Power-Down Attributes---------- + PD_TRANS_TIME_FROM_P2 => (x"03c"), + PD_TRANS_TIME_NONE_P2 => (x"3c"), + PD_TRANS_TIME_TO_P2 => (x"64"), + + -------------RX OOB Signaling Attributes---------- + SAS_MAX_COM => (64), + SAS_MIN_COM => (36), + SATA_BURST_SEQ_LEN => ("0101"), + SATA_BURST_VAL => ("100"), + SATA_EIDLE_VAL => ("100"), + SATA_MAX_BURST => (8), + SATA_MAX_INIT => (21), + SATA_MAX_WAKE => (7), + SATA_MIN_BURST => (4), + SATA_MIN_INIT => (12), + SATA_MIN_WAKE => (4), + + -------------RX Fabric Clock Output Control Attributes---------- + TRANS_TIME_RATE => (x"0E"), + + --------------TX Buffer Attributes---------------- + TXBUF_EN => ("FALSE"), + TXBUF_RESET_ON_RATE_CHANGE => ("TRUE"), + TXDLY_CFG => (x"001F"), + TXDLY_LCFG => (x"030"), + TXDLY_TAP_CFG => (x"0000"), + TXPH_CFG => (x"0780"), + TXPHDLY_CFG => (x"084020"), + TXPH_MONITOR_SEL => ("00000"), + TX_XCLK_SEL => ("TXUSR"), + + -------------------------FPGA TX Interface Attributes------------------------- + TX_DATA_WIDTH => (20), + + -------------------------TX Configurable Driver Attributes------------------------- + TX_DEEMPH0 => ("00000"), + TX_DEEMPH1 => ("00000"), + TX_EIDLE_ASSERT_DELAY => ("110"), + TX_EIDLE_DEASSERT_DELAY => ("100"), + TX_LOOPBACK_DRIVE_HIZ => ("FALSE"), + TX_MAINCURSOR_SEL => ('0'), + TX_DRIVE_MODE => ("DIRECT"), + TX_MARGIN_FULL_0 => ("1001110"), + TX_MARGIN_FULL_1 => ("1001001"), + TX_MARGIN_FULL_2 => ("1000101"), + TX_MARGIN_FULL_3 => ("1000010"), + TX_MARGIN_FULL_4 => ("1000000"), + TX_MARGIN_LOW_0 => ("1000110"), + TX_MARGIN_LOW_1 => ("1000100"), + TX_MARGIN_LOW_2 => ("1000010"), + TX_MARGIN_LOW_3 => ("1000000"), + TX_MARGIN_LOW_4 => ("1000000"), + + -------------------------TX Gearbox Attributes-------------------------- + TXGEARBOX_EN => ("FALSE"), + + -------------------------TX Initialization and Reset Attributes-------------------------- + TXPCSRESET_TIME => ("00001"), + TXPMARESET_TIME => ("00001"), + + -------------------------TX Receiver Detection Attributes-------------------------- + TX_RXDETECT_CFG => (x"1832"), + TX_RXDETECT_REF => ("100"), + + ----------------------------CPLL Attributes---------------------------- + CPLL_CFG => (x"BC07DC"), + CPLL_FBDIV => (5), + CPLL_FBDIV_45 => (5), + CPLL_INIT_CFG => (x"00001E"), + CPLL_LOCK_CFG => (x"01E8"), + CPLL_REFCLK_DIV => (1), + RXOUT_DIV => (2), + TXOUT_DIV => (2), + SATA_CPLL_CFG => ("VCO_3000MHZ"), + + --------------RX Initialization and Reset Attributes------------- + RXDFELPMRESET_TIME => ("0001111"), + + --------------RX Equalizer Attributes------------- + RXLPM_HF_CFG => ("00000011110000"), + RXLPM_LF_CFG => ("00000011110000"), + RX_DFE_GAIN_CFG => (x"020FEA"), + RX_DFE_H2_CFG => ("000000000000"), + RX_DFE_H3_CFG => ("000001000000"), + RX_DFE_H4_CFG => ("00011110000"), + RX_DFE_H5_CFG => ("00011100000"), + RX_DFE_KL_CFG => ("0000011111110"), + RX_DFE_LPM_CFG => (x"0904"), + RX_DFE_LPM_HOLD_DURING_EIDLE => ('0'), + RX_DFE_UT_CFG => ("10001111000000000"), + RX_DFE_VP_CFG => ("00011111100000011"), + + -------------------------Power-Down Attributes------------------------- + RX_CLKMUX_PD => ('1'), + TX_CLKMUX_PD => ('1'), + + -------------------------FPGA RX Interface Attribute------------------------- + RX_INT_DATAWIDTH => (0), + + -------------------------FPGA TX Interface Attribute------------------------- + TX_INT_DATAWIDTH => (0), + + ------------------TX Configurable Driver Attributes--------------- + TX_QPI_STATUS_EN => ('0'), + + -------------------------RX Equalizer Attributes-------------------------- + RX_DFE_KL_CFG2 => (RX_DFE_KL_CFG2_IN), + RX_DFE_XYD_CFG => ("0000000000000"), + + -------------------------TX Configurable Driver Attributes-------------------------- + TX_PREDRIVER_MODE => ('0') + + + ) + port map + ( + --------------------------------- CPLL Ports ------------------------------- + CPLLFBCLKLOST => cpllfbclklost_out, + CPLLLOCK => cplllock_out, + CPLLLOCKDETCLK => cplllockdetclk_in, + CPLLLOCKEN => tied_to_vcc_i, + CPLLPD => cpllpd_in, + CPLLREFCLKLOST => cpllrefclklost_out, + CPLLREFCLKSEL => cpllrefclksel_in, + CPLLRESET => cpllreset_in, + GTRSVD => "0000000000000000", + PCSRSVDIN => "0000000000000000", + PCSRSVDIN2 => "00000", + PMARSVDIN => "00000", + PMARSVDIN2 => "00000", + TSTIN => "11111111111111111111", + TSTOUT => open, + ---------------------------------- Channel --------------------------------- + CLKRSVD => tied_to_ground_vec_i(3 downto 0), + -------------------------- Channel - Clocking Ports ------------------------ + GTGREFCLK => tied_to_ground_i, + GTNORTHREFCLK0 => tied_to_ground_i, + GTNORTHREFCLK1 => tied_to_ground_i, + GTREFCLK0 => gtrefclk0_in, + GTREFCLK1 => gtrefclk1_in, + GTSOUTHREFCLK0 => tied_to_ground_i, + GTSOUTHREFCLK1 => tied_to_ground_i, + ---------------------------- Channel - DRP Ports -------------------------- + DRPADDR => drpaddr_in, + DRPCLK => drpclk_in, + DRPDI => drpdi_in, + DRPDO => drpdo_out, + DRPEN => drpen_in, + DRPRDY => drprdy_out, + DRPWE => drpwe_in, + ------------------------------- Clocking Ports ----------------------------- + GTREFCLKMONITOR => open, + QPLLCLK => qpllclk_in, + QPLLREFCLK => qpllrefclk_in, + RXSYSCLKSEL => "00", + TXSYSCLKSEL => "00", + --------------------------- Digital Monitor Ports -------------------------- + DMONITOROUT => dmonitorout_out, + ----------------- FPGA TX Interface Datapath Configuration ---------------- + TX8B10BEN => tied_to_vcc_i, + ------------------------------- Loopback Ports ----------------------------- + LOOPBACK => tied_to_ground_vec_i(2 downto 0), + ----------------------------- PCI Express Ports ---------------------------- + PHYSTATUS => open, + RXRATE => tied_to_ground_vec_i(2 downto 0), + RXVALID => open, + ------------------------------ Power-Down Ports ---------------------------- + RXPD => "00", + TXPD => "00", + -------------------------- RX 8B/10B Decoder Ports ------------------------- + SETERRSTATUS => tied_to_ground_i, + --------------------- RX Initialization and Reset Ports -------------------- + EYESCANRESET => eyescanreset_in, + RXUSERRDY => rxuserrdy_in, + -------------------------- RX Margin Analysis Ports ------------------------ + EYESCANDATAERROR => eyescandataerror_out, + EYESCANMODE => tied_to_ground_i, + EYESCANTRIGGER => eyescantrigger_in, + ------------------------- Receive Ports - CDR Ports ------------------------ + RXCDRFREQRESET => tied_to_ground_i, + RXCDRHOLD => tied_to_ground_i, + RXCDRLOCK => RXCDRLOCK_OUT, --// Modified + RXCDROVRDEN => tied_to_ground_i, + RXCDRRESET => RXCDRRESET_IN, --// Modified tied_to_ground_i, + RXCDRRESETRSV => tied_to_ground_i, + ------------------- Receive Ports - Clock Correction Ports ----------------- + RXCLKCORCNT => open, + ---------- Receive Ports - FPGA RX Interface Datapath Configuration -------- + RX8B10BEN => tied_to_vcc_i, + ------------------ Receive Ports - FPGA RX Interface Ports ----------------- + RXUSRCLK => rxusrclk_in, + RXUSRCLK2 => rxusrclk2_in, + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + RXDATA => rxdata_i, + ------------------- Receive Ports - Pattern Checker Ports ------------------ + RXPRBSERR => open, + RXPRBSSEL => tied_to_ground_vec_i(2 downto 0), + ------------------- Receive Ports - Pattern Checker ports ------------------ + RXPRBSCNTRESET => tied_to_ground_i, + -------------------- Receive Ports - RX Equalizer Ports ------------------- + RXDFEXYDEN => tied_to_vcc_i, + RXDFEXYDHOLD => tied_to_ground_i, + RXDFEXYDOVRDEN => tied_to_ground_i, + ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- + RXDISPERR(7 downto 2) => rxdisperr_float_i, + RXDISPERR(1 downto 0) => rxdisperr_out, + RXNOTINTABLE(7 downto 2) => rxnotintable_float_i, + RXNOTINTABLE(1 downto 0) => rxnotintable_out, + --------------------------- Receive Ports - RX AFE ------------------------- + GTXRXP => gtxrxp_in, + ------------------------ Receive Ports - RX AFE Ports ---------------------- + GTXRXN => gtxrxn_in, + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + RXBUFRESET => tied_to_ground_i, + RXBUFSTATUS => open, + RXDDIEN => tied_to_vcc_i, + RXDLYBYPASS => tied_to_ground_i, + RXDLYEN => rxdlyen_in, + RXDLYOVRDEN => tied_to_ground_i, + RXDLYSRESET => rxdlysreset_in, + RXDLYSRESETDONE => rxdlysresetdone_out, + RXPHALIGN => rxphalign_in, + RXPHALIGNDONE => rxphaligndone_out, + RXPHALIGNEN => rxphalignen_in, + RXPHDLYPD => tied_to_ground_i, + RXPHDLYRESET => rxphdlyreset_in, + RXPHMONITOR => rxphmonitor_out, + RXPHOVRDEN => tied_to_ground_i, + RXPHSLIPMONITOR => rxphslipmonitor_out, + RXSTATUS => open, + -------------- Receive Ports - RX Byte and Word Alignment Ports ------------ + RXBYTEISALIGNED => open, + RXBYTEREALIGN => open, + RXCOMMADET => open, + RXCOMMADETEN => tied_to_vcc_i, + RXMCOMMAALIGNEN => tied_to_vcc_i, + RXPCOMMAALIGNEN => tied_to_vcc_i, + ------------------ Receive Ports - RX Channel Bonding Ports ---------------- + RXCHANBONDSEQ => open, + RXCHBONDEN => tied_to_ground_i, + RXCHBONDLEVEL => tied_to_ground_vec_i(2 downto 0), + RXCHBONDMASTER => tied_to_ground_i, + RXCHBONDO => open, + RXCHBONDSLAVE => tied_to_ground_i, + ----------------- Receive Ports - RX Channel Bonding Ports ---------------- + RXCHANISALIGNED => open, + RXCHANREALIGN => open, + -------------------- Receive Ports - RX Equailizer Ports ------------------- + RXLPMHFHOLD => rxlpmhfhold_in, + RXLPMHFOVRDEN => tied_to_ground_i, + RXLPMLFHOLD => rxlpmlfhold_in, + --------------------- Receive Ports - RX Equalizer Ports ------------------- + RXDFEAGCHOLD => tied_to_ground_i, + RXDFEAGCOVRDEN => tied_to_ground_i, + RXDFECM1EN => tied_to_ground_i, + RXDFELFHOLD => tied_to_ground_i, + RXDFELFOVRDEN => tied_to_ground_i, + RXDFELPMRESET => rxdfelpmreset_in, + RXDFETAP2HOLD => tied_to_ground_i, + RXDFETAP2OVRDEN => tied_to_ground_i, + RXDFETAP3HOLD => tied_to_ground_i, + RXDFETAP3OVRDEN => tied_to_ground_i, + RXDFETAP4HOLD => tied_to_ground_i, + RXDFETAP4OVRDEN => tied_to_ground_i, + RXDFETAP5HOLD => tied_to_ground_i, + RXDFETAP5OVRDEN => tied_to_ground_i, + RXDFEUTHOLD => tied_to_ground_i, + RXDFEUTOVRDEN => tied_to_ground_i, + RXDFEVPHOLD => tied_to_ground_i, + RXDFEVPOVRDEN => tied_to_ground_i, + RXDFEVSEN => tied_to_ground_i, + RXLPMLFKLOVRDEN => tied_to_ground_i, + RXMONITOROUT => rxmonitorout_out, + RXMONITORSEL => rxmonitorsel_in, + RXOSHOLD => tied_to_ground_i, + RXOSOVRDEN => tied_to_ground_i, + ------------ Receive Ports - RX Fabric ClocK Output Control Ports ---------- + RXRATEDONE => open, + --------------- Receive Ports - RX Fabric Output Control Ports ------------- + RXOUTCLK => rxoutclk_out, + RXOUTCLKFABRIC => open, + RXOUTCLKPCS => open, + RXOUTCLKSEL => "010", + ---------------------- Receive Ports - RX Gearbox Ports -------------------- + RXDATAVALID => open, + RXHEADER => open, + RXHEADERVALID => open, + RXSTARTOFSEQ => open, + --------------------- Receive Ports - RX Gearbox Ports -------------------- + RXGEARBOXSLIP => tied_to_ground_i, + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + GTRXRESET => gtrxreset_in, + RXOOBRESET => tied_to_ground_i, + RXPCSRESET => tied_to_ground_i, + RXPMARESET => rxpmareset_in, + ------------------ Receive Ports - RX Margin Analysis ports ---------------- + RXLPMEN => tied_to_vcc_i, + ------------------- Receive Ports - RX OOB Signaling ports ----------------- + RXCOMSASDET => open, + RXCOMWAKEDET => open, + ------------------ Receive Ports - RX OOB Signaling ports ----------------- + RXCOMINITDET => open, + ------------------ Receive Ports - RX OOB signalling Ports ----------------- + RXELECIDLE => open, + RXELECIDLEMODE => "11", + ----------------- Receive Ports - RX Polarity Control Ports ---------------- + RXPOLARITY => tied_to_ground_i, + ---------------------- Receive Ports - RX gearbox ports -------------------- + RXSLIDE => tied_to_ground_i, + ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- + RXCHARISCOMMA => open, + RXCHARISK(7 downto 2) => rxcharisk_float_i, + RXCHARISK(1 downto 0) => rxcharisk_out, + ------------------ Receive Ports - Rx Channel Bonding Ports ---------------- + RXCHBONDI => "00000", + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + RXRESETDONE => rxresetdone_out, + -------------------------------- Rx AFE Ports ------------------------------ + RXQPIEN => tied_to_ground_i, + RXQPISENN => open, + RXQPISENP => open, + --------------------------- TX Buffer Bypass Ports ------------------------- + TXPHDLYTSTCLK => tied_to_ground_i, + ------------------------ TX Configurable Driver Ports ---------------------- + TXPOSTCURSOR => "00000", + TXPOSTCURSORINV => tied_to_ground_i, + TXPRECURSOR => tied_to_ground_vec_i(4 downto 0), + TXPRECURSORINV => tied_to_ground_i, + TXQPIBIASEN => tied_to_ground_i, + TXQPISTRONGPDOWN => tied_to_ground_i, + TXQPIWEAKPUP => tied_to_ground_i, + --------------------- TX Initialization and Reset Ports -------------------- + CFGRESET => tied_to_ground_i, + GTTXRESET => gttxreset_in, + PCSRSVDOUT => open, + TXUSERRDY => txuserrdy_in, + ---------------------- Transceiver Reset Mode Operation -------------------- + GTRESETSEL => tied_to_ground_i, + RESETOVRD => tied_to_ground_i, + ---------------- Transmit Ports - 8b10b Encoder Control Ports -------------- + TXCHARDISPMODE => tied_to_ground_vec_i(7 downto 0), + TXCHARDISPVAL => tied_to_ground_vec_i(7 downto 0), + ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- + TXUSRCLK => txusrclk_in, + TXUSRCLK2 => txusrclk2_in, + --------------------- Transmit Ports - PCI Express Ports ------------------- + TXELECIDLE => tied_to_ground_i, + TXMARGIN => tied_to_ground_vec_i(2 downto 0), + TXRATE => tied_to_ground_vec_i(2 downto 0), + TXSWING => tied_to_ground_i, + ------------------ Transmit Ports - Pattern Generator Ports ---------------- + TXPRBSFORCEERR => tied_to_ground_i, + ------------------ Transmit Ports - TX Buffer Bypass Ports ----------------- + TXDLYBYPASS => tied_to_ground_i, + TXDLYEN => txdlyen_in, + TXDLYHOLD => tied_to_ground_i, + TXDLYOVRDEN => tied_to_ground_i, + TXDLYSRESET => txdlysreset_in, + TXDLYSRESETDONE => txdlysresetdone_out, + TXDLYUPDOWN => tied_to_ground_i, + TXPHALIGN => txphalign_in, + TXPHALIGNDONE => txphaligndone_out, + TXPHALIGNEN => txphalignen_in, + TXPHDLYPD => tied_to_ground_i, + TXPHDLYRESET => txphdlyreset_in, + TXPHINIT => txphinit_in, + TXPHINITDONE => txphinitdone_out, + TXPHOVRDEN => tied_to_ground_i, + ---------------------- Transmit Ports - TX Buffer Ports -------------------- + TXBUFSTATUS => open, + --------------- Transmit Ports - TX Configurable Driver Ports -------------- + TXBUFDIFFCTRL => "100", + TXDEEMPH => tied_to_ground_i, + TXDIFFCTRL => "1000", + TXDIFFPD => tied_to_ground_i, + TXINHIBIT => tied_to_ground_i, + TXMAINCURSOR => "0000000", + TXPISOPD => tied_to_ground_i, + ------------------ Transmit Ports - TX Data Path interface ----------------- + TXDATA => txdata_i, + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + GTXTXN => gtxtxn_out, + GTXTXP => gtxtxp_out, + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + TXOUTCLK => txoutclk_out, + TXOUTCLKFABRIC => txoutclkfabric_out, + TXOUTCLKPCS => txoutclkpcs_out, + TXOUTCLKSEL => "011", + TXRATEDONE => open, + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + TXCHARISK(7 downto 2) => tied_to_ground_vec_i(5 downto 0), + TXCHARISK(1 downto 0) => txcharisk_in, + TXGEARBOXREADY => open, + TXHEADER => tied_to_ground_vec_i(2 downto 0), + TXSEQUENCE => tied_to_ground_vec_i(6 downto 0), + TXSTARTSEQ => tied_to_ground_i, + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + TXPCSRESET => tied_to_ground_i, + TXPMARESET => tied_to_ground_i, + TXRESETDONE => txresetdone_out, + ------------------ Transmit Ports - TX OOB signalling Ports ---------------- + TXCOMFINISH => open, + TXCOMINIT => tied_to_ground_i, + TXCOMSAS => tied_to_ground_i, + TXCOMWAKE => tied_to_ground_i, + TXPDELECIDLEMODE => tied_to_ground_i, + ----------------- Transmit Ports - TX Polarity Control Ports --------------- + TXPOLARITY => tied_to_ground_i, + --------------- Transmit Ports - TX Receiver Detection Ports -------------- + TXDETECTRX => tied_to_ground_i, + ------------------ Transmit Ports - TX8b/10b Encoder Ports ----------------- + TX8B10BBYPASS => tied_to_ground_vec_i(7 downto 0), + ------------------ Transmit Ports - pattern Generator Ports ---------------- + TXPRBSSEL => tied_to_ground_vec_i(2 downto 0), + ----------------------- Tx Configurable Driver Ports ---------------------- + TXQPISENN => open, + TXQPISENP => open + + ); + + + end RTL; + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_init.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_init.vhd new file mode 100644 index 0000000..bec1524 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_init.vhd @@ -0,0 +1,885 @@ +------------------------------------------------------------------------------ +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 3.5 +-- \ \ Application : 7 Series FPGAs Transceivers Wizard +-- / / Filename : gtxkintex7fee80_init.vhd +-- /___/ /\ +-- \ \ / \ +-- \___\/\___\ +-- +-- Description : This module instantiates the modules required for +-- reset and initialisation of the Transceiver +-- +-- Module gtxKintex7FEE80_init +-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard +-- +-- +-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; + +--***********************************Entity Declaration************************ + +entity gtxKintex7FEE80_init is +generic +( + EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model + EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation + USE_BUFG : integer := 0; -- Set to 1 for bufg usage for cpll railing logic + + STABLE_CLOCK_PERIOD : integer := 12; + -- Set to 1 for simulation + EXAMPLE_USE_CHIPSCOPE : integer := 1 --// Modified -- Set to 1 to use Chipscope to drive resets + +); +port +( + SYSCLK_IN : in std_logic; + SOFT_RESET_TX_IN : in std_logic; + SOFT_RESET_RX_IN : in std_logic; + DONT_RESET_ON_DATA_ERROR_IN : in std_logic; + GT0_TX_FSM_RESET_DONE_OUT : out std_logic; + GT0_RX_FSM_RESET_DONE_OUT : out std_logic; + GT0_DATA_VALID_IN : in std_logic; + GT0_TX_MMCM_LOCK_IN : in std_logic; + GT0_TX_MMCM_RESET_OUT : out std_logic; + --_________________________________________________________________________ + --GT0 (X1Y0) + --____________________________CHANNEL PORTS________________________________ + --------------------------------- CPLL Ports ------------------------------- + gt0_cpllfbclklost_out : out std_logic; + gt0_cplllock_out : out std_logic; + gt0_cplllockdetclk_in : in std_logic; + gt0_cpllreset_in : in std_logic; + -------------------------- Channel - Clocking Ports ------------------------ + gt0_gtrefclk0_in : in std_logic; + gt0_gtrefclk1_in : in std_logic; + ---------------------------- Channel - DRP Ports -------------------------- + gt0_drpaddr_in : in std_logic_vector(8 downto 0); + gt0_drpclk_in : in std_logic; + gt0_drpdi_in : in std_logic_vector(15 downto 0); + gt0_drpdo_out : out std_logic_vector(15 downto 0); + gt0_drpen_in : in std_logic; + gt0_drprdy_out : out std_logic; + gt0_drpwe_in : in std_logic; + --------------------------- Digital Monitor Ports -------------------------- + gt0_dmonitorout_out : out std_logic_vector(7 downto 0); + --------------------- RX Initialization and Reset Ports -------------------- + gt0_eyescanreset_in : in std_logic; + gt0_rxuserrdy_in : in std_logic; + -------------------------- RX Margin Analysis Ports ------------------------ + gt0_eyescandataerror_out : out std_logic; + gt0_eyescantrigger_in : in std_logic; + ------------------------- Receive Ports - CDR Ports ------------------------ + GT0_RXCDRRESET_IN : in std_logic; --// Modified + GT0_RXCDRLOCK_OUT : out std_logic; --// Modified + ------------------ Receive Ports - FPGA RX Interface Ports ----------------- + gt0_rxusrclk_in : in std_logic; + gt0_rxusrclk2_in : in std_logic; + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + gt0_rxdata_out : out std_logic_vector(15 downto 0); + ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- + gt0_rxdisperr_out : out std_logic_vector(1 downto 0); + gt0_rxnotintable_out : out std_logic_vector(1 downto 0); + --------------------------- Receive Ports - RX AFE ------------------------- + gt0_gtxrxp_in : in std_logic; + ------------------------ Receive Ports - RX AFE Ports ---------------------- + gt0_gtxrxn_in : in std_logic; + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + gt0_rxphmonitor_out : out std_logic_vector(4 downto 0); + gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0); + --------------------- Receive Ports - RX Equalizer Ports ------------------- + gt0_rxdfelpmreset_in : in std_logic; + gt0_rxmonitorout_out : out std_logic_vector(6 downto 0); + gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0); + --------------- Receive Ports - RX Fabric Output Control Ports ------------- + gt0_rxoutclk_out : out std_logic; + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + gt0_gtrxreset_in : in std_logic; + gt0_rxpmareset_in : in std_logic; + ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- + gt0_rxcharisk_out : out std_logic_vector(1 downto 0); + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + gt0_rxresetdone_out : out std_logic; + --------------------- TX Initialization and Reset Ports -------------------- + gt0_gttxreset_in : in std_logic; + gt0_txuserrdy_in : in std_logic; + ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- + gt0_txusrclk_in : in std_logic; + gt0_txusrclk2_in : in std_logic; + ------------------ Transmit Ports - TX Data Path interface ----------------- + gt0_txdata_in : in std_logic_vector(15 downto 0); + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + gt0_gtxtxn_out : out std_logic; + gt0_gtxtxp_out : out std_logic; + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + gt0_txoutclk_out : out std_logic; + gt0_txoutclkfabric_out : out std_logic; + gt0_txoutclkpcs_out : out std_logic; + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + gt0_txcharisk_in : in std_logic_vector(1 downto 0); + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + gt0_txresetdone_out : out std_logic; + + + --____________________________COMMON PORTS________________________________ + GT0_QPLLOUTCLK_IN : in std_logic; + GT0_QPLLOUTREFCLK_IN : in std_logic + +); + +end gtxKintex7FEE80_init; + +architecture RTL of gtxKintex7FEE80_init is +attribute DowngradeIPIdentifiedWarnings: string; +attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes"; + +--**************************Component Declarations***************************** + + +component gtxKintex7FEE80_multi_gt +generic +( + -- Simulation attributes + USE_BUFG : integer := 0; -- Set to 1 for bufg usage for cpll railing logic + WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" -- Set to "TRUE" to speed up sim reset + +); +port +( + + --_________________________________________________________________________ + --_________________________________________________________________________ + --GT0 (X1Y0) + --____________________________CHANNEL PORTS________________________________ + + --------------------------------- CPLL Ports ------------------------------- + gt0_cpllfbclklost_out : out std_logic; + gt0_cplllock_out : out std_logic; + gt0_cplllockdetclk_in : in std_logic; + gt0_cpllrefclklost_out : out std_logic; + gt0_cpllreset_in : in std_logic; + -------------------------- Channel - Clocking Ports ------------------------ + gt0_gtrefclk0_in : in std_logic; + gt0_gtrefclk1_in : in std_logic; + ---------------------------- Channel - DRP Ports -------------------------- + gt0_drpaddr_in : in std_logic_vector(8 downto 0); + gt0_drpclk_in : in std_logic; + gt0_drpdi_in : in std_logic_vector(15 downto 0); + gt0_drpdo_out : out std_logic_vector(15 downto 0); + gt0_drpen_in : in std_logic; + gt0_drprdy_out : out std_logic; + gt0_drpwe_in : in std_logic; + --------------------------- Digital Monitor Ports -------------------------- + gt0_dmonitorout_out : out std_logic_vector(7 downto 0); + --------------------- RX Initialization and Reset Ports -------------------- + gt0_eyescanreset_in : in std_logic; + gt0_rxuserrdy_in : in std_logic; + -------------------------- RX Margin Analysis Ports ------------------------ + gt0_eyescandataerror_out : out std_logic; + gt0_eyescantrigger_in : in std_logic; + ------------------------- Receive Ports - CDR Ports ------------------------ + GT0_RXCDRRESET_IN : in std_logic; --// Modified + GT0_RXCDRLOCK_OUT : out std_logic; --// Modified + ------------------ Receive Ports - FPGA RX Interface Ports ----------------- + gt0_rxusrclk_in : in std_logic; + gt0_rxusrclk2_in : in std_logic; + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + gt0_rxdata_out : out std_logic_vector(15 downto 0); + ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- + gt0_rxdisperr_out : out std_logic_vector(1 downto 0); + gt0_rxnotintable_out : out std_logic_vector(1 downto 0); + --------------------------- Receive Ports - RX AFE ------------------------- + gt0_gtxrxp_in : in std_logic; + ------------------------ Receive Ports - RX AFE Ports ---------------------- + gt0_gtxrxn_in : in std_logic; + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + gt0_rxdlyen_in : in std_logic; + gt0_rxdlysreset_in : in std_logic; + gt0_rxdlysresetdone_out : out std_logic; + gt0_rxphalign_in : in std_logic; + gt0_rxphaligndone_out : out std_logic; + gt0_rxphalignen_in : in std_logic; + gt0_rxphdlyreset_in : in std_logic; + gt0_rxphmonitor_out : out std_logic_vector(4 downto 0); + gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0); + -------------------- Receive Ports - RX Equailizer Ports ------------------- + gt0_rxlpmhfhold_in : in std_logic; + gt0_rxlpmlfhold_in : in std_logic; + --------------------- Receive Ports - RX Equalizer Ports ------------------- + gt0_rxdfelpmreset_in : in std_logic; + gt0_rxmonitorout_out : out std_logic_vector(6 downto 0); + gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0); + --------------- Receive Ports - RX Fabric Output Control Ports ------------- + gt0_rxoutclk_out : out std_logic; + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + gt0_gtrxreset_in : in std_logic; + gt0_rxpmareset_in : in std_logic; + ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- + gt0_rxcharisk_out : out std_logic_vector(1 downto 0); + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + gt0_rxresetdone_out : out std_logic; + --------------------- TX Initialization and Reset Ports -------------------- + gt0_gttxreset_in : in std_logic; + gt0_txuserrdy_in : in std_logic; + ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- + gt0_txusrclk_in : in std_logic; + gt0_txusrclk2_in : in std_logic; + ------------------ Transmit Ports - TX Buffer Bypass Ports ----------------- + gt0_txdlyen_in : in std_logic; + gt0_txdlysreset_in : in std_logic; + gt0_txdlysresetdone_out : out std_logic; + gt0_txphalign_in : in std_logic; + gt0_txphaligndone_out : out std_logic; + gt0_txphalignen_in : in std_logic; + gt0_txphdlyreset_in : in std_logic; + gt0_txphinit_in : in std_logic; + gt0_txphinitdone_out : out std_logic; + ------------------ Transmit Ports - TX Data Path interface ----------------- + gt0_txdata_in : in std_logic_vector(15 downto 0); + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + gt0_gtxtxn_out : out std_logic; + gt0_gtxtxp_out : out std_logic; + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + gt0_txoutclk_out : out std_logic; + gt0_txoutclkfabric_out : out std_logic; + gt0_txoutclkpcs_out : out std_logic; + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + gt0_txcharisk_in : in std_logic_vector(1 downto 0); + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + gt0_txresetdone_out : out std_logic; + + + --____________________________COMMON PORTS________________________________ + GT0_QPLLOUTCLK_IN : in std_logic; + GT0_QPLLOUTREFCLK_IN : in std_logic + +); +end component; + +component gtxKintex7FEE80_TX_STARTUP_FSM + Generic( + EXAMPLE_SIMULATION : integer := 0; + STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns] + RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8; + TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must + RX_QPLL_USED : boolean := False; -- share these two generic values + PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic + -- is enough. For single-lane applications the automatic alignment is + -- sufficient + ); + Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB + --or reference-clock present at startup. + TXUSERCLK : in STD_LOGIC; --TXUSERCLK as used in the design + SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time + QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost + CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost + QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT + CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT + TXRESETDONE : in STD_LOGIC; + MMCM_LOCK : in STD_LOGIC; + GTTXRESET : out STD_LOGIC:='0'; + MMCM_RESET : out STD_LOGIC:='0'; + QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL + CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL + TX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished. + TXUSERRDY : out STD_LOGIC:='0'; + RUN_PHALIGNMENT : out STD_LOGIC:='0'; + RESET_PHALIGNMENT : out STD_LOGIC:='0'; + PHALIGNMENT_DONE : in STD_LOGIC; + + RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of + -- Retries it took to get the transceiver up and running + ); +end component; + +component gtxKintex7FEE80_RX_STARTUP_FSM + Generic( + EXAMPLE_SIMULATION : integer := 0; + EQ_MODE : string := "DFE"; + STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns] + RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8; + TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must + RX_QPLL_USED : boolean := False; -- share these two generic values + PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic + -- is enough. For single-lane applications the automatic alignment is + -- sufficient + ); + Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB + --or reference-clock present at startup. + RXUSERCLK : in STD_LOGIC; --RXUSERCLK as used in the design + SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time + QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost + CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost + QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT + CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT + RXRESETDONE : in STD_LOGIC; + MMCM_LOCK : in STD_LOGIC; + RECCLK_STABLE : in STD_LOGIC; + RECCLK_MONITOR_RESTART : in STD_LOGIC; + DATA_VALID : in STD_LOGIC; + TXUSERRDY : in STD_LOGIC; --TXUSERRDY from GT + DONT_RESET_ON_DATA_ERROR : in STD_LOGIC; + GTRXRESET : out STD_LOGIC:='0'; + MMCM_RESET : out STD_LOGIC:='0'; + QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL (only if RX uses QPLL) + CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL (only if RX uses CPLL) + RX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished. + RXUSERRDY : out STD_LOGIC:='0'; + RUN_PHALIGNMENT : out STD_LOGIC; + PHALIGNMENT_DONE : in STD_LOGIC; + RESET_PHALIGNMENT : out STD_LOGIC:='0'; + RXDFEAGCHOLD : out STD_LOGIC; + RXDFELFHOLD : out STD_LOGIC; + RXLPMLFHOLD : out STD_LOGIC; + RXLPMHFHOLD : out STD_LOGIC; + RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of + -- Retries it took to get the transceiver up and running + ); +end component; + + + + +component gtxKintex7FEE80_AUTO_PHASE_ALIGN + port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB + --or reference-clock present at startup. + RUN_PHALIGNMENT : in STD_LOGIC; --Signal from the main Reset-FSM to run the auto phase-alignment procedure + PHASE_ALIGNMENT_DONE : out STD_LOGIC; -- Auto phase-alignment performed sucessfully + PHALIGNDONE : in STD_LOGIC; --\ Phase-alignment signals from and to the + DLYSRESET : out STD_LOGIC; -- |transceiver. + DLYSRESETDONE : in STD_LOGIC; --/ + RECCLKSTABLE : in STD_LOGIC --/on the RX-side. + + ); +end component; + + +component gtxKintex7FEE80_TX_MANUAL_PHASE_ALIGN + Generic( NUMBER_OF_LANES : integer range 1 to 32:= 4; -- Number of lanes that are controlled using this FSM. + MASTER_LANE_ID : integer range 0 to 31:= 0 -- Number of the lane which is considered the master in manual phase-alignment + ); + + Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB + --or reference-clock present at startup. + RESET_PHALIGNMENT : in STD_LOGIC; + RUN_PHALIGNMENT : in STD_LOGIC; + PHASE_ALIGNMENT_DONE : out STD_LOGIC := '0'; -- Manual phase-alignment performed sucessfully + TXDLYSRESET : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0'); + TXDLYSRESETDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0); + TXPHINIT : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0'); + TXPHINITDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0); + TXPHALIGN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0'); + TXPHALIGNDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0); + TXDLYEN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0') + ); +end component; + +component gtxKintex7FEE80_RX_MANUAL_PHASE_ALIGN + Generic( NUMBER_OF_LANES : integer range 1 to 32:= 4; -- Number of lanes that are controlled using this FSM. + MASTER_LANE_ID : integer range 0 to 31:= 0 -- Number of the lane which is considered the master in manual phase-alignment + ); + + Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB + --or reference-clock present at startup. + RESET_PHALIGNMENT : in STD_LOGIC; + RUN_PHALIGNMENT : in STD_LOGIC; + PHASE_ALIGNMENT_DONE : out STD_LOGIC := '0'; -- Manual phase-alignment performed sucessfully + RXDLYSRESET : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0'); + RXDLYSRESETDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0); + RXPHALIGN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0'); + RXPHALIGNDONE : in STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0); + RXDLYEN : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0') + ); +end component; + + function get_cdrlock_time(is_sim : in integer) return integer is + variable lock_time: integer; + begin + if (is_sim = 1) then + lock_time := 1000; + else + lock_time := 50000 / integer(2); --Typical CDR lock time is 50,000UI as per DS183 + end if; + return lock_time; + end function; + + +--***********************************Parameter Declarations******************** + + constant DLY : time := 1 ns; + constant RX_CDRLOCK_TIME : integer := get_cdrlock_time(EXAMPLE_SIMULATION); -- 200us + constant WAIT_TIME_CDRLOCK : integer := RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD; -- 200 us time-out + + + + -------------------------- GT Wrapper Wires ------------------------------ + signal gt0_txpmaresetdone_i : std_logic; + signal gt0_rxpmaresetdone_i : std_logic; + signal gt0_cpllreset_i : std_logic; + signal gt0_cpllreset_t : std_logic; + signal gt0_cpllrefclklost_i : std_logic; + signal gt0_cplllock_i : std_logic; + signal gt0_txresetdone_i : std_logic; + signal gt0_rxresetdone_i : std_logic; + signal gt0_gttxreset_i : std_logic; + signal gt0_gttxreset_t : std_logic; + signal gt0_gtrxreset_i : std_logic; + signal gt0_gtrxreset_t : std_logic; + signal gt0_rxdfelpmreset_i : std_logic; + signal gt0_txuserrdy_i : std_logic; + signal gt0_txuserrdy_t : std_logic; + signal gt0_rxuserrdy_i : std_logic; + signal gt0_rxuserrdy_t : std_logic; + + signal gt0_rxdfeagchold_i : std_logic; + signal gt0_rxdfelfhold_i : std_logic; + signal gt0_rxlpmlfhold_i : std_logic; + signal gt0_rxlpmhfhold_i : std_logic; + + + + signal gt0_qpllreset_i : std_logic; + signal gt0_qpllreset_t : std_logic; + signal gt0_qpllrefclklost_i : std_logic; + signal gt0_qplllock_i : std_logic; + + + ------------------------------- Global Signals ----------------------------- + signal tied_to_ground_i : std_logic; + signal tied_to_vcc_i : std_logic; + signal gt0_txphaligndone_i : std_logic; + signal gt0_txdlysreset_i : std_logic; + signal gt0_txdlysresetdone_i : std_logic; + signal gt0_txphdlyreset_i : std_logic; + signal gt0_txphalignen_i : std_logic; + signal gt0_txdlyen_i : std_logic; + signal gt0_txphalign_i : std_logic; + signal gt0_txphinit_i : std_logic; + signal gt0_txphinitdone_i : std_logic; + signal gt0_run_tx_phalignment_i : std_logic; + signal gt0_rst_tx_phalignment_i : std_logic; + signal gt0_tx_phalignment_done_i : std_logic; + + signal gt0_txoutclk_i : std_logic; + signal gt0_rxoutclk_i : std_logic; + signal gt0_rxoutclk_i2 : std_logic; + signal gt0_txoutclk_i2 : std_logic; + signal gt0_recclk_stable_i : std_logic; + signal gt0_rx_cdrlocked : std_logic; + signal gt0_rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ; + signal gt0_rxphaligndone_i : std_logic; + signal gt0_rxdlysreset_i : std_logic; + signal gt0_rxdlysresetdone_i : std_logic; + signal gt0_rxphdlyreset_i : std_logic; + signal gt0_rxphalignen_i : std_logic; + signal gt0_rxdlyen_i : std_logic; + signal gt0_rxphalign_i : std_logic; + signal gt0_run_rx_phalignment_i : std_logic; + signal gt0_rst_rx_phalignment_i : std_logic; + signal gt0_rx_phalignment_done_i : std_logic; + + + + --------------------------- TX Buffer Bypass Signals -------------------- + signal mstr0_txsyncallin_i : std_logic; + signal U0_TXDLYEN : std_logic_vector(0 downto 0); + signal U0_TXDLYSRESET : std_logic_vector(0 downto 0); + signal U0_TXDLYSRESETDONE : std_logic_vector(0 downto 0); + signal U0_TXPHINIT : std_logic_vector(0 downto 0); + signal U0_TXPHINITDONE : std_logic_vector(0 downto 0); + signal U0_TXPHALIGN : std_logic_vector(0 downto 0); + signal U0_TXPHALIGNDONE : std_logic_vector(0 downto 0); + signal U0_run_tx_phalignment_i : std_logic; + signal U0_rst_tx_phalignment_i : std_logic; + + + --------------------------- RX Buffer Bypass Signals -------------------- + signal rxmstr0_rxsyncallin_i : std_logic; + signal U0_RXDLYEN : std_logic_vector(0 downto 0); + signal U0_RXDLYSRESET : std_logic_vector(0 downto 0); + signal U0_RXDLYSRESETDONE : std_logic_vector(0 downto 0); + signal U0_RXPHALIGN : std_logic_vector(0 downto 0); + signal U0_RXPHALIGNDONE : std_logic_vector(0 downto 0); + signal U0_run_rx_phalignment_i : std_logic; + signal U0_rst_rx_phalignment_i : std_logic; + + + + signal rx_cdrlocked : std_logic; + + + + + +--**************************** Main Body of Code ******************************* +begin + -- Static signal Assigments + tied_to_ground_i <= '0'; + tied_to_vcc_i <= '1'; + + ----------------------------- The GT Wrapper ----------------------------- + + -- Use the instantiation template in the example directory to add the GT wrapper to your design. + -- In this example, the wrapper is wired up for basic operation with a frame generator and frame + -- checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is + -- enabled, bonding should occur after alignment. + + + gtxKintex7FEE80_i : gtxKintex7FEE80_multi_gt + generic map + ( + USE_BUFG => USE_BUFG, + WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP + ) + port map + ( + --_____________________________________________________________________ + --_____________________________________________________________________ + --GT0 (X1Y0) + + --------------------------------- CPLL Ports ------------------------------- + gt0_cpllfbclklost_out => gt0_cpllfbclklost_out, + gt0_cplllock_out => gt0_cplllock_i, + gt0_cplllockdetclk_in => gt0_cplllockdetclk_in, + gt0_cpllrefclklost_out => gt0_cpllrefclklost_i, + gt0_cpllreset_in => gt0_cpllreset_i, + -------------------------- Channel - Clocking Ports ------------------------ + gt0_gtrefclk0_in => gt0_gtrefclk0_in, + gt0_gtrefclk1_in => gt0_gtrefclk1_in, + ---------------------------- Channel - DRP Ports -------------------------- + gt0_drpaddr_in => gt0_drpaddr_in, + gt0_drpclk_in => gt0_drpclk_in, + gt0_drpdi_in => gt0_drpdi_in, + gt0_drpdo_out => gt0_drpdo_out, + gt0_drpen_in => gt0_drpen_in, + gt0_drprdy_out => gt0_drprdy_out, + gt0_drpwe_in => gt0_drpwe_in, + --------------------------- Digital Monitor Ports -------------------------- + gt0_dmonitorout_out => gt0_dmonitorout_out, + --------------------- RX Initialization and Reset Ports -------------------- + gt0_eyescanreset_in => gt0_eyescanreset_in, + gt0_rxuserrdy_in => gt0_rxuserrdy_i, + -------------------------- RX Margin Analysis Ports ------------------------ + gt0_eyescandataerror_out => gt0_eyescandataerror_out, + gt0_eyescantrigger_in => gt0_eyescantrigger_in, + ------------------------- Receive Ports - CDR Ports ------------------------ + GT0_RXCDRRESET_IN => GT0_RXCDRRESET_IN, --// Modified + GT0_RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT, --// Modified + ------------------ Receive Ports - FPGA RX Interface Ports ----------------- + gt0_rxusrclk_in => gt0_rxusrclk_in, + gt0_rxusrclk2_in => gt0_rxusrclk2_in, + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + gt0_rxdata_out => gt0_rxdata_out, + ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- + gt0_rxdisperr_out => gt0_rxdisperr_out, + gt0_rxnotintable_out => gt0_rxnotintable_out, + --------------------------- Receive Ports - RX AFE ------------------------- + gt0_gtxrxp_in => gt0_gtxrxp_in, + ------------------------ Receive Ports - RX AFE Ports ---------------------- + gt0_gtxrxn_in => gt0_gtxrxn_in, + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + gt0_rxdlyen_in => gt0_rxdlyen_i, + gt0_rxdlysreset_in => gt0_rxdlysreset_i, + gt0_rxdlysresetdone_out => gt0_rxdlysresetdone_i, + gt0_rxphalign_in => gt0_rxphalign_i, + gt0_rxphaligndone_out => gt0_rxphaligndone_i, + gt0_rxphalignen_in => gt0_rxphalignen_i, + gt0_rxphdlyreset_in => gt0_rxphdlyreset_i, + gt0_rxphmonitor_out => gt0_rxphmonitor_out, + gt0_rxphslipmonitor_out => gt0_rxphslipmonitor_out, + -------------------- Receive Ports - RX Equailizer Ports ------------------- + gt0_rxlpmhfhold_in => gt0_rxlpmhfhold_i, + gt0_rxlpmlfhold_in => gt0_rxlpmlfhold_i, + --------------------- Receive Ports - RX Equalizer Ports ------------------- + gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in, + gt0_rxmonitorout_out => gt0_rxmonitorout_out, + gt0_rxmonitorsel_in => gt0_rxmonitorsel_in, + --------------- Receive Ports - RX Fabric Output Control Ports ------------- + gt0_rxoutclk_out => gt0_rxoutclk_i, + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + gt0_gtrxreset_in => gt0_gtrxreset_i, + gt0_rxpmareset_in => gt0_rxpmareset_in, + ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- + gt0_rxcharisk_out => gt0_rxcharisk_out, + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + gt0_rxresetdone_out => gt0_rxresetdone_i, + --------------------- TX Initialization and Reset Ports -------------------- + gt0_gttxreset_in => gt0_gttxreset_i, + gt0_txuserrdy_in => gt0_txuserrdy_i, + ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- + gt0_txusrclk_in => gt0_txusrclk_in, + gt0_txusrclk2_in => gt0_txusrclk2_in, + ------------------ Transmit Ports - TX Buffer Bypass Ports ----------------- + gt0_txdlyen_in => gt0_txdlyen_i, + gt0_txdlysreset_in => gt0_txdlysreset_i, + gt0_txdlysresetdone_out => gt0_txdlysresetdone_i, + gt0_txphalign_in => gt0_txphalign_i, + gt0_txphaligndone_out => gt0_txphaligndone_i, + gt0_txphalignen_in => gt0_txphalignen_i, + gt0_txphdlyreset_in => gt0_txphdlyreset_i, + gt0_txphinit_in => gt0_txphinit_i, + gt0_txphinitdone_out => gt0_txphinitdone_i, + ------------------ Transmit Ports - TX Data Path interface ----------------- + gt0_txdata_in => gt0_txdata_in, + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + gt0_gtxtxn_out => gt0_gtxtxn_out, + gt0_gtxtxp_out => gt0_gtxtxp_out, + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + gt0_txoutclk_out => gt0_txoutclk_i, + gt0_txoutclkfabric_out => gt0_txoutclkfabric_out, + gt0_txoutclkpcs_out => gt0_txoutclkpcs_out, + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + gt0_txcharisk_in => gt0_txcharisk_in, + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + gt0_txresetdone_out => gt0_txresetdone_i, + + + + + --____________________________COMMON PORTS________________________________ + gt0_qplloutclk_in => gt0_qplloutclk_in, + gt0_qplloutrefclk_in => gt0_qplloutrefclk_in + ); + + +gt0_rxdfelpmreset_i <= tied_to_ground_i; + + +GT0_CPLLLOCK_OUT <= gt0_cplllock_i; +GT0_TXRESETDONE_OUT <= gt0_txresetdone_i; +GT0_RXRESETDONE_OUT <= gt0_rxresetdone_i; +GT0_RXOUTCLK_OUT <= gt0_rxoutclk_i; +GT0_TXOUTCLK_OUT <= gt0_txoutclk_i; + +chipscope : if EXAMPLE_USE_CHIPSCOPE = 1 generate +gt0_cpllreset_i <= GT0_CPLLRESET_IN or gt0_cpllreset_t; + gt0_gttxreset_i <= GT0_GTTXRESET_IN or gt0_gttxreset_t; + gt0_gtrxreset_i <= GT0_GTRXRESET_IN or gt0_gtrxreset_t; + gt0_txuserrdy_i <= GT0_TXUSERRDY_IN or gt0_txuserrdy_t; + gt0_rxuserrdy_i <= GT0_RXUSERRDY_IN or gt0_rxuserrdy_t; +end generate chipscope; + +no_chipscope : if EXAMPLE_USE_CHIPSCOPE = 0 generate +gt0_cpllreset_i <= gt0_cpllreset_t; +gt0_gttxreset_i <= gt0_gttxreset_t; +gt0_gtrxreset_i <= gt0_gtrxreset_t; +gt0_txuserrdy_i <= gt0_txuserrdy_t; +gt0_rxuserrdy_i <= gt0_rxuserrdy_t; +end generate no_chipscope; + + +gt0_txresetfsm_i: gtxKintex7FEE80_TX_STARTUP_FSM + + generic map( + EXAMPLE_SIMULATION => EXAMPLE_SIMULATION, + STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns] + RETRY_COUNTER_BITWIDTH => 8, + TX_QPLL_USED => FALSE , -- the TX and RX Reset FSMs must + RX_QPLL_USED => FALSE, -- share these two generic values + PHASE_ALIGNMENT_MANUAL => TRUE -- Decision if a manual phase-alignment is necessary or the automatic + -- is enough. For single-lane applications the automatic alignment is + -- sufficient + ) + port map ( + STABLE_CLOCK => SYSCLK_IN, + TXUSERCLK => GT0_TXUSRCLK_IN, + SOFT_RESET => SOFT_RESET_TX_IN, + QPLLREFCLKLOST => tied_to_ground_i, + CPLLREFCLKLOST => gt0_cpllrefclklost_i, + QPLLLOCK => tied_to_vcc_i, + CPLLLOCK => gt0_cplllock_i, + TXRESETDONE => gt0_txresetdone_i, + MMCM_LOCK => GT0_TX_MMCM_LOCK_IN, + GTTXRESET => gt0_gttxreset_t, + MMCM_RESET => GT0_TX_MMCM_RESET_OUT, + QPLL_RESET => open, + CPLL_RESET => gt0_cpllreset_t, + TX_FSM_RESET_DONE => GT0_TX_FSM_RESET_DONE_OUT, + TXUSERRDY => gt0_txuserrdy_t, + RUN_PHALIGNMENT => gt0_run_tx_phalignment_i, + RESET_PHALIGNMENT => gt0_rst_tx_phalignment_i, + PHALIGNMENT_DONE => gt0_tx_phalignment_done_i, + RETRY_COUNTER => open + ); + + + + + + + + +gt0_rxresetfsm_i: gtxKintex7FEE80_RX_STARTUP_FSM + + generic map( + EXAMPLE_SIMULATION => EXAMPLE_SIMULATION, + EQ_MODE => "LPM", --Rx Equalization Mode - Set to DFE or LPM + STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns] + RETRY_COUNTER_BITWIDTH => 8, + TX_QPLL_USED => FALSE , -- the TX and RX Reset FSMs must + RX_QPLL_USED => FALSE, -- share these two generic values + PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic + -- is enough. For single-lane applications the automatic alignment is + -- sufficient + ) + port map ( + STABLE_CLOCK => SYSCLK_IN, + RXUSERCLK => GT0_RXUSRCLK_IN, + SOFT_RESET => SOFT_RESET_RX_IN, + DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN, + QPLLREFCLKLOST => tied_to_ground_i, + CPLLREFCLKLOST => gt0_cpllrefclklost_i, + QPLLLOCK => tied_to_vcc_i, + CPLLLOCK => gt0_cplllock_i, + RXRESETDONE => gt0_rxresetdone_i, + MMCM_LOCK => tied_to_vcc_i, + RECCLK_STABLE => gt0_recclk_stable_i, + RECCLK_MONITOR_RESTART => tied_to_ground_i, + DATA_VALID => GT0_DATA_VALID_IN, + TXUSERRDY => tied_to_vcc_i, + GTRXRESET => gt0_gtrxreset_t, + MMCM_RESET => open, + QPLL_RESET => open, + CPLL_RESET => open, + RX_FSM_RESET_DONE => GT0_RX_FSM_RESET_DONE_OUT, + RXUSERRDY => gt0_rxuserrdy_t, + RUN_PHALIGNMENT => gt0_run_rx_phalignment_i, + RESET_PHALIGNMENT => gt0_rst_rx_phalignment_i, + PHALIGNMENT_DONE => gt0_rx_phalignment_done_i, + RXDFEAGCHOLD => gt0_rxdfeagchold_i, + RXDFELFHOLD => gt0_rxdfelfhold_i, + RXLPMLFHOLD => gt0_rxlpmlfhold_i, + RXLPMHFHOLD => gt0_rxlpmhfhold_i, + RETRY_COUNTER => open + ); + + + + gt0_cdrlock_timeout:process(SYSCLK_IN) + begin + if rising_edge(SYSCLK_IN) then + if(gt0_gtrxreset_i = '1') then + gt0_rx_cdrlocked <= '0'; + gt0_rx_cdrlock_counter <= 0 after DLY; + elsif (gt0_rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then + gt0_rx_cdrlocked <= '1'; + gt0_rx_cdrlock_counter <= gt0_rx_cdrlock_counter after DLY; + else + gt0_rx_cdrlock_counter <= gt0_rx_cdrlock_counter + 1 after DLY; + end if; + end if; + end process; + +gt0_recclk_stable_i <= gt0_rx_cdrlocked; + + + + --------------------------- TX Buffer Bypass Logic -------------------- + -- The TX SYNC Module drives the ports needed to Bypass the TX Buffer. + -- Include the TX SYNC module in your own design if TX Buffer is bypassed. + + +--Auto +gt0_txphdlyreset_i <= tied_to_ground_i; +gt0_txphalignen_i <= tied_to_ground_i; +gt0_txdlyen_i <= tied_to_ground_i; +gt0_txphalign_i <= tied_to_ground_i; +gt0_txphinit_i <= tied_to_ground_i; + +gt0_tx_auto_phase_align_i : gtxKintex7FEE80_AUTO_PHASE_ALIGN + port map ( + STABLE_CLOCK => SYSCLK_IN, + RUN_PHALIGNMENT => gt0_run_tx_phalignment_i, + PHASE_ALIGNMENT_DONE => gt0_tx_phalignment_done_i, + PHALIGNDONE => gt0_txphaligndone_i, + DLYSRESET => gt0_txdlysreset_i, + DLYSRESETDONE => gt0_txdlysresetdone_i, + RECCLKSTABLE => tied_to_vcc_i + ); + + + + + --------------------------- RX Buffer Bypass Logic -------------------- +-- The RX SYNC Module drives the ports needed to Bypass the RX Buffer. +-- Include the RX SYNC module in your own design if RX Buffer is bypassed. + + +--Auto +gt0_rxphdlyreset_i <= '1'; --// Modified??????? tied_to_ground_i; +gt0_rxphalignen_i <= '1'; --// Modified??????? tied_to_ground_i; +gt0_rxdlyen_i <= tied_to_ground_i; +gt0_rxphalign_i <= tied_to_ground_i; + + +gt0_rx_phalignment_done_i <= '1'; --// Modified +gt0_rxdlysreset_i <= '1'; --// Modified +-- gt0_rx_auto_phase_align_i : gtxKintex7FEE80_AUTO_PHASE_ALIGN + -- port map ( + -- STABLE_CLOCK => SYSCLK_IN, + -- RUN_PHALIGNMENT => gt0_run_rx_phalignment_i, + -- PHASE_ALIGNMENT_DONE => gt0_rx_phalignment_done_i, + -- PHALIGNDONE => gt0_rxphaligndone_i, + -- DLYSRESET => gt0_rxdlysreset_i, + -- DLYSRESETDONE => gt0_rxdlysresetdone_i, + -- RECCLKSTABLE => gt0_recclk_stable_i + -- ); + + + +end RTL; + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_multi_gt.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_multi_gt.vhd new file mode 100644 index 0000000..0bdbbd2 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_multi_gt.vhd @@ -0,0 +1,509 @@ +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 3.5 +-- \ \ Application : 7 Series FPGAs Transceivers Wizard +-- / / Filename : gtxkintex7fee80_multi_gt.vhd +-- /___/ /\ +-- \ \ / \ +-- \___\/\___\ +-- +-- +-- Module gtxKintex7FEE80_multi_gt (a Multi GT Wrapper) +-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard +-- +-- +-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; + + +--***************************** Entity Declaration **************************** + +entity gtxKintex7FEE80_multi_gt is +generic +( + -- Simulation attributes + WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "TRUE" to speed up sim reset + RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC"; + USE_BUFG : integer := 0; -- Set to 1 for bufg usage for cpll railing logic + + PMA_RSV_IN : bit_vector := x"00018480" +); +port +( + --_________________________________________________________________________ + --_________________________________________________________________________ + --GT0 (X0Y0) + --____________________________CHANNEL PORTS________________________________ + --------------------------------- CPLL Ports ------------------------------- + gt0_cpllfbclklost_out : out std_logic; + gt0_cplllock_out : out std_logic; + gt0_cplllockdetclk_in : in std_logic; + gt0_cpllrefclklost_out : out std_logic; + gt0_cpllreset_in : in std_logic; + -------------------------- Channel - Clocking Ports ------------------------ + gt0_gtrefclk0_in : in std_logic; + gt0_gtrefclk1_in : in std_logic; + ---------------------------- Channel - DRP Ports -------------------------- + gt0_drpaddr_in : in std_logic_vector(8 downto 0); + gt0_drpclk_in : in std_logic; + gt0_drpdi_in : in std_logic_vector(15 downto 0); + gt0_drpdo_out : out std_logic_vector(15 downto 0); + gt0_drpen_in : in std_logic; + gt0_drprdy_out : out std_logic; + gt0_drpwe_in : in std_logic; + --------------------------- Digital Monitor Ports -------------------------- + gt0_dmonitorout_out : out std_logic_vector(7 downto 0); + --------------------- RX Initialization and Reset Ports -------------------- + gt0_eyescanreset_in : in std_logic; + gt0_rxuserrdy_in : in std_logic; + -------------------------- RX Margin Analysis Ports ------------------------ + gt0_eyescandataerror_out : out std_logic; + gt0_eyescantrigger_in : in std_logic; + ------------------------- Receive Ports - CDR Ports ------------------------ + GT0_RXCDRRESET_IN : in std_logic; --// Modified + GT0_RXCDRLOCK_OUT : out std_logic; --// Modified + ------------------ Receive Ports - FPGA RX Interface Ports ----------------- + gt0_rxusrclk_in : in std_logic; + gt0_rxusrclk2_in : in std_logic; + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + gt0_rxdata_out : out std_logic_vector(15 downto 0); + ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- + gt0_rxdisperr_out : out std_logic_vector(1 downto 0); + gt0_rxnotintable_out : out std_logic_vector(1 downto 0); + --------------------------- Receive Ports - RX AFE ------------------------- + gt0_gtxrxp_in : in std_logic; + ------------------------ Receive Ports - RX AFE Ports ---------------------- + gt0_gtxrxn_in : in std_logic; + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + gt0_rxdlyen_in : in std_logic; + gt0_rxdlysreset_in : in std_logic; + gt0_rxdlysresetdone_out : out std_logic; + gt0_rxphalign_in : in std_logic; + gt0_rxphaligndone_out : out std_logic; + gt0_rxphalignen_in : in std_logic; + gt0_rxphdlyreset_in : in std_logic; + gt0_rxphmonitor_out : out std_logic_vector(4 downto 0); + gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0); + -------------------- Receive Ports - RX Equailizer Ports ------------------- + gt0_rxlpmhfhold_in : in std_logic; + gt0_rxlpmlfhold_in : in std_logic; + --------------------- Receive Ports - RX Equalizer Ports ------------------- + gt0_rxdfelpmreset_in : in std_logic; + gt0_rxmonitorout_out : out std_logic_vector(6 downto 0); + gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0); + --------------- Receive Ports - RX Fabric Output Control Ports ------------- + gt0_rxoutclk_out : out std_logic; + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + gt0_gtrxreset_in : in std_logic; + gt0_rxpmareset_in : in std_logic; + ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- + gt0_rxcharisk_out : out std_logic_vector(1 downto 0); + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + gt0_rxresetdone_out : out std_logic; + --------------------- TX Initialization and Reset Ports -------------------- + gt0_gttxreset_in : in std_logic; + gt0_txuserrdy_in : in std_logic; + ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- + gt0_txusrclk_in : in std_logic; + gt0_txusrclk2_in : in std_logic; + ------------------ Transmit Ports - TX Buffer Bypass Ports ----------------- + gt0_txdlyen_in : in std_logic; + gt0_txdlysreset_in : in std_logic; + gt0_txdlysresetdone_out : out std_logic; + gt0_txphalign_in : in std_logic; + gt0_txphaligndone_out : out std_logic; + gt0_txphalignen_in : in std_logic; + gt0_txphdlyreset_in : in std_logic; + gt0_txphinit_in : in std_logic; + gt0_txphinitdone_out : out std_logic; + ------------------ Transmit Ports - TX Data Path interface ----------------- + gt0_txdata_in : in std_logic_vector(15 downto 0); + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + gt0_gtxtxn_out : out std_logic; + gt0_gtxtxp_out : out std_logic; + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + gt0_txoutclk_out : out std_logic; + gt0_txoutclkfabric_out : out std_logic; + gt0_txoutclkpcs_out : out std_logic; + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + gt0_txcharisk_in : in std_logic_vector(1 downto 0); + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + gt0_txresetdone_out : out std_logic; + + + --____________________________COMMON PORTS________________________________ + GT0_QPLLOUTCLK_IN : in std_logic; + GT0_QPLLOUTREFCLK_IN : in std_logic + +); + + +end gtxKintex7FEE80_multi_gt; + +architecture RTL of gtxKintex7FEE80_multi_gt is + attribute DowngradeIPIdentifiedWarnings: string; + attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes"; + + attribute CORE_GENERATION_INFO : string; + attribute CORE_GENERATION_INFO of RTL : architecture is "gtxKintex7FEE80_multi_gt,gtwizard_v3_5,{protocol_file=Start_from_scratch}"; + + +--***********************************Parameter Declarations******************** + + constant DLY : time := 1 ns; + +--***************************** Signal Declarations ***************************** + + -- ground and tied_to_vcc_i signals + signal tied_to_ground_i : std_logic; + signal tied_to_ground_vec_i : std_logic_vector(63 downto 0); + signal tied_to_vcc_i : std_logic; + signal gt0_qplloutclk_i : std_logic; + signal gt0_qplloutrefclk_i : std_logic; + + signal gt0_mgtrefclktx_i : std_logic_vector(1 downto 0); + signal gt0_mgtrefclkrx_i : std_logic_vector(1 downto 0); + + signal gt0_qpllclk_i : std_logic; + signal gt0_qpllrefclk_i : std_logic; + signal gt0_cpllreset_i : std_logic; + signal gt0_cpllpd_i : std_logic; + signal cpll_reset0_i : std_logic; + signal cpll_pd0_i : std_logic; + +--*************************** Component Declarations ************************** +component gtxKintex7FEE80_GT +generic +( + -- Simulation attributes + GT_SIM_GTRESET_SPEEDUP : string := "FALSE"; + RX_DFE_KL_CFG2_IN : bit_vector := X"3010D90C"; + PMA_RSV_IN : bit_vector := X"00000000"; + SIM_CPLLREFCLK_SEL : bit_vector := "001"; + PCS_RSVD_ATTR_IN : bit_vector := X"000000000000" +); +port +( + cpllpd_in : in std_logic; + cpllrefclksel_in : in std_logic_vector (2 downto 0); + --------------------------------- CPLL Ports ------------------------------- + cpllfbclklost_out : out std_logic; + cplllock_out : out std_logic; + cplllockdetclk_in : in std_logic; + cpllrefclklost_out : out std_logic; + cpllreset_in : in std_logic; + -------------------------- Channel - Clocking Ports ------------------------ + gtrefclk0_in : in std_logic; + gtrefclk1_in : in std_logic; + ---------------------------- Channel - DRP Ports -------------------------- + drpaddr_in : in std_logic_vector(8 downto 0); + drpclk_in : in std_logic; + drpdi_in : in std_logic_vector(15 downto 0); + drpdo_out : out std_logic_vector(15 downto 0); + drpen_in : in std_logic; + drprdy_out : out std_logic; + drpwe_in : in std_logic; + ------------------------------- Clocking Ports ----------------------------- + qpllclk_in : in std_logic; + qpllrefclk_in : in std_logic; + --------------------------- Digital Monitor Ports -------------------------- + dmonitorout_out : out std_logic_vector(7 downto 0); + --------------------- RX Initialization and Reset Ports -------------------- + eyescanreset_in : in std_logic; + rxuserrdy_in : in std_logic; + -------------------------- RX Margin Analysis Ports ------------------------ + eyescandataerror_out : out std_logic; + eyescantrigger_in : in std_logic; + ------------------------- Receive Ports - CDR Ports ------------------------ + RXCDRRESET_IN : in std_logic; --// Modified + RXCDRLOCK_OUT : out std_logic; --// Modified + ------------------ Receive Ports - FPGA RX Interface Ports ----------------- + rxusrclk_in : in std_logic; + rxusrclk2_in : in std_logic; + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + rxdata_out : out std_logic_vector(15 downto 0); + ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- + rxdisperr_out : out std_logic_vector(1 downto 0); + rxnotintable_out : out std_logic_vector(1 downto 0); + --------------------------- Receive Ports - RX AFE ------------------------- + gtxrxp_in : in std_logic; + ------------------------ Receive Ports - RX AFE Ports ---------------------- + gtxrxn_in : in std_logic; + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + rxdlyen_in : in std_logic; + rxdlysreset_in : in std_logic; + rxdlysresetdone_out : out std_logic; + rxphalign_in : in std_logic; + rxphaligndone_out : out std_logic; + rxphalignen_in : in std_logic; + rxphdlyreset_in : in std_logic; + rxphmonitor_out : out std_logic_vector(4 downto 0); + rxphslipmonitor_out : out std_logic_vector(4 downto 0); + -------------------- Receive Ports - RX Equailizer Ports ------------------- + rxlpmhfhold_in : in std_logic; + rxlpmlfhold_in : in std_logic; + --------------------- Receive Ports - RX Equalizer Ports ------------------- + rxdfelpmreset_in : in std_logic; + rxmonitorout_out : out std_logic_vector(6 downto 0); + rxmonitorsel_in : in std_logic_vector(1 downto 0); + --------------- Receive Ports - RX Fabric Output Control Ports ------------- + rxoutclk_out : out std_logic; + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + gtrxreset_in : in std_logic; + rxpmareset_in : in std_logic; + ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- + rxcharisk_out : out std_logic_vector(1 downto 0); + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + rxresetdone_out : out std_logic; + --------------------- TX Initialization and Reset Ports -------------------- + gttxreset_in : in std_logic; + txuserrdy_in : in std_logic; + ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- + txusrclk_in : in std_logic; + txusrclk2_in : in std_logic; + ------------------ Transmit Ports - TX Buffer Bypass Ports ----------------- + txdlyen_in : in std_logic; + txdlysreset_in : in std_logic; + txdlysresetdone_out : out std_logic; + txphalign_in : in std_logic; + txphaligndone_out : out std_logic; + txphalignen_in : in std_logic; + txphdlyreset_in : in std_logic; + txphinit_in : in std_logic; + txphinitdone_out : out std_logic; + ------------------ Transmit Ports - TX Data Path interface ----------------- + txdata_in : in std_logic_vector(15 downto 0); + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + gtxtxn_out : out std_logic; + gtxtxp_out : out std_logic; + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + txoutclk_out : out std_logic; + txoutclkfabric_out : out std_logic; + txoutclkpcs_out : out std_logic; + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + txcharisk_in : in std_logic_vector(1 downto 0); + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + txresetdone_out : out std_logic + + +); +end component; +component gtxKintex7FEE80_cpll_railing + Generic( + USE_BUFG : integer := 0 +); +port +( + cpll_reset_out : out std_logic; + cpll_pd_out : out std_logic; + refclk_out : out std_logic; + + refclk_in : in std_logic + +); +end component; + + + +--********************************* Main Body of Code************************** + +begin + + tied_to_ground_i <= '0'; + tied_to_ground_vec_i(63 downto 0) <= (others => '0'); + tied_to_vcc_i <= '1'; + gt0_qpllclk_i <= GT0_QPLLOUTCLK_IN; + gt0_qpllrefclk_i <= GT0_QPLLOUTREFCLK_IN; + + + + --------------------------- GT Instances ------------------------------- + + --_________________________________________________________________________ + --_________________________________________________________________________ + --GT0 (X0Y0) + +gt0_gtxKintex7FEE80_i : gtxKintex7FEE80_GT + generic map + ( + -- Simulation attributes + GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP, + RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN, + SIM_CPLLREFCLK_SEL => "001", + PMA_RSV_IN => PMA_RSV_IN, + PCS_RSVD_ATTR_IN => X"000000000000" + ) + port map + ( + cpllpd_in => gt0_cpllpd_i, + cpllrefclksel_in => "001", + --------------------------------- CPLL Ports ------------------------------- + cpllfbclklost_out => gt0_cpllfbclklost_out, + cplllock_out => gt0_cplllock_out, + cplllockdetclk_in => gt0_cplllockdetclk_in, + cpllrefclklost_out => gt0_cpllrefclklost_out, + cpllreset_in => gt0_cpllreset_i, + -------------------------- Channel - Clocking Ports ------------------------ + gtrefclk0_in => gt0_gtrefclk0_in, + gtrefclk1_in => gt0_gtrefclk1_in, + ---------------------------- Channel - DRP Ports -------------------------- + drpaddr_in => gt0_drpaddr_in, + drpclk_in => gt0_drpclk_in, + drpdi_in => gt0_drpdi_in, + drpdo_out => gt0_drpdo_out, + drpen_in => gt0_drpen_in, + drprdy_out => gt0_drprdy_out, + drpwe_in => gt0_drpwe_in, + ------------------------------- Clocking Ports ----------------------------- + qpllclk_in => gt0_qpllclk_i, + qpllrefclk_in => gt0_qpllrefclk_i, + --------------------------- Digital Monitor Ports -------------------------- + dmonitorout_out => gt0_dmonitorout_out, + --------------------- RX Initialization and Reset Ports -------------------- + eyescanreset_in => gt0_eyescanreset_in, + rxuserrdy_in => gt0_rxuserrdy_in, + -------------------------- RX Margin Analysis Ports ------------------------ + eyescandataerror_out => gt0_eyescandataerror_out, + eyescantrigger_in => gt0_eyescantrigger_in, + ------------------------- Receive Ports - CDR Ports ------------------------ + RXCDRRESET_IN => GT0_RXCDRRESET_IN, --// Modified + RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT, --// Modified + ------------------ Receive Ports - FPGA RX Interface Ports ----------------- + rxusrclk_in => gt0_rxusrclk_in, + rxusrclk2_in => gt0_rxusrclk2_in, + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + rxdata_out => gt0_rxdata_out, + ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- + rxdisperr_out => gt0_rxdisperr_out, + rxnotintable_out => gt0_rxnotintable_out, + --------------------------- Receive Ports - RX AFE ------------------------- + gtxrxp_in => gt0_gtxrxp_in, + ------------------------ Receive Ports - RX AFE Ports ---------------------- + gtxrxn_in => gt0_gtxrxn_in, + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + rxdlyen_in => gt0_rxdlyen_in, + rxdlysreset_in => gt0_rxdlysreset_in, + rxdlysresetdone_out => gt0_rxdlysresetdone_out, + rxphalign_in => gt0_rxphalign_in, + rxphaligndone_out => gt0_rxphaligndone_out, + rxphalignen_in => gt0_rxphalignen_in, + rxphdlyreset_in => gt0_rxphdlyreset_in, + rxphmonitor_out => gt0_rxphmonitor_out, + rxphslipmonitor_out => gt0_rxphslipmonitor_out, + -------------------- Receive Ports - RX Equailizer Ports ------------------- + rxlpmhfhold_in => gt0_rxlpmhfhold_in, + rxlpmlfhold_in => gt0_rxlpmlfhold_in, + --------------------- Receive Ports - RX Equalizer Ports ------------------- + rxdfelpmreset_in => gt0_rxdfelpmreset_in, + rxmonitorout_out => gt0_rxmonitorout_out, + rxmonitorsel_in => gt0_rxmonitorsel_in, + --------------- Receive Ports - RX Fabric Output Control Ports ------------- + rxoutclk_out => gt0_rxoutclk_out, + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + gtrxreset_in => gt0_gtrxreset_in, + rxpmareset_in => gt0_rxpmareset_in, + ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- + rxcharisk_out => gt0_rxcharisk_out, + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + rxresetdone_out => gt0_rxresetdone_out, + --------------------- TX Initialization and Reset Ports -------------------- + gttxreset_in => gt0_gttxreset_in, + txuserrdy_in => gt0_txuserrdy_in, + ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- + txusrclk_in => gt0_txusrclk_in, + txusrclk2_in => gt0_txusrclk2_in, + ------------------ Transmit Ports - TX Buffer Bypass Ports ----------------- + txdlyen_in => gt0_txdlyen_in, + txdlysreset_in => gt0_txdlysreset_in, + txdlysresetdone_out => gt0_txdlysresetdone_out, + txphalign_in => gt0_txphalign_in, + txphaligndone_out => gt0_txphaligndone_out, + txphalignen_in => gt0_txphalignen_in, + txphdlyreset_in => gt0_txphdlyreset_in, + txphinit_in => gt0_txphinit_in, + txphinitdone_out => gt0_txphinitdone_out, + ------------------ Transmit Ports - TX Data Path interface ----------------- + txdata_in => gt0_txdata_in, + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + gtxtxn_out => gt0_gtxtxn_out, + gtxtxp_out => gt0_gtxtxp_out, + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + txoutclk_out => gt0_txoutclk_out, + txoutclkfabric_out => gt0_txoutclkfabric_out, + txoutclkpcs_out => gt0_txoutclkpcs_out, + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + txcharisk_in => gt0_txcharisk_in, + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + txresetdone_out => gt0_txresetdone_out + + ); + + + cpll_railing0_i : gtxKintex7FEE80_cpll_railing + generic map( + USE_BUFG => USE_BUFG + ) + port map + ( + cpll_reset_out => cpll_reset0_i, + cpll_pd_out => cpll_pd0_i, + refclk_out => open, + refclk_in => gt0_gtrefclk0_in +); + + +gt0_cpllreset_i <= cpll_reset0_i or gt0_cpllreset_in; +gt0_cpllpd_i <= cpll_pd0_i ; +end RTL; diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_rx_startup_fsm.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_rx_startup_fsm.vhd new file mode 100644 index 0000000..60c1802 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_rx_startup_fsm.vhd @@ -0,0 +1,788 @@ +--//////////////////////////////////////////////////////////////////////////////// +--// ____ ____ +--// / /\/ / +--// /___/ \ / Vendor: Xilinx +--// \ \ \/ Version : 3.5 +--// \ \ Application : 7 Series FPGAs Transceivers Wizard +--// / / Filename : gtxkintex7fee80_rx_startup_fsm.vhd +--// /___/ /\ +--// \ \ / \ +--// \___\/\___\ +--// +--// +-- Description : This module performs RX reset and initialization. +-- +-- +-- +-- Module gtxKintex7FEE80_rx_startup_fsm +-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard +-- +-- +-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + + +--***************************************************************************** + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +library unisim; +use unisim.vcomponents.all; + +entity gtxKintex7FEE80_RX_STARTUP_FSM is + Generic( EXAMPLE_SIMULATION : integer := 0; + EQ_MODE : string := "DFE"; --RX Equalisation Mode; set to DFE or LPM + STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns] + RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8; + TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must + RX_QPLL_USED : boolean := False; -- share these two generic values + PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic + -- is enough. For single-lane applications the automatic alignment is + -- sufficient + ); + Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB + --or reference-clock present at startup. + RXUSERCLK : in STD_LOGIC; --RXUSERCLK as used in the design + SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time + + QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost + CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost + QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT + CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT + RXRESETDONE : in STD_LOGIC; + MMCM_LOCK : in STD_LOGIC; + RECCLK_STABLE : in STD_LOGIC; + RECCLK_MONITOR_RESTART : in STD_LOGIC:='0'; + DATA_VALID : in STD_LOGIC; + TXUSERRDY : in STD_LOGIC; --TXUSERRDY from GT + DONT_RESET_ON_DATA_ERROR : in STD_LOGIC; --Used to control the Auto-Reset of FSM when Data Error is detected + GTRXRESET : out STD_LOGIC; + MMCM_RESET : out STD_LOGIC; + QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL (only if RX uses QPLL) + CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL (only if RX uses CPLL) + RX_FSM_RESET_DONE : out STD_LOGIC; --Reset-sequence has sucessfully been finished. + RXUSERRDY : out STD_LOGIC:='0'; + RUN_PHALIGNMENT : out STD_LOGIC; + PHALIGNMENT_DONE : in STD_LOGIC; + RESET_PHALIGNMENT : out STD_LOGIC:='0'; + RXDFEAGCHOLD : out STD_LOGIC; + RXDFELFHOLD : out STD_LOGIC; + RXLPMLFHOLD : out STD_LOGIC; + RXLPMHFHOLD : out STD_LOGIC; + RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of + -- Retries it took to get the transceiver up and running + ); +end gtxKintex7FEE80_RX_STARTUP_FSM; + +--Interdependencies: +-- * Timing depends on the frequency of the stable clock. Hence counters-sizes +-- are calculated at design-time based on the Generics +-- +-- * if either of the PLLs is reset during TX-startup, it does not need to be reset again by RX +-- => signal which PLL has been reset +-- * + + + +architecture RTL of gtxKintex7FEE80_RX_STARTUP_FSM is + + component gtxKintex7FEE80_sync_block + generic ( + INITIALISE : bit_vector(5 downto 0) := "000000" + ); + port ( + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); + end component; + type rx_rst_fsm_type is( + INIT, ASSERT_ALL_RESETS, WAIT_FOR_PLL_LOCK, RELEASE_PLL_RESET, VERIFY_RECCLK_STABLE, + RELEASE_MMCM_RESET, WAIT_FOR_RXUSRCLK, WAIT_RESET_DONE, DO_PHASE_ALIGNMENT, + MONITOR_DATA_VALID, FSM_DONE); + + signal rx_state : rx_rst_fsm_type := INIT; + + constant MMCM_LOCK_CNT_MAX : integer := 256; + constant STARTUP_DELAY : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration + constant WAIT_CYCLES : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration + constant WAIT_MAX : integer := WAIT_CYCLES + 10; -- 500 ns plus some additional margin + constant WAIT_TIMEOUT_2ms : integer := 2000000 / STABLE_CLOCK_PERIOD;-- 2 ms time-out + constant WAIT_TLOCK_MAX : integer := 100000 / STABLE_CLOCK_PERIOD;--100 us time-out + constant WAIT_TIMEOUT_500us : integer := 500000 / STABLE_CLOCK_PERIOD;--500 us time-out + constant WAIT_TIMEOUT_1us : integer := 1000 / STABLE_CLOCK_PERIOD; --1 us time-out + constant WAIT_TIMEOUT_100us : integer := 100000 / STABLE_CLOCK_PERIOD; --100 us time-out + constant WAIT_TIME_ADAPT : integer := (37000000 /integer(2))/STABLE_CLOCK_PERIOD; + constant WAIT_TIME_MAX : integer := 100 ; --10 us time-out + + signal init_wait_count : integer range 0 to WAIT_MAX:=0; + signal init_wait_done : std_logic := '0'; + signal pll_reset_asserted : std_logic := '0'; + signal rx_fsm_reset_done_int : std_logic := '0'; + signal rx_fsm_reset_done_int_s2 : std_logic := '0'; + signal rx_fsm_reset_done_int_s3 : std_logic := '0'; + + signal rxresetdone_s2 : std_logic := '0'; + signal rxresetdone_s3 : std_logic := '0'; + + constant MAX_RETRIES : integer := 2**RETRY_COUNTER_BITWIDTH-1; + signal retry_counter_int : integer range 0 to MAX_RETRIES := 0; + signal time_out_counter : integer range 0 to WAIT_TIMEOUT_2ms := 0; + signal recclk_mon_restart_count : integer range 0 to 3:= 0; + signal recclk_mon_count_reset : std_logic := '0'; + + signal reset_time_out : std_logic := '0'; + signal time_out_2ms : std_logic := '0';--\Flags that the various time-out points + signal time_tlock_max : std_logic := '0';--|have been reached. + signal time_out_500us : std_logic := '0';--| + signal time_out_1us : std_logic := '0';--/ + signal time_out_100us : std_logic := '0';--/ + signal check_tlock_max : std_logic := '0'; + + signal mmcm_lock_count : integer range 0 to MMCM_LOCK_CNT_MAX-1:=0; + signal mmcm_lock_int : std_logic := '0'; + signal mmcm_lock_i : std_logic := '0'; + signal mmcm_lock_reclocked : std_logic := '0'; + signal gtrxreset_i : std_logic := '0'; + signal mmcm_reset_i : std_logic := '1'; + signal rxpmaresetdone_i : std_logic := '0'; + signal txpmaresetdone_i : std_logic := '0'; + signal rxpmaresetdone_ss : std_logic := '0'; + signal rxpmaresetdone_sync : std_logic ; + signal txpmaresetdone_sync : std_logic ; + signal rxpmaresetdone_s : std_logic ; + signal rxpmaresetdone_rx_s : std_logic ; + signal pmaresetdone_fallingedge_detect : std_logic ; + signal pmaresetdone_fallingedge_detect_s : std_logic ; + + signal run_phase_alignment_int: std_logic := '0'; + signal run_phase_alignment_int_s2 : std_logic := '0'; + signal run_phase_alignment_int_s3 : std_logic := '0'; + + constant MAX_WAIT_BYPASS : integer := 5000;--5000 RXUSRCLK cycles is the max time for Multi lanes designs + signal wait_bypass_count : integer range 0 to MAX_WAIT_BYPASS-1; + signal time_out_wait_bypass : std_logic := '0'; + signal time_out_wait_bypass_s2 : std_logic := '0'; + signal time_out_wait_bypass_s3 : std_logic := '0'; + + signal refclk_lost : std_logic; + + signal time_out_adapt : std_logic := '0'; + signal adapt_count_reset : std_logic := '0'; + signal adapt_count : integer range 0 to WAIT_TIME_ADAPT-1; + signal data_valid_sync: std_logic := '0'; + signal cplllock_sync: std_logic := '0'; + signal qplllock_sync: std_logic := '0'; + signal cplllock_prev: std_logic := '0'; + signal qplllock_prev: std_logic := '0'; + signal cplllock_ris_edge: std_logic := '0'; + signal qplllock_ris_edge: std_logic := '0'; + signal wait_time_cnt : integer range 0 to WAIT_TIME_MAX; + signal wait_time_done : std_logic; + + + attribute shreg_extract : string; + attribute ASYNC_REG : string; + + signal reset_sync_reg1_tx : std_logic; + signal reset_sync_reg1 : std_logic; + signal gtrxreset_s : std_logic; + signal gtrxreset_tx_s : std_logic; + signal txpmaresetdone_s : std_logic; +begin + --Alias section, signals used within this module mapped to output ports: + RETRY_COUNTER <= STD_LOGIC_VECTOR(TO_UNSIGNED(retry_counter_int,RETRY_COUNTER_BITWIDTH)); + RUN_PHALIGNMENT <= run_phase_alignment_int; + RX_FSM_RESET_DONE <= rx_fsm_reset_done_int; + GTRXRESET <= gtrxreset_i; + MMCM_RESET <= mmcm_reset_i; + process(STABLE_CLOCK,SOFT_RESET) + begin + if (SOFT_RESET = '1') then + init_wait_done <= '0'; + init_wait_count <= 0 ; + elsif rising_edge(STABLE_CLOCK) then + -- The counter starts running when configuration has finished and + -- the clock is stable. When its maximum count-value has been reached, + -- the 500 ns from Answer Record 43482 have been passed. + if init_wait_count = WAIT_MAX then + init_wait_done <= '1'; + else + init_wait_count <= init_wait_count + 1; + end if; + end if; + end process; + + + adapt_wait_sim:if(EXAMPLE_SIMULATION = 1) generate + time_out_adapt <= '1'; + end generate; + + adapt_wait_hw:if(EXAMPLE_SIMULATION = 0) generate + process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + if(adapt_count_reset = '1') then + adapt_count <= 0; + time_out_adapt <= '0'; + elsif(adapt_count = WAIT_TIME_ADAPT -1) then + time_out_adapt <= '1'; + else + adapt_count <= adapt_count + 1; + end if; + end if; + end process; + end generate; + + retries_recclk_monitor:process(STABLE_CLOCK) + begin + --This counter monitors, how many retries the RECCLK monitor + --runs. If during startup too many retries are necessary, the whole + --initialisation-process of the transceivers gets restarted. + if rising_edge(STABLE_CLOCK) then + if recclk_mon_count_reset = '1' then + recclk_mon_restart_count <= 0; + elsif RECCLK_MONITOR_RESTART = '1' then + if recclk_mon_restart_count = 3 then + recclk_mon_restart_count <= 0; + else + recclk_mon_restart_count <= recclk_mon_restart_count + 1; + end if; + end if; + end if; + end process; + + timeouts:process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + -- One common large counter for generating three time-out signals. + -- Intermediate time-outs are derived from calculated values, based + -- on the period of the provided clock. + if reset_time_out = '1' then + time_out_counter <= 0; + time_out_2ms <= '0'; + time_tlock_max <= '0'; + time_out_500us <= '0'; + time_out_1us <= '0'; + time_out_100us <= '0'; + else + if time_out_counter = WAIT_TIMEOUT_2ms then + time_out_2ms <= '1'; + else + time_out_counter <= time_out_counter + 1; + end if; + + if (time_out_counter > WAIT_TLOCK_MAX) and (check_tlock_max='1') then + time_tlock_max <= '1'; + end if; + + if time_out_counter = WAIT_TIMEOUT_500us then + time_out_500us <= '1'; + end if; + + if time_out_counter = WAIT_TIMEOUT_1us then + time_out_1us <= '1'; + end if; + + if time_out_counter = WAIT_TIMEOUT_100us then + time_out_100us <= '1'; + end if; + + end if; + end if; + end process; + + + + mmcm_lock_wait:process(STABLE_CLOCK) + begin + --The lock-signal from the MMCM is not immediately used but + --enabling a counter. Only when the counter hits its maximum, + --the MMCM is considered as "really" locked. + --The counter avoids that the FSM already starts on only a + --coarse lock of the MMCM (=toggling of the LOCK-signal). + if rising_edge(STABLE_CLOCK) then + if mmcm_lock_i = '0' then + mmcm_lock_count <= 0; + mmcm_lock_reclocked <= '0'; + else + if mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1 then + mmcm_lock_count <= mmcm_lock_count + 1; + else + mmcm_lock_reclocked <= '1'; + end if; + end if; + end if; + end process; + + + -- Clock Domain Crossing + + sync_run_phase_alignment_int : gtxKintex7FEE80_sync_block + port map + ( + clk => RXUSERCLK, + data_in => run_phase_alignment_int, + data_out => run_phase_alignment_int_s2 + ); + + sync_rx_fsm_reset_done_int : gtxKintex7FEE80_sync_block + port map + ( + clk => RXUSERCLK, + data_in => rx_fsm_reset_done_int, + data_out => rx_fsm_reset_done_int_s2 + ); + + process(RXUSERCLK) + begin + if rising_edge(RXUSERCLK) then + run_phase_alignment_int_s3 <= run_phase_alignment_int_s2; + + rx_fsm_reset_done_int_s3 <= rx_fsm_reset_done_int_s2; + end if; + end process; + + sync_RXRESETDONE : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => RXRESETDONE, + data_out => rxresetdone_s2 + ); + + sync_time_out_wait_bypass : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => time_out_wait_bypass, + data_out => time_out_wait_bypass_s2 + ); + + sync_mmcm_lock_reclocked : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => MMCM_LOCK, + data_out => mmcm_lock_i + ); + + sync_data_valid : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => DATA_VALID, + data_out => data_valid_sync + ); + + process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + rxresetdone_s3 <= rxresetdone_s2; + + time_out_wait_bypass_s3 <= time_out_wait_bypass_s2; + + cplllock_prev <= cplllock_sync; + qplllock_prev <= qplllock_sync; + end if; + end process; + + sync_CPLLLOCK : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => CPLLLOCK, + data_out => cplllock_sync + ); + + sync_QPLLLOCK : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => QPLLLOCK, + data_out => qplllock_sync + ); + + + + process (STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + if(SOFT_RESET = '1' ) then + cplllock_ris_edge <= '0'; + elsif((cplllock_prev = '0') and (cplllock_sync = '1')) then + cplllock_ris_edge <= '1'; + elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then + cplllock_ris_edge <= cplllock_ris_edge; + else + cplllock_ris_edge <= '0'; + end if; + end if; + end process; + + process (STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + if(SOFT_RESET = '1' ) then + qplllock_ris_edge <= '0'; + elsif((qplllock_prev = '0') and (qplllock_sync = '1')) then + qplllock_ris_edge <= '1'; + elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then + qplllock_ris_edge <= qplllock_ris_edge; + else + qplllock_ris_edge <= '0'; + end if; + end if; + end process; + + + timeout_buffer_bypass:process(RXUSERCLK) + begin + if rising_edge(RXUSERCLK) then + if run_phase_alignment_int_s3 = '0' then + wait_bypass_count <= 0; + time_out_wait_bypass <= '0'; + elsif (run_phase_alignment_int_s3 = '1') and (rx_fsm_reset_done_int_s3 = '0') then + if wait_bypass_count = MAX_WAIT_BYPASS - 1 then + time_out_wait_bypass <= '1'; + else + wait_bypass_count <= wait_bypass_count + 1; + end if; + end if; + end if; + end process; + + refclk_lost <= '1' when ((RX_QPLL_USED and QPLLREFCLKLOST='1') or (not RX_QPLL_USED and CPLLREFCLKLOST='1')) else '0'; + + + + timeout_max:process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + if((rx_state = ASSERT_ALL_RESETS) or + (rx_state = RELEASE_MMCM_RESET)) then + wait_time_cnt <= WAIT_TIME_MAX; + elsif (wait_time_cnt > 0 ) then + wait_time_cnt <= wait_time_cnt - 1; + end if; + end if; + end process; + + wait_time_done <= '1' when (wait_time_cnt = 0) else '0'; + + --FSM for resetting the GTX/GTH/GTP in the 7-series. + --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + -- + -- Following steps are performed: + -- 1) After configuration wait for approximately 500 ns as specified in + -- answer-record 43482 + -- 2) Assert all resets on the GT and on an MMCM potentially connected. + -- After that wait until a reference-clock has been detected. + -- 3) Release the reset to the GT and wait until the GT-PLL has locked. + -- 4) Release the MMCM-reset and wait until the MMCM has signalled lock. + -- Also get info from the TX-side which PLL has been reset. + -- 5) Wait for the RESET_DONE-signal from the GT. + -- 6) Signal to start the phase-alignment procedure and wait for it to + -- finish. + -- 7) Reset-sequence has successfully run through. Signal this to the + -- rest of the design by asserting RX_FSM_RESET_DONE. + + reset_fsm:process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + if (SOFT_RESET = '1' ) then + --if (SOFT_RESET = '1' or (not(rx_state = INIT) and not(rx_state = ASSERT_ALL_RESETS) and refclk_lost = '1')) then + rx_state <= INIT; + RXUSERRDY <= '0'; + gtrxreset_i <= '0'; + mmcm_reset_i <= '0'; + rx_fsm_reset_done_int <= '0'; + QPLL_RESET <= '0'; + CPLL_RESET <= '0'; + pll_reset_asserted <= '0'; + reset_time_out <= '1'; + retry_counter_int <= 0; + run_phase_alignment_int <= '0'; + check_tlock_max <= '0'; + RESET_PHALIGNMENT <= '1'; + recclk_mon_count_reset <= '1'; + adapt_count_reset <= '1'; + RXDFEAGCHOLD <= '0'; + RXDFELFHOLD <= '0'; + RXLPMLFHOLD <= '0'; + RXLPMHFHOLD <= '0'; + + else + + case rx_state is + when INIT => + --Initial state after configuration. This state will be left after + --approx. 500 ns and not be re-entered. + if init_wait_done = '1' then + rx_state <= ASSERT_ALL_RESETS; + end if; + + when ASSERT_ALL_RESETS => + --This is the state into which the FSM will always jump back if any + --time-outs will occur. + --The number of retries is reported on the output RETRY_COUNTER. In + --case the transceiver never comes up for some reason, this machine + --will still continue its best and rerun until the FPGA is turned off + --or the transceivers come up correctly. + if RX_QPLL_USED and not TX_QPLL_USED then + if pll_reset_asserted = '0' then + QPLL_RESET <= '1'; + pll_reset_asserted <= '1'; + else + QPLL_RESET <= '0'; + end if; + elsif not RX_QPLL_USED and TX_QPLL_USED then + if pll_reset_asserted = '0' then + CPLL_RESET <= '1'; + pll_reset_asserted <= '1'; + else + CPLL_RESET <= '0'; + end if; + end if; + + RXUSERRDY <= '0'; + gtrxreset_i <= '1'; + mmcm_reset_i <= '1'; + run_phase_alignment_int <= '0'; + RESET_PHALIGNMENT <= '1'; + check_tlock_max <= '0'; + recclk_mon_count_reset <= '1'; + adapt_count_reset <= '1'; + + if (RX_QPLL_USED and not TX_QPLL_USED and (qplllock_sync = '0') and pll_reset_asserted = '1') or + (not RX_QPLL_USED and TX_QPLL_USED and (cplllock_sync = '0') and pll_reset_asserted = '1') or + (not RX_QPLL_USED and not TX_QPLL_USED ) or + (RX_QPLL_USED and TX_QPLL_USED ) then + rx_state <= WAIT_FOR_PLL_LOCK; + reset_time_out <= '1'; + end if; + + when WAIT_FOR_PLL_LOCK => + if(wait_time_done = '1') then + rx_state <= RELEASE_PLL_RESET; + end if; + + when RELEASE_PLL_RESET => + --PLL-Reset of the GTX gets released and the time-out counter + --starts running. + pll_reset_asserted <= '0'; + reset_time_out <= '0'; + + if (RX_QPLL_USED and not TX_QPLL_USED and (qplllock_sync = '1')) or + (not RX_QPLL_USED and TX_QPLL_USED and (cplllock_sync = '1')) then + rx_state <= VERIFY_RECCLK_STABLE; + reset_time_out <= '1'; + recclk_mon_count_reset <= '0'; + adapt_count_reset <= '0'; + elsif (RX_QPLL_USED and (qplllock_sync = '1')) or + (not RX_QPLL_USED and (cplllock_sync = '1')) then + rx_state <= VERIFY_RECCLK_STABLE; + reset_time_out <= '1'; + recclk_mon_count_reset <= '0'; + adapt_count_reset <= '0'; + end if; + + if time_out_2ms = '1' then + if retry_counter_int = MAX_RETRIES then + -- If too many retries are performed compared to what is specified in + -- the generic, the counter simply wraps around. + retry_counter_int <= 0; + else + retry_counter_int <= retry_counter_int + 1; + end if; + rx_state <= ASSERT_ALL_RESETS; + end if; + + when VERIFY_RECCLK_STABLE => + --reset_time_out <= '0'; + --Time-out counter is not released in this state as here the FSM + --does not wait for a certain period of time but checks on the number + --of retries in the RECCLK monitor + gtrxreset_i <= '0'; + if RECCLK_STABLE = '1' then + rx_state <= RELEASE_MMCM_RESET; + reset_time_out <= '1'; + + end if; + + if recclk_mon_restart_count = 2 then + --If two retries are performed in the RECCLK monitor + --the whole initialisation-sequence gets restarted. + if retry_counter_int = MAX_RETRIES then + -- If too many retries are performed compared to what is specified in + -- the generic, the counter simply wraps around. + retry_counter_int <= 0; + else + retry_counter_int <= retry_counter_int + 1; + end if; + rx_state <= ASSERT_ALL_RESETS; + end if; + + when RELEASE_MMCM_RESET => + --Release of the MMCM-reset. Waiting for the MMCM to lock. + check_tlock_max <= '1'; + + mmcm_reset_i <= '0'; + reset_time_out <= '0'; + + if mmcm_lock_reclocked = '1' then + rx_state <= WAIT_FOR_RXUSRCLK; + reset_time_out <= '1'; + end if; + + if (time_tlock_max = '1' and reset_time_out = '0' )then + if retry_counter_int = MAX_RETRIES then + -- If too many retries are performed compared to what is specified in + -- the generic, the counter simply wraps around. + retry_counter_int <= 0; + else + retry_counter_int <= retry_counter_int + 1; + end if; + rx_state <= ASSERT_ALL_RESETS; + end if; + + when WAIT_FOR_RXUSRCLK => + if wait_time_done = '1' then + rx_state <= WAIT_RESET_DONE; + end if; + + when WAIT_RESET_DONE => + --When TXOUTCLK is the source for RXUSRCLK, RXUSERRDY depends on TXUSERRDY + --If RXOUTCLK is the source for RXUSRCLK, TXUSERRDY can be tied to '1' + if TXUSERRDY = '1' then + RXUSERRDY <= '1'; + end if; + reset_time_out <= '0'; + if rxresetdone_s3 = '1' then + rx_state <= DO_PHASE_ALIGNMENT; + reset_time_out <= '1'; + end if; + + if time_out_2ms = '1' and reset_time_out = '0' then + if retry_counter_int = MAX_RETRIES then + -- If too many retries are performed compared to what is specified in + -- the generic, the counter simply wraps around. + retry_counter_int <= 0; + else + retry_counter_int <= retry_counter_int + 1; + end if; + rx_state <= ASSERT_ALL_RESETS; + end if; + + when DO_PHASE_ALIGNMENT => + --The direct handling of the signals for the Phase Alignment is done outside + --this state-machine. + RESET_PHALIGNMENT <= '0'; + run_phase_alignment_int <= '1'; + reset_time_out <= '0'; + + if PHALIGNMENT_DONE = '1' then + rx_state <= MONITOR_DATA_VALID; + reset_time_out <= '1'; + end if; + + if time_out_wait_bypass_s3 = '1' then + if retry_counter_int = MAX_RETRIES then + -- If too many retries are performed compared to what is specified in + -- the generic, the counter simply wraps around. + retry_counter_int <= 0; + else + retry_counter_int <= retry_counter_int + 1; + end if; + rx_state <= ASSERT_ALL_RESETS; + end if; + + when MONITOR_DATA_VALID => + reset_time_out <= '0'; + + if(time_out_100us = '1' and data_valid_sync ='0' and DONT_RESET_ON_DATA_ERROR = '0' and reset_time_out = '0') then + rx_state <= ASSERT_ALL_RESETS; + rx_fsm_reset_done_int <= '0'; + elsif (data_valid_sync = '1') then + rx_state <= FSM_DONE; + rx_fsm_reset_done_int <= '0'; + reset_time_out <= '1'; + end if; + + when FSM_DONE => + reset_time_out <= '0'; + if data_valid_sync = '0' then + rx_fsm_reset_done_int <= '0'; + reset_time_out <= '1'; + rx_state <= MONITOR_DATA_VALID; + + elsif(time_out_1us = '1' and reset_time_out = '0') then + rx_fsm_reset_done_int <= '1'; + end if; + + if(time_out_adapt = '1') then + if(EQ_MODE = "DFE") then + RXDFEAGCHOLD <= '1'; + RXDFELFHOLD <= '1'; + RXLPMHFHOLD <= '0'; + RXLPMLFHOLD <= '0'; + else + RXDFEAGCHOLD <= '0'; + RXDFELFHOLD <= '0'; + RXLPMHFHOLD <= '0'; + RXLPMLFHOLD <= '0'; + end if; + end if; + when OTHERS => + rx_state <= INIT; + end case; + end if; + end if; + end process; + +end RTL; + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_sync_block.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_sync_block.vhd new file mode 100644 index 0000000..9ce2535 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_sync_block.vhd @@ -0,0 +1,194 @@ +--//////////////////////////////////////////////////////////////////////////////// +--// ____ ____ +--// / /\/ / +--// /___/ \ / Vendor: Xilinx +--// \ \ \/ Version : 3.5 +--// \ \ Application : 7 Series FPGAs Transceivers Wizard +--// / / Filename : gtxkintex7fee80_sync_block.vhd +--// /___/ /\ +--// \ \ / \ +--// \___\/\___\ +--// +--// +-- +-- Description: Used on signals crossing from one clock domain to +-- another, this is a flip-flop pair, with both flops +-- placed together with RLOCs into the same slice. Thus +-- the routing delay between the two is minimum to safe- +-- guard against metastability issues. +-- +-- +-- Module gtxKintex7FEE80_sync_block +-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard +-- +-- +-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + + + + + +library ieee; +use ieee.std_logic_1164.all; + +library unisim; +use unisim.vcomponents.all; + +entity gtxKintex7FEE80_sync_block is + generic ( + INITIALISE : bit_vector(5 downto 0) := "000000" + ); + port ( + clk : in std_logic; -- clock to be sync'ed to + data_in : in std_logic; -- Data to be 'synced' + data_out : out std_logic -- synced data + ); + +-- attribute dont_touch : string; +-- attribute dont_touch of gtxKintex7FEE80_sync_block : entity is "yes"; + +end gtxKintex7FEE80_sync_block; + + +architecture structural of gtxKintex7FEE80_sync_block is + + + -- Internal Signals + signal data_sync1 : std_logic; + signal data_sync2 : std_logic; + signal data_sync3 : std_logic; + signal data_sync4 : std_logic; + signal data_sync5 : std_logic; + + -- These attributes will stop timing errors being reported in back annotated + -- SDF simulation. + attribute ASYNC_REG : string; + attribute ASYNC_REG of data_sync_reg1 : label is "true"; + attribute ASYNC_REG of data_sync_reg2 : label is "true"; + attribute ASYNC_REG of data_sync_reg3 : label is "true"; + attribute ASYNC_REG of data_sync_reg4 : label is "true"; + attribute ASYNC_REG of data_sync_reg5 : label is "true"; + attribute ASYNC_REG of data_sync_reg6 : label is "true"; + + -- These attributes will stop XST translating the desired flip-flops into an + -- SRL based shift register. + attribute shreg_extract : string; + attribute shreg_extract of data_sync_reg1 : label is "no"; + attribute shreg_extract of data_sync_reg2 : label is "no"; + attribute shreg_extract of data_sync_reg3 : label is "no"; + attribute shreg_extract of data_sync_reg4 : label is "no"; + attribute shreg_extract of data_sync_reg5 : label is "no"; + attribute shreg_extract of data_sync_reg6 : label is "no"; + + +begin + + data_sync_reg1 : FD + generic map ( + INIT => INITIALISE(0) + ) + port map ( + C => clk, + D => data_in, + Q => data_sync1 + ); + + data_sync_reg2 : FD + generic map ( + INIT => INITIALISE(1) + ) + port map ( + C => clk, + D => data_sync1, + Q => data_sync2 + ); + + data_sync_reg3 : FD + generic map ( + INIT => INITIALISE(2) + ) + port map ( + C => clk, + D => data_sync2, + Q => data_sync3 + ); + + data_sync_reg4 : FD + generic map ( + INIT => INITIALISE(3) + ) + port map ( + C => clk, + D => data_sync3, + Q => data_sync4 + ); + + data_sync_reg5 : FD + generic map ( + INIT => INITIALISE(4) + ) + port map ( + C => clk, + D => data_sync4, + Q => data_sync5 + ); + + data_sync_reg6 : FD + generic map ( + INIT => INITIALISE(5) + ) + port map ( + C => clk, + D => data_sync5, + Q => data_out + ); + + + +end structural; + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_tx_startup_fsm.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_tx_startup_fsm.vhd new file mode 100644 index 0000000..5ce8c64 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_tx_startup_fsm.vhd @@ -0,0 +1,609 @@ +--////////////////////////////////////////////////////////////////////////////// +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 3.5 +-- \ \ Application : 7 Series FPGAs Transceivers Wizard +-- / / Filename :gtxkintex7fee80_tx_startup_fsm.vhd +-- /___/ /\ +-- \ \ / \ +-- \___\/\___\ +-- +-- +-- Description : This module performs TX reset and initialization. +-- +-- +-- +-- Module gtxKintex7FEE80_tx_startup_fsm +-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard +-- +-- +-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + + +--***************************************************************************** + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity gtxKintex7FEE80_TX_STARTUP_FSM is + Generic( + EXAMPLE_SIMULATION : integer := 0; + STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns] + RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8; + TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must + RX_QPLL_USED : boolean := False; -- share these two generic values + PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic + -- is enough. For single-lane applications the automatic alignment is + -- sufficient + ); + Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB + --or reference-clock present at startup. + TXUSERCLK : in STD_LOGIC; --TXUSERCLK as used in the design + SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time + QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost + CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost + QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT + CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT + TXRESETDONE : in STD_LOGIC; + MMCM_LOCK : in STD_LOGIC; + GTTXRESET : out STD_LOGIC; + MMCM_RESET : out STD_LOGIC:='1'; + QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL + CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL + TX_FSM_RESET_DONE : out STD_LOGIC; --Reset-sequence has sucessfully been finished. + TXUSERRDY : out STD_LOGIC:='0'; + RUN_PHALIGNMENT : out STD_LOGIC:='0'; + RESET_PHALIGNMENT : out STD_LOGIC:='0'; + PHALIGNMENT_DONE : in STD_LOGIC; + + RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of + -- Retries it took to get the transceiver up and running + ); +end gtxKintex7FEE80_TX_STARTUP_FSM; + +--Interdependencies: +-- * Timing depends on the frequency of the stable clock. Hence counters-sizes +-- are calculated at design-time based on the Generics +-- +-- * if either of PLLs is reset during TX-startup, it does not need to be reset again by RX +-- => signal which PLL has been reset +-- * + + + +architecture RTL of gtxKintex7FEE80_TX_STARTUP_FSM is + + component gtxKintex7FEE80_sync_block + generic ( + INITIALISE : bit_vector(5 downto 0) := "000000" + ); + port ( + clk : in std_logic; + data_in : in std_logic; + data_out : out std_logic + ); + end component; + + type tx_rst_fsm_type is( + INIT, ASSERT_ALL_RESETS, WAIT_FOR_PLL_LOCK, RELEASE_PLL_RESET, + WAIT_FOR_TXOUTCLK, RELEASE_MMCM_RESET, WAIT_FOR_TXUSRCLK, WAIT_RESET_DONE, DO_PHASE_ALIGNMENT, + RESET_FSM_DONE); + + signal tx_state : tx_rst_fsm_type := INIT; + + constant MMCM_LOCK_CNT_MAX : integer := 256; + constant STARTUP_DELAY : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration + constant WAIT_CYCLES : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration + constant WAIT_MAX : integer := WAIT_CYCLES + 10; -- 500 ns plus some additional margin + + constant WAIT_TIMEOUT_2ms : integer := 2000000 / STABLE_CLOCK_PERIOD;-- 2 ms time-out + constant WAIT_TLOCK_MAX : integer := 100000 / STABLE_CLOCK_PERIOD;--100 us time-out + constant WAIT_TIMEOUT_500us : integer := 500000 / STABLE_CLOCK_PERIOD;--100 us time-out + constant WAIT_1us_cycles : integer := 1000 / STABLE_CLOCK_PERIOD;--1 us time-out + constant WAIT_1us : integer := WAIT_1us_cycles+ 10; -- 1us plus some additional margin + + signal init_wait_count : integer range 0 to WAIT_MAX:=0; + signal init_wait_done : std_logic := '0'; + signal pll_reset_asserted : std_logic := '0'; + + signal tx_fsm_reset_done_int : std_logic := '0'; + signal tx_fsm_reset_done_int_s2 : std_logic := '0'; + signal tx_fsm_reset_done_int_s3 : std_logic := '0'; + + signal txresetdone_s2 : std_logic := '0'; + signal txresetdone_s3 : std_logic := '0'; + + constant MAX_RETRIES : integer := 2**RETRY_COUNTER_BITWIDTH-1; + signal retry_counter_int : integer range 0 to MAX_RETRIES; + signal time_out_counter : integer range 0 to WAIT_TIMEOUT_2ms := 0; + + signal reset_time_out : std_logic := '0'; + signal time_out_2ms : std_logic := '0';--\Flags that the various time-out points + signal time_tlock_max : std_logic := '0';--|have been reached. + signal time_out_500us : std_logic := '0';--/ + + signal mmcm_lock_count : integer range 0 to MMCM_LOCK_CNT_MAX-1:=0; + signal mmcm_lock_int : std_logic := '0'; + signal mmcm_lock_i : std_logic := '0'; + signal mmcm_lock_reclocked : std_logic := '0'; + + signal run_phase_alignment_int : std_logic := '0'; + signal run_phase_alignment_int_s2 : std_logic := '0'; + signal run_phase_alignment_int_s3 : std_logic := '0'; + constant MAX_WAIT_BYPASS : integer := 45824; --110000 TXUSRCLK cycles is the max time for Multi lane designs + + constant WAIT_TIME_MAX : integer := 100 ; --10 us time-out + + signal wait_bypass_count : integer range 0 to MAX_WAIT_BYPASS-1; + signal time_out_wait_bypass : std_logic := '0'; + signal time_out_wait_bypass_s2 : std_logic := '0'; + signal time_out_wait_bypass_s3 : std_logic := '0'; + signal txuserrdy_i : std_logic := '0'; + signal refclk_lost : std_logic; + signal gttxreset_i : std_logic := '0'; + signal txpmaresetdone_i : std_logic := '0'; + signal txpmaresetdone_sync : std_logic ; + + signal cplllock_sync: std_logic := '0'; + signal qplllock_sync: std_logic := '0'; + signal cplllock_prev: std_logic := '0'; + signal qplllock_prev: std_logic := '0'; + signal cplllock_ris_edge: std_logic := '0'; + signal qplllock_ris_edge: std_logic := '0'; + signal wait_time_cnt : integer range 0 to WAIT_TIME_MAX; + signal wait_time_done :std_logic; + +begin + --Alias section, signals used within this module mapped to output ports: + RETRY_COUNTER <= STD_LOGIC_VECTOR(TO_UNSIGNED(retry_counter_int,RETRY_COUNTER_BITWIDTH)); + RUN_PHALIGNMENT <= run_phase_alignment_int; + TX_FSM_RESET_DONE <= tx_fsm_reset_done_int; + GTTXRESET <= gttxreset_i; + + process(STABLE_CLOCK,SOFT_RESET) + begin + if (SOFT_RESET = '1') then + init_wait_done <= '0'; + init_wait_count <= 0 ; + elsif rising_edge(STABLE_CLOCK) then + -- The counter starts running when configuration has finished and + -- the clock is stable. When its maximum count-value has been reached, + -- the 500 ns from Answer Record 43482 have been passed. + if init_wait_count = WAIT_MAX then + init_wait_done <= '1'; + else + init_wait_count <= init_wait_count + 1; + end if; + end if; + end process; + + timeouts:process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + -- One common large counter for generating three time-out signals. + -- Intermediate time-outs are derived from calculated values, based + -- on the period of the provided clock. + if reset_time_out = '1' then + time_out_counter <= 0; + time_out_2ms <= '0'; + time_tlock_max <= '0'; + time_out_500us <= '0'; + else + if time_out_counter = WAIT_TIMEOUT_2ms then + time_out_2ms <= '1'; + else + time_out_counter <= time_out_counter + 1; + end if; + + if time_out_counter = WAIT_TLOCK_MAX then + time_tlock_max <= '1'; + end if; + + if time_out_counter = WAIT_TIMEOUT_500us then + time_out_500us <= '1'; + end if; + end if; + end if; + end process; + + mmcm_lock_wait:process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + if mmcm_lock_i = '0' then + mmcm_lock_count <= 0; + mmcm_lock_reclocked <= '0'; + else + if mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1 then + mmcm_lock_count <= mmcm_lock_count + 1; + else + mmcm_lock_reclocked <= '1'; + end if; + end if; + end if; + end process; + + + + -- Clock Domain Crossing + + sync_run_phase_alignment_int : gtxKintex7FEE80_sync_block + port map + ( + clk => TXUSERCLK, + data_in => run_phase_alignment_int, + data_out => run_phase_alignment_int_s2 + ); + + sync_tx_fsm_reset_done_int : gtxKintex7FEE80_sync_block + port map + ( + clk => TXUSERCLK, + data_in => tx_fsm_reset_done_int, + data_out => tx_fsm_reset_done_int_s2 + ); + + process(TXUSERCLK) + begin + if rising_edge(TXUSERCLK) then + run_phase_alignment_int_s3 <= run_phase_alignment_int_s2; + + tx_fsm_reset_done_int_s3 <= tx_fsm_reset_done_int_s2; + end if; + end process; + + sync_TXRESETDONE : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => TXRESETDONE, + data_out => txresetdone_s2 + ); + + sync_time_out_wait_bypass : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => time_out_wait_bypass, + data_out => time_out_wait_bypass_s2 + ); + + sync_mmcm_lock_reclocked : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => MMCM_LOCK, + data_out => mmcm_lock_i + ); + + process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + txresetdone_s3 <= txresetdone_s2; + + time_out_wait_bypass_s3 <= time_out_wait_bypass_s2; + + cplllock_prev <= cplllock_sync; + qplllock_prev <= qplllock_sync; + end if; + end process; + + sync_CPLLLOCK : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => CPLLLOCK, + data_out => cplllock_sync + ); + + sync_QPLLLOCK : gtxKintex7FEE80_sync_block + port map + ( + clk => STABLE_CLOCK, + data_in => QPLLLOCK, + data_out => qplllock_sync + ); + + + process (STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + if(SOFT_RESET = '1' ) then + cplllock_ris_edge <= '0'; + elsif((cplllock_prev = '0') and (cplllock_sync = '1')) then + cplllock_ris_edge <= '1'; + elsif(tx_state = ASSERT_ALL_RESETS or tx_state = RELEASE_PLL_RESET) then + cplllock_ris_edge <= cplllock_ris_edge; + else + cplllock_ris_edge <= '0'; + end if; + end if; + end process; + + process (STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + if(SOFT_RESET = '1' ) then + qplllock_ris_edge <= '0'; + elsif((qplllock_prev = '0') and (qplllock_sync = '1')) then + qplllock_ris_edge <= '1'; + elsif(tx_state = ASSERT_ALL_RESETS or tx_state = RELEASE_PLL_RESET) then + qplllock_ris_edge <= qplllock_ris_edge; + else + qplllock_ris_edge <= '0'; + end if; + end if; + end process; + + + + timeout_buffer_bypass:process(TXUSERCLK) + begin + if rising_edge(TXUSERCLK) then + if run_phase_alignment_int_s3 = '0' then + wait_bypass_count <= 0; + time_out_wait_bypass <= '0'; + elsif (run_phase_alignment_int_s3 = '1') and (tx_fsm_reset_done_int_s3 = '0') then + if wait_bypass_count = MAX_WAIT_BYPASS - 1 then + time_out_wait_bypass <= '1'; + else + wait_bypass_count <= wait_bypass_count + 1; + end if; + end if; + end if; + end process; + + refclk_lost <= '1' when ((TX_QPLL_USED and QPLLREFCLKLOST='1') or (not TX_QPLL_USED and CPLLREFCLKLOST='1')) else '0'; + + + timeout_max:process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + if((tx_state = ASSERT_ALL_RESETS) or + (tx_state = RELEASE_PLL_RESET) or + (tx_state = RELEASE_MMCM_RESET)) then + wait_time_cnt <= WAIT_TIME_MAX; + elsif (wait_time_cnt > 0 ) then + wait_time_cnt <= wait_time_cnt - 1; + end if; + end if; + end process; + + wait_time_done <= '1' when (wait_time_cnt = 0) else '0'; + + --FSM for resetting the GTX/GTH/GTP in the 7-series. + --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + -- + -- Following steps are performed: + -- 1) Only for GTX - After configuration wait for approximately 500 ns as specified in + -- answer-record 43482 + -- 2) Assert all resets on the GT and on an MMCM potentially connected. + -- After that wait until a reference-clock has been detected. + -- 3) Release the reset to the GT and wait until the GT-PLL has locked. + -- 4) Release the MMCM-reset and wait until the MMCM has signalled lock. + -- Also signal to the RX-side which PLL has been reset. + -- 5) Wait for the RESET_DONE-signal from the GT. + -- 6) Signal to start the phase-alignment procedure and wait for it to + -- finish. + -- 7) Reset-sequence has successfully run through. Signal this to the + -- rest of the design by asserting TX_FSM_RESET_DONE. + + reset_fsm:process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + if(SOFT_RESET = '1') then + --if(SOFT_RESET = '1' or (not(tx_state = INIT) and not(tx_state = ASSERT_ALL_RESETS) and refclk_lost = '1')) then + tx_state <= INIT; + TXUSERRDY <= '0'; + gttxreset_i <= '0'; + MMCM_RESET <= '0'; + tx_fsm_reset_done_int <= '0'; + QPLL_RESET <= '0'; + CPLL_RESET <= '0'; + pll_reset_asserted <= '0'; + reset_time_out <= '0'; + retry_counter_int <= 0; + run_phase_alignment_int <= '0'; + RESET_PHALIGNMENT <= '1'; + else + + case tx_state is + when INIT => + --Initial state after configuration. This state will be left after + --approx. 500 ns and not be re-entered. + if init_wait_done = '1' then + tx_state <= ASSERT_ALL_RESETS; + reset_time_out <= '1'; + end if; + + when ASSERT_ALL_RESETS => + --This is the state into which the FSM will always jump back if any + --time-outs will occur. + --The number of retries is reported on the output RETRY_COUNTER. In + --case the transceiver never comes up for some reason, this machine + --will still continue its best and rerun until the FPGA is turned off + --or the transceivers come up correctly. + if TX_QPLL_USED then + if pll_reset_asserted = '0' then + QPLL_RESET <= '1'; + pll_reset_asserted <= '1'; + else + QPLL_RESET <= '0'; + end if; + else + if pll_reset_asserted = '0' then + CPLL_RESET <= '1'; + pll_reset_asserted <= '1'; + else + CPLL_RESET <= '0'; + end if; + end if; + TXUSERRDY <= '0'; + gttxreset_i <= '1'; + MMCM_RESET <= '1'; + reset_time_out <= '1'; + run_phase_alignment_int <= '0'; + RESET_PHALIGNMENT <= '1'; + + if (TX_QPLL_USED and (qplllock_sync = '0') and pll_reset_asserted = '1') or + (not TX_QPLL_USED and (cplllock_sync = '0') and pll_reset_asserted = '1') then + tx_state <= WAIT_FOR_PLL_LOCK; + end if; + + when WAIT_FOR_PLL_LOCK => + if(wait_time_done = '1') then + tx_state <= RELEASE_PLL_RESET; + end if; + + when RELEASE_PLL_RESET => + --PLL-Reset of the GTX gets released and the time-out counter + --starts running. + pll_reset_asserted <= '0'; + + if (TX_QPLL_USED and (qplllock_sync = '1')) or + (not TX_QPLL_USED and (cplllock_sync = '1')) then + tx_state <= WAIT_FOR_TXOUTCLK; + reset_time_out <= '1'; + end if; + + if time_out_2ms = '1' then + if retry_counter_int = MAX_RETRIES then + -- If too many retries are performed compared to what is specified in + -- the generic, the counter simply wraps around. + retry_counter_int <= 0; + else + retry_counter_int <= retry_counter_int + 1; + end if; + tx_state <= ASSERT_ALL_RESETS; + end if; + + when WAIT_FOR_TXOUTCLK => + gttxreset_i <= '0'; + if(wait_time_done = '1') then + tx_state <= RELEASE_MMCM_RESET; + end if; + + when RELEASE_MMCM_RESET => + --Release of the MMCM-reset. Waiting for the MMCM to lock. + MMCM_RESET <= '0'; + reset_time_out <= '0'; + if mmcm_lock_reclocked = '1' then + tx_state <= WAIT_FOR_TXUSRCLK; + reset_time_out <= '1'; + end if; + + if (time_tlock_max = '1' and mmcm_lock_reclocked = '0' and reset_time_out = '0') then + if retry_counter_int = MAX_RETRIES then + -- If too many retries are performed compared to what is specified in + -- the generic, the counter simply wraps around. + retry_counter_int <= 0; + else + retry_counter_int <= retry_counter_int + 1; + end if; + tx_state <= ASSERT_ALL_RESETS; + end if; + + when WAIT_FOR_TXUSRCLK => + if(wait_time_done = '1') then + tx_state <= WAIT_RESET_DONE; + end if; + + when WAIT_RESET_DONE => + TXUSERRDY <= '1'; + reset_time_out <= '0'; + if txresetdone_s3 = '1' then + tx_state <= DO_PHASE_ALIGNMENT; + reset_time_out <= '1'; + end if; + + if (time_out_500us = '1' and reset_time_out = '0') then + if retry_counter_int = MAX_RETRIES then + -- If too many retries are performed compared to what is specified in + -- the generic, the counter simply wraps around. + retry_counter_int <= 0; + else + retry_counter_int <= retry_counter_int + 1; + end if; + tx_state <= ASSERT_ALL_RESETS; + end if; + + when DO_PHASE_ALIGNMENT => + --The direct handling of the signals for the Phase Alignment is done outside + --this state-machine. + RESET_PHALIGNMENT <= '0'; + run_phase_alignment_int <= '1'; + reset_time_out <= '0'; + + if PHALIGNMENT_DONE = '1' then + tx_state <= RESET_FSM_DONE; + end if; + + if time_out_wait_bypass_s3 = '1' then + if retry_counter_int = MAX_RETRIES then + -- If too many retries are performed compared to what is specified in + -- the generic, the counter simply wraps around. + retry_counter_int <= 0; + else + retry_counter_int <= retry_counter_int + 1; + end if; + tx_state <= ASSERT_ALL_RESETS; + end if; + + when RESET_FSM_DONE => + reset_time_out <= '1'; + tx_fsm_reset_done_int <= '1'; + + when OTHERS => + tx_state <= INIT; + + end case; + end if; + end if; + end process; + +end RTL; diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxKintex7FEE80/gtxKintex7FEE80.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxKintex7FEE80/gtxKintex7FEE80.xci new file mode 100644 index 0000000..49de6c9 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxKintex7FEE80/gtxKintex7FEE80.xci @@ -0,0 +1,1239 @@ + + + xilinx.com + xci + unknown + 1.0 + + + gtxKintex7FEE80 + + + gtxKintex7FEE80 + true + Start_from_scratch + GTX + right_column + no_silicon_version_loaded + 2 + false + 2 + false + false + 60 + true + CPLL + REFCLK0_Q0 + CPLL + REFCLK0_Q0 + false + REFCLK1_Q0 + REFCLK1_Q0 + false + REFCLK1_Q0 + REFCLK1_Q0 + false + REFCLK1_Q0 + REFCLK1_Q0 + false + REFCLK1_Q1 + REFCLK1_Q1 + false + REFCLK1_Q1 + REFCLK1_Q1 + false + REFCLK1_Q1 + REFCLK1_Q1 + false + REFCLK1_Q1 + REFCLK1_Q1 + false + REFCLK1_Q2 + REFCLK1_Q2 + false + REFCLK1_Q2 + REFCLK1_Q2 + false + REFCLK1_Q2 + REFCLK1_Q2 + false + REFCLK1_Q2 + REFCLK1_Q2 + false + REFCLK1_Q3 + REFCLK1_Q3 + false + REFCLK1_Q3 + REFCLK1_Q3 + false + REFCLK1_Q3 + REFCLK1_Q3 + false + REFCLK1_Q3 + REFCLK1_Q3 + false + REFCLK1_Q4 + REFCLK1_Q4 + false + REFCLK1_Q4 + REFCLK1_Q4 + false + REFCLK1_Q4 + REFCLK1_Q4 + false + REFCLK1_Q4 + REFCLK1_Q4 + false + REFCLK1_Q5 + REFCLK1_Q5 + false + REFCLK1_Q5 + REFCLK1_Q5 + false + REFCLK1_Q5 + REFCLK1_Q5 + false + REFCLK1_Q5 + REFCLK1_Q5 + false + REFCLK1_Q6 + REFCLK1_Q6 + false + REFCLK1_Q6 + REFCLK1_Q6 + false + REFCLK1_Q6 + REFCLK1_Q6 + false + REFCLK1_Q6 + REFCLK1_Q6 + false + REFCLK1_Q7 + REFCLK1_Q7 + false + REFCLK1_Q7 + REFCLK1_Q7 + false + REFCLK1_Q7 + REFCLK1_Q7 + false + REFCLK1_Q7 + REFCLK1_Q7 + false + REFCLK1_Q8 + REFCLK1_Q8 + false + REFCLK1_Q8 + REFCLK1_Q8 + false + REFCLK1_Q8 + REFCLK1_Q8 + false + REFCLK1_Q8 + REFCLK1_Q8 + false + REFCLK1_Q9 + REFCLK1_Q9 + false + REFCLK1_Q9 + REFCLK1_Q9 + false + REFCLK1_Q9 + REFCLK1_Q9 + false + REFCLK1_Q9 + REFCLK1_Q9 + false + REFCLK1_Q10 + REFCLK1_Q10 + false + REFCLK1_Q10 + REFCLK1_Q10 + false + REFCLK1_Q10 + REFCLK1_Q10 + false + REFCLK1_Q10 + REFCLK1_Q10 + false + REFCLK1_Q11 + REFCLK1_Q11 + false + REFCLK1_Q11 + REFCLK1_Q11 + false + REFCLK1_Q11 + REFCLK1_Q11 + false + REFCLK1_Q11 + REFCLK1_Q11 + false + 80.000 + 80.000 + Start_from_scratch + false + false + 2 + 16 + 8B/10B + 20 + 80.000 + 2 + 16 + 8B/10B + 20 + 80.000 + 5 + 5 + 1 + 1 + 16 + 2 + 2 + true + 80 + false + false + false + false + true + false + false + Auto + TXOUTCLK + true + false + Auto + RXOUTCLK + false + false + false + false + false + false + false + false + false + false + true + false + false + false + false + false + false + One_Hop + DFE + true + true + true + true + true + false + K28.5 + 0101111100 + 1010000011 + 1111111111 + false + Any_Byte_Boundary + false + false + false + false + false + false + Custom + false + false + false + false + LPM-Auto + Auto + AVTT + 800 + false + false + false + false + false + false + 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+ true + false + true + OFF + false + true + true + true + true + true + true + true + true + Start_from_scratch + Start_from_scratch + Start_from_scratch + Start_from_scratch + Start_from_scratch + Start_from_scratch + Start_from_scratch + Start_from_scratch + Start_from_scratch + 25.78125 + 25.78125 + 25.78125 + 25.78125 + 25.78125 + 25.78125 + 25.78125 + 25.78125 + 25.78125 + false + false + false + false + false + false + false + false + false + 25.78125 + 25.78125 + 25.78125 + 25.78125 + 25.78125 + 25.78125 + 25.78125 + 25.78125 + 25.78125 + false + false + false + false + false + false + false + false + false + REFCLK0 + REFCLK0 + REFCLK0 + REFCLK0 + REFCLK0 + REFCLK0 + REFCLK0 + REFCLK0 + REFCLK0 + 322.266 + 322.266 + TXOUTCLK_LANE0 + TXOUTCLK_LANE0 + RXOUTCLK_LANE0 + RXOUTCLK_LANE0 + RXOUTCLK_LANE0 + RXOUTCLK_LANE0 + DRPCLK0 + TX_FIFO_CLK + TX_FIFO_CLK + TX_FIFO_CLK + TX_FIFO_CLK + TX_FIFO_CLK + TX_FIFO_CLK + TX_FIFO_CLK + TX_FIFO_CLK + RX_FIFO_CLK + RX_FIFO_CLK + RX_FIFO_CLK + RX_FIFO_CLK + RX_FIFO_CLK + RX_FIFO_CLK + RX_FIFO_CLK + RX_FIFO_CLK + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + TXUSRCLK0 + TXUSRCLK0 + TXUSRCLK0 + TXUSRCLK0 + TXUSRCLK0 + TXUSRCLK0 + TXUSRCLK0 + TXUSRCLK0 + RXUSRCLK0 + RXUSRCLK0 + RXUSRCLK0 + RXUSRCLK0 + RXUSRCLK0 + RXUSRCLK0 + RXUSRCLK0 + RXUSRCLK0 + 160 + 160 + 160 + 160 + 160 + 160 + 160 + 160 + 100GBASER_MODE + 100GBASER_MODE + 100GBASER_MODE + 100GBASER_MODE + 100GBASER_MODE + 100GBASER_MODE + 100GBASER_MODE + 100GBASER_MODE + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 0 + false + false + false + false + false + false + false + false + false + gtxKintex7FEE80 + GTX + right_column + true + Start_from_scratch + 2 + 80.000 + false + 2 + 80.000 + false + false + 60 + true + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + REFCLK0_Q0 + REFCLK1_Q0 + REFCLK1_Q0 + REFCLK1_Q0 + REFCLK1_Q1 + REFCLK1_Q1 + REFCLK1_Q1 + REFCLK1_Q1 + REFCLK1_Q2 + REFCLK1_Q2 + REFCLK1_Q2 + REFCLK1_Q2 + REFCLK1_Q3 + REFCLK1_Q3 + REFCLK1_Q3 + REFCLK1_Q3 + REFCLK1_Q4 + REFCLK1_Q4 + REFCLK1_Q4 + REFCLK1_Q4 + REFCLK1_Q5 + REFCLK1_Q5 + REFCLK1_Q5 + REFCLK1_Q5 + REFCLK1_Q6 + REFCLK1_Q6 + REFCLK1_Q6 + REFCLK1_Q6 + REFCLK1_Q7 + REFCLK1_Q7 + REFCLK1_Q7 + REFCLK1_Q7 + REFCLK1_Q8 + REFCLK1_Q8 + REFCLK1_Q8 + REFCLK1_Q8 + REFCLK0_Q0 + REFCLK1_Q0 + REFCLK1_Q0 + REFCLK1_Q0 + REFCLK1_Q1 + REFCLK1_Q1 + REFCLK1_Q1 + REFCLK1_Q1 + REFCLK1_Q2 + REFCLK1_Q2 + REFCLK1_Q2 + REFCLK1_Q2 + REFCLK1_Q3 + REFCLK1_Q3 + REFCLK1_Q3 + REFCLK1_Q3 + REFCLK1_Q4 + REFCLK1_Q4 + REFCLK1_Q4 + REFCLK1_Q4 + REFCLK1_Q5 + REFCLK1_Q5 + REFCLK1_Q5 + REFCLK1_Q5 + REFCLK1_Q6 + REFCLK1_Q6 + REFCLK1_Q6 + REFCLK1_Q6 + REFCLK1_Q7 + REFCLK1_Q7 + REFCLK1_Q7 + REFCLK1_Q7 + REFCLK1_Q8 + REFCLK1_Q8 + REFCLK1_Q8 + REFCLK1_Q8 + false + false + Start_from_scratch + false + false + 2 + 20 + 8B/10B + 20 + 80.000 + 5 + 5 + 16 + 1 + 1 + 2 + 2 + 20 + 8B/10B + 20 + 80.000 + 2 + true + 80 + false + false + false + false + false + true + false + false + TXOUTCLK + false + RXOUTCLK + false + false + true + false + false + false + false + true + false + true + true + true + true + true + false + K28.5 + 0101111100 + 1010000011 + 1111111111 + false + Any_Byte_Boundary + false + false + false + false + false + false + Custom + false + false + LPM-Auto + Auto + AVTT + 800 + false + false + false + false + false + false + false + false + false + false + false + true + false + false + false + false + 4 + 4 + 100 + 60 + 60 + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + false + false + false + false + false + false + 1 + 1 + false + false + 1 + 100 + 5000 + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + 00000000 + false + false + false + OFF + 7 + USE_TXPLLREFCLK + AUTO + 1 + 1 + -1 + xc7k160t + bottom_row + no_silicon_version_loaded + false + false + false + false + false + false + false + false + false + false + false + false + CPLL + CPLL + REFCLK1_Q9 + REFCLK1_Q9 + REFCLK1_Q9 + REFCLK1_Q9 + REFCLK1_Q10 + REFCLK1_Q10 + REFCLK1_Q10 + REFCLK1_Q10 + REFCLK1_Q11 + REFCLK1_Q11 + REFCLK1_Q11 + REFCLK1_Q11 + REFCLK1_Q9 + REFCLK1_Q9 + REFCLK1_Q9 + REFCLK1_Q9 + REFCLK1_Q10 + REFCLK1_Q10 + REFCLK1_Q10 + REFCLK1_Q10 + REFCLK1_Q11 + REFCLK1_Q11 + REFCLK1_Q11 + REFCLK1_Q11 + false + 0 + 1 + 4 + 1 + 1 + 1 + 1 + 4 + 1 + 1 + 1 + false + false + DFE + One_Hop + false + false + false + false + false + Auto + Auto + false + false + true + false + false + false + false + false + false + false + false + false + true + false + true + 0000 + false + true + true + true + true + true + true + true + true + Start_from_scratch + Start_from_scratch + Start_from_scratch + Start_from_scratch + Start_from_scratch + Start_from_scratch + Start_from_scratch + Start_from_scratch + Start_from_scratch + 25.78125 + 25.78125 + 25.78125 + 25.78125 + 25.78125 + 25.78125 + 25.78125 + 25.78125 + 25.78125 + false + false + false + false + false + false + false + false + false + 25.78125 + 25.78125 + 25.78125 + 25.78125 + 25.78125 + 25.78125 + 25.78125 + 25.78125 + 25.78125 + false + false + false + false + false + false + false + false + false + REFCLK0 + 322.266 + 322.266 + LANE0 + LANE0 + LANE0 + LANE0 + LANE0 + LANE0 + DRPCLK0 + REFCLK0 + REFCLK0 + REFCLK0 + REFCLK0 + REFCLK0 + REFCLK0 + REFCLK0 + REFCLK0 + TXOUTCLKPMA_DIV4 + TXOUTCLKPMA_DIV4 + TXOUTCLKPMA_DIV4 + TXOUTCLKPMA_DIV4 + TXOUTCLKPMA_DIV4 + TXOUTCLKPMA_DIV4 + TXOUTCLKPMA_DIV4 + TXOUTCLKPMA_DIV4 + RXRECCLKPMA_DIV4 + RXRECCLKPMA_DIV4 + RXRECCLKPMA_DIV4 + RXRECCLKPMA_DIV4 + RXRECCLKPMA_DIV4 + RXRECCLKPMA_DIV4 + RXRECCLKPMA_DIV4 + RXRECCLKPMA_DIV4 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_TXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + OCTAL0_RXOUTCLK0 + TXUSRCLK0 + TXUSRCLK0 + TXUSRCLK0 + TXUSRCLK0 + TXUSRCLK0 + TXUSRCLK0 + TXUSRCLK0 + TXUSRCLK0 + RXUSRCLK0 + RXUSRCLK0 + RXUSRCLK0 + RXUSRCLK0 + RXUSRCLK0 + RXUSRCLK0 + RXUSRCLK0 + RXUSRCLK0 + 160 + 160 + 160 + 160 + 160 + 160 + 160 + 160 + GB_100GBASE_R4 + GB_100GBASE_R4 + GB_100GBASE_R4 + GB_100GBASE_R4 + GB_100GBASE_R4 + GB_100GBASE_R4 + GB_100GBASE_R4 + GB_100GBASE_R4 + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 5 + 8 + 0.5 + 5 + 8 + 0.5 + 5 + 8 + 0.5 + 5 + 8 + 0.5 + 5 + 8 + 0.5 + 5 + 8 + 0.5 + 5 + 8 + 0.5 + 5 + 8 + 0.5 + 5 + 8 + 0.5 + 5 + 8 + 0.5 + 5 + 8 + 0.5 + 5 + 8 + 0.5 + 5 + 8 + 0.5 + 5 + 8 + 0.5 + 5 + 8 + 0.5 + 5 + 8 + 0.5 + kintex7 + xc7k160t + fbg484 + -1 + C + + VHDL + MIXED + TRUE + TRUE + + TRUE + 2015.1 + 0 + OUT_OF_CONTEXT + + . + . + IP_Flow + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80_top.ucf b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxKintex7FEE80_exdes.xdc similarity index 60% rename from FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80_top.ucf rename to FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxKintex7FEE80_exdes.xdc index 09fb567..9a528fe 100644 --- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80_top.ucf +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxKintex7FEE80_exdes.xdc @@ -1,96 +1,104 @@ -################################################################################ -## ____ ____ -## / /\/ / -## /___/ \ / Vendor: Xilinx -## \ \ \/ Version : 1.12 -## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard -## / / Filename : gtxVirtex6FEE80_top.ucf -## /___/ /\ -## \ \ / \ -## \___\/\___\ -## -## -## USER CONSTRAINTS FILE FOR MGT WRAPPER EXAMPLE DESIGN -## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard -## -## Device: xc6vlx130t -## Package: ff484 -## -## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved. -## -## This file contains confidential and proprietary information -## of Xilinx, Inc. and is protected under U.S. and -## international copyright and other intellectual property -## laws. -## -## DISCLAIMER -## This disclaimer is not a license and does not grant any -## rights to the materials distributed herewith. Except as -## otherwise provided in a valid license issued to you by -## Xilinx, and to the maximum extent permitted by applicable -## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -## (2) Xilinx shall not be liable (whether in contract or tort, -## including negligence, or under any other theory of -## liability) for any loss or damage of any kind or nature -## related to, arising under or in connection with these -## materials, including for any direct, or any indirect, -## special, incidental, or consequential loss or damage -## (including loss of data, profits, goodwill, or any type of -## loss or damage suffered as a result of any action brought -## by a third party) even if such damage or loss was -## reasonably foreseeable or Xilinx had been advised of the -## possibility of the same. -## -## CRITICAL APPLICATIONS -## Xilinx products are not designed or intended to be fail- -## safe, or for use in any application requiring fail-safe -## performance, such as life-support or safety devices or -## systems, Class III medical devices, nuclear facilities, -## applications related to the deployment of airbags, or any -## other applications that could lead to death, personal -## injury, or severe property or environmental damage -## (individually and collectively, "Critical -## Applications"). Customer assumes the sole risk and -## liability of any use of Xilinx products in Critical -## Applications, subject only to applicable laws and -## regulations governing limitations on product liability. -## -## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -## PART OF THIS FILE AT ALL TIMES. - -################################## Clock Constraints ########################## - -NET "q3_clk0_refclk_i" TNM_NET = "q3_clk0_refclk_i"; -TIMESPEC "TS_q3_clk0_refclk_i" = PERIOD "q3_clk0_refclk_i" 12.5; - - - -# User Clock Constraints -NET "gtx0_txusrclk2_i" TNM_NET = "gtx0_txusrclk2_i"; -TIMESPEC "TS_gtx0_txusrclk2_i" = PERIOD "gtx0_txusrclk2_i" 5.0; - -NET "gtx0_rxusrclk2_i" TNM_NET = "gtx0_rxusrclk2_i"; -TIMESPEC "TS_gtx0_rxusrclk2_i" = PERIOD "gtx0_rxusrclk2_i" 5.0; - - - -#################### locs for top level ports (ML623 Board) ################### - - - -####################### GTX reference clock constraints ####################### -NET Q3_CLK0_MGTREFCLK_PAD_N_IN LOC=L3; -NET Q3_CLK0_MGTREFCLK_PAD_P_IN LOC=L4; - - -################################# mgt wrapper constraints ##################### - -##---------- Set placement for gtx0_gtx_wrapper_i/GTX_DUAL ------ -INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i LOC=GTXE1_X0Y12; - - - +################################################################################ +## ____ ____ +## / /\/ / +## /___/ \ / Vendor: Xilinx +## \ \ \/ Version : 3.5 +## \ \ Application : 7 Series FPGAs Transceivers Wizard +## / / Filename : gtxKintex7FEE80_exdes.xdc +## /___/ /\ +## \ \ / \ +## \___\/\___\ +## +## +## USER CONSTRAINTS FILE FOR MGT WRAPPER EXAMPLE DESIGN +## Generated by Xilinx 7 Series FPGAs Transceivers Wizard +## +## Device: xc7k160t +## Package: fbg484 +## +## (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +## +## This file contains confidential and proprietary information +## of Xilinx, Inc. and is protected under U.S. and +## international copyright and other intellectual property +## laws. +## +## DISCLAIMER +## This disclaimer is not a license and does not grant any +## rights to the materials distributed herewith. Except as +## otherwise provided in a valid license issued to you by +## Xilinx, and to the maximum extent permitted by applicable +## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +## (2) Xilinx shall not be liable (whether in contract or tort, +## including negligence, or under any other theory of +## liability) for any loss or damage of any kind or nature +## related to, arising under or in connection with these +## materials, including for any direct, or any indirect, +## special, incidental, or consequential loss or damage +## (including loss of data, profits, goodwill, or any type of +## loss or damage suffered as a result of any action brought +## by a third party) even if such damage or loss was +## reasonably foreseeable or Xilinx had been advised of the +## possibility of the same. +## +## CRITICAL APPLICATIONS +## Xilinx products are not designed or intended to be fail- +## safe, or for use in any application requiring fail-safe +## performance, such as life-support or safety devices or +## systems, Class III medical devices, nuclear facilities, +## applications related to the deployment of airbags, or any +## other applications that could lead to death, personal +## injury, or severe property or environmental damage +## (individually and collectively, "Critical +## Applications"). Customer assumes the sole risk and +## liability of any use of Xilinx products in Critical +## Applications, subject only to applicable laws and +## regulations governing limitations on product liability. +## +## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +## PART OF THIS FILE AT ALL TIMES. + + +################################## Clock Constraints ########################## + + +####################### GT reference clock constraints ######################### + + + create_clock -period 12.5 [get_ports Q0_CLK0_GTREFCLK_PAD_P_IN] + + + + + +create_clock -name drpclk_in_i -period 12.5 [get_ports DRP_CLK_IN_P] + + +# User Clock Constraints + + +set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/CLR}] +set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/D}] +set_false_path -to [get_pins -hierarchical -filter {NAME =~ *reset_on_error_in_r*/D}] +################################# RefClk Location constraints ##################### +set_property LOC D5 [get_ports Q0_CLK0_GTREFCLK_PAD_N_IN ] +set_property LOC D6 [get_ports Q0_CLK0_GTREFCLK_PAD_P_IN ] + +## LOC constrain for DRP_CLK_P/N +## set_property LOC C25 [get_ports DRP_CLK_IN_P] +## set_property LOC B25 [get_ports DRP_CLK_IN_N] + +################################# mgt wrapper constraints ##################### + +##---------- Set placement for gt0_gtx_wrapper_i/GTXE2_CHANNEL ------ +set_property LOC GTXE2_CHANNEL_X0Y0 [get_cells gtxKintex7FEE80_support_i/gtxKintex7FEE80_init_i/U0/gtxKintex7FEE80_i/gt0_gtxKintex7FEE80_i/gtxe2_i] + +##---------- Set ASYNC_REG for flop which have async input ---------- +##set_property ASYNC_REG TRUE [get_cells -hier -filter {name=~*gt0_frame_gen*system_reset_r_reg}] +##set_property ASYNC_REG TRUE [get_cells -hier -filter {name=~*gt0_frame_check*system_reset_r_reg}] + +##---------- Set False Path from one clock to other ---------- diff --git a/FEE_ADC32board/project/ipcore_dir/clockmodule80M.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_clock_module.vhd similarity index 64% rename from FEE_ADC32board/project/ipcore_dir/clockmodule80M.vhd rename to FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_clock_module.vhd index 43be5a5..6ef9b3e 100644 --- a/FEE_ADC32board/project/ipcore_dir/clockmodule80M.vhd +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_clock_module.vhd @@ -1,199 +1,245 @@ --- file: clockmodule80M.vhd --- --- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- ------------------------------------------------------------------------------- --- User entered comments ------------------------------------------------------------------------------- --- None --- ------------------------------------------------------------------------------- --- "Output Output Phase Duty Pk-to-Pk Phase" --- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" ------------------------------------------------------------------------------- --- CLK_OUT1____99.999______0.000______50.0______144.151____174.045 --- ------------------------------------------------------------------------------- --- "Input Clock Freq (MHz) Input Jitter (UI)" ------------------------------------------------------------------------------- --- __primary__________155.52____________0.010 - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; -use ieee.numeric_std.all; - -library unisim; -use unisim.vcomponents.all; - -entity clockmodule80M is -port - (-- Clock in ports - CLK_IN1 : in std_logic; - -- Clock out ports - CLK_OUT1 : out std_logic; - -- Status and control signals - LOCKED : out std_logic - ); -end clockmodule80M; - -architecture xilinx of clockmodule80M is - attribute CORE_GENERATION_INFO : string; - attribute CORE_GENERATION_INFO of xilinx : architecture is "clockmodule80M,clk_wiz_v3_6,{component_name=clockmodule80M,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=6.430,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}"; - -- Input clock buffering / unused connectors - signal clkin1 : std_logic; - -- Output clock buffering / unused connectors - signal clkfbout : std_logic; - signal clkfbout_buf : std_logic; - signal clkfboutb_unused : std_logic; - signal clkout0 : std_logic; - signal clkout0b_unused : std_logic; - signal clkout1_unused : std_logic; - signal clkout1b_unused : std_logic; - signal clkout2_unused : std_logic; - signal clkout2b_unused : std_logic; - signal clkout3_unused : std_logic; - signal clkout3b_unused : std_logic; - signal clkout4_unused : std_logic; - signal clkout5_unused : std_logic; - signal clkout6_unused : std_logic; - -- Dynamic programming unused signals - signal do_unused : std_logic_vector(15 downto 0); - signal drdy_unused : std_logic; - -- Dynamic phase shift unused signals - signal psdone_unused : std_logic; - -- Unused status signals - signal clkfbstopped_unused : std_logic; - signal clkinstopped_unused : std_logic; -begin - - - -- Input buffering - -------------------------------------- - clkin1 <= CLK_IN1; - - - -- Clocking primitive - -------------------------------------- - -- Instantiation of the MMCM primitive - -- * Unused inputs are tied off - -- * Unused outputs are labeled unused - mmcm_adv_inst : MMCM_ADV - generic map - (BANDWIDTH => "OPTIMIZED", - CLKOUT4_CASCADE => FALSE, - CLOCK_HOLD => FALSE, - COMPENSATION => "ZHOLD", - STARTUP_WAIT => FALSE, - DIVCLK_DIVIDE => 5, - CLKFBOUT_MULT_F => 43.000, - CLKFBOUT_PHASE => 0.000, - CLKFBOUT_USE_FINE_PS => FALSE, - CLKOUT0_DIVIDE_F => 13.375, - CLKOUT0_PHASE => 0.000, - CLKOUT0_DUTY_CYCLE => 0.500, - CLKOUT0_USE_FINE_PS => FALSE, - CLKIN1_PERIOD => 6.430, - REF_JITTER1 => 0.010) - port map - -- Output clocks - (CLKFBOUT => clkfbout, - CLKFBOUTB => clkfboutb_unused, - CLKOUT0 => clkout0, - CLKOUT0B => clkout0b_unused, - CLKOUT1 => clkout1_unused, - CLKOUT1B => clkout1b_unused, - CLKOUT2 => clkout2_unused, - CLKOUT2B => clkout2b_unused, - CLKOUT3 => clkout3_unused, - CLKOUT3B => clkout3b_unused, - CLKOUT4 => clkout4_unused, - CLKOUT5 => clkout5_unused, - CLKOUT6 => clkout6_unused, - -- Input clock control - CLKFBIN => clkfbout_buf, - CLKIN1 => clkin1, - CLKIN2 => '0', - -- Tied to always select the primary input clock - CLKINSEL => '1', - -- Ports for dynamic reconfiguration - DADDR => (others => '0'), - DCLK => '0', - DEN => '0', - DI => (others => '0'), - DO => do_unused, - DRDY => drdy_unused, - DWE => '0', - -- Ports for dynamic phase shift - PSCLK => '0', - PSEN => '0', - PSINCDEC => '0', - PSDONE => psdone_unused, - -- Other control and status signals - LOCKED => LOCKED, - CLKINSTOPPED => clkinstopped_unused, - CLKFBSTOPPED => clkfbstopped_unused, - PWRDWN => '0', - RST => '0'); - - -- Output buffering - ------------------------------------- - clkf_buf : BUFG - port map - (O => clkfbout_buf, - I => clkfbout); - - - clkout1_buf : BUFG - port map - (O => CLK_OUT1, - I => clkout0); - - - -end xilinx; +-- file: clk_wiz_v2_1.vhd +-- +-- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +------------------------------------------------------------------------------ +-- User entered comments +------------------------------------------------------------------------------ +-- None +-- +------------------------------------------------------------------------------ +-- Output Output Phase Duty Cycle Pk-to-Pk Phase +-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +------------------------------------------------------------------------------ +-- CLK_OUT1 100.000 0.000 50.000 130.958 98.575 +-- CLK_OUT2 200.000 0.000 50.000 114.829 98.575 +-- +------------------------------------------------------------------------------ +-- Input Clock Input Freq (MHz) Input Jitter (UI) +------------------------------------------------------------------------------ +-- primary 100.000 0.010 + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; +use ieee.numeric_std.all; + +library unisim; +use unisim.vcomponents.all; + +entity gtxKintex7FEE80_CLOCK_MODULE is +generic +( + MULT : real := 2.0; + DIVIDE : integer := 2; + CLK_PERIOD : real := 6.4; + OUT0_DIVIDE : real := 2.0; + OUT1_DIVIDE : integer := 2; + OUT2_DIVIDE : integer := 2; + OUT3_DIVIDE : integer := 2 +); +port + (-- Clock in ports + CLK_IN : in std_logic; + -- Clock out ports + CLK0_OUT : out std_logic; + CLK1_OUT : out std_logic; + CLK2_OUT : out std_logic; + CLK3_OUT : out std_logic; + -- Status and control signals + MMCM_RESET_IN : in std_logic; + MMCM_LOCKED_OUT : out std_logic + ); +end gtxKintex7FEE80_CLOCK_MODULE; + +architecture xilinx of gtxKintex7FEE80_CLOCK_MODULE is + attribute X_CORE_INFO : string; + attribute X_CORE_INFO of xilinx : architecture is "gtxKintex7FEE80,gtwizard_v3_5,{protocol_file=Start_from_scratch}"; + attribute CORE_GENERATION_INFO : string; + attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_v2_1,clk_wiz_v2_1,{component_name=clk_wiz_v2_1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}"; + -- Input clock buffering / unused connectors + signal clkin1 : std_logic; + -- Output clock buffering / unused connectors + signal clkfbout : std_logic; + signal clkfbout_buf : std_logic; + signal clkfboutb_unused : std_logic; + signal clkout0 : std_logic; + signal clkout0b_unused : std_logic; + signal clkout1 : std_logic; + signal clkout1b_unused : std_logic; + signal clkout2 : std_logic; + signal clkout2b_unused : std_logic; + signal clkout3 : std_logic; + signal clkout3b_unused : std_logic; + signal clkout4_unused : std_logic; + signal clkout5_unused : std_logic; + signal clkout6_unused : std_logic; + -- Dynamic programming unused signals + signal do_unused : std_logic_vector(15 downto 0); + signal drdy_unused : std_logic; + -- Dynamic phase shift unused signals + signal psdone_unused : std_logic; + -- Unused status signals + signal clkfbstopped_unused : std_logic; + signal clkinstopped_unused : std_logic; +begin + + + -- Input buffering + -------------------------------------- + clkin1_buf : BUFG + port map + (O => clkin1, + I => CLK_IN); + + -- Clocking primitive + -------------------------------------- + -- Instantiation of the MMCM primitive + -- * Unused inputs are tied off + -- * Unused outputs are labeled unused + + mmcm_adv_inst : MMCME2_ADV + generic map + (BANDWIDTH => "OPTIMIZED", + CLKOUT4_CASCADE => FALSE, + COMPENSATION => "ZHOLD", + STARTUP_WAIT => FALSE, + DIVCLK_DIVIDE => DIVIDE, + CLKFBOUT_MULT_F => MULT, + CLKFBOUT_PHASE => 0.000, + CLKFBOUT_USE_FINE_PS => FALSE, + CLKOUT0_DIVIDE_F => OUT0_DIVIDE, + CLKOUT0_PHASE => 0.000, + CLKOUT0_DUTY_CYCLE => 0.500, + CLKOUT0_USE_FINE_PS => FALSE, + CLKIN1_PERIOD => CLK_PERIOD, + CLKOUT1_DIVIDE => OUT1_DIVIDE, + CLKOUT1_PHASE => 0.000, + CLKOUT1_DUTY_CYCLE => 0.500, + CLKOUT1_USE_FINE_PS => FALSE, + CLKOUT2_DIVIDE => OUT2_DIVIDE, + CLKOUT2_PHASE => 0.000, + CLKOUT2_DUTY_CYCLE => 0.500, + CLKOUT2_USE_FINE_PS => FALSE, + CLKOUT3_DIVIDE => OUT3_DIVIDE, + CLKOUT3_PHASE => 0.000, + CLKOUT3_DUTY_CYCLE => 0.500, + CLKOUT3_USE_FINE_PS => FALSE, + REF_JITTER1 => 0.010) + port map + -- Output clocks + (CLKFBOUT => clkfbout, + CLKFBOUTB => clkfboutb_unused, + CLKOUT0 => clkout0, + CLKOUT0B => clkout0b_unused, + CLKOUT1 => clkout1, + CLKOUT1B => clkout1b_unused, + CLKOUT2 => clkout2, + CLKOUT2B => clkout2b_unused, + CLKOUT3 => clkout3, + CLKOUT3B => clkout3b_unused, + CLKOUT4 => clkout4_unused, + CLKOUT5 => clkout5_unused, + CLKOUT6 => clkout6_unused, + -- Input clock control + CLKFBIN => clkfbout, + CLKIN1 => clkin1, + CLKIN2 => '0', + -- Tied to always select the primary input clock + CLKINSEL => '1', + -- Ports for dynamic reconfiguration + DADDR => (others => '0'), + DCLK => '0', + DEN => '0', + DI => (others => '0'), + DO => do_unused, + DRDY => drdy_unused, + DWE => '0', + -- Ports for dynamic phase shift + PSCLK => '0', + PSEN => '0', + PSINCDEC => '0', + PSDONE => psdone_unused, + -- Other control and status signals + LOCKED => MMCM_LOCKED_OUT, + CLKINSTOPPED => clkinstopped_unused, + CLKFBSTOPPED => clkfbstopped_unused, + PWRDWN => '0', + RST => MMCM_RESET_IN); + + -- Output buffering + ------------------------------------- + --clkf_buf : BUFG + --port map + -- (O => clkfbout_buf, + -- I => clkfbout); + + + clkout0_buf : BUFG + port map + (O => CLK0_OUT, + I => clkout0); + + clkout1_buf : BUFG + port map + (O => CLK1_OUT, + I => clkout1); + +-- clkout2_buf : BUFG +-- port map +-- (O => CLK2_OUT, +-- I => clkout2); +-- +-- clkout3_buf : BUFG +-- port map +-- (O => CLK3_OUT, +-- I => clkout3); + +CLK2_OUT <= '0'; +CLK3_OUT <= '0'; +end xilinx; diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_common.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_common.vhd new file mode 100644 index 0000000..0857143 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_common.vhd @@ -0,0 +1,247 @@ +--------------------------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 3.5 +-- \ \ Application : 7 Series FPGAs Transceivers Wizard +-- / / Filename : gtxkintex7fee80_common.vhd +-- /___/ /\ +-- \ \ / \ +-- \___\/\___\ +-- +-- +-- Module gtxKintex7FEE80_common +-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard +-- +-- +-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; + + +--***************************** Entity Declaration **************************** +entity gtxKintex7FEE80_common is +generic +( + -- Simulation attributes + WRAPPER_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- Set to "true" to speed up sim reset + SIM_QPLLREFCLK_SEL : bit_vector := "001" +); +port +( + QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0); + GTREFCLK1_IN : in std_logic; + GTREFCLK0_IN : in std_logic; + QPLLLOCK_OUT : out std_logic; + QPLLLOCKDETCLK_IN : in std_logic; + QPLLOUTCLK_OUT : out std_logic; + QPLLOUTREFCLK_OUT : out std_logic; + QPLLREFCLKLOST_OUT : out std_logic; + QPLLRESET_IN : in std_logic +); + +end gtxKintex7FEE80_common; + +architecture RTL of gtxKintex7FEE80_common is + + attribute CORE_GENERATION_INFO : string; + attribute CORE_GENERATION_INFO of RTL : architecture is "gtxKintex7FEE80_common,gtwizard_v3_5,{protocol_file=Start_from_scratch}"; + + + +--***********************************Parameter Declarations******************** + + constant DLY : time := 1 ns; + +--*************************Logic to set Attribute QPLL_FB_DIV***************************** + impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is + begin + if (qpllfbdiv_top = 16) then + return "0000100000"; + elsif (qpllfbdiv_top = 20) then + return "0000110000" ; + elsif (qpllfbdiv_top = 32) then + return "0001100000" ; + elsif (qpllfbdiv_top = 40) then + return "0010000000" ; + elsif (qpllfbdiv_top = 64) then + return "0011100000" ; + elsif (qpllfbdiv_top = 66) then + return "0101000000" ; + elsif (qpllfbdiv_top = 80) then + return "0100100000" ; + elsif (qpllfbdiv_top = 100) then + return "0101110000" ; + else + return "0000000000" ; + end if; + end function; + + impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is + begin + if (qpllfbdiv_top = 16) then + return '1'; + elsif (qpllfbdiv_top = 20) then + return '1' ; + elsif (qpllfbdiv_top = 32) then + return '1' ; + elsif (qpllfbdiv_top = 40) then + return '1' ; + elsif (qpllfbdiv_top = 64) then + return '1' ; + elsif (qpllfbdiv_top = 66) then + return '0' ; + elsif (qpllfbdiv_top = 80) then + return '1' ; + elsif (qpllfbdiv_top = 100) then + return '1' ; + else + return '1' ; + end if; + end function; + + constant QPLL_FBDIV_TOP : integer := 16; + constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP); + constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP); + + -- ground and tied_to_vcc_i signals + signal tied_to_ground_i : std_logic; + signal tied_to_ground_vec_i : std_logic_vector(63 downto 0); + signal tied_to_vcc_i : std_logic; + signal tied_to_vcc_vec_i : std_logic_vector(63 downto 0); + +begin + tied_to_ground_i <= '0'; + tied_to_ground_vec_i(63 downto 0) <= (others => '0'); + tied_to_vcc_i <= '1'; + tied_to_vcc_vec_i(63 downto 0) <= (others => '1'); + + --_________________________________________________________________________ + --_________________________________________________________________________ + --_________________________GTXE2_COMMON____________________________________ + + gtxe2_common_i : GTXE2_COMMON + generic map + ( + -- Simulation attributes + SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP, + SIM_QPLLREFCLK_SEL => (SIM_QPLLREFCLK_SEL), + SIM_VERSION => "4.0", + + + ------------------COMMON BLOCK Attributes--------------- + BIAS_CFG => (x"0000040000001000"), + COMMON_CFG => (x"00000000"), + QPLL_CFG => (x"06801C1"), + QPLL_CLKOUT_CFG => ("0000"), + QPLL_COARSE_FREQ_OVRD => ("010000"), + QPLL_COARSE_FREQ_OVRD_EN => ('0'), + QPLL_CP => ("0000011111"), + QPLL_CP_MONITOR_EN => ('0'), + QPLL_DMONITOR_SEL => ('0'), + QPLL_FBDIV => (QPLL_FBDIV_IN), + QPLL_FBDIV_MONITOR_EN => ('0'), + QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO), + QPLL_INIT_CFG => (x"000006"), + QPLL_LOCK_CFG => (x"21E8"), + QPLL_LPF => ("1111"), + QPLL_REFCLK_DIV => (1) + + + ) + port map + ( + ------------- Common Block - Dynamic Reconfiguration Port (DRP) ----------- + DRPADDR => tied_to_ground_vec_i(7 downto 0), + DRPCLK => tied_to_ground_i, + DRPDI => tied_to_ground_vec_i(15 downto 0), + DRPDO => open, + DRPEN => tied_to_ground_i, + DRPRDY => open, + DRPWE => tied_to_ground_i, + ---------------------- Common Block - Ref Clock Ports --------------------- + GTGREFCLK => tied_to_ground_i, + GTNORTHREFCLK0 => tied_to_ground_i, + GTNORTHREFCLK1 => tied_to_ground_i, + GTREFCLK0 => GTREFCLK0_IN, + GTREFCLK1 => GTREFCLK1_IN, + GTSOUTHREFCLK0 => tied_to_ground_i, + GTSOUTHREFCLK1 => tied_to_ground_i, + ------------------------- Common Block - QPLL Ports ----------------------- + QPLLDMONITOR => open, + ----------------------- Common Block - Clocking Ports ---------------------- + QPLLOUTCLK => QPLLOUTCLK_OUT, + QPLLOUTREFCLK => QPLLOUTREFCLK_OUT, + REFCLKOUTMONITOR => open, + ------------------------- Common Block - QPLL Ports ------------------------ + QPLLFBCLKLOST => open, + QPLLLOCK => QPLLLOCK_OUT, + QPLLLOCKDETCLK => QPLLLOCKDETCLK_IN, + QPLLLOCKEN => tied_to_vcc_i, + QPLLOUTRESET => tied_to_ground_i, + QPLLPD => tied_to_vcc_i, + QPLLREFCLKLOST => QPLLREFCLKLOST_OUT, + QPLLREFCLKSEL => QPLLREFCLKSEL_IN, + QPLLRESET => QPLLRESET_IN, + QPLLRSVD1 => "0000000000000000", + QPLLRSVD2 => "11111", + --------------------------------- QPLL Ports ------------------------------- + BGBYPASSB => tied_to_vcc_i, + BGMONITORENB => tied_to_vcc_i, + BGPDB => tied_to_vcc_i, + BGRCALOVRD => "11111", + PMARSVD => "00000000", + RCALENB => tied_to_vcc_i + + ); + +end RTL; diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_common_reset.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_common_reset.vhd new file mode 100644 index 0000000..65ebb28 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_common_reset.vhd @@ -0,0 +1,154 @@ +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 3.5 +-- \ \ Application : 7 Series FPGAs Transceivers Wizard +-- / / Filename : gtxkintex7fee80_common_reset.vhd +-- /___/ /\ +-- \ \ / \ +-- \___\/\___\ +-- +-- +-- Description : This module performs TX reset and initialization. +-- +-- +-- +-- Module gtxKintex7FEE80_common_reset +-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard +-- +-- +-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + + +--***************************************************************************** +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; +use std.textio.all; +use ieee.std_logic_textio.all; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; + +entity gtxKintex7FEE80_common_reset is +generic +( + STABLE_CLOCK_PERIOD : integer := 8 -- Period of the stable clock driving this state-machine, unit is [ns] + ); +port + ( + STABLE_CLOCK : in std_logic; --Stable Clock, either a stable clock from the PCB + SOFT_RESET : in std_logic; --User Reset, can be pulled any time + COMMON_RESET : out std_logic:= '0' --Reset QPLL + ); +end gtxKintex7FEE80_common_reset; + +architecture RTL of gtxKintex7FEE80_common_reset is + + + constant STARTUP_DELAY : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration + constant WAIT_CYCLES : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration + constant WAIT_MAX : integer := WAIT_CYCLES + 10; -- 500 ns plus some additional margin + + + signal init_wait_count : std_logic_vector(7 downto 0) :=(others => '0'); + signal init_wait_done : std_logic :='0'; + signal common_reset_asserted : std_logic :='0'; + signal common_reset_i : std_logic ; + + type rst_type is( + INIT, ASSERT_COMMON_RESET); + + signal state : rst_type := INIT; + +begin + process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + -- The counter starts running when configuration has finished and + -- the clock is stable. When its maximum count-value has been reached, + -- the 500 ns from Answer Record 43482 have been passed. + if init_wait_count = WAIT_MAX then + init_wait_done <= '1'; + else + init_wait_count <= init_wait_count + 1; + end if; + end if; + end process; + + process(STABLE_CLOCK) + begin + if rising_edge(STABLE_CLOCK) then + if(SOFT_RESET = '1') then + state <= INIT; + common_reset_asserted <= '0'; + COMMON_RESET <= '0'; + else + + case state is + when INIT => + if init_wait_done = '1' then + state <= ASSERT_COMMON_RESET; + end if; + + when ASSERT_COMMON_RESET => + if common_reset_asserted = '0' then + COMMON_RESET <= '1'; + common_reset_asserted <= '1'; + else + COMMON_RESET <= '0'; + end if; + when OTHERS => + state <= INIT; + end case; + end if; + end if; + end process; + + +end RTL; diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_gt_usrclk_source.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_gt_usrclk_source.vhd new file mode 100644 index 0000000..63414e5 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_gt_usrclk_source.vhd @@ -0,0 +1,206 @@ +------------------------------------------------------------------------------ +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 3.5 +-- \ \ Application : 7 Series FPGAs Transceivers Wizard +-- / / Filename : gtxkintex7fee80_gt_usrclk_source.vhd +-- /___/ /\ +-- \ \ / \ +-- \___\/\___\ +-- +-- +-- Module gtxKintex7FEE80_GT_USRCLK_SOURCE (for use with GTs) +-- Generated by Xilinx 7 Series FPGAs Transceivers 7 Series FPGAs Transceivers Wizard +-- +-- +-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; + +--***********************************Entity Declaration******************************* +entity gtxKintex7FEE80_GT_USRCLK_SOURCE is +port +( + + GT0_TXUSRCLK_OUT : out std_logic; + GT0_TXUSRCLK2_OUT : out std_logic; + GT0_TXUSRCLKX2_OUT : out std_logic; --// Modified + GT0_TXOUTCLK_IN : in std_logic; + GT0_TXCLK_LOCK_OUT : out std_logic; + GT0_TX_MMCM_RESET_IN : in std_logic; + GT0_RXUSRCLK_OUT : out std_logic; + GT0_RXUSRCLK2_OUT : out std_logic; + GT0_RXOUTCLK_IN : in std_logic; + Q0_CLK0_GTREFCLK_PAD_N_IN : in std_logic; + Q0_CLK0_GTREFCLK_PAD_P_IN : in std_logic; + Q0_CLK0_GTREFCLK_OUT : out std_logic +); + + +end gtxKintex7FEE80_GT_USRCLK_SOURCE; + +architecture RTL of gtxKintex7FEE80_GT_USRCLK_SOURCE is + +component GTXKINTEX7FEE80_CLOCK_MODULE is +generic +( + MULT : real := 2.0; + DIVIDE : integer := 2; + CLK_PERIOD : real := 6.4; + OUT0_DIVIDE : real := 2.0; + OUT1_DIVIDE : integer := 2; + OUT2_DIVIDE : integer := 2; + OUT3_DIVIDE : integer := 2 +); +port + (-- Clock in ports + CLK_IN : in std_logic; + -- Clock out ports + CLK0_OUT : out std_logic; + CLK1_OUT : out std_logic; + CLK2_OUT : out std_logic; + CLK3_OUT : out std_logic; + -- Status and control signals + MMCM_RESET_IN : in std_logic; + MMCM_LOCKED_OUT : out std_logic + ); +end component; + +--*********************************Wire Declarations********************************** + + signal tied_to_ground_i : std_logic; + signal tied_to_vcc_i : std_logic; + + signal gt0_txoutclk_i : std_logic; + signal gt0_rxoutclk_i : std_logic; + + attribute syn_noclockbuf : boolean; + signal q0_clk0_gtrefclk : std_logic; + attribute syn_noclockbuf of q0_clk0_gtrefclk : signal is true; + + signal gt0_txusrclk_i : std_logic; + signal gt0_rxusrclk_i : std_logic; + signal txoutclk_mmcm0_locked_i : std_logic; + signal txoutclk_mmcm0_reset_i : std_logic; + signal gt0_txoutclk_to_mmcm_i : std_logic; + + +begin + +--*********************************** Beginning of Code ******************************* + + -- Static signal Assigments + tied_to_ground_i <= '0'; + tied_to_vcc_i <= '1'; + gt0_txoutclk_i <= GT0_TXOUTCLK_IN; + gt0_rxoutclk_i <= GT0_RXOUTCLK_IN; + + Q0_CLK0_GTREFCLK_OUT <= q0_clk0_gtrefclk; + + --IBUFDS_GTE2 + ibufds_instq0_clk0 : IBUFDS_GTE2 + port map + ( + O => q0_clk0_gtrefclk, + ODIV2 => open, + CEB => tied_to_ground_i, + I => Q0_CLK0_GTREFCLK_PAD_P_IN, + IB => Q0_CLK0_GTREFCLK_PAD_N_IN + ); + + + + -- Instantiate a MMCM module to divide the reference clock. Uses internal feedback + -- for improved jitter performance, and to avoid consuming an additional BUFG + txoutclk_mmcm0_reset_i <= GT0_TX_MMCM_RESET_IN; + txoutclk_mmcm0_i : gtxKintex7FEE80_CLOCK_MODULE + generic map + ( + MULT => 40.0, --// 35.0, Modified + DIVIDE => 4, + CLK_PERIOD => 12.5, + OUT0_DIVIDE => 8.0, --// 7.0 Modified + OUT1_DIVIDE => 4, --// 1 Modified + OUT2_DIVIDE => 1, + OUT3_DIVIDE => 1 + ) + port map + ( + CLK0_OUT => gt0_txusrclk_i, + CLK1_OUT => GT0_TXUSRCLKX2_OUT, --// Modified + CLK2_OUT => open, + CLK3_OUT => open, + CLK_IN => gt0_txoutclk_i, + MMCM_LOCKED_OUT => txoutclk_mmcm0_locked_i, + MMCM_RESET_IN => txoutclk_mmcm0_reset_i + ); + + + rxoutclk_bufg1_i : BUFG + port map + ( + I => gt0_rxoutclk_i, + O => gt0_rxusrclk_i + ); + + + + +GT0_TXUSRCLK_OUT <= gt0_txusrclk_i; +GT0_TXUSRCLK2_OUT <= gt0_txusrclk_i; +GT0_TXCLK_LOCK_OUT <= txoutclk_mmcm0_locked_i; +GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i; +GT0_RXUSRCLK2_OUT <= gt0_rxusrclk_i; +end RTL; + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_support.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_support.vhd new file mode 100644 index 0000000..0ee8e9d --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_support.vhd @@ -0,0 +1,663 @@ +------------------------------------------------------------------------------ +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 3.5 +-- \ \ Application : 7 Series FPGAs Transceivers Wizard +-- / / Filename : gtxkintex7fee80_support.vhd +-- /___/ /\ +-- \ \ / \ +-- \___\/\___\ +-- +-- Description : This module instantiates the modules required for +-- reset and initialisation of the Transceiver +-- +-- Module gtxKintex7FEE80_support +-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard +-- +-- +-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +--***********************************Entity Declaration************************ + +entity gtxKintex7FEE80_support is +generic +( + EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model + STABLE_CLOCK_PERIOD : integer := 12 + +); +port +( + SOFT_RESET_TX_IN : in std_logic; + SOFT_RESET_RX_IN : in std_logic; + DONT_RESET_ON_DATA_ERROR_IN : in std_logic; + Q0_CLK0_GTREFCLK_PAD_N_IN : in std_logic; + Q0_CLK0_GTREFCLK_PAD_P_IN : in std_logic; + + GT0_TX_FSM_RESET_DONE_OUT : out std_logic; + GT0_RX_FSM_RESET_DONE_OUT : out std_logic; + GT0_DATA_VALID_IN : in std_logic; + GT0_TX_MMCM_LOCK_OUT : out std_logic; + + GT0_TXUSRCLK_OUT : out std_logic; + GT0_TXUSRCLK2_OUT : out std_logic; + GT0_TXUSRCLKX2_OUT : out std_logic; --// Modified + GT0_RXUSRCLK_OUT : out std_logic; + GT0_RXUSRCLK2_OUT : out std_logic; + + --_________________________________________________________________________ + --GT0 (X1Y0) + --____________________________CHANNEL PORTS________________________________ + --------------------------------- CPLL Ports ------------------------------- + gt0_cpllfbclklost_out : out std_logic; + gt0_cplllock_out : out std_logic; + gt0_cpllreset_in : in std_logic; + ---------------------------- Channel - DRP Ports -------------------------- + gt0_drpaddr_in : in std_logic_vector(8 downto 0); + gt0_drpdi_in : in std_logic_vector(15 downto 0); + gt0_drpdo_out : out std_logic_vector(15 downto 0); + gt0_drpen_in : in std_logic; + gt0_drprdy_out : out std_logic; + gt0_drpwe_in : in std_logic; + --------------------------- Digital Monitor Ports -------------------------- + gt0_dmonitorout_out : out std_logic_vector(7 downto 0); + --------------------- RX Initialization and Reset Ports -------------------- + gt0_eyescanreset_in : in std_logic; + gt0_rxuserrdy_in : in std_logic; + -------------------------- RX Margin Analysis Ports ------------------------ + gt0_eyescandataerror_out : out std_logic; + gt0_eyescantrigger_in : in std_logic; + ------------------------- Receive Ports - CDR Ports ------------------------ + GT0_RXCDRRESET_IN : in std_logic; --// Modified + GT0_RXCDRLOCK_OUT : out std_logic; --// Modified + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + gt0_rxdata_out : out std_logic_vector(15 downto 0); + ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- + gt0_rxdisperr_out : out std_logic_vector(1 downto 0); + gt0_rxnotintable_out : out std_logic_vector(1 downto 0); + --------------------------- Receive Ports - RX AFE ------------------------- + gt0_gtxrxp_in : in std_logic; + ------------------------ Receive Ports - RX AFE Ports ---------------------- + gt0_gtxrxn_in : in std_logic; + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + gt0_rxphmonitor_out : out std_logic_vector(4 downto 0); + gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0); + --------------------- Receive Ports - RX Equalizer Ports ------------------- + gt0_rxdfelpmreset_in : in std_logic; + gt0_rxmonitorout_out : out std_logic_vector(6 downto 0); + gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0); + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + gt0_gtrxreset_in : in std_logic; + gt0_rxpmareset_in : in std_logic; + ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- + gt0_rxcharisk_out : out std_logic_vector(1 downto 0); + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + gt0_rxresetdone_out : out std_logic; + --------------------- TX Initialization and Reset Ports -------------------- + gt0_gttxreset_in : in std_logic; + gt0_txuserrdy_in : in std_logic; + ------------------ Transmit Ports - TX Data Path interface ----------------- + gt0_txdata_in : in std_logic_vector(15 downto 0); + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + gt0_gtxtxn_out : out std_logic; + gt0_gtxtxp_out : out std_logic; + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + gt0_txoutclkfabric_out : out std_logic; + gt0_txoutclkpcs_out : out std_logic; + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + gt0_txcharisk_in : in std_logic_vector(1 downto 0); + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + gt0_txresetdone_out : out std_logic; + + --____________________________COMMON PORTS________________________________ + GT0_QPLLOUTCLK_IN : in std_logic; --// Modified + GT0_QPLLOUTREFCLK_IN : in std_logic; --// Modified + sysclk_in : in std_logic; + refclk_out : out std_logic --// Modified + +); + +end gtxKintex7FEE80_support; + +architecture RTL of gtxKintex7FEE80_support is +attribute DowngradeIPIdentifiedWarnings: string; +attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes"; + +--**************************Component Declarations***************************** + +component gtxKintex7FEE80 + +port +( + SYSCLK_IN : in std_logic; + SOFT_RESET_TX_IN : in std_logic; + SOFT_RESET_RX_IN : in std_logic; + DONT_RESET_ON_DATA_ERROR_IN : in std_logic; + GT0_TX_FSM_RESET_DONE_OUT : out std_logic; + GT0_RX_FSM_RESET_DONE_OUT : out std_logic; + GT0_DATA_VALID_IN : in std_logic; + GT0_TX_MMCM_LOCK_IN : in std_logic; + GT0_TX_MMCM_RESET_OUT : out std_logic; + + --_________________________________________________________________________ + --GT0 (X1Y0) + --____________________________CHANNEL PORTS________________________________ + --------------------------------- CPLL Ports ------------------------------- + gt0_cpllfbclklost_out : out std_logic; + gt0_cplllock_out : out std_logic; + gt0_cplllockdetclk_in : in std_logic; + gt0_cpllreset_in : in std_logic; + -------------------------- Channel - Clocking Ports ------------------------ + gt0_gtrefclk0_in : in std_logic; + gt0_gtrefclk1_in : in std_logic; + ---------------------------- Channel - DRP Ports -------------------------- + gt0_drpaddr_in : in std_logic_vector(8 downto 0); + gt0_drpclk_in : in std_logic; + gt0_drpdi_in : in std_logic_vector(15 downto 0); + gt0_drpdo_out : out std_logic_vector(15 downto 0); + gt0_drpen_in : in std_logic; + gt0_drprdy_out : out std_logic; + gt0_drpwe_in : in std_logic; + --------------------------- Digital Monitor Ports -------------------------- + gt0_dmonitorout_out : out std_logic_vector(7 downto 0); + --------------------- RX Initialization and Reset Ports -------------------- + gt0_eyescanreset_in : in std_logic; + gt0_rxuserrdy_in : in std_logic; + -------------------------- RX Margin Analysis Ports ------------------------ + gt0_eyescandataerror_out : out std_logic; + gt0_eyescantrigger_in : in std_logic; + ------------------------- Receive Ports - CDR Ports ------------------------ + GT0_RXCDRRESET_IN : in std_logic; --// Modified + GT0_RXCDRLOCK_OUT : out std_logic; --// Modified + ------------------ Receive Ports - FPGA RX Interface Ports ----------------- + gt0_rxusrclk_in : in std_logic; + gt0_rxusrclk2_in : in std_logic; + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + gt0_rxdata_out : out std_logic_vector(15 downto 0); + ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- + gt0_rxdisperr_out : out std_logic_vector(1 downto 0); + gt0_rxnotintable_out : out std_logic_vector(1 downto 0); + --------------------------- Receive Ports - RX AFE ------------------------- + gt0_gtxrxp_in : in std_logic; + ------------------------ Receive Ports - RX AFE Ports ---------------------- + gt0_gtxrxn_in : in std_logic; + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + gt0_rxphmonitor_out : out std_logic_vector(4 downto 0); + gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0); + --------------------- Receive Ports - RX Equalizer Ports ------------------- + gt0_rxdfelpmreset_in : in std_logic; + gt0_rxmonitorout_out : out std_logic_vector(6 downto 0); + gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0); + --------------- Receive Ports - RX Fabric Output Control Ports ------------- + gt0_rxoutclk_out : out std_logic; + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + gt0_gtrxreset_in : in std_logic; + gt0_rxpmareset_in : in std_logic; + ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- + gt0_rxcharisk_out : out std_logic_vector(1 downto 0); + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + gt0_rxresetdone_out : out std_logic; + --------------------- TX Initialization and Reset Ports -------------------- + gt0_gttxreset_in : in std_logic; + gt0_txuserrdy_in : in std_logic; + ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- + gt0_txusrclk_in : in std_logic; + gt0_txusrclk2_in : in std_logic; + ------------------ Transmit Ports - TX Data Path interface ----------------- + gt0_txdata_in : in std_logic_vector(15 downto 0); + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + gt0_gtxtxn_out : out std_logic; + gt0_gtxtxp_out : out std_logic; + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + gt0_txoutclk_out : out std_logic; + gt0_txoutclkfabric_out : out std_logic; + gt0_txoutclkpcs_out : out std_logic; + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + gt0_txcharisk_in : in std_logic_vector(1 downto 0); + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + gt0_txresetdone_out : out std_logic; + + + --____________________________COMMON PORTS________________________________ + GT0_QPLLOUTCLK_IN : in std_logic; + GT0_QPLLOUTREFCLK_IN : in std_logic + +); + +end component; + +component gtxKintex7FEE80_common_reset +generic +( + STABLE_CLOCK_PERIOD : integer := 8 -- Period of the stable clock driving this state-machine, unit is [ns] + ); +port + ( + STABLE_CLOCK : in std_logic; --Stable Clock, either a stable clock from the PCB + SOFT_RESET : in std_logic; --User Reset, can be pulled any time + COMMON_RESET : out std_logic --Reset QPLL + ); +end component; + +component gtxKintex7FEE80_common +generic +( + -- Simulation attributes + WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" ; -- Set to "TRUE" to speed up sim reset + SIM_QPLLREFCLK_SEL :bit_vector := "001" + +); +port +( + QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0); + GTREFCLK0_IN : in std_logic; + GTREFCLK1_IN : in std_logic; + QPLLLOCK_OUT : out std_logic; + QPLLLOCKDETCLK_IN : in std_logic; + QPLLOUTCLK_OUT : out std_logic; + QPLLOUTREFCLK_OUT : out std_logic; + QPLLREFCLKLOST_OUT : out std_logic; + QPLLRESET_IN : in std_logic + +); + +end component; +component gtxKintex7FEE80_GT_USRCLK_SOURCE +port +( + + GT0_TXUSRCLK_OUT : out std_logic; + GT0_TXUSRCLK2_OUT : out std_logic; + GT0_TXUSRCLKX2_OUT : out std_logic; --// Modified + GT0_TXOUTCLK_IN : in std_logic; + GT0_TXCLK_LOCK_OUT : out std_logic; + GT0_TX_MMCM_RESET_IN : in std_logic; + GT0_RXUSRCLK_OUT : out std_logic; + GT0_RXUSRCLK2_OUT : out std_logic; + GT0_RXOUTCLK_IN : in std_logic; + Q0_CLK0_GTREFCLK_PAD_N_IN : in std_logic; + Q0_CLK0_GTREFCLK_PAD_P_IN : in std_logic; + Q0_CLK0_GTREFCLK_OUT : out std_logic +); +end component; + +--***********************************Parameter Declarations******************** + + constant DLY : time := 1 ns; + +--************************** Register Declarations **************************** + + signal gt0_txfsmresetdone_i : std_logic; +signal gt0_rxfsmresetdone_i : std_logic; + signal gt0_txfsmresetdone_r : std_logic; + signal gt0_txfsmresetdone_r2 : std_logic; +signal gt0_rxresetdone_r : std_logic; +signal gt0_rxresetdone_r2 : std_logic; +signal gt0_rxresetdone_r3 : std_logic; + + +signal reset_pulse : std_logic_vector(3 downto 0); + signal reset_counter : unsigned(5 downto 0) := "000000"; + + +--**************************** Wire Declarations ****************************** + -------------------------- GT Wrapper Wires ------------------------------ + --________________________________________________________________________ + --________________________________________________________________________ + --GT0 (X1Y0) + + --------------------------------- CPLL Ports ------------------------------- + signal gt0_cpllfbclklost_i : std_logic; + signal gt0_cplllock_i : std_logic; + signal gt0_cpllrefclklost_i : std_logic; + signal gt0_cpllreset_i : std_logic; + ---------------------------- Channel - DRP Ports -------------------------- + signal gt0_drpaddr_i : std_logic_vector(8 downto 0); + signal gt0_drpdi_i : std_logic_vector(15 downto 0); + signal gt0_drpdo_i : std_logic_vector(15 downto 0); + signal gt0_drpen_i : std_logic; + signal gt0_drprdy_i : std_logic; + signal gt0_drpwe_i : std_logic; + --------------------------- Digital Monitor Ports -------------------------- + signal gt0_dmonitorout_i : std_logic_vector(7 downto 0); + --------------------- RX Initialization and Reset Ports -------------------- + signal gt0_eyescanreset_i : std_logic; + signal gt0_rxuserrdy_i : std_logic; + -------------------------- RX Margin Analysis Ports ------------------------ + signal gt0_eyescandataerror_i : std_logic; + signal gt0_eyescantrigger_i : std_logic; + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + signal gt0_rxdata_i : std_logic_vector(15 downto 0); + ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- + signal gt0_rxdisperr_i : std_logic_vector(1 downto 0); + signal gt0_rxnotintable_i : std_logic_vector(1 downto 0); + --------------------------- Receive Ports - RX AFE ------------------------- + signal gt0_gtxrxp_i : std_logic; + ------------------------ Receive Ports - RX AFE Ports ---------------------- + signal gt0_gtxrxn_i : std_logic; + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + signal gt0_rxdlyen_i : std_logic; + signal gt0_rxdlysreset_i : std_logic; + signal gt0_rxdlysresetdone_i : std_logic; + signal gt0_rxphalign_i : std_logic; + signal gt0_rxphaligndone_i : std_logic; + signal gt0_rxphalignen_i : std_logic; + signal gt0_rxphdlyreset_i : std_logic; + signal gt0_rxphmonitor_i : std_logic_vector(4 downto 0); + signal gt0_rxphslipmonitor_i : std_logic_vector(4 downto 0); + -------------------- Receive Ports - RX Equailizer Ports ------------------- + signal gt0_rxlpmhfhold_i : std_logic; + signal gt0_rxlpmlfhold_i : std_logic; + --------------------- Receive Ports - RX Equalizer Ports ------------------- + signal gt0_rxdfelpmreset_i : std_logic; + signal gt0_rxmonitorout_i : std_logic_vector(6 downto 0); + signal gt0_rxmonitorsel_i : std_logic_vector(1 downto 0); + --------------- Receive Ports - RX Fabric Output Control Ports ------------- + signal gt0_rxoutclk_i : std_logic; + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + signal gt0_gtrxreset_i : std_logic; + signal gt0_rxpmareset_i : std_logic; + ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- + signal gt0_rxcharisk_i : std_logic_vector(1 downto 0); + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + signal gt0_rxresetdone_i : std_logic; + --------------------- TX Initialization and Reset Ports -------------------- + signal gt0_gttxreset_i : std_logic; + signal gt0_txuserrdy_i : std_logic; + ------------------ Transmit Ports - TX Buffer Bypass Ports ----------------- + signal gt0_txdlyen_i : std_logic; + signal gt0_txdlysreset_i : std_logic; + signal gt0_txdlysresetdone_i : std_logic; + signal gt0_txphalign_i : std_logic; + signal gt0_txphaligndone_i : std_logic; + signal gt0_txphalignen_i : std_logic; + signal gt0_txphdlyreset_i : std_logic; + signal gt0_txphinit_i : std_logic; + signal gt0_txphinitdone_i : std_logic; + ------------------ Transmit Ports - TX Data Path interface ----------------- + signal gt0_txdata_i : std_logic_vector(15 downto 0); + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + signal gt0_gtxtxn_i : std_logic; + signal gt0_gtxtxp_i : std_logic; + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + signal gt0_txoutclk_i : std_logic; + signal gt0_txoutclkfabric_i : std_logic; + signal gt0_txoutclkpcs_i : std_logic; + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + signal gt0_txcharisk_i : std_logic_vector(1 downto 0); + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + signal gt0_txresetdone_i : std_logic; + + --____________________________COMMON PORTS________________________________ + signal gt0_qplllock_i : std_logic; + signal gt0_qpllrefclklost_i : std_logic; + signal gt0_qpllreset_i : std_logic; + signal gt0_qpllreset_t : std_logic; + signal gt0_qplloutclk_i : std_logic; + signal gt0_qplloutrefclk_i : std_logic; + + ------------------------------- Global Signals ----------------------------- + signal gt0_tx_system_reset_c : std_logic; + signal gt0_rx_system_reset_c : std_logic; + signal tied_to_ground_i : std_logic; + signal tied_to_ground_vec_i : std_logic_vector(63 downto 0); + signal tied_to_vcc_i : std_logic; + signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0); + signal drpclk_in_i : std_logic; + signal sysclk_in_i : std_logic; + signal GTTXRESET_IN : std_logic; + signal GTRXRESET_IN : std_logic; + signal CPLLRESET_IN : std_logic; + signal QPLLRESET_IN : std_logic; + + attribute keep: string; + ------------------------------- User Clocks --------------------------------- + signal gt0_txusrclk_i : std_logic; + signal gt0_txusrclk2_i : std_logic; + signal gt0_rxusrclk_i : std_logic; + signal gt0_rxusrclk2_i : std_logic; + + + + + signal gt0_txmmcm_lock_i : std_logic; + signal gt0_txmmcm_reset_i : std_logic; + ----------------------------- Reference Clocks ---------------------------- + +signal q0_clk0_refclk_i : std_logic; + +signal commonreset_i : std_logic; +--**************************** Main Body of Code ******************************* +begin + + -- Static signal Assigments +tied_to_ground_i <= '0'; +tied_to_ground_vec_i <= x"0000000000000000"; +tied_to_vcc_i <= '1'; +tied_to_vcc_vec_i <= "11111111"; + + GT0_TX_MMCM_LOCK_OUT <= gt0_txmmcm_lock_i; + + gt0_qpllreset_t <= tied_to_vcc_i; + gt0_qplloutclk_i <= gt0_qplloutclk_in; --// Modified + gt0_qplloutrefclk_i <= gt0_qplloutrefclk_in; --// Modified + + + + GT0_TXUSRCLK_OUT <= gt0_txusrclk_i; + GT0_TXUSRCLK2_OUT <= gt0_txusrclk2_i; + GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i; + GT0_RXUSRCLK2_OUT <= gt0_rxusrclk2_i; + + + + + gt_usrclk_source : gtxKintex7FEE80_GT_USRCLK_SOURCE + port map + ( + + GT0_TXUSRCLK_OUT => gt0_txusrclk_i, + GT0_TXUSRCLK2_OUT => gt0_txusrclk2_i, + GT0_TXUSRCLKX2_OUT => GT0_TXUSRCLKX2_OUT, --// Modified + GT0_TXOUTCLK_IN => gt0_txoutclk_i, + GT0_TXCLK_LOCK_OUT => gt0_txmmcm_lock_i, + GT0_TX_MMCM_RESET_IN => gt0_txmmcm_reset_i, + GT0_RXUSRCLK_OUT => gt0_rxusrclk_i, + GT0_RXUSRCLK2_OUT => gt0_rxusrclk2_i, + GT0_RXOUTCLK_IN => gt0_rxoutclk_i, + Q0_CLK0_GTREFCLK_PAD_N_IN => Q0_CLK0_GTREFCLK_PAD_N_IN, + Q0_CLK0_GTREFCLK_PAD_P_IN => Q0_CLK0_GTREFCLK_PAD_P_IN, + Q0_CLK0_GTREFCLK_OUT => q0_clk0_refclk_i + + ); +refclk_out <= q0_clk0_refclk_i; --// Modified +sysclk_in_i <= sysclk_in; + +--// Modified + -- common0_i:gtxKintex7FEE80_common + -- generic map + -- ( + -- WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP, + -- SIM_QPLLREFCLK_SEL => "001" + -- ) + -- port map + -- ( + -- QPLLREFCLKSEL_IN => "001", + -- GTREFCLK0_IN => q0_clk0_refclk_i, + -- GTREFCLK1_IN => tied_to_ground_i, + -- QPLLLOCK_OUT => gt0_qplllock_i, + -- QPLLLOCKDETCLK_IN => sysclk_in_i, + -- QPLLOUTCLK_OUT => gt0_qplloutclk_i, + -- QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_i, + -- QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i, + -- QPLLRESET_IN => gt0_qpllreset_t + +-- ); + + common_reset_i:gtxKintex7FEE80_common_reset + generic map + ( + STABLE_CLOCK_PERIOD =>STABLE_CLOCK_PERIOD -- Period of the stable clock driving this state-machine, unit is [ns] + ) + port map + ( + STABLE_CLOCK => sysclk_in_i, --Stable Clock, either a stable clock from the PCB + SOFT_RESET => soft_reset_tx_in, --User Reset, can be pulled any time + COMMON_RESET => commonreset_i --Reset QPLL + ); + + + gtxKintex7FEE80_init_i : gtxKintex7FEE80 + port map + ( + sysclk_in => sysclk_in_i, + soft_reset_tx_in => SOFT_RESET_TX_IN, + soft_reset_rx_in => SOFT_RESET_RX_IN, + dont_reset_on_data_error_in => DONT_RESET_ON_DATA_ERROR_IN, + gt0_tx_mmcm_lock_in => gt0_txmmcm_lock_i, + gt0_tx_mmcm_reset_out => gt0_txmmcm_reset_i, + gt0_tx_fsm_reset_done_out => gt0_tx_fsm_reset_done_out, + gt0_rx_fsm_reset_done_out => gt0_rx_fsm_reset_done_out, + gt0_data_valid_in => gt0_data_valid_in, + + --_____________________________________________________________________ + --_____________________________________________________________________ + --GT0 (X1Y0) + + --------------------------------- CPLL Ports ------------------------------- + gt0_cpllfbclklost_out => gt0_cpllfbclklost_out, + gt0_cplllock_out => gt0_cplllock_out, + gt0_cplllockdetclk_in => sysclk_in_i, + gt0_cpllreset_in => gt0_cpllreset_in, + -------------------------- Channel - Clocking Ports ------------------------ + gt0_gtrefclk0_in => q0_clk0_refclk_i, + gt0_gtrefclk1_in => tied_to_ground_i, + ---------------------------- Channel - DRP Ports -------------------------- + gt0_drpaddr_in => gt0_drpaddr_in, + gt0_drpclk_in => sysclk_in_i, + gt0_drpdi_in => gt0_drpdi_in, + gt0_drpdo_out => gt0_drpdo_out, + gt0_drpen_in => gt0_drpen_in, + gt0_drprdy_out => gt0_drprdy_out, + gt0_drpwe_in => gt0_drpwe_in, + --------------------------- Digital Monitor Ports -------------------------- + gt0_dmonitorout_out => gt0_dmonitorout_out, + --------------------- RX Initialization and Reset Ports -------------------- + gt0_eyescanreset_in => gt0_eyescanreset_in, + gt0_rxuserrdy_in => gt0_rxuserrdy_in, + -------------------------- RX Margin Analysis Ports ------------------------ + gt0_eyescandataerror_out => gt0_eyescandataerror_out, + gt0_eyescantrigger_in => gt0_eyescantrigger_in, + ------------------------- Receive Ports - CDR Ports ------------------------ + GT0_RXCDRRESET_IN => GT0_RXCDRRESET_IN, --// Modified + GT0_RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT, --// Modified + ------------------ Receive Ports - FPGA RX Interface Ports ----------------- + gt0_rxusrclk_in => gt0_rxusrclk_i, + gt0_rxusrclk2_in => gt0_rxusrclk2_i, + ------------------ Receive Ports - FPGA RX interface Ports ----------------- + gt0_rxdata_out => gt0_rxdata_out, + ------------------ Receive Ports - RX 8B/10B Decoder Ports ----------------- + gt0_rxdisperr_out => gt0_rxdisperr_out, + gt0_rxnotintable_out => gt0_rxnotintable_out, + --------------------------- Receive Ports - RX AFE ------------------------- + gt0_gtxrxp_in => gt0_gtxrxp_in, + ------------------------ Receive Ports - RX AFE Ports ---------------------- + gt0_gtxrxn_in => gt0_gtxrxn_in, + ------------------- Receive Ports - RX Buffer Bypass Ports ----------------- + gt0_rxphmonitor_out => gt0_rxphmonitor_out, + gt0_rxphslipmonitor_out => gt0_rxphslipmonitor_out, + --------------------- Receive Ports - RX Equalizer Ports ------------------- + gt0_rxdfelpmreset_in => gt0_rxdfelpmreset_in, + gt0_rxmonitorout_out => gt0_rxmonitorout_out, + gt0_rxmonitorsel_in => gt0_rxmonitorsel_in, + --------------- Receive Ports - RX Fabric Output Control Ports ------------- + gt0_rxoutclk_out => gt0_rxoutclk_i, + ------------- Receive Ports - RX Initialization and Reset Ports ------------ + gt0_gtrxreset_in => gt0_gtrxreset_in, + gt0_rxpmareset_in => gt0_rxpmareset_in, + ------------------- Receive Ports - RX8B/10B Decoder Ports ----------------- + gt0_rxcharisk_out => gt0_rxcharisk_out, + -------------- Receive Ports -RX Initialization and Reset Ports ------------ + gt0_rxresetdone_out => gt0_rxresetdone_out, + --------------------- TX Initialization and Reset Ports -------------------- + gt0_gttxreset_in => gt0_gttxreset_in, + gt0_txuserrdy_in => gt0_txuserrdy_in, + ------------------ Transmit Ports - FPGA TX Interface Ports ---------------- + gt0_txusrclk_in => gt0_txusrclk_i, + gt0_txusrclk2_in => gt0_txusrclk2_i, + ------------------ Transmit Ports - TX Data Path interface ----------------- + gt0_txdata_in => gt0_txdata_in, + ---------------- Transmit Ports - TX Driver and OOB signaling -------------- + gt0_gtxtxn_out => gt0_gtxtxn_out, + gt0_gtxtxp_out => gt0_gtxtxp_out, + ----------- Transmit Ports - TX Fabric Clock Output Control Ports ---------- + gt0_txoutclk_out => gt0_txoutclk_i, + gt0_txoutclkfabric_out => gt0_txoutclkfabric_out, + gt0_txoutclkpcs_out => gt0_txoutclkpcs_out, + --------------------- Transmit Ports - TX Gearbox Ports -------------------- + gt0_txcharisk_in => gt0_txcharisk_in, + ------------- Transmit Ports - TX Initialization and Reset Ports ----------- + gt0_txresetdone_out => gt0_txresetdone_out, + + + + gt0_qplloutclk_in => gt0_qplloutclk_i, + gt0_qplloutrefclk_in => gt0_qplloutrefclk_i + ); + + + +end RTL; + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/SystemMonitorKintex/SystemMonitorKintex.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/SystemMonitorKintex/SystemMonitorKintex.xci new file mode 100644 index 0000000..892d773 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/SystemMonitorKintex/SystemMonitorKintex.xci @@ -0,0 +1,284 @@ + + + xilinx.com + xci + unknown + 1.0 + + + SystemMonitorKintex + + + 46573 + 22500 + 21845 + 20753 + 39321 + 37355 + 27306 + 25122 + 41287 + 51763 + 43322 + 21190 + 38229 + 44622 + 22937 + 20753 + 0 + 16640 + 1024 + 80 + 0 + VP_VN + 7 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 769230.7692307692 + 2048 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + design + ./ + Default + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + SystemMonitorKintex + 4 + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 1000 + false + false + 32 + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + None + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + true + false + false + SystemMonitorKintex + 32 + 80 + false + true + true + true + true + false + true + true + true + true + false + true + true + true + true + true + false + false + false + false + false + false + VP_VN + 7 + false + ENABLE_DRP + 1 + true + false + false + false + false + Off + design + ./ + Default + false + true + TEMPERATURE + single_channel + 1.0 + 70.0 + 125.0 + 60.0 + 85.0 + Continuous + true + 0.95 + 1.05 + true + 1.75 + 1.89 + 1.15 + 1.25 + 1_2 + true + 0.97 + 1.03 + 1.71 + 1.8 + 0.95 + 1.00 + CONSTANT + simultaneous_sampling + kintex7 + + xc7k160t + fbg484 + VHDL + + MIXED + -1 + C + TRUE + TRUE + IP_Flow + 0 + TRUE + . + + . + 2015.3 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/async_fifo_16x9/async_fifo_16x9.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/async_fifo_16x9/async_fifo_16x9.xci new file mode 100644 index 0000000..a75af03 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/async_fifo_16x9/async_fifo_16x9.xci @@ -0,0 +1,423 @@ + + + xilinx.com + xci + unknown + 1.0 + + + async_fifo_16x9 + + + 100000000 + 100000000 + 100000000 + 100000000 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 4 + BlankString + 9 + 1 + 32 + 64 + 32 + 64 + 2 + 0 + 9 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + kintex7 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + BlankString + 1 + 0 + 0 + 0 + 1 + 0 + 512x36 + 1kx18 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + 0 + 0 + 0 + 0 + 0 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false + false + false + Active_High + 0 + false + Active_High + 1 + false + 4 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + kintex7 + + xc7k160t + fbg484 + VHDL + + MIXED + -1 + C + TRUE + TRUE + IP_Flow + 0 + TRUE + . + + . + 2015.3 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/async_fifo_256x32/async_fifo_256x32.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/async_fifo_256x32/async_fifo_256x32.xci new file mode 100644 index 0000000..66a996c --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/async_fifo_256x32/async_fifo_256x32.xci @@ -0,0 +1,425 @@ + + + xilinx.com + xci + unknown + 1.0 + + + async_fifo_256x32 + + + 100000000 + 100000000 + 100000000 + 100000000 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 8 + BlankString + 32 + 1 + 32 + 64 + 32 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No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 8 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 8 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + kintex7 + + xc7k160t + fbg484 + VHDL + + MIXED + -1 + C + TRUE + TRUE + IP_Flow + 0 + TRUE + . + + . + 2015.3 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/async_fifo_512x32/async_fifo_512x32.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/async_fifo_512x32/async_fifo_512x32.xci new file mode 100644 index 0000000..5fed711 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/async_fifo_512x32/async_fifo_512x32.xci @@ -0,0 +1,423 @@ + + + xilinx.com + xci + unknown + 1.0 + + + async_fifo_512x32 + + + 100000000 + 100000000 + 100000000 + 100000000 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 9 + BlankString + 32 + 1 + 32 + 64 + 32 + 64 + 2 + 0 + 32 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + kintex7 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + BlankString + 1 + 0 + 0 + 0 + 1 + 0 + 512x36 + 1kx18 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + 0 + 0 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false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 32 + 512 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 32 + 512 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 9 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 9 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + kintex7 + + xc7k160t + fbg484 + VHDL + + MIXED + -1 + C + TRUE + TRUE + IP_Flow + 0 + TRUE + . + + . + 2015.3 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/async_progfull448_progempty128_fifo_512x34/async_progfull448_progempty128_fifo_512x34.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/async_progfull448_progempty128_fifo_512x34/async_progfull448_progempty128_fifo_512x34.xci new file mode 100644 index 0000000..b255f47 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/async_progfull448_progempty128_fifo_512x34/async_progfull448_progempty128_fifo_512x34.xci @@ -0,0 +1,429 @@ + + + xilinx.com + xci + unknown + 1.0 + + + async_progfull448_progempty128_fifo_512x34 + + + 100000000 + 100000000 + 100000000 + 100000000 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 9 + BlankString + 34 + 1 + 32 + 64 + 32 + 64 + 2 + 0 + 34 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + kintex7 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + BlankString + 1 + 0 + 0 + 0 + 1 + 0 + 512x36 + 1kx18 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 128 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 129 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 448 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 447 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 9 + 512 + 1 + 9 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 9 + 512 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 9 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + Slave_Interface_Clock_Enable + Common_Clock + async_progfull448_progempty128_fifo_512x34 + 64 + false + 9 + false + false + 0 + 128 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 129 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Block_RAM + 1 + 448 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 447 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 34 + 512 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 34 + 512 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + Single_Programmable_Empty_Threshold_Constant + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + Single_Programmable_Full_Threshold_Constant + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 9 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 9 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + kintex7 + + xc7k160t + fbg484 + VHDL + + MIXED + -1 + C + TRUE + TRUE + IP_Flow + 0 + TRUE + . + + . + 2015.3 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual/aurora_dual.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual/aurora_dual.xci new file mode 100644 index 0000000..59d8fd5 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual/aurora_dual.xci @@ -0,0 +1,243 @@ + + + xilinx.com + xci + unknown + 1.0 + + + aurora_dual + + + false + BL7 + BL8 + none + X0Y0 + X0Y0 + 1 + false + false + 3 + 16 + 8 + Sidebands + 2 + left + 5 + 5 + 1 + xc7k160t + true + false + kintex7 + GTXQ0 + None + X + X + X + X + X + X + X + X + X + X + X + 1 + X + X + X + X + X + X + X + X + X + X + 2 + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + 80.0 + 2 + 20000 + true + IMM + 80000 + 2 + None + 2 + false + TX + false + 2 + right + true + 32 + 2 + 4 + false + false + false + false + fbg484 + -1 + aurora_dual + Duplex + 80.0 + UFC+_Immediate_NFC + 1 + Framing + true + None + false + 7 + false + false + AXI_4_Streaming + Sidebands + X0Y0 + 2 + left + false + true + false + GTXQ0 + None + X + X + X + X + X + X + X + X + X + X + X + 1 + X + X + X + X + X + X + X + X + X + X + 2 + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + 80 + 2 + 2 + 80.000 + none + None + X0Y0 + X0Y0 + right + false + false + false + false + 1 + aurora_dual + 80 + Duplex + UFC+_Immediate_NFC + Framing + false + false + 0 + false + kintex7 + + xc7k160t + fbg484 + VHDL + + MIXED + -1 + C + TRUE + TRUE + IP_Flow + 2 + TRUE + . + + . + 2015.3 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/sim_reset_mgt_model.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_aurora_pkg.vhd similarity index 54% rename from FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/sim_reset_mgt_model.vhd rename to FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_aurora_pkg.vhd index f1ed3db..3ceea68 100644 --- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/sim_reset_mgt_model.vhd +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_aurora_pkg.vhd @@ -1,31 +1,10 @@ --------------------------------------------------------------------------------- --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx --- \ \ \/ Version : 1.12 --- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard --- / / Filename : sim_reset_mgt_model.vhd --- /___/ /\ --- \ \ / \ --- \___\/\___\ --- --- --- Module SIM_RESET_MGT_MODEL --- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard --- --- The Reset On Configuration(ROC) module is part of the UNISIM library --- and is required for emulating the GSR pulse at the beginning of functional --- simulation in order to correctly reset the VHDL MGT smart model.This module --- is required for simulation only. --- --- --- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved. --- +-- (c) Copyright 2008 Xilinx, Inc. All rights reserved. +-- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. --- +-- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as @@ -47,7 +26,7 @@ -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. --- +-- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe @@ -61,43 +40,45 @@ -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. --- +-- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; - ---***************************** Entity Declaration ***************************** - -entity SIM_RESET_MGT_MODEL is -port -( - GSR_IN : in std_logic -); -end SIM_RESET_MGT_MODEL; - -architecture BEHAVIORAL of SIM_RESET_MGT_MODEL is - - ---********************************* Main Body of Code**************************** - -begin - GSR <= GSR_IN; - ------------------------------ ROCBUF Instantiation ----------------------- - -- This component is required for correctly resetting the VHDL GTX component on configuration - -- It is for simulation alone and will be ripped out during synthesis. - U1 : ROCBUF - port map - ( - I => GSR, - O => open - ); - - -end BEHAVIORAL; - +-- PART OF THIS FILE AT ALL TIMES. +-- +-- + +-- +-- AURORA +-- +-- +-- Description: Aurora Package Definition +-- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use STD.TEXTIO.all; + +package AURORA_PKG is + + function std_bool (EXP_IN : in boolean) return std_logic; + +end; + +package body AURORA_PKG is + + function std_bool (EXP_IN : in boolean) return std_logic is + + begin + + if (EXP_IN) then + + return('1'); + + else + + return('0'); + + end if; + + end std_bool; + +end; diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_axi_to_ll_exdes.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_axi_to_ll_exdes.vhd new file mode 100644 index 0000000..78bdc04 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_axi_to_ll_exdes.vhd @@ -0,0 +1,183 @@ +------------------------------------------------------------------------------ +-- (c) Copyright 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- +------------------------------------------------------------------------------ +-- +-- AXI_TO_LL_EXDES +-- +-- +-- Description: This light wrapper/shim convertes Legacy LocalLink interface +-- signals from AXI-4 Stream protocol signals +-- +-- +------------------------------------------------------------------------------/ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_MISC.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +entity aurora_dual_AXI_TO_LL_EXDES is +generic +( + DATA_WIDTH : integer := 16; -- DATA bus width + STRB_WIDTH : integer := 2; -- STROBE bus width + REM_WIDTH : integer := 1; -- REM bus width + USE_UFC_REM : integer := 0 -- UFC REM bus width identifier +); + +port +( + + ---------------------- AXI4-S Interface ------------------------------- + + AXI4_S_IP_TX_TDATA : in std_logic_vector (0 to DATA_WIDTH-1); + AXI4_S_IP_TX_TKEEP : in std_logic_vector (0 to STRB_WIDTH-1); + AXI4_S_IP_TX_TVALID : in std_logic; + AXI4_S_IP_TX_TLAST : in std_logic; + AXI4_S_OP_TX_TREADY : out std_logic; + + ---------------------- LocalLink Interface ---------------------------- + LL_OP_DATA : out std_logic_vector (0 to DATA_WIDTH-1); + LL_OP_REM : out std_logic_vector (0 to REM_WIDTH -1); + LL_OP_SRC_RDY_N : out std_logic; + LL_OP_SOF_N : out std_logic; + LL_OP_EOF_N : out std_logic; + LL_IP_DST_RDY_N : in std_logic; + + ---------------------- System Interface ---------------------------- + USER_CLK : in std_logic; + RESET : in std_logic; + CHANNEL_UP : in std_logic + +); + +end aurora_dual_AXI_TO_LL_EXDES; + +architecture BEHAVIORAL of aurora_dual_AXI_TO_LL_EXDES is + attribute core_generation_info : string; +attribute core_generation_info of BEHAVIORAL : architecture is "aurora_dual,aurora_8b10b_v11_0_2,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=2,c_column_used=left,c_gt_clock_1=GTXQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=2,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=40000,c_nfc=true,c_nfc_mode=IMM,c_refclk_frequency=80000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC+_Immediate_NFC,interface_mode=Framing,dataflow_config=Duplex}"; + +--***********************************Parameter Declarations*************************** + + constant DLY : time := 1 ns; + + signal new_pkt_r : std_logic; + signal new_pkt : std_logic; + signal temp_cond : std_logic; + signal ll_op_sof : std_logic; + signal ll_ip_dst_rdy : std_logic; + signal AXI4_S_IP_TX_TKEEP_i : std_logic_vector(0 to STRB_WIDTH-1); + +begin + +--*********************************Main Body of Code********************************** + + + + ll_ip_dst_rdy <= not LL_IP_DST_RDY_N; + + + process(USER_CLK) + begin + if(USER_CLK'event and USER_CLK='1') then + LL_OP_DATA <= AXI4_S_IP_TX_TDATA; + end if; + end process; + + + AXI4_S_IP_TX_TKEEP_i <= AXI4_S_IP_TX_TKEEP; + + + + + process(USER_CLK) + begin + if(USER_CLK'event and USER_CLK='1') then + LL_OP_SRC_RDY_N <= not AXI4_S_IP_TX_TVALID; + LL_OP_EOF_N <= not AXI4_S_IP_TX_TLAST; + end if; + end process; + process(USER_CLK) + begin + if(USER_CLK'event and USER_CLK='1') then + LL_OP_REM <= ("0" & AXI4_S_IP_TX_TKEEP_i(0)) + ("0" & AXI4_S_IP_TX_TKEEP_i(1)) + ("0" & AXI4_S_IP_TX_TKEEP_i(2)) + ("0" & AXI4_S_IP_TX_TKEEP_i(3)) - '1'; + end if; + end process; + new_pkt <= '0' when ((AXI4_S_IP_TX_TVALID AND ll_ip_dst_rdy AND AXI4_S_IP_TX_TLAST) = '1') else + '1' when ((AXI4_S_IP_TX_TVALID AND ll_ip_dst_rdy AND not AXI4_S_IP_TX_TLAST) = '1') else + new_pkt_r; + + temp_cond <= '0' when (new_pkt_r = '1') else + '1'; + ll_op_sof <= temp_cond when ((AXI4_S_IP_TX_TVALID AND ll_ip_dst_rdy AND AXI4_S_IP_TX_TLAST) = '1') else + (new_pkt and (not new_pkt_r)); + + process(USER_CLK) + begin + if(USER_CLK'event and USER_CLK='1') then + LL_OP_SOF_N <= not ll_op_sof; + end if; + end process; + + process(USER_CLK) + begin + if(USER_CLK'event and USER_CLK='1') then + if(RESET = '1') then + new_pkt_r <= '0' after DLY; + elsif(CHANNEL_UP = '1') then + new_pkt_r <= new_pkt after DLY; + else + new_pkt_r <= '0' after DLY; + end if; + end if; + end process; + + -- Assign output from temp signal + AXI4_S_OP_TX_TREADY <= ll_ip_dst_rdy; + +end BEHAVIORAL; diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_cdc_sync_exdes.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_cdc_sync_exdes.vhd new file mode 100644 index 0000000..7836bcb --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_cdc_sync_exdes.vhd @@ -0,0 +1,741 @@ +------------------------------------------------------------------------------/ +-- (c) Copyright 2013 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- +-------------------------------------------------------------------------------- + +--Generic Help +--C_CDC_TYPE : Defines the type of CDC needed +-- 0 means pulse synchronizer. Used to transfer one clock pulse +-- from prmry domain to scndry domain. +-- 1 means level synchronizer. Used to transfer level signal. +-- 2 means level synchronizer with ack. Used to transfer level +-- signal. Input signal should change only when prmry_ack is detected +-- +--C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal +-- Set to 0 when incoming signal is purely floped signal. +-- +--C_RESET_STATE : Generally sync flops need not have resets. However, in some cases +-- it might be needed. +-- 0 means reset not needed for sync flops +-- 1 means reset needed for sync flops. i +-- In this case prmry_resetn should be in prmry clock, +-- while scndry_reset should be in scndry clock. +-- +--C_SINGLE_BIT : CDC should normally be done for single bit signals only. +-- However, based on design buses can also be CDC'ed. +-- 0 means it is a bus. In this case input be connected to prmry_vect_in. +-- Output is on scndry_vect_out. +-- 1 means it is a single bit. In this case input be connected to prmry_in. +-- Output is on scndry_out. +-- +--C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1 +-- +--C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6. +-- Value of 0, 1 is allowed only for level CDC. +-- Min value for Pulse CDC is 2 +-- +--Whenever this file is used following XDC constraint has to be added + +-- set_false_path -to [get_pins -hier *cdc_to*] + + +--IO Ports +-- +-- prmry_aclk : clock of originating domain (source domain) +-- prmry_resetn : sync reset of originating clock domain (source domain) +-- prmry_in : input signal bit. This should be a pure flop output without +-- any combi logic. This is source. +-- prmry_vect_in : bus signal. From Source domain. +-- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain. +-- Used only when C_CDC_TYPE = 2 +-- scndry_aclk : destination clock. +-- scndry_resetn : sync reset of destination domain +-- scndry_out : sync'ed output in destination domain. Single bit. +-- scndry_vect_out : sync'ed output in destination domain. bus. + + + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_misc.all; + + + +entity aurora_dual_cdc_sync_exdes is + generic ( + C_CDC_TYPE : integer range 0 to 2 := 1 ; + -- 0 is pulse synch + -- 1 is level synch + -- 2 is ack based level sync + C_RESET_STATE : integer range 0 to 1 := 0 ; + -- 0 is reset not needed + -- 1 is reset needed + C_SINGLE_BIT : integer range 0 to 1 := 1 ; + -- 0 is bus input + -- 1 is single bit input + C_FLOP_INPUT : integer range 0 to 1 := 0 ; + C_VECTOR_WIDTH : integer range 0 to 32 := 32 ; + C_MTBF_STAGES : integer range 0 to 6 := 2 + -- Vector Data witdth + ); + + port ( + prmry_aclk : in std_logic ; -- + prmry_resetn : in std_logic ; -- + prmry_in : in std_logic ; -- + prmry_vect_in : in std_logic_vector -- + (C_VECTOR_WIDTH - 1 downto 0) ; -- + prmry_ack : out std_logic ; + -- + scndry_aclk : in std_logic ; -- + scndry_resetn : in std_logic ; -- + -- + -- Primary to Secondary Clock Crossing -- + scndry_out : out std_logic ; -- + -- + scndry_vect_out : out std_logic_vector -- + (C_VECTOR_WIDTH - 1 downto 0) -- + + ); + +end aurora_dual_cdc_sync_exdes; + +------------------------------------------------------------------------------- +-- Architecture +------------------------------------------------------------------------------- +architecture implementation of aurora_dual_cdc_sync_exdes is + attribute DowngradeIPIdentifiedWarnings: string; + attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; + +------------------------------------------------------------------------------- +-- Functions +------------------------------------------------------------------------------- + +-- No Functions Declared + +------------------------------------------------------------------------------- +-- Constants Declarations +------------------------------------------------------------------------------- + +-- No Constants Declared + +------------------------------------------------------------------------------- +-- Begin architecture logic +------------------------------------------------------------------------------- +begin +-- Generate PULSE clock domain crossing +GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate + +-- Primary to Secondary +signal s_out_d1_cdc_to : std_logic := '0'; +signal s_out_d2 : std_logic := '0'; +signal s_out_d3 : std_logic := '0'; +signal s_out_d4 : std_logic := '0'; +signal s_out_d5 : std_logic := '0'; +signal s_out_d6 : std_logic := '0'; +signal s_out_d7 : std_logic := '0'; +signal s_out_re : std_logic := '0'; +signal prmry_in_xored : std_logic := '0'; +signal p_in_d1_cdc_from : std_logic := '0'; + + + + ----------------------------------------------------------------------------- + -- ATTRIBUTE Declarations + ----------------------------------------------------------------------------- + -- Prevent x-propagation on clock-domain crossing register + ATTRIBUTE async_reg : STRING; + ATTRIBUTE async_reg OF s_out_d1_cdc_to : SIGNAL IS "true"; + ATTRIBUTE async_reg OF s_out_d2 : SIGNAL IS "true"; + ATTRIBUTE async_reg OF s_out_d3 : SIGNAL IS "true"; + ATTRIBUTE async_reg OF s_out_d4 : SIGNAL IS "true"; + ATTRIBUTE async_reg OF s_out_d5 : SIGNAL IS "true"; + ATTRIBUTE async_reg OF s_out_d6 : SIGNAL IS "true"; + ATTRIBUTE async_reg OF s_out_d7 : SIGNAL IS "true"; + + ATTRIBUTE shift_extract : STRING; + ATTRIBUTE shift_extract OF s_out_d1_cdc_to : SIGNAL IS "no"; + ATTRIBUTE shift_extract OF s_out_d2 : SIGNAL IS "no"; + ATTRIBUTE shift_extract OF s_out_d3 : SIGNAL IS "no"; + ATTRIBUTE shift_extract OF s_out_d4 : SIGNAL IS "no"; + ATTRIBUTE shift_extract OF s_out_d5 : SIGNAL IS "no"; + ATTRIBUTE shift_extract OF s_out_d6 : SIGNAL IS "no"; + ATTRIBUTE shift_extract OF s_out_d7 : SIGNAL IS "no"; + +begin + + --***************************************************************************** + --** Asynchronous Pulse Clock Crossing ** + --** PRIMARY TO SECONDARY OPEN-ENDED ** + --***************************************************************************** + +prmry_in_xored <= prmry_in xor p_in_d1_cdc_from; + + REG_P_IN : process(prmry_aclk) + begin + if(prmry_aclk'EVENT and prmry_aclk ='1')then + if(prmry_resetn = '0' and C_RESET_STATE = 1)then + p_in_d1_cdc_from <= '0'; + else + p_in_d1_cdc_from <= prmry_in_xored; + end if; + end if; + end process REG_P_IN; + + + P_IN_CROSS2SCNDRY : process(scndry_aclk) + begin + if(scndry_aclk'EVENT and scndry_aclk ='1')then + if(scndry_resetn = '0' and C_RESET_STATE = 1)then + s_out_d1_cdc_to <= '0'; + s_out_d2 <= '0'; + s_out_d3 <= '0'; + s_out_d4 <= '0'; + s_out_d5 <= '0'; + s_out_d6 <= '0'; + s_out_d7 <= '0'; + scndry_out <= '0'; + else + s_out_d1_cdc_to <= p_in_d1_cdc_from; + s_out_d2 <= s_out_d1_cdc_to; + s_out_d3 <= s_out_d2; + s_out_d4 <= s_out_d3; + s_out_d5 <= s_out_d4; + s_out_d6 <= s_out_d5; + s_out_d7 <= s_out_d6; + scndry_out <= s_out_re; + end if; + end if; + end process P_IN_CROSS2SCNDRY; + +MTBF_2 : if C_MTBF_STAGES = 2 generate +begin + s_out_re <= s_out_d2 xor s_out_d3; + +end generate MTBF_2; + +MTBF_3 : if C_MTBF_STAGES = 3 generate +begin + s_out_re <= s_out_d3 xor s_out_d4; + +end generate MTBF_3; + +MTBF_4 : if C_MTBF_STAGES = 4 generate +begin + s_out_re <= s_out_d4 xor s_out_d5; + +end generate MTBF_4; + +MTBF_5 : if C_MTBF_STAGES = 5 generate +begin + s_out_re <= s_out_d5 xor s_out_d6; + +end generate MTBF_5; + +MTBF_6 : if C_MTBF_STAGES = 6 generate +begin + s_out_re <= s_out_d6 xor s_out_d7; + +end generate MTBF_6; + + -- Feed secondary pulse out + +end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED; + + +-- Generate LEVEL clock domain crossing with reset state = 0 +GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate +begin +-- Primary to Secondary + +SINGLE_BIT : if C_SINGLE_BIT = 1 generate + +signal p_level_in_d1_cdc_from : std_logic := '0'; +signal p_level_in_int : std_logic := '0'; +signal s_level_out_d1_cdc_to : std_logic := '0'; +signal s_level_out_d2 : std_logic := '0'; +signal s_level_out_d3 : std_logic := '0'; +signal s_level_out_d4 : std_logic := '0'; +signal s_level_out_d5 : std_logic := '0'; +signal s_level_out_d6 : std_logic := '0'; + ----------------------------------------------------------------------------- + -- ATTRIBUTE Declarations + ----------------------------------------------------------------------------- + -- Prevent x-propagation on clock-domain crossing register + ATTRIBUTE async_reg : STRING; + ATTRIBUTE async_reg OF s_level_out_d1_cdc_to : SIGNAL IS "true"; + ATTRIBUTE async_reg OF s_level_out_d2 : SIGNAL IS "true"; + ATTRIBUTE async_reg OF s_level_out_d3 : SIGNAL IS "true"; + ATTRIBUTE async_reg OF s_level_out_d4 : SIGNAL IS "true"; + ATTRIBUTE async_reg OF s_level_out_d5 : SIGNAL IS "true"; + ATTRIBUTE async_reg OF s_level_out_d6 : SIGNAL IS "true"; + + ATTRIBUTE shift_extract : STRING; + ATTRIBUTE shift_extract OF s_level_out_d1_cdc_to : SIGNAL IS "no"; + ATTRIBUTE shift_extract OF s_level_out_d2 : SIGNAL IS "no"; + ATTRIBUTE shift_extract OF s_level_out_d3 : SIGNAL IS "no"; + ATTRIBUTE shift_extract OF s_level_out_d4 : SIGNAL IS "no"; + ATTRIBUTE shift_extract OF s_level_out_d5 : SIGNAL IS "no"; + ATTRIBUTE shift_extract OF s_level_out_d6 : SIGNAL IS "no"; + + ATTRIBUTE keep : STRING; + ATTRIBUTE keep OF p_level_in_d1_cdc_from : SIGNAL IS "true"; +begin + + --***************************************************************************** + --** Asynchronous Level Clock Crossing ** + --** PRIMARY TO SECONDARY ** + --***************************************************************************** + -- register is scndry to provide clean ff output to clock crossing logic + +INPUT_FLOP : if C_FLOP_INPUT = 1 generate +begin + + REG_PLEVEL_IN : process(prmry_aclk) + begin + if(prmry_aclk'EVENT and prmry_aclk ='1')then + if(prmry_resetn = '0' and C_RESET_STATE = 1)then + p_level_in_d1_cdc_from <= '0'; + else + p_level_in_d1_cdc_from <= prmry_in; + end if; + end if; + end process REG_PLEVEL_IN; + + p_level_in_int <= p_level_in_d1_cdc_from; + +end generate INPUT_FLOP; + + +NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate +begin + + p_level_in_int <= prmry_in; + +end generate NO_INPUT_FLOP; + + CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) + begin + if(scndry_aclk'EVENT and scndry_aclk ='1')then + if(scndry_resetn = '0' and C_RESET_STATE = 1)then + s_level_out_d1_cdc_to <= '0'; + s_level_out_d2 <= '0'; + s_level_out_d3 <= '0'; + s_level_out_d4 <= '0'; + s_level_out_d5 <= '0'; + s_level_out_d6 <= '0'; + else + s_level_out_d1_cdc_to <= p_level_in_int; + s_level_out_d2 <= s_level_out_d1_cdc_to; + s_level_out_d3 <= s_level_out_d2; + s_level_out_d4 <= s_level_out_d3; + s_level_out_d5 <= s_level_out_d4; + s_level_out_d6 <= s_level_out_d5; + end if; + end if; + end process CROSS_PLEVEL_IN2SCNDRY; + + + + +MTBF_L1 : if C_MTBF_STAGES = 1 generate +begin + scndry_out <= s_level_out_d1_cdc_to; + + +end generate MTBF_L1; + +MTBF_L2 : if C_MTBF_STAGES = 2 generate +begin + + scndry_out <= s_level_out_d2; + + +end generate MTBF_L2; + +MTBF_L3 : if C_MTBF_STAGES = 3 generate +begin + + scndry_out <= s_level_out_d3; + + + +end generate MTBF_L3; + +MTBF_L4 : if C_MTBF_STAGES = 4 generate +begin + scndry_out <= s_level_out_d4; + + + +end generate MTBF_L4; + +MTBF_L5 : if C_MTBF_STAGES = 5 generate +begin + + scndry_out <= s_level_out_d5; + + +end generate MTBF_L5; + +MTBF_L6 : if C_MTBF_STAGES = 6 generate +begin + + scndry_out <= s_level_out_d6; + + +end generate MTBF_L6; + +end generate SINGLE_BIT; + + + +MULTI_BIT : if C_SINGLE_BIT = 0 generate + +signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); +signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); + ----------------------------------------------------------------------------- + -- ATTRIBUTE Declarations + ----------------------------------------------------------------------------- + -- Prevent x-propagation on clock-domain crossing register + ATTRIBUTE async_reg : STRING; + ATTRIBUTE async_reg OF s_level_out_bus_d1_cdc_to : SIGNAL IS "true"; + ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true"; + ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true"; + ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true"; + ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true"; + ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true"; + + ATTRIBUTE shift_extract : STRING; + ATTRIBUTE shift_extract OF s_level_out_bus_d1_cdc_to : SIGNAL IS "no"; + ATTRIBUTE shift_extract OF s_level_out_bus_d2 : SIGNAL IS "no"; + ATTRIBUTE shift_extract OF s_level_out_bus_d3 : SIGNAL IS "no"; + ATTRIBUTE shift_extract OF s_level_out_bus_d4 : SIGNAL IS "no"; + ATTRIBUTE shift_extract OF s_level_out_bus_d5 : SIGNAL IS "no"; + ATTRIBUTE shift_extract OF s_level_out_bus_d6 : SIGNAL IS "no"; + +begin + + --***************************************************************************** + --** Asynchronous Level Clock Crossing ** + --** PRIMARY TO SECONDARY ** + --***************************************************************************** + -- register is scndry to provide clean ff output to clock crossing logic +-- REG_PLEVEL_IN : process(prmry_aclk) +-- begin +-- if(prmry_aclk'EVENT and prmry_aclk ='1')then +-- if(prmry_resetn = '0' and C_RESET_STATE = 1)then +-- p_level_in_bus_d1_cdc_from <= (others => '0'); +-- else +-- p_level_in_bus_d1_cdc_from <= prmry_vect_in; +-- end if; +-- end if; +-- end process REG_PLEVEL_IN; + + CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) + begin + if(scndry_aclk'EVENT and scndry_aclk ='1')then + if(scndry_resetn = '0' and C_RESET_STATE = 1)then + s_level_out_bus_d1_cdc_to <= (others => '0'); + s_level_out_bus_d2 <= (others => '0'); + s_level_out_bus_d3 <= (others => '0'); + s_level_out_bus_d4 <= (others => '0'); + s_level_out_bus_d5 <= (others => '0'); + s_level_out_bus_d6 <= (others => '0'); + else + s_level_out_bus_d1_cdc_to <= prmry_vect_in; + s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to; + s_level_out_bus_d3 <= s_level_out_bus_d2; + s_level_out_bus_d4 <= s_level_out_bus_d3; + s_level_out_bus_d5 <= s_level_out_bus_d4; + s_level_out_bus_d6 <= s_level_out_bus_d5; + end if; + end if; + end process CROSS_PLEVEL_IN2SCNDRY; + + + +MTBF_L1 : if C_MTBF_STAGES = 1 generate +begin + + scndry_vect_out <= s_level_out_bus_d1_cdc_to; + + +end generate MTBF_L1; + +MTBF_L2 : if C_MTBF_STAGES = 2 generate +begin + + scndry_vect_out <= s_level_out_bus_d2; + + +end generate MTBF_L2; + +MTBF_L3 : if C_MTBF_STAGES = 3 generate +begin + + scndry_vect_out <= s_level_out_bus_d3; + + + +end generate MTBF_L3; + +MTBF_L4 : if C_MTBF_STAGES = 4 generate +begin + scndry_vect_out <= s_level_out_bus_d4; + + + +end generate MTBF_L4; + +MTBF_L5 : if C_MTBF_STAGES = 5 generate +begin + + scndry_vect_out <= s_level_out_bus_d5; + + +end generate MTBF_L5; + +MTBF_L6 : if C_MTBF_STAGES = 6 generate +begin + + scndry_vect_out <= s_level_out_bus_d6; + + +end generate MTBF_L6; + +end generate MULTI_BIT; + + +end generate GENERATE_LEVEL_P_S_CDC; + + +GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate +-- Primary to Secondary + + +signal p_level_in_d1_cdc_from : std_logic := '0'; +signal p_level_in_int : std_logic := '0'; +signal s_level_out_d1_cdc_to : std_logic := '0'; +signal s_level_out_d2 : std_logic := '0'; +signal s_level_out_d3 : std_logic := '0'; +signal s_level_out_d4 : std_logic := '0'; +signal s_level_out_d5 : std_logic := '0'; +signal s_level_out_d6 : std_logic := '0'; +signal p_level_out_d1_cdc_to : std_logic := '0'; +signal p_level_out_d2 : std_logic := '0'; +signal p_level_out_d3 : std_logic := '0'; +signal p_level_out_d4 : std_logic := '0'; +signal p_level_out_d5 : std_logic := '0'; +signal p_level_out_d6 : std_logic := '0'; +signal p_level_out_d7 : std_logic := '0'; +signal scndry_out_int : std_logic := '0'; +signal prmry_pulse_ack : std_logic := '0'; + ----------------------------------------------------------------------------- + -- ATTRIBUTE Declarations + ----------------------------------------------------------------------------- + -- Prevent x-propagation on clock-domain crossing register + ATTRIBUTE async_reg : STRING; + ATTRIBUTE async_reg OF s_level_out_d1_cdc_to : SIGNAL IS "true"; + ATTRIBUTE async_reg OF s_level_out_d2 : SIGNAL IS "true"; + ATTRIBUTE async_reg OF s_level_out_d3 : SIGNAL IS "true"; + ATTRIBUTE async_reg OF s_level_out_d4 : SIGNAL IS "true"; + ATTRIBUTE async_reg OF s_level_out_d5 : SIGNAL IS "true"; + ATTRIBUTE async_reg OF s_level_out_d6 : SIGNAL IS "true"; + + ATTRIBUTE async_reg OF p_level_out_d1_cdc_to : SIGNAL IS "true"; + ATTRIBUTE async_reg OF p_level_out_d2 : SIGNAL IS "true"; + ATTRIBUTE async_reg OF p_level_out_d3 : SIGNAL IS "true"; + ATTRIBUTE async_reg OF p_level_out_d4 : SIGNAL IS "true"; + ATTRIBUTE async_reg OF p_level_out_d5 : SIGNAL IS "true"; + ATTRIBUTE async_reg OF p_level_out_d6 : SIGNAL IS "true"; + +begin + + --***************************************************************************** + --** Asynchronous Level Clock Crossing ** + --** PRIMARY TO SECONDARY ** + --***************************************************************************** + -- register is scndry to provide clean ff output to clock crossing logic +INPUT_FLOP : if C_FLOP_INPUT = 1 generate +begin + + REG_PLEVEL_IN : process(prmry_aclk) + begin + if(prmry_aclk'EVENT and prmry_aclk ='1')then + if(prmry_resetn = '0' and C_RESET_STATE = 1)then + p_level_in_d1_cdc_from <= '0'; + else + p_level_in_d1_cdc_from <= prmry_in; + end if; + end if; + end process REG_PLEVEL_IN; + + p_level_in_int <= p_level_in_d1_cdc_from; + +end generate INPUT_FLOP; + + +NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate +begin + + p_level_in_int <= prmry_in; + +end generate NO_INPUT_FLOP; + + CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) + begin + if(scndry_aclk'EVENT and scndry_aclk ='1')then + if(scndry_resetn = '0' and C_RESET_STATE = 1)then + s_level_out_d1_cdc_to <= '0'; + s_level_out_d2 <= '0'; + s_level_out_d3 <= '0'; + s_level_out_d4 <= '0'; + s_level_out_d5 <= '0'; + s_level_out_d6 <= '0'; + else + s_level_out_d1_cdc_to <= p_level_in_int; + s_level_out_d2 <= s_level_out_d1_cdc_to; + s_level_out_d3 <= s_level_out_d2; + s_level_out_d4 <= s_level_out_d3; + s_level_out_d5 <= s_level_out_d4; + s_level_out_d6 <= s_level_out_d5; + end if; + end if; + end process CROSS_PLEVEL_IN2SCNDRY; + + + CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk) + begin + if(prmry_aclk'EVENT and prmry_aclk ='1')then + if(prmry_resetn = '0' and C_RESET_STATE = 1)then + p_level_out_d1_cdc_to <= '0'; + p_level_out_d2 <= '0'; + p_level_out_d3 <= '0'; + p_level_out_d4 <= '0'; + p_level_out_d5 <= '0'; + p_level_out_d6 <= '0'; + p_level_out_d7 <= '0'; + prmry_ack <= '0'; + else + p_level_out_d1_cdc_to <= scndry_out_int; + p_level_out_d2 <= p_level_out_d1_cdc_to; + p_level_out_d3 <= p_level_out_d2; + p_level_out_d4 <= p_level_out_d3; + p_level_out_d5 <= p_level_out_d4; + p_level_out_d6 <= p_level_out_d5; + p_level_out_d7 <= p_level_out_d6; + prmry_ack <= prmry_pulse_ack; + end if; + end if; + end process CROSS_PLEVEL_SCNDRY2PRMRY; + + + + +MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate +begin + + scndry_out_int <= s_level_out_d2; + prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2; + + +end generate MTBF_L2; + +MTBF_L3 : if C_MTBF_STAGES = 3 generate +begin + + scndry_out_int <= s_level_out_d3; + prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3; + + + +end generate MTBF_L3; + +MTBF_L4 : if C_MTBF_STAGES = 4 generate +begin + scndry_out_int <= s_level_out_d4; + prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4; + + + +end generate MTBF_L4; + +MTBF_L5 : if C_MTBF_STAGES = 5 generate +begin + + scndry_out_int <= s_level_out_d5; + prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5; + + +end generate MTBF_L5; + +MTBF_L6 : if C_MTBF_STAGES = 6 generate +begin + + scndry_out_int <= s_level_out_d6; + prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6; + + +end generate MTBF_L6; + + scndry_out <= scndry_out_int; + + +end generate GENERATE_LEVEL_ACK_P_S_CDC; + + +end implementation; diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_clock_module.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_clock_module.vhd new file mode 100644 index 0000000..bc4966b --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_clock_module.vhd @@ -0,0 +1,148 @@ +-- (c) Copyright 2008 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- + +-- +-- CLOCK_MODULE +-- +-- +-- +-- Description: A module provided as a convenience for desingners using 4-byte +-- lane Aurora Modules. This module takes the V5 reference clock as +-- input, and produces a fabric clock on a global clock net suitable +-- for driving application logic connected to the Aurora User Interface. +-- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +-- synthesis translate_off +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +-- synthesis translate_on + +entity aurora_dual_CLOCK_MODULE is + + port ( + INIT_CLK_P : in std_logic; + INIT_CLK_N : in std_logic; + INIT_CLK_O : out std_logic; + GT_CLK : in std_logic; + GT_CLK_LOCKED : in std_logic; + USER_CLK : out std_logic; + SYNC_CLK : out std_logic; + PLL_NOT_LOCKED : out std_logic + + ); + +end aurora_dual_CLOCK_MODULE; + +architecture MAPPED of aurora_dual_CLOCK_MODULE is + attribute core_generation_info : string; + attribute core_generation_info of MAPPED : architecture is "aurora_dual,aurora_8b10b_v11_0_2,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=2,c_column_used=left,c_gt_clock_1=GTXQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=2,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=40000,c_nfc=true,c_nfc_mode=IMM,c_refclk_frequency=80000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC+_Immediate_NFC,interface_mode=Framing,dataflow_config=Duplex}"; + + component IBUFDS + port ( + + O : out std_ulogic; + I : in std_ulogic; + IB : in std_ulogic); + + end component; + + +-- External Register Declarations -- + + + component BUFG + + port ( + + O : out std_ulogic; + I : in std_ulogic + + ); + + end component; + + signal user_clk_i : std_logic; + signal INIT_CLK_I : std_logic; + +begin + + + + USER_CLK <= user_clk_i; + SYNC_CLK <= user_clk_i; + PLL_NOT_LOCKED <= not GT_CLK_LOCKED; + + -- The User Clock is distributed on a global clock net. + user_clk_buf_i : BUFG + + port map ( + + I => GT_CLK, + O => user_clk_i + + ); + -- init_clk_ibufg_i : IBUFDS --// Modified + -- port map ( + -- I => INIT_CLK_P, + -- IB => INIT_CLK_N, + -- O => INIT_CLK_I + -- ); + + -- init_clk_buf_i : BUFG + -- port map + -- ( + -- I => INIT_CLK_I, + -- O => INIT_CLK_O + -- ); +INIT_CLK_O <= '0'; --// Modified + +end MAPPED; diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_gt_common_wrapper.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_gt_common_wrapper.vhd new file mode 100644 index 0000000..e639721 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_gt_common_wrapper.vhd @@ -0,0 +1,229 @@ +------------------------------------------------------------------------------/ +-- (c) Copyright 2013 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- +-------------------------------------------------------------------------------- +library IEEE; + use IEEE.numeric_std.all; + use ieee.std_logic_unsigned.all; + use ieee.std_logic_misc.all; + use ieee.std_logic_1164.all; + +library UNISIM; + use UNISIM.Vcomponents.ALL; + +--***************************** Entity Declaration **************************** + +entity aurora_dual_gt_common_wrapper is +generic +( + -- Simulation attributes + WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" -- Set to "TRUE" to speed up sim reset +); +port +( +--____________________________COMMON PORTS ,_______________________________{ + gt_qpllclk_quad1_i : out std_logic; + gt_qpllrefclk_quad1_i : out std_logic; +--____________________________COMMON PORTS ,_______________________________} + ---------------------- Common Block - Ref Clock Ports --------------------- + gt0_gtrefclk0_common_in : in std_logic; + ------------------------- Common Block - QPLL Ports ------------------------ + gt0_qplllock_out : out std_logic; + gt0_qplllockdetclk_in : in std_logic; + gt0_qpllrefclklost_out : out std_logic; + gt0_qpllreset_in : in std_logic +); + +end aurora_dual_gt_common_wrapper; + +architecture STRUCTURE of aurora_dual_gt_common_wrapper is + +--*************************Logic to set Attribute QPLL_FB_DIV***************************** + impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is + begin + if (qpllfbdiv_top = 16) then + return "0000100000"; + elsif (qpllfbdiv_top = 20) then + return "0000110000" ; + elsif (qpllfbdiv_top = 32) then + return "0001100000" ; + elsif (qpllfbdiv_top = 40) then + return "0010000000" ; + elsif (qpllfbdiv_top = 64) then + return "0011100000" ; + elsif (qpllfbdiv_top = 66) then + return "0101000000" ; + elsif (qpllfbdiv_top = 80) then + return "0100100000" ; + elsif (qpllfbdiv_top = 100) then + return "0101110000" ; + else + return "0000000000" ; + end if; + end function; + + impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is + begin + if (qpllfbdiv_top = 16) then + return '1'; + elsif (qpllfbdiv_top = 20) then + return '1' ; + elsif (qpllfbdiv_top = 32) then + return '1' ; + elsif (qpllfbdiv_top = 40) then + return '1' ; + elsif (qpllfbdiv_top = 64) then + return '1' ; + elsif (qpllfbdiv_top = 66) then + return '0' ; + elsif (qpllfbdiv_top = 80) then + return '1' ; + elsif (qpllfbdiv_top = 100) then + return '1' ; + else + return '1' ; + end if; + end function; + + constant QPLL_FBDIV_TOP : integer := 40; + constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP); + constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP); + + -- ground and tied_to_vcc_i signals + signal tied_to_ground_i : std_logic; + signal tied_to_ground_vec_i : std_logic_vector(63 downto 0); + signal tied_to_vcc_i : std_logic; + +--********************************* Main Body of Code************************** + +begin + +--********************************* Main Body of Code************************** + tied_to_ground_i <= '0'; + tied_to_ground_vec_i(63 downto 0) <= (others => '0'); + tied_to_vcc_i <= '1'; + + + --_________________________________________________________________________ + --_________________________________________________________________________ + --_________________________GTXE2_COMMON____________________________________ +gtxe2_common_i : GTXE2_COMMON + generic map + ( + -- Simulation attributes + SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP, + SIM_QPLLREFCLK_SEL => ("001"), + SIM_VERSION => ("4.0"), + + + ------------------COMMON BLOCK Attributes--------------- + BIAS_CFG => (x"0000040000001000"), + COMMON_CFG => (x"00000000"), + QPLL_CFG => (x"06801C1"), + QPLL_CLKOUT_CFG => ("0000"), + QPLL_COARSE_FREQ_OVRD => ("010000"), + QPLL_COARSE_FREQ_OVRD_EN => ('0'), + QPLL_CP => ("0000011111"), + QPLL_CP_MONITOR_EN => ('0'), + QPLL_DMONITOR_SEL => ('0'), + QPLL_FBDIV => (QPLL_FBDIV_IN), + QPLL_FBDIV_MONITOR_EN => ('0'), + QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO), + QPLL_INIT_CFG => (x"000006"), + QPLL_LOCK_CFG => (x"21E8"), + QPLL_LPF => ("1111"), + QPLL_REFCLK_DIV => (1) + + + ) + port map + ( + ------------- Common Block - Dynamic Reconfiguration Port (DRP) ----------- + DRPADDR => tied_to_ground_vec_i(7 downto 0), + DRPCLK => tied_to_ground_i, + DRPDI => tied_to_ground_vec_i(15 downto 0), + DRPDO => open, + DRPEN => tied_to_ground_i, + DRPRDY => open, + DRPWE => tied_to_ground_i, + ---------------------- Common Block - Ref Clock Ports --------------------- + GTGREFCLK => tied_to_ground_i, + GTNORTHREFCLK0 => tied_to_ground_i, + GTNORTHREFCLK1 => tied_to_ground_i, + GTREFCLK0 => gt0_gtrefclk0_common_in, + GTREFCLK1 => tied_to_ground_i, + GTSOUTHREFCLK0 => tied_to_ground_i, + GTSOUTHREFCLK1 => tied_to_ground_i, + ------------------------- Common Block - QPLL Ports ------------------------ + QPLLDMONITOR => open, + QPLLFBCLKLOST => open, + QPLLLOCK => gt0_qplllock_out, + QPLLLOCKDETCLK => gt0_qplllockdetclk_in, + QPLLLOCKEN => tied_to_vcc_i, + QPLLOUTCLK => gt_qpllclk_quad1_i, + QPLLOUTREFCLK => gt_qpllrefclk_quad1_i, + QPLLOUTRESET => tied_to_ground_i, + QPLLPD => tied_to_vcc_i, + QPLLREFCLKLOST => gt0_qpllrefclklost_out, + QPLLREFCLKSEL => "001", + QPLLRESET => gt0_qpllreset_in, + QPLLRSVD1 => "0000000000000000", + QPLLRSVD2 => "11111", + REFCLKOUTMONITOR => open, + ----------------------------- Common Block Ports --------------------------- + BGBYPASSB => tied_to_vcc_i, + BGMONITORENB => tied_to_vcc_i, + BGPDB => tied_to_vcc_i, + BGRCALOVRD => "11111", + PMARSVD => "00000000", + RCALENB => tied_to_vcc_i + + ); + +end STRUCTURE; + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_ll_to_axi_exdes.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_ll_to_axi_exdes.vhd new file mode 100644 index 0000000..f7af7a8 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_ll_to_axi_exdes.vhd @@ -0,0 +1,140 @@ +------------------------------------------------------------------------------ +-- (c) Copyright 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- +------------------------------------------------------------------------------ +-- +-- LL_TO_AXI_EXDES +-- +-- +-- Description: This light wrapper/shim convertes Legacy LocalLink interface +-- signals from AXI-4 Stream protocol signals +-- +-- +------------------------------------------------------------------------------/ +library IEEE; +use IEEE.numeric_std.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_misc.all; +use ieee.std_logic_1164.all; + +entity aurora_dual_LL_TO_AXI_EXDES is +generic +( + DATA_WIDTH : integer := 16; -- DATA bus width + STRB_WIDTH : integer := 2; -- STROBE bus width + USE_UFC_REM : integer := 0; -- UFC REM bus width identifier + USE_4_NFC : integer := 0; -- 0 => PDU, 1 => NFC, 2 => UFC + REM_WIDTH : integer := 1 -- REM bus width +); + +port +( + + ---------------------- AXI4-S Interface ------------------------------- + AXI4_S_OP_TDATA : out std_logic_vector (0 to DATA_WIDTH-1); + AXI4_S_OP_TKEEP : out std_logic_vector (0 to STRB_WIDTH-1); + AXI4_S_OP_TVALID : out std_logic; + AXI4_S_OP_TLAST : out std_logic; + AXI4_S_IP_TREADY : in std_logic; + + ---------------------- LocalLink Interface ---------------------------- + LL_IP_DATA : in std_logic_vector (0 to DATA_WIDTH-1); + LL_IP_REM : in std_logic_vector (0 to REM_WIDTH-1); + LL_IP_SRC_RDY_N : in std_logic; + LL_IP_SOF_N : in std_logic; + LL_IP_EOF_N : in std_logic; + LL_OP_DST_RDY_N : out std_logic + +); + +end aurora_dual_LL_TO_AXI_EXDES; + +architecture BEHAVIORAL of aurora_dual_LL_TO_AXI_EXDES is + attribute core_generation_info : string; +attribute core_generation_info of BEHAVIORAL : architecture is "aurora_dual,aurora_8b10b_v11_0_2,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=2,c_column_used=left,c_gt_clock_1=GTXQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=2,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=40000,c_nfc=true,c_nfc_mode=IMM,c_refclk_frequency=80000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC+_Immediate_NFC,interface_mode=Framing,dataflow_config=Duplex}"; + +--***********************************Parameter Declarations*************************** + + constant DLY : time := 1 ns; + signal ll_ip_rem_inc_shift : std_logic_vector(0 to STRB_WIDTH-1); + signal rem_int : integer range 0 to 4; + signal ufc_rem_int : integer range 0 to 16; +signal AXI4_S_OP_TKEEP_i : std_logic_vector(0 to STRB_WIDTH-1); +begin + +--*********************************Main Body of Code********************************** + + + AXI4_S_OP_TDATA <= LL_IP_DATA; + + + AXI4_S_OP_TKEEP <= AXI4_S_OP_TKEEP_i ; + + + + + +pdu_rem : if USE_UFC_REM = 0 generate + rem_int <= TO_INTEGER(unsigned (LL_IP_REM + '1')); +ll_ip_rem_inc_shift <= to_stdlogicvector("1111" srl rem_int); +AXI4_S_OP_TKEEP_i <= "1111" when (LL_IP_REM = "11") else + (not ll_ip_rem_inc_shift); +end generate pdu_rem; + +ufc_rem : if USE_UFC_REM = 1 generate + ufc_rem_int <= TO_INTEGER(unsigned (LL_IP_REM + '1')); +ll_ip_rem_inc_shift <= to_stdlogicvector("1111" srl ufc_rem_int); +AXI4_S_OP_TKEEP_i <= "1111" when (LL_IP_REM = "11") else + (not ll_ip_rem_inc_shift); +end generate ufc_rem; + + AXI4_S_OP_TVALID <= not LL_IP_SRC_RDY_N; + AXI4_S_OP_TLAST <= not LL_IP_EOF_N; + LL_OP_DST_RDY_N <= not AXI4_S_IP_TREADY; + +end BEHAVIORAL; diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_module.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_module.vhd new file mode 100644 index 0000000..3fc835f --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_module.vhd @@ -0,0 +1,877 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_MISC.all; +USE ieee.std_logic_unsigned.all ; +USE ieee.std_logic_arith.all ; +use WORK.AURORA_PKG.all; + +-- synthesis translate_off +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +-- synthesis translate_on + +entity aurora_dual_module is + port ( + stable_clock : in std_logic; -- 80MHz + reset : in std_logic; + user_clock : out std_logic; + tx_data : in std_logic_vector(31 downto 0); + tx_first : in std_logic; + tx_last : in std_logic; + tx_write : in std_logic; + tx_allowed : out std_logic; + tx_inpipe : in std_logic; + rx_data : out std_logic_vector(31 downto 0); + rx_first : out std_logic; + rx_last : out std_logic; + rx_write : out std_logic; + rx_almostfull : in std_logic; + rx_inpipe : out std_logic; + locked : out std_logic; + error : out std_logic; + RXP : in std_logic_vector(0 to 1); + RXN : in std_logic_vector(0 to 1); + TXP : out std_logic_vector(0 to 1); + TXN : out std_logic_vector(0 to 1); + GTXQ0_P : in std_logic; + GTXQ0_N : in std_logic; + gt0_refclk_in : in std_logic; + gt0_qplllock_in : in std_logic; + gt0_qpllrefclklost_in : in std_logic; + gt0_qpllreset_out : out std_logic; + GT_QPLLOUTCLK_IN : in std_logic; + GT_QPLLOUTREFCLK_IN : in std_logic + ); +end aurora_dual_module; + +architecture MAPPED of aurora_dual_module is + attribute DowngradeIPIdentifiedWarnings: string; + attribute DowngradeIPIdentifiedWarnings of MAPPED : architecture is "yes"; + attribute core_generation_info : string; + attribute core_generation_info of MAPPED : architecture is "aurora_dual,aurora_8b10b_v11_0_2,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=2,c_column_used=left,c_gt_clock_1=GTXQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=2,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=40000,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=80000,c_simplex=false,c_simplex_mode=TX,c_stream=true,c_ufc=false,flow_mode=None,interface_mode=Streaming,dataflow_config=Duplex}"; + +-- Parameter Declarations -- + + constant DLY : time := 1 ns; + +-- External Register Declarations -- + + signal HARD_ERR_Buffer : std_logic; + signal SOFT_ERR_Buffer : std_logic; +signal LANE_UP_Buffer : std_logic_vector(0 to 1); + signal CHANNEL_UP_Buffer : std_logic; +signal TXP_Buffer : std_logic_vector(0 to 1); +signal TXN_Buffer : std_logic_vector(0 to 1); + +-- Internal Register Declarations -- + + signal gt_reset_i : std_logic; + signal system_reset_i : std_logic; + signal sysreset_vio_i : std_logic; + signal sysreset_i : std_logic; + signal gtreset_vio_i : std_logic; + signal gtreset_vio_o : std_logic; + signal loopback_vio_i : std_logic_vector(2 downto 0); + signal loopback_vio_o : std_logic_vector(2 downto 0); + +-- Wire Declarations -- + + -- Stream TX Interface + +signal tx_d_i : std_logic_vector(0 to 31); +signal tx_rem_i : std_logic_vector(0 to 1); + signal tx_src_rdy_n_i : std_logic; + signal tx_sof_n_i : std_logic; + signal tx_eof_n_i : std_logic; + + signal tx_dst_rdy_n_i : std_logic; + + -- LocalLink RX Interface + +signal rx_d_i : std_logic_vector(0 to 31); +signal rx_rem_i : std_logic_vector(0 to 1) := (others => '1'); + signal rx_src_rdy_n_i : std_logic; + signal rx_sof_n_i : std_logic; + signal rx_eof_n_i : std_logic; + + + -- Native Flow Control TX Interface + + signal nfc_req_n_i : std_logic; + signal nfc_nb_i : std_logic_vector(0 to 3); + signal nfc_ack_n_i : std_logic; + + -- Native Flow Control RX Interface + signal rx_snf_i : std_logic; + signal rx_fc_nb_i : std_logic_vector(0 to 3); + signal rx_fc_nb_int : std_logic_vector(0 to 3); + + -- User Flow Control TX Interface + + signal ufc_tx_req_n_i : std_logic; + signal ufc_tx_ms_i : std_logic_vector(0 to 2); + signal ufc_tx_ack_n_i : std_logic; + + -- User Flow Control RX Inteface + +signal ufc_rx_data_i : std_logic_vector(0 to 31); +signal ufc_rx_rem_i : std_logic_vector(0 to 1); + signal ufc_rx_src_rdy_n_i : std_logic; + signal ufc_rx_sof_n_i : std_logic; + signal ufc_rx_eof_n_i : std_logic; + + + -- Error Detection Interface + + signal hard_err_i : std_logic; + signal soft_err_i : std_logic; + signal frame_err_i : std_logic; + -- Status + + signal channel_up_i : std_logic; + signal channel_up_r : std_logic; + signal channel_up_r_vio : std_logic; +signal lane_up_i : std_logic_vector(0 to 1); + + -- Clock Compensation Control Interface + + signal warn_cc_i : std_logic; + + -- System Interface + + signal pll_not_locked_i : std_logic; + signal pll_not_locked_ila : std_logic; + signal user_clk_i : std_logic; + signal reset_i : std_logic; + signal power_down_i : std_logic; + signal loopback_i : std_logic_vector(2 downto 0); + signal tx_lock_i : std_logic; + signal link_reset_i : std_logic := '0'; + signal link_reset_ila : std_logic := '0'; + signal rx_resetdone_i : std_logic; + signal tx_resetdone_i : std_logic; + signal tx_resetdone_ila : std_logic; + attribute keep : string; + signal init_clk_i : std_logic; + attribute keep of init_clk_i : signal is "true"; +signal daddr_in_i : std_logic_vector(8 downto 0); +signal dclk_in_i : std_logic; +signal den_in_i : std_logic; +signal di_in_i : std_logic_vector(15 downto 0); +signal drdy_out_unused_i : std_logic; +signal drpdo_out_unused_i : std_logic_vector(15 downto 0); +signal dwe_in_i : std_logic; +signal daddr_in_LANE1_i : std_logic_vector(8 downto 0); +signal dclk_in_LANE1_i : std_logic; +signal den_in_LANE1_i : std_logic; +signal di_in_LANE1_i : std_logic_vector(15 downto 0); +signal drdy_out_LANE1_unused_i : std_logic; +signal drpdo_out_LANE1_unused_i : std_logic_vector(15 downto 0); +signal dwe_in_LANE1_i : std_logic; + --Frame check signals +signal tied_to_ground_i : std_logic; +signal tied_to_gnd_vec_i : std_logic_vector(0 to 31); + + -- TX AXI PDU I/F signals +signal tx_data_i : std_logic_vector(0 to 31); + signal tx_tvalid_i : std_logic; + signal tx_tready_i : std_logic; + +signal tx_tkeep_i : std_logic_vector(0 to 3); + signal tx_tlast_i : std_logic; + -- RX AXI PDU I/F signals +signal rx_data_i : std_logic_vector(0 to 31); + signal rx_tvalid_i : std_logic; +signal rx_tkeep_i : std_logic_vector(0 to 3); + signal rx_tlast_i : std_logic; + + -- TX AXI UFC I/F signals +signal axi_ufc_tx_ms_i : std_logic_vector(0 to 2); + signal axi_ufc_tx_req_n_i : std_logic; + signal axi_ufc_tx_ack_n_i : std_logic; + + -- RX AXI UFC I/F signals +signal axi_ufc_rx_data_i : std_logic_vector(0 to 31); +signal axi_ufc_rx_rem_i : std_logic_vector(0 to 3); + signal axi_ufc_rx_src_rdy_n_i : std_logic; + signal axi_ufc_rx_eof_n_i : std_logic; + + -- TX AXI NFC I/F signals + signal axi_nfc_nb_i : std_logic_vector(0 to 3); + signal axi_nfc_req_n_i : std_logic; + signal axi_nfc_ack_n_i : std_logic; + + + + + + --SLACK Registers + signal lane_up_r : std_logic_vector(0 to 1); + signal lane_up_r2 : std_logic_vector(0 to 1); + signal drpclk_i : std_logic; + +-- Component Declarations -- + + component BUFG is + port ( + + O : out std_ulogic; + I : in std_ulogic + + ); + end component; + + + -- AXI Shim modules + component aurora_dual_LL_TO_AXI_EXDES is + generic + ( + DATA_WIDTH : integer := 16; -- DATA bus width + USE_UFC_REM : integer := 0; -- UFC REM bus width identifier + STRB_WIDTH : integer := 2; -- STROBE bus width + USE_4_NFC : integer := 0; -- 0 => PDU, 1 => NFC, 2 => UFC + REM_WIDTH : integer := 1 -- REM bus width + ); + + port + ( + + ---------------------- AXI4-S Interface ------------------------------- + AXI4_S_OP_TDATA : out std_logic_vector (0 to DATA_WIDTH-1); + AXI4_S_OP_TKEEP : out std_logic_vector (0 to STRB_WIDTH-1); + AXI4_S_OP_TVALID : out std_logic; + AXI4_S_OP_TLAST : out std_logic; + AXI4_S_IP_TREADY : in std_logic; + + ---------------------- LocalLink Interface ---------------------------- + LL_IP_DATA : in std_logic_vector (0 to DATA_WIDTH-1); + LL_IP_REM : in std_logic_vector (0 to REM_WIDTH-1); + LL_IP_SRC_RDY_N : in std_logic; + LL_IP_SOF_N : in std_logic; + LL_IP_EOF_N : in std_logic; + LL_OP_DST_RDY_N : out std_logic + + ); + end component; + + component aurora_dual_AXI_TO_LL_EXDES is + generic + ( + DATA_WIDTH : integer := 16; -- DATA bus width + STRB_WIDTH : integer := 2; -- STROBE bus width + REM_WIDTH : integer := 1; -- REM bus width + USE_UFC_REM : integer := 0 -- UFC REM bus width identifier + ); + + port + ( + + ---------------------- AXI4-S Interface ------------------------------- + AXI4_S_IP_TX_TDATA : in std_logic_vector (0 to DATA_WIDTH-1); + AXI4_S_IP_TX_TKEEP : in std_logic_vector (0 to STRB_WIDTH-1); + AXI4_S_IP_TX_TVALID : in std_logic; + AXI4_S_IP_TX_TLAST : in std_logic; + AXI4_S_OP_TX_TREADY : out std_logic; + + ---------------------- LocalLink Interface ---------------------------- + LL_OP_DATA : out std_logic_vector (0 to DATA_WIDTH-1); + LL_OP_REM : out std_logic_vector (0 to REM_WIDTH -1); + LL_OP_SRC_RDY_N : out std_logic; + LL_OP_SOF_N : out std_logic; + LL_OP_EOF_N : out std_logic; + LL_IP_DST_RDY_N : in std_logic; + + ---------------------- System Interface ---------------------------- + USER_CLK : in std_logic; + RESET : in std_logic; + CHANNEL_UP : in std_logic + + ); + end component; + + + + + component aurora_dual_support + port ( + -- TX Stream Interface +s_axi_tx_tdata : in std_logic_vector(0 to 31); + s_axi_tx_tvalid : in std_logic; + s_axi_tx_tready : out std_logic; +s_axi_tx_tkeep : in std_logic_vector(0 to 3); + s_axi_tx_tlast : in std_logic; + + -- RX Stream Interface +m_axi_rx_tdata : out std_logic_vector(0 to 31); +m_axi_rx_tkeep : out std_logic_vector(0 to 3); + m_axi_rx_tvalid : out std_logic; + m_axi_rx_tlast : out std_logic; + -- Native Flow Control TX Interface + s_axi_nfc_req : in std_logic; + s_axi_nfc_nb : in std_logic_vector(0 to 3); + s_axi_nfc_ack : out std_logic; + + -- Native Flow Control RX Interface + m_axi_rx_snf : out std_logic; + m_axi_rx_fc_nb : out std_logic_vector(0 to 3); + -- User Flow Control TX Interface + s_axi_ufc_tx_req : in std_logic; + s_axi_ufc_tx_ms : in std_logic_vector(0 to 2); + s_axi_ufc_tx_ack : out std_logic; + -- User Flow Control RX Inteface + +m_axi_ufc_rx_tdata : out std_logic_vector(0 to 31); +m_axi_ufc_rx_tkeep : out std_logic_vector(0 to 3); + m_axi_ufc_rx_tvalid : out std_logic; + m_axi_ufc_rx_tlast : out std_logic; + -- GT Serial I/O + + rxp : in std_logic_vector(0 to 1); + rxn : in std_logic_vector(0 to 1); + + txp : out std_logic_vector(0 to 1); + txn : out std_logic_vector(0 to 1); + + -- GT Reference Clock Interface + gt_refclk1_p : in std_logic; + gt_refclk1_n : in std_logic; + -- Error Detection Interface + + hard_err : out std_logic; + soft_err : out std_logic; + + frame_err : out std_logic; + + + -- Status + + channel_up : out std_logic; + lane_up : out std_logic_vector(0 to 1); + -- System Interface + + user_clk_out : out std_logic; + sys_reset_out : out std_logic; + gt_reset : in std_logic; + reset : in std_logic; + power_down : in std_logic; + loopback : in std_logic_vector(2 downto 0); + init_clk_p : in std_logic; + init_clk_n : in std_logic; + init_clk_out : out std_logic; + pll_not_locked_out : out std_logic; + tx_resetdone_out : out std_logic; + rx_resetdone_out : out std_logic; + link_reset_out : out std_logic; + +drpclk_in : in std_logic; +drpaddr_in : in std_logic_vector(8 downto 0); +drpdi_in : in std_logic_vector(15 downto 0); +drpdo_out : out std_logic_vector(15 downto 0); +drpen_in : in std_logic; +drprdy_out : out std_logic; +drpwe_in : in std_logic; +drpaddr_in_lane1 : in std_logic_vector(8 downto 0); +drpdi_in_lane1 : in std_logic_vector(15 downto 0); +drpdo_out_lane1 : out std_logic_vector(15 downto 0); +drpen_in_lane1 : in std_logic; +drprdy_out_lane1 : out std_logic; +drpwe_in_lane1 : in std_logic; + + + tx_lock : out std_logic; + sysclk_in : in std_logic; --// Modified + gt0_refclk_in : in std_logic; --// Modified + gt0_qplllock_in : in std_logic; --// Modified + gt0_qpllrefclklost_in : in std_logic; --// Modified + gt0_qpllreset_out : out std_logic; --// Modified + GT_QPLLOUTCLK_IN : in std_logic; --// Modified + GT_QPLLOUTREFCLK_IN : in std_logic --// Modified + ); + + end component; + + + + + +signal tx_allowed_S : std_logic; +signal tx_data_S : std_logic_vector(31 downto 0); +signal insertUFC_word_S : std_logic_vector(31 downto 0); +signal insertUFC_S : std_logic; + +attribute mark_debug : string; + +-- attribute mark_debug of pll_not_locked_i : signal is "true"; +-- attribute mark_debug of power_down_i : signal is "true"; +-- attribute mark_debug of tx_lock_i : signal is "true"; +-- attribute mark_debug of rx_resetdone_i : signal is "true"; +-- attribute mark_debug of tx_resetdone_i : signal is "true"; +-- attribute mark_debug of lane_up_r2 : signal is "true"; +-- attribute mark_debug of hard_err_i : signal is "true"; +-- attribute mark_debug of soft_err_i : signal is "true"; +-- attribute mark_debug of frame_err_i : signal is "true"; +attribute mark_debug of lane_up_i : signal is "true"; +attribute mark_debug of locked : signal is "true"; +-- attribute mark_debug of channel_up_i : signal is "true"; +-- attribute mark_debug of gt0_qplllock_in : signal is "true"; +-- attribute mark_debug of gt0_qpllrefclklost_in : signal is "true"; +-- attribute mark_debug of gt0_qpllreset_out : signal is "true"; +-- attribute mark_debug of system_reset_i : signal is "true"; +-- attribute mark_debug of reset_i : signal is "true"; +-- attribute mark_debug of gtreset_vio_o : signal is "true"; + +attribute mark_debug of tx_allowed_S : signal is "true"; +attribute mark_debug of tx_data_S : signal is "true"; +attribute mark_debug of nfc_req_n_i : signal is "true"; +attribute mark_debug of nfc_ack_n_i : signal is "true"; +attribute mark_debug of nfc_nb_i : signal is "true"; + +attribute mark_debug of tx_write : signal is "true"; +attribute mark_debug of tx_data : signal is "true"; +attribute mark_debug of tx_first : signal is "true"; +attribute mark_debug of tx_last : signal is "true"; +attribute mark_debug of tx_allowed : signal is "true"; +attribute mark_debug of rx_data : signal is "true"; +attribute mark_debug of rx_write : signal is "true"; +attribute mark_debug of rx_first : signal is "true"; +attribute mark_debug of rx_last : signal is "true"; +attribute mark_debug of rx_almostfull : signal is "true"; +attribute mark_debug of rx_rem_i : signal is "true"; + +attribute mark_debug of tx_inpipe : signal is "true"; +attribute mark_debug of rx_inpipe : signal is "true"; +attribute mark_debug of insertUFC_S : signal is "true"; +attribute mark_debug of ufc_tx_req_n_i : signal is "true"; +attribute mark_debug of ufc_tx_ack_n_i : signal is "true"; +attribute mark_debug of ufc_rx_src_rdy_n_i : signal is "true"; +attribute mark_debug of ufc_rx_sof_n_i : signal is "true"; +attribute mark_debug of ufc_rx_eof_n_i : signal is "true"; +attribute mark_debug of ufc_rx_data_i : signal is "true"; + + + +begin + +tx_allowed <= tx_allowed_S; +tx_allowed_S <= '1' when tx_dst_rdy_n_i='0' else '0'; +tx_src_rdy_n_i <= '0' when tx_write='1' else '1'; +reset_i <= reset; +gtreset_vio_o <= reset; +user_clock <= user_clk_i; +rx_write <= '1' when rx_src_rdy_n_i='0' else '0'; +rx_first <= '1' when rx_sof_n_i='0' else '0'; +rx_last <= '1' when rx_eof_n_i='0' else '0'; +loopback_vio_o <= "000"; --// Modified 000 +tx_data_S <= insertUFC_word_S when insertUFC_S='1' else tx_data; +gendata: for i in 0 to 31 generate +tx_d_i(i) <= tx_data_S(i); +rx_data(i) <= rx_d_i(i); +end generate; +tx_rem_i <= (others => '1'); +tx_sof_n_i<= '0' when tx_first='1' else '1'; +tx_eof_n_i<= '0' when tx_last='1' else '1'; +error <= '1' when (HARD_ERR_Buffer='1') or (SOFT_ERR_Buffer='1') else '0'; +locked <= '1' when (LANE_UP_Buffer="11") and (CHANNEL_UP_Buffer='1') else '0'; + +TXP <= TXP_Buffer; +TXN <= TXN_Buffer; +init_clk_i <= stable_clock; +drpclk_i <= stable_clock; +-- drpclk_bufg : BUFG +-- port map + -- ( + -- I => stable_clock, + -- O => drpclk_i + -- ); + +process (user_clk_i) +variable retrycount_V : std_logic_vector(11 downto 0); +begin + if (user_clk_i 'event and user_clk_i = '1') then + if nfc_req_n_i='0' then + retrycount_V := (others => '0'); + if nfc_ack_n_i='0' then + nfc_req_n_i <= '1'; + end if; + elsif (rx_almostfull='1') then + nfc_nb_i <= (others => '1'); + if retrycount_V(retrycount_V'left)='1' then + nfc_req_n_i <= '0'; + else + retrycount_V := retrycount_V+1; + end if; + else + nfc_nb_i <= (others => '0'); + if rx_src_rdy_n_i='0' then + retrycount_V := (others => '0'); + end if; + if retrycount_V(retrycount_V'left)='1' then + nfc_req_n_i <= '0'; + else + retrycount_V := retrycount_V+1; + end if; + end if; + end if; +end process; + +ufc_tx_ms_i <= "001"; +process (user_clk_i) +variable retrycount_V : std_logic_vector(12 downto 0); +variable busy_V : std_logic := '0'; +variable tx_insert_inpipe0_V : std_logic := '0'; +begin + if (user_clk_i 'event and user_clk_i = '1') then + insertUFC_S <= '0'; + if (tx_write='1') and (tx_allowed_S='1') and (tx_first='1') then + busy_V := '1'; + elsif (tx_write='1') and (tx_allowed_S='1') and (tx_last='1') then + busy_V := '0'; + end if; + if ufc_tx_req_n_i='0' then + if ufc_tx_ack_n_i='0' then + ufc_tx_req_n_i <= '1'; + insertUFC_S <= '1'; + end if; + elsif tx_inpipe='0' then + insertUFC_word_S <= x"00000000"; + if (busy_V='0') and (tx_write='0') and (tx_allowed_S='1') then + if tx_insert_inpipe0_V='0' then + retrycount_V := (others => '0'); + ufc_tx_req_n_i <= '0'; + tx_insert_inpipe0_V := '1'; + elsif retrycount_V(retrycount_V'left)='1' then + retrycount_V := (others => '0'); + ufc_tx_req_n_i <= '0'; + tx_insert_inpipe0_V := '1'; + else + retrycount_V := retrycount_V+1; + end if; + end if; + else + insertUFC_word_S <= x"00000001"; + if tx_insert_inpipe0_V='1' then + tx_insert_inpipe0_V := '0'; + retrycount_V := (others => '0'); + ufc_tx_req_n_i <= '0'; + tx_insert_inpipe0_V := '0'; + else + if retrycount_V(retrycount_V'left)='1' then + retrycount_V := (others => '0'); + ufc_tx_req_n_i <= '0'; + tx_insert_inpipe0_V := '0'; + else + retrycount_V := retrycount_V+1; + end if; + end if; + end if; + end if; +end process; + +process (user_clk_i) +begin + if (user_clk_i 'event and user_clk_i = '1') then + if (ufc_rx_src_rdy_n_i='0') and (ufc_rx_sof_n_i='0') and (ufc_rx_eof_n_i='0') then + rx_inpipe <= ufc_rx_data_i(0); + end if; + end if; +end process; + + tied_to_ground_i <= '0'; + + process (user_clk_i) + begin + if (user_clk_i 'event and user_clk_i = '1') then + lane_up_r <= lane_up_i; + lane_up_r2 <= lane_up_r; + end if; + end process; + + + + + + -- Register User I/O -- + + -- Register User Outputs from core. + + process (user_clk_i) + + begin + + if (user_clk_i 'event and user_clk_i = '1') then + + HARD_ERR_Buffer <= hard_err_i; + SOFT_ERR_Buffer <= soft_err_i; + LANE_UP_Buffer <= lane_up_i; + CHANNEL_UP_Buffer <= channel_up_i; + + end if; + + end process; + + -- System Interface + + power_down_i <= '0'; + + process (user_clk_i) + begin + if (user_clk_i 'event and user_clk_i = '1') then + channel_up_r <= channel_up_i; + end if; + end process; + + +daddr_in_i <= (others=>'0'); +dclk_in_i <= '0'; +den_in_i <= '0'; +di_in_i <= (others=>'0'); +dwe_in_i <= '0'; +daddr_in_LANE1_i <= (others=>'0'); +dclk_in_LANE1_i <= '0'; +den_in_LANE1_i <= '0'; +di_in_LANE1_i <= (others=>'0'); +dwe_in_LANE1_i <= '0'; + -- _______________________________ Module Instantiations ________________________-- + + + --_____________________________ RX AXI SHIM _______________________________ + frame_chk_axi_to_ll_pdu_i : aurora_dual_AXI_TO_LL_EXDES + generic map + ( + DATA_WIDTH => 32, + STRB_WIDTH => 4, + REM_WIDTH => 2, + USE_UFC_REM => 0 + ) + port map + ( + -- AXI4-S input signals + AXI4_S_IP_TX_TVALID => rx_tvalid_i, + AXI4_S_OP_TX_TREADY => OPEN, + AXI4_S_IP_TX_TDATA => rx_data_i, + AXI4_S_IP_TX_TKEEP => rx_tkeep_i, + AXI4_S_IP_TX_TLAST => rx_tlast_i, + + -- LocalLink output Interface + LL_OP_DATA => rx_d_i, + LL_OP_SOF_N => rx_sof_n_i, + LL_OP_EOF_N => rx_eof_n_i, + LL_OP_REM => rx_rem_i, + LL_OP_SRC_RDY_N => rx_src_rdy_n_i, + LL_IP_DST_RDY_N => tied_to_ground_i, + + -- System Interface + USER_CLK => user_clk_i, + RESET => system_reset_i, + CHANNEL_UP => channel_up_r + ); + + + frame_chk_axi_to_ll_ufc_i : aurora_dual_AXI_TO_LL_EXDES + generic map + ( + DATA_WIDTH => 32, + STRB_WIDTH => 4, + REM_WIDTH => 2, + USE_UFC_REM => 1 + ) + port map + ( + -- AXI4-S input signals + AXI4_S_IP_TX_TVALID => axi_ufc_rx_src_rdy_n_i, + AXI4_S_OP_TX_TREADY => OPEN, + AXI4_S_IP_TX_TDATA => axi_ufc_rx_data_i, + AXI4_S_IP_TX_TKEEP => axi_ufc_rx_rem_i, + AXI4_S_IP_TX_TLAST => axi_ufc_rx_eof_n_i, + + -- LocalLink output Interface + LL_OP_DATA => ufc_rx_data_i, + LL_OP_SOF_N => ufc_rx_sof_n_i, + LL_OP_EOF_N => ufc_rx_eof_n_i, + LL_OP_REM => ufc_rx_rem_i, + LL_OP_SRC_RDY_N => ufc_rx_src_rdy_n_i, + LL_IP_DST_RDY_N => tied_to_ground_i, + + -- System Interface + USER_CLK => user_clk_i, + RESET => system_reset_i, + CHANNEL_UP => channel_up_r + ); + + --_____________________________ TX AXI SHIM _______________________________ + frame_gen_ll_to_axi_pdu_i : aurora_dual_LL_TO_AXI_EXDES + generic map + ( + DATA_WIDTH => 32, + STRB_WIDTH => 4, + USE_4_NFC => 0, + REM_WIDTH => 2 + ) + + port map + ( + LL_IP_DATA => tx_d_i, + LL_IP_SOF_N => tx_sof_n_i, + LL_IP_EOF_N => tx_eof_n_i, + LL_IP_REM => tx_rem_i, + LL_IP_SRC_RDY_N => tx_src_rdy_n_i, + LL_OP_DST_RDY_N => tx_dst_rdy_n_i, + + AXI4_S_OP_TVALID => tx_tvalid_i, + AXI4_S_OP_TDATA => tx_data_i, + AXI4_S_OP_TKEEP => tx_tkeep_i, + AXI4_S_OP_TLAST => tx_tlast_i, + AXI4_S_IP_TREADY => tx_tready_i + + ); + + frame_gen_ll_to_axi_ufc_i : aurora_dual_LL_TO_AXI_EXDES + generic map + ( + DATA_WIDTH => 3, + USE_UFC_REM => 1, + STRB_WIDTH => 4, + USE_4_NFC => 2, + REM_WIDTH => 2 + ) + + port map + ( + LL_IP_DATA => ufc_tx_ms_i, + LL_IP_SOF_N => tied_to_ground_i, + LL_IP_EOF_N => tied_to_ground_i, +LL_IP_REM => "00", + LL_IP_SRC_RDY_N => ufc_tx_req_n_i, + LL_OP_DST_RDY_N => ufc_tx_ack_n_i, + + -- AXI4-S output signals + AXI4_S_OP_TVALID => axi_ufc_tx_req_n_i, + AXI4_S_OP_TDATA => axi_ufc_tx_ms_i, + AXI4_S_OP_TKEEP => OPEN, + AXI4_S_OP_TLAST => OPEN, + AXI4_S_IP_TREADY => axi_ufc_tx_ack_n_i + ); + + frame_gen_ll_to_axi_nfc_i : aurora_dual_LL_TO_AXI_EXDES + generic map + ( + DATA_WIDTH => 4, + STRB_WIDTH => 4, + USE_4_NFC => 1, + REM_WIDTH => 2 + ) + + port map + ( + LL_IP_DATA => nfc_nb_i, + LL_IP_SOF_N => tied_to_ground_i, + LL_IP_EOF_N => tied_to_ground_i, +LL_IP_REM => "00", + LL_IP_SRC_RDY_N => nfc_req_n_i, + LL_OP_DST_RDY_N => nfc_ack_n_i, + + -- AXI4-S output signals + AXI4_S_OP_TVALID => axi_nfc_req_n_i, + AXI4_S_OP_TDATA => axi_nfc_nb_i, + AXI4_S_OP_TKEEP => OPEN, + AXI4_S_OP_TLAST => OPEN, + AXI4_S_IP_TREADY => axi_nfc_ack_n_i + + ); + + -- Module Instantiations -- + aurora_module_i : aurora_dual_support + port map ( + -- AXI TX Interface + s_axi_tx_tdata => tx_data_i, + s_axi_tx_tkeep => tx_tkeep_i, + s_axi_tx_tvalid => tx_tvalid_i, + s_axi_tx_tlast => tx_tlast_i, + s_axi_tx_tready => tx_tready_i, + + -- AXI RX Interface + m_axi_rx_tdata => rx_data_i, + m_axi_rx_tkeep => rx_tkeep_i, + m_axi_rx_tvalid => rx_tvalid_i, + m_axi_rx_tlast => rx_tlast_i, + + -- Native Flow Control TX Interface + s_axi_nfc_req => axi_nfc_req_n_i, + s_axi_nfc_nb => axi_nfc_nb_i, + s_axi_nfc_ack => axi_nfc_ack_n_i, + + -- Native Flow Control RX Interface + m_axi_rx_snf => rx_snf_i, + m_axi_rx_fc_nb => rx_fc_nb_int, + -- User Flow Control TX Interface + s_axi_ufc_tx_req => axi_ufc_tx_req_n_i, + s_axi_ufc_tx_ms => axi_ufc_tx_ms_i, + s_axi_ufc_tx_ack => axi_ufc_tx_ack_n_i, + -- User Flow Control RX Inteface + m_axi_ufc_rx_tdata => axi_ufc_rx_data_i, + m_axi_ufc_rx_tkeep => axi_ufc_rx_rem_i, + m_axi_ufc_rx_tvalid => axi_ufc_rx_src_rdy_n_i, + m_axi_ufc_rx_tlast => axi_ufc_rx_eof_n_i, + -- GT Serial I/O + rxp => RXP, + rxn => RXN, + txp => TXP_Buffer, + txn => TXN_Buffer, + + -- GT Reference Clock Interface + gt_refclk1_p => GTXQ0_P, + gt_refclk1_n => GTXQ0_N, + + + -- Error Detection Interface + + hard_err => hard_err_i, + soft_err => soft_err_i, + frame_err => frame_err_i, + + -- Status + + channel_up => channel_up_i, + lane_up => lane_up_i, + + -- System Interface + + user_clk_out => user_clk_i, + sys_reset_out => system_reset_i, + reset => reset_i, + power_down => power_down_i, + loopback => loopback_vio_o, + gt_reset => gtreset_vio_o, + init_clk_p => '1', + init_clk_n => '0', + init_clk_out => open, + pll_not_locked_out => pll_not_locked_i, + tx_resetdone_out => tx_resetdone_i, + rx_resetdone_out => rx_resetdone_i, + link_reset_out => link_reset_i, + + +drpclk_in => drpclk_i, +drpaddr_in => daddr_in_i, +drpen_in => den_in_i, +drpdi_in => di_in_i, +drprdy_out => drdy_out_unused_i, +drpdo_out => drpdo_out_unused_i, +drpwe_in => dwe_in_i, +drpaddr_in_lane1 => daddr_in_lane1_i, +drpen_in_lane1 => den_in_lane1_i, +drpdi_in_lane1 => di_in_lane1_i, +drprdy_out_lane1 => drdy_out_lane1_unused_i, +drpdo_out_lane1 => drpdo_out_lane1_unused_i, +drpwe_in_lane1 => dwe_in_lane1_i, + tx_lock => tx_lock_i, + sysclk_in => stable_clock, + gt0_refclk_in => gt0_refclk_in, --// Modified + gt0_qplllock_in => gt0_qplllock_in, --// Modified + gt0_qpllrefclklost_in => gt0_qpllrefclklost_in, --// Modified + gt0_qpllreset_out => gt0_qpllreset_out, --// Modified + GT_QPLLOUTCLK_IN => GT_QPLLOUTCLK_IN, --// Modified + GT_QPLLOUTREFCLK_IN => GT_QPLLOUTREFCLK_IN --// Modified + ); + +end MAPPED; diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_support.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_support.vhd new file mode 100644 index 0000000..92d88b0 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_support.vhd @@ -0,0 +1,587 @@ +------------------------------------------------------------------------------/ +-- (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +------------------------------------------------------------------------------/ + library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_misc.all; + use IEEE.numeric_std.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +-- synthesis translate_off +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +-- synthesis translate_on + +entity aurora_dual_support is +port ( + -- AXI TX Interface + s_axi_tx_tdata : in std_logic_vector(0 to 31); + s_axi_tx_tkeep : in std_logic_vector(0 to 3); + s_axi_tx_tvalid : in std_logic; + s_axi_tx_tready : out std_logic; + s_axi_tx_tlast : in std_logic; + + + -- AXI RX Interface + m_axi_rx_tdata : out std_logic_vector(0 to 31); + m_axi_rx_tkeep : out std_logic_vector(0 to 3); + m_axi_rx_tvalid : out std_logic; + m_axi_rx_tlast : out std_logic; + + -- Native Flow Control TX Interface + s_axi_nfc_req : in std_logic; + + s_axi_nfc_nb : in std_logic_vector(0 to 3); + s_axi_nfc_ack : out std_logic; + + -- Native Flow Control RX Interface + m_axi_rx_snf : out std_logic; + + m_axi_rx_fc_nb : out std_logic_vector(0 to 3); + + -- User Flow Control TX Interface + s_axi_ufc_tx_req : in std_logic; + + s_axi_ufc_tx_ms : in std_logic_vector(0 to 2); + s_axi_ufc_tx_ack : out std_logic; + + + -- User Flow Control RX Inteface + + m_axi_ufc_rx_tdata : out std_logic_vector(0 to 31); + m_axi_ufc_rx_tkeep : out std_logic_vector(0 to 3); + m_axi_ufc_rx_tvalid : out std_logic; + m_axi_ufc_rx_tlast : out std_logic; + + + + -- GT Serial I/O + rxp : in std_logic_vector(0 to 1); + rxn : in std_logic_vector(0 to 1); + + txp : out std_logic_vector(0 to 1); + txn : out std_logic_vector(0 to 1); + + -- GT Reference Clock Interface + gt_refclk1_p : in std_logic; + gt_refclk1_n : in std_logic; + + -- Error Detection Interface + + frame_err : out std_logic; + hard_err : out std_logic; + soft_err : out std_logic; + channel_up : out std_logic; + lane_up : out std_logic_vector(0 to 1); + + + + + -- System Interface + user_clk_out : out std_logic; + reset : in std_logic; + gt_reset : in std_logic; + sys_reset_out : out std_logic; + + power_down : in std_logic; + loopback : in std_logic_vector(2 downto 0); + tx_lock : out std_logic; + init_clk_p : in std_logic; + init_clk_n : in std_logic; + init_clk_out : out std_logic; + tx_resetdone_out : out std_logic; + rx_resetdone_out : out std_logic; + link_reset_out : out std_logic; + + + --DRP Ports + drpclk_in : in std_logic; + drpaddr_in : in std_logic_vector(8 downto 0); + drpdi_in : in std_logic_vector(15 downto 0); + drpdo_out : out std_logic_vector(15 downto 0); + drpen_in : in std_logic; + drprdy_out : out std_logic; + drpwe_in : in std_logic; + drpaddr_in_lane1 : in std_logic_vector(8 downto 0); + drpdi_in_lane1 : in std_logic_vector(15 downto 0); + drpdo_out_lane1 : out std_logic_vector(15 downto 0); + drpen_in_lane1 : in std_logic; + drprdy_out_lane1 : out std_logic; + drpwe_in_lane1 : in std_logic; + + + pll_not_locked_out : out std_logic; + sysclk_in : in std_logic; --// Modified + gt0_refclk_in : in std_logic; --// Modified + gt0_qplllock_in : in std_logic; --// Modified + gt0_qpllrefclklost_in : in std_logic; --// Modified + gt0_qpllreset_out : out std_logic; --// Modified + GT_QPLLOUTCLK_IN : in std_logic; --// Modified + GT_QPLLOUTREFCLK_IN : in std_logic --// Modified + ); + +end aurora_dual_support; + + +architecture STRUCTURE of aurora_dual_support is + attribute core_generation_info : string; + attribute core_generation_info of STRUCTURE : architecture is "aurora_dual,aurora_8b10b_v11_0_2,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=2,c_column_used=left,c_gt_clock_1=GTXQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=2,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=40000,c_nfc=true,c_nfc_mode=IMM,c_refclk_frequency=80000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC+_Immediate_NFC,interface_mode=Framing,dataflow_config=Duplex}"; + + component aurora_dual + port ( + -- TX Stream Interface + S_AXI_TX_TDATA : in std_logic_vector(0 to 31); + S_AXI_TX_TKEEP : in std_logic_vector(0 to 3); + S_AXI_TX_TVALID : in std_logic; + S_AXI_TX_TREADY : out std_logic; + S_AXI_TX_TLAST : in std_logic; + + -- RX Stream Interface + M_AXI_RX_TDATA : out std_logic_vector(0 to 31); + M_AXI_RX_TKEEP : out std_logic_vector(0 to 3); + M_AXI_RX_TVALID : out std_logic; + M_AXI_RX_TLAST : out std_logic; + -- Native Flow Control TX Interface + S_AXI_NFC_TX_TVALID : in std_logic; + S_AXI_NFC_TX_TDATA : in std_logic_vector(0 to 3); + S_AXI_NFC_TX_TREADY : out std_logic; + + -- Native Flow Control RX Interface + M_AXI_NFC_RX_TVALID : out std_logic; + M_AXI_NFC_RX_TDATA : out std_logic_vector(0 to 3); + -- User Flow Control TX Interface + + S_AXI_UFC_TX_TVALID : in std_logic; + S_AXI_UFC_TX_TDATA : in std_logic_vector(0 to 2); + S_AXI_UFC_TX_TREADY : out std_logic; + + -- User Flow Control RX Inteface + M_AXI_UFC_RX_TDATA : out std_logic_vector(0 to 31); + M_AXI_UFC_RX_TKEEP : out std_logic_vector(0 to 3); + M_AXI_UFC_RX_TVALID : out std_logic; + M_AXI_UFC_RX_TLAST : out std_logic; + + -- GT Serial I/O + RXP : in std_logic_vector(0 to 1); + RXN : in std_logic_vector(0 to 1); + TXP : out std_logic_vector(0 to 1); + TXN : out std_logic_vector(0 to 1); + + -- GT Reference Clock Interface + gt_refclk1 : in std_logic; + + -- Error Detection Interface + HARD_ERR : out std_logic; + SOFT_ERR : out std_logic; + + -- Status + CHANNEL_UP : out std_logic; + LANE_UP : out std_logic_vector(0 to 1); + + + FRAME_ERR : out std_logic; + + + + + -- System Interface + + USER_CLK : in std_logic; + SYNC_CLK : in std_logic; + GT_RESET : in std_logic; + RESET : in std_logic; + sys_reset_out : out std_logic; + POWER_DOWN : in std_logic; + LOOPBACK : in std_logic_vector(2 downto 0); + TX_OUT_CLK : out std_logic; + INIT_CLK_IN : in std_logic; + PLL_NOT_LOCKED : in std_logic; + TX_RESETDONE_OUT : out std_logic; + RX_RESETDONE_OUT : out std_logic; + LINK_RESET_OUT : out std_logic; + + drpclk_in : in std_logic; + drpaddr_in : in std_logic_vector(8 downto 0); + drpdi_in : in std_logic_vector(15 downto 0); + drpdo_out : out std_logic_vector(15 downto 0); + drpen_in : in std_logic; + drprdy_out : out std_logic; + drpwe_in : in std_logic; + drpaddr_in_lane1 : in std_logic_vector(8 downto 0); + drpdi_in_lane1 : in std_logic_vector(15 downto 0); + drpdo_out_lane1 : out std_logic_vector(15 downto 0); + drpen_in_lane1 : in std_logic; + drprdy_out_lane1 : out std_logic; + drpwe_in_lane1 : in std_logic; + +--------------------{ +--__________COMMON PORTS _______________________________{ + ------------------------- Common Block - QPLL Ports ------------------------ + gt0_qplllock_in : in std_logic; + gt0_qpllrefclklost_in : in std_logic; + gt0_qpllreset_out : out std_logic; + gt_qpllclk_quad1_in : in std_logic; + gt_qpllrefclk_quad1_in : in std_logic; +--____________________________COMMON PORTS _______________________________} + TX_LOCK : out std_logic + ); + + end component; + + +component aurora_dual_gt_common_wrapper +port +( +--____________________________COMMON PORTS ,_______________________________{ + gt_qpllclk_quad1_i : out std_logic; + gt_qpllrefclk_quad1_i : out std_logic; +--____________________________COMMON PORTS ,_______________________________} + ---------------------- Common Block - Ref Clock Ports --------------------- + gt0_gtrefclk0_common_in : in std_logic; + ------------------------- Common Block - QPLL Ports ------------------------ + gt0_qplllock_out : out std_logic; + gt0_qplllockdetclk_in : in std_logic; + gt0_qpllrefclklost_out : out std_logic; + gt0_qpllreset_in : in std_logic + +); +end component; + + + component IBUFDS_GTE2 + port ( + O : out std_ulogic; + ODIV2 : out std_ulogic; + CEB : in std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); + end component; + + component BUFG + + port ( + + O : out std_ulogic; + I : in std_ulogic + + ); + + end component; + + component aurora_dual_CLOCK_MODULE + port ( + INIT_CLK_P : in std_logic; + INIT_CLK_N : in std_logic; + INIT_CLK_O : out std_logic; + GT_CLK : in std_logic; + GT_CLK_LOCKED : in std_logic; + USER_CLK : out std_logic; + SYNC_CLK : out std_logic; + PLL_NOT_LOCKED : out std_logic + ); + end component; + + component aurora_dual_SUPPORT_RESET_LOGIC + port ( + RESET : in std_logic; + USER_CLK : in std_logic; + INIT_CLK_IN : in std_logic; + GT_RESET_IN : in std_logic; + SYSTEM_RESET : out std_logic; + GT_RESET_OUT : out std_logic + ); + end component; + + component aurora_dual_cdc_sync is + generic ( + C_CDC_TYPE : integer range 0 to 2 := 1 ; + -- 0 is pulse synch + -- 1 is level synch + -- 2 is ack based level sync + C_RESET_STATE : integer range 0 to 1 := 0 ; + -- 0 is reset not needed + -- 1 is reset needed + C_SINGLE_BIT : integer range 0 to 1 := 1 ; + -- 0 is bus input + -- 1 is single bit input + C_FLOP_INPUT : integer range 0 to 1 := 0 ; + C_VECTOR_WIDTH : integer range 0 to 32 := 32 ; + C_MTBF_STAGES : integer range 0 to 6 := 2 + -- Vector Data witdth + ); + + port ( + prmry_aclk : in std_logic ; -- + prmry_resetn : in std_logic ; -- + prmry_in : in std_logic ; -- + prmry_vect_in : in std_logic_vector -- + (C_VECTOR_WIDTH - 1 downto 0) ; -- + prmry_ack : out std_logic ; + -- + scndry_aclk : in std_logic ; -- + scndry_resetn : in std_logic ; -- + -- + -- Primary to Secondary Clock Crossing -- + scndry_out : out std_logic ; -- + -- + scndry_vect_out : out std_logic_vector -- + (C_VECTOR_WIDTH - 1 downto 0) -- + + ); + end component; + +------------ Wire declarations +--------------------{ + ------------------------- Common Block - QPLL Ports ------------------------ +signal gt0_qplllock_i : std_logic; +signal gt0_qpllrefclklost_i : std_logic; +signal gt0_qpllreset_i : std_logic; +signal gt_qpllclk_quad1_i : std_logic; +signal gt_qpllrefclk_quad1_i : std_logic; +--------------------} +signal gt_refclk1_i : std_logic; + +signal tx_out_clk_i : std_logic; +signal user_clk_i : std_logic; +signal sync_clk_i : std_logic; +signal pll_not_locked_i : std_logic; +signal tx_lock_i : std_logic; + +signal init_clk_i : std_logic; +signal tx_resetdone_i : std_logic; +signal rx_resetdone_i : std_logic; +signal link_reset_i : std_logic; +signal system_reset_i : std_logic; +signal gt_reset_i : std_logic; +signal drpclk_i : std_logic; +signal reset_sync_user_clk : std_logic; +signal gt_reset_sync_init_clk : std_logic; +begin + + --*********************************Main Body of Code********************************** + + --// Modified + -- IBUFDS_GTE2_CLK1 : IBUFDS_GTE2 + -- port map ( + -- I => gt_refclk1_p, + -- IB => gt_refclk1_n, + -- CEB => '0', + -- O => gt_refclk1_i, + -- ODIV2 => OPEN); + + + drpclk_i <= drpclk_in; + + -- Instantiate a clock module for clock division + + clock_module_i : aurora_dual_CLOCK_MODULE + port map ( + INIT_CLK_P => init_clk_p, + INIT_CLK_N => init_clk_n, + INIT_CLK_O => open, --// Modified init_clk_i, + GT_CLK => tx_out_clk_i, + GT_CLK_LOCKED => tx_lock_i, + USER_CLK => user_clk_i, + SYNC_CLK => sync_clk_i, + PLL_NOT_LOCKED => pll_not_locked_i + ); + + -- outputs + init_clk_out <= init_clk_i; + user_clk_out <= user_clk_i; + pll_not_locked_out <= pll_not_locked_i; + tx_lock <= tx_lock_i; + tx_resetdone_out <= tx_resetdone_i; + rx_resetdone_out <= rx_resetdone_i; + link_reset_out <= link_reset_i; + + + reset_sync_user_clk <= reset; + gt_reset_sync_init_clk <= gt_reset; + + support_reset_logic_i : aurora_dual_SUPPORT_RESET_LOGIC + port map ( + RESET => reset_sync_user_clk, + USER_CLK => user_clk_i, + INIT_CLK_IN => init_clk_i, + GT_RESET_IN => gt_reset_sync_init_clk, + SYSTEM_RESET => system_reset_i, + GT_RESET_OUT => gt_reset_i + ); + + --// Modified +-- -------- instance of _gt_common_wrapper ---{ +-- gt_common_support : aurora_dual_gt_common_wrapper + +-- port map +-- ( +-- --____________________________COMMON PORTS ,_______________________________{ + -- gt_qpllclk_quad1_i => gt_qpllclk_quad1_i , + -- gt_qpllrefclk_quad1_i => gt_qpllrefclk_quad1_i , + -- ---------------------- Common Block - Ref Clock Ports --------------------- + -- gt0_gtrefclk0_common_in => gt_refclk1_i, + + -- ------------------------- Common Block - QPLL Ports ------------------------ + -- gt0_qplllock_out => gt0_qplllock_i, + -- gt0_qplllockdetclk_in => init_clk_i, + -- gt0_qpllrefclklost_out => gt0_qpllrefclklost_i , + -- gt0_qpllreset_in => gt0_qpllreset_i +-- --____________________________COMMON PORTS ,_______________________________} +-- ); +init_clk_i <= sysclk_in; --// Modified +gt_qpllclk_quad1_i <= GT_QPLLOUTCLK_IN; --// Modified +gt_qpllrefclk_quad1_i <= GT_QPLLOUTREFCLK_IN; --// Modified +gt_refclk1_i <= gt0_refclk_in; --// Modified +gt0_qplllock_i <= gt0_qplllock_in; --// Modified +gt0_qpllrefclklost_i <= gt0_qpllrefclklost_in; --// Modified +gt0_qpllreset_out <= gt0_qpllreset_i; --// Modified +-------- instance of _gt_common_wrapper ---} + + aurora_dual_i : aurora_dual + port map ( + -- AXI TX Interface + s_axi_tx_tdata => s_axi_tx_tdata, + s_axi_tx_tkeep => s_axi_tx_tkeep, + s_axi_tx_tvalid => s_axi_tx_tvalid, + s_axi_tx_tlast => s_axi_tx_tlast, + s_axi_tx_tready => s_axi_tx_tready, + + -- AXI RX Interface + m_axi_rx_tdata => m_axi_rx_tdata, + m_axi_rx_tkeep => m_axi_rx_tkeep, + m_axi_rx_tvalid => m_axi_rx_tvalid, + m_axi_rx_tlast => m_axi_rx_tlast, + -- Native Flow Control TX Interface + s_axi_nfc_tx_tvalid => s_axi_nfc_req, + s_axi_nfc_tx_tdata => s_axi_nfc_nb, + s_axi_nfc_tx_tready => s_axi_nfc_ack, + + -- Native Flow Control RX Interface + m_axi_nfc_rx_tvalid => m_axi_rx_snf, + m_axi_nfc_rx_tdata => m_axi_rx_fc_nb, + + + -- User Flow Control TX Interface + s_axi_ufc_tx_tvalid => s_axi_ufc_tx_req, + s_axi_ufc_tx_tdata => s_axi_ufc_tx_ms, + s_axi_ufc_tx_tready => s_axi_ufc_tx_ack, + + -- User Flow Control RX Inteface + m_axi_ufc_rx_tdata => m_axi_ufc_rx_tdata, + m_axi_ufc_rx_tkeep => m_axi_ufc_rx_tkeep, + m_axi_ufc_rx_tvalid => m_axi_ufc_rx_tvalid, + m_axi_ufc_rx_tlast => m_axi_ufc_rx_tlast, + + -- GT Serial I/O + rxp => rxp, + rxn => rxn, + txp => txp, + txn => txn, + + -- GT Reference Clock Interface + gt_refclk1 => gt_refclk1_i, + -- Error Detection Interface + frame_err => frame_err, + + -- Error Detection Interface + hard_err => hard_err, + soft_err => soft_err, + + -- Status + channel_up => channel_up, + lane_up => lane_up, + + + + + -- System Interface + user_clk => user_clk_i, + sync_clk => sync_clk_i, + reset => system_reset_i, + sys_reset_out => sys_reset_out, + power_down => power_down, + loopback => loopback, + gt_reset => gt_reset_i, + tx_lock => tx_lock_i, + init_clk_in => init_clk_i, + pll_not_locked => pll_not_locked_i, + tx_resetdone_out => tx_resetdone_i, + rx_resetdone_out => rx_resetdone_i, + link_reset_out => link_reset_i, + + + drpclk_in => drpclk_i, + drpaddr_in => drpaddr_in, + drpen_in => drpen_in, + drpdi_in => drpdi_in, + drprdy_out => drprdy_out, + drpdo_out => drpdo_out, + drpwe_in => drpwe_in, + drpaddr_in_lane1 => drpaddr_in_lane1, + drpen_in_lane1 => drpen_in_lane1, + drpdi_in_lane1 => drpdi_in_lane1, + drprdy_out_lane1 => drprdy_out_lane1, + drpdo_out_lane1 => drpdo_out_lane1, + drpwe_in_lane1 => drpwe_in_lane1, +--------------------{ +--__________COMMON PORTS _______________________________{ + ------------------------- Common Block - QPLL Ports ------------------------ + gt0_qplllock_in => gt0_qplllock_i, + gt0_qpllrefclklost_in => gt0_qpllrefclklost_i, + gt0_qpllreset_out => gt0_qpllreset_i, + gt_qpllclk_quad1_in => gt_qpllclk_quad1_i , + gt_qpllrefclk_quad1_in => gt_qpllrefclk_quad1_i , +--____________________________COMMON PORTS ,_______________________________} +--------------------} + tx_out_clk => tx_out_clk_i + + ); + + end STRUCTURE; diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_support_reset_logic.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_support_reset_logic.vhd new file mode 100644 index 0000000..af12dc2 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_support_reset_logic.vhd @@ -0,0 +1,220 @@ + +-- (c) Copyright 2008 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- +--------------------------------------------------------------------------------------------- +-- AURORA RESET LOGIC +-- +-- +-- Description: RESET logic using Debouncer +-- +-- + +library IEEE; +use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_misc.all; +use ieee.std_logic_1164.all; + +-- synthesis translate_off +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +-- synthesis translate_on + +entity aurora_dual_SUPPORT_RESET_LOGIC is + port ( + + RESET : in std_logic; + USER_CLK : in std_logic; + INIT_CLK_IN : in std_logic; + GT_RESET_IN : in std_logic; + SYSTEM_RESET : out std_logic; + GT_RESET_OUT : out std_logic + ); + +end aurora_dual_SUPPORT_RESET_LOGIC; + +architecture MAPPED of aurora_dual_SUPPORT_RESET_LOGIC is + attribute DowngradeIPIdentifiedWarnings: string; + attribute DowngradeIPIdentifiedWarnings of MAPPED : architecture is "yes"; + attribute core_generation_info : string; +attribute core_generation_info of MAPPED : architecture is "aurora_dual,aurora_8b10b_v11_0_2,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=2,c_column_used=left,c_gt_clock_1=GTXQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=2,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=40000,c_nfc=true,c_nfc_mode=IMM,c_refclk_frequency=80000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC+_Immediate_NFC,interface_mode=Framing,dataflow_config=Duplex}"; + +-- Parameter Declarations -- + + constant DLY : time := 1 ns; + +-- Internal Register Declarations -- + + signal reset_debounce_r : std_logic_vector(0 to 3); + signal debounce_gt_rst_r : std_logic_vector(0 to 3) := "0000"; + signal reset_debounce_r2 : std_logic; + signal gt_rst_r : std_logic; + signal tied_to_ground_i : std_logic; + signal gt_rst_sync : std_logic; + + attribute ASYNC_REG : string; + attribute SHIFT_EXTRACT : string; + + attribute ASYNC_REG of debounce_gt_rst_r: signal is "true"; + attribute SHIFT_EXTRACT of debounce_gt_rst_r: signal is "no"; + +-- Component Declarations -- + + component aurora_dual_cdc_sync_exdes is + generic ( + C_CDC_TYPE : integer range 0 to 2 := 1 ; + -- 0 is pulse synch + -- 1 is level synch + -- 2 is ack based level sync + C_RESET_STATE : integer range 0 to 1 := 0 ; + -- 0 is reset not needed + -- 1 is reset needed + C_SINGLE_BIT : integer range 0 to 1 := 1 ; + -- 0 is bus input + -- 1 is single bit input + C_FLOP_INPUT : integer range 0 to 1 := 0 ; + C_VECTOR_WIDTH : integer range 0 to 32 := 32 ; + C_MTBF_STAGES : integer range 0 to 6 := 2 + -- Vector Data witdth + ); + + port ( + prmry_aclk : in std_logic ; -- + prmry_resetn : in std_logic ; -- + prmry_in : in std_logic ; -- + prmry_vect_in : in std_logic_vector -- + (C_VECTOR_WIDTH - 1 downto 0) ; -- + prmry_ack : out std_logic ; + -- + scndry_aclk : in std_logic ; -- + scndry_resetn : in std_logic ; -- + -- + -- Primary to Secondary Clock Crossing -- + scndry_out : out std_logic ; -- + -- + scndry_vect_out : out std_logic_vector -- + (C_VECTOR_WIDTH - 1 downto 0) -- + + ); + + end component; + +begin + + -- Tie off top level constants. + tied_to_ground_i <= '0'; + + -- ___________________________Debouncing circuit for GT_RESET_IN________________________ +-- Reset sync from INIT_CLK to USER_CLK + + gt_rst_r_cdc_sync : aurora_dual_cdc_sync_exdes + generic map + ( + c_cdc_type => 1 , + c_flop_input => 1 , + c_reset_state => 0 , + c_single_bit => 1 , + c_vector_width => 2 , + c_mtbf_stages => 4 + ) + port map + ( + prmry_aclk => INIT_CLK_IN , + prmry_resetn => '1' , + prmry_in => gt_rst_r , + prmry_vect_in => "00" , + scndry_aclk => USER_CLK , + scndry_resetn => '1' , + prmry_ack => open , + scndry_out => gt_rst_sync , + scndry_vect_out => open + ); + + + -- Debounce the GT_RESET_IN signal using the INIT_CLK + process(INIT_CLK_IN) + begin + if(INIT_CLK_IN'event and INIT_CLK_IN='1') then + debounce_gt_rst_r <= GT_RESET_IN & debounce_gt_rst_r(0 to 2); + gt_rst_r <= debounce_gt_rst_r(0) and + debounce_gt_rst_r(1) and + debounce_gt_rst_r(2) and + debounce_gt_rst_r(3); + end if; + end process; + + + GT_RESET_OUT <= gt_rst_r; + + -- _______________________Debounce the Reset signal________________________ -- + + -- Simple Debouncer for Reset button. The debouncer has an + -- asynchronous reset tied to GT_RESET_IN. This is primarily for simulation, to ensure + -- that unknown values are not driven into the reset line + process (USER_CLK, gt_rst_sync) + begin + if (gt_rst_sync = '1') then + reset_debounce_r <= "1111"; + elsif (USER_CLK 'event and USER_CLK = '1') then + reset_debounce_r <= RESET & reset_debounce_r(0 to 2); + end if; + end process; + + process(USER_CLK) + begin + if(USER_CLK'event and USER_CLK='1') then + reset_debounce_r2 <= (reset_debounce_r(0) and + reset_debounce_r(1) and + reset_debounce_r(2) and + reset_debounce_r(3)); + end if; + end process; + + SYSTEM_RESET <= reset_debounce_r2; + +end MAPPED; diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem1x18_xilinx/blockmem1x18_xilinx.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem1x18_xilinx/blockmem1x18_xilinx.xci new file mode 100644 index 0000000..27c9002 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem1x18_xilinx/blockmem1x18_xilinx.xci @@ -0,0 +1,200 @@ + + + xilinx.com + xci + unknown + 1.0 + + + blockmem1x18_xilinx + + + 4096 + 1 + 1 + 1 + 4 + 0 + 1 + 9 + 1 + 1 + 0 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 3.10055 mW + kintex7 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + blockmem1x18_xilinx.mem + no_coe_file_loaded + 0 + 0 + 1 + 0 + 1 + 2 + 2 + 18 + 18 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 2 + 2 + WRITE_FIRST + READ_FIRST + 18 + 18 + kintex7 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + true + 9 + NONE + no_coe_file_loaded + ALL + blockmem1x18_xilinx + false + false + false + false + false + false + false + false + false + Always_Enabled + Use_ENB_Pin + Single_Bit_Error_Injection + false + Native + false + no_mem_loaded + Simple_Dual_Port_RAM + WRITE_FIRST + READ_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 100 + 100 + 0 + 8kx2 + false + false + 18 + 18 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 2 + 18 + 18 + No_ECC + false + false + false + Stand_Alone + kintex7 + + xc7k160t + fbg484 + VHDL + + MIXED + -1 + C + TRUE + TRUE + IP_Flow + 0 + TRUE + . + + . + 2015.3 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem1x96_xilinx/blockmem1x96_xilinx.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem1x96_xilinx/blockmem1x96_xilinx.xci new file mode 100644 index 0000000..b14b2c6 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem1x96_xilinx/blockmem1x96_xilinx.xci @@ -0,0 +1,199 @@ + + + xilinx.com + xci + unknown + 1.0 + + + blockmem1x96_xilinx + + + 4096 + 1 + 1 + 1 + 4 + 0 + 1 + 9 + 1 + 1 + 1 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 10.67465 mW + kintex7 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + blockmem1x96_xilinx.mem + no_coe_file_loaded + 0 + 0 + 1 + 0 + 1 + 2 + 2 + 96 + 96 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 2 + 2 + WRITE_FIRST + READ_FIRST + 96 + 96 + kintex7 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + true + 9 + NONE + no_coe_file_loaded + ALL + blockmem1x96_xilinx + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + false + no_mem_loaded + Simple_Dual_Port_RAM + WRITE_FIRST + READ_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 100 + 100 + 0 + 8kx2 + false + false + 96 + 96 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 2 + 96 + 96 + No_ECC + false + false + false + Stand_Alone + kintex7 + + xc7k160t + fbg484 + VHDL + + MIXED + -1 + C + TRUE + TRUE + IP_Flow + 0 + TRUE + . + + . + 2015.3 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem2x18_xilinx/blockmem2x18_xilinx.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem2x18_xilinx/blockmem2x18_xilinx.xci new file mode 100644 index 0000000..2656cdd --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem2x18_xilinx/blockmem2x18_xilinx.xci @@ -0,0 +1,199 @@ + + + xilinx.com + xci + unknown + 1.0 + + + blockmem2x18_xilinx + + + 4096 + 2 + 2 + 1 + 4 + 0 + 1 + 9 + 1 + 1 + 0 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 3.10055 mW + kintex7 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + blockmem2x18_xilinx.mem + no_coe_file_loaded + 0 + 0 + 1 + 0 + 1 + 4 + 4 + 18 + 18 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 4 + 4 + NO_CHANGE + READ_FIRST + 18 + 18 + kintex7 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + true + 9 + NONE + no_coe_file_loaded + ALL + blockmem2x18_xilinx + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + false + no_mem_loaded + Simple_Dual_Port_RAM + NO_CHANGE + READ_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 100 + 100 + 0 + 8kx2 + false + false + 18 + 18 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 4 + 18 + 18 + No_ECC + false + false + false + Stand_Alone + kintex7 + + xc7k160t + fbg484 + VHDL + + MIXED + -1 + C + TRUE + TRUE + IP_Flow + 0 + TRUE + . + + . + 2015.3 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem2x96_xilinx/blockmem2x96_xilinx.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem2x96_xilinx/blockmem2x96_xilinx.xci new file mode 100644 index 0000000..37bdcfb --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem2x96_xilinx/blockmem2x96_xilinx.xci @@ -0,0 +1,199 @@ + + + xilinx.com + xci + unknown + 1.0 + + + blockmem2x96_xilinx + + + 4096 + 2 + 2 + 1 + 4 + 0 + 1 + 9 + 1 + 1 + 1 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 10.67465 mW + kintex7 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + blockmem2x96_xilinx.mem + no_coe_file_loaded + 0 + 0 + 1 + 0 + 1 + 4 + 4 + 96 + 96 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 4 + 4 + WRITE_FIRST + READ_FIRST + 96 + 96 + kintex7 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + true + 9 + NONE + no_coe_file_loaded + ALL + blockmem2x96_xilinx + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + false + no_mem_loaded + Simple_Dual_Port_RAM + WRITE_FIRST + READ_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 100 + 100 + 0 + 8kx2 + false + false + 96 + 96 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 4 + 96 + 96 + No_ECC + false + false + false + Stand_Alone + kintex7 + + xc7k160t + fbg484 + VHDL + + MIXED + -1 + C + TRUE + TRUE + IP_Flow + 0 + TRUE + . + + . + 2015.3 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem3x18_xilinx/blockmem3x18_xilinx.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem3x18_xilinx/blockmem3x18_xilinx.xci new file mode 100644 index 0000000..c3ca32f --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem3x18_xilinx/blockmem3x18_xilinx.xci @@ -0,0 +1,199 @@ + + + xilinx.com + xci + unknown + 1.0 + + + blockmem3x18_xilinx + + + 4096 + 3 + 3 + 1 + 4 + 0 + 1 + 9 + 1 + 1 + 0 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 3.10055 mW + kintex7 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + blockmem3x18_xilinx.mem + no_coe_file_loaded + 0 + 0 + 1 + 0 + 1 + 8 + 8 + 18 + 18 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 8 + 8 + NO_CHANGE + READ_FIRST + 18 + 18 + kintex7 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + true + 9 + NONE + no_coe_file_loaded + ALL + blockmem3x18_xilinx + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + false + no_mem_loaded + Simple_Dual_Port_RAM + NO_CHANGE + READ_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 100 + 100 + 0 + 8kx2 + false + false + 18 + 18 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 8 + 18 + 18 + No_ECC + false + false + false + Stand_Alone + kintex7 + + xc7k160t + fbg484 + VHDL + + MIXED + -1 + C + TRUE + TRUE + IP_Flow + 0 + TRUE + . + + . + 2015.3 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem3x96_xilinx/blockmem3x96_xilinx.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem3x96_xilinx/blockmem3x96_xilinx.xci new file mode 100644 index 0000000..bd17c6d --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem3x96_xilinx/blockmem3x96_xilinx.xci @@ -0,0 +1,199 @@ + + + xilinx.com + xci + unknown + 1.0 + + + blockmem3x96_xilinx + + + 4096 + 3 + 3 + 1 + 4 + 0 + 1 + 9 + 1 + 1 + 1 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 10.67465 mW + kintex7 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + blockmem3x96_xilinx.mem + no_coe_file_loaded + 0 + 0 + 1 + 0 + 1 + 8 + 8 + 96 + 96 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 8 + 8 + WRITE_FIRST + READ_FIRST + 96 + 96 + kintex7 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + true + 9 + NONE + no_coe_file_loaded + ALL + blockmem3x96_xilinx + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + false + no_mem_loaded + Simple_Dual_Port_RAM + WRITE_FIRST + READ_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 100 + 100 + 0 + 8kx2 + false + false + 96 + 96 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 8 + 96 + 96 + No_ECC + false + false + false + Stand_Alone + kintex7 + + xc7k160t + fbg484 + VHDL + + MIXED + -1 + C + TRUE + TRUE + IP_Flow + 0 + TRUE + . + + . + 2015.3 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem4x18_xilinx/blockmem4x18_xilinx.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem4x18_xilinx/blockmem4x18_xilinx.xci new file mode 100644 index 0000000..8dd9f34 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem4x18_xilinx/blockmem4x18_xilinx.xci @@ -0,0 +1,199 @@ + + + xilinx.com + xci + unknown + 1.0 + + + blockmem4x18_xilinx + + + 4096 + 4 + 4 + 1 + 4 + 0 + 1 + 9 + 1 + 1 + 0 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 3.10055 mW + kintex7 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + blockmem4x18_xilinx.mem + no_coe_file_loaded + 0 + 0 + 1 + 0 + 1 + 16 + 16 + 18 + 18 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 16 + 16 + NO_CHANGE + READ_FIRST + 18 + 18 + kintex7 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + true + 9 + NONE + no_coe_file_loaded + ALL + blockmem4x18_xilinx + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + false + no_mem_loaded + Simple_Dual_Port_RAM + NO_CHANGE + READ_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 100 + 100 + 0 + 8kx2 + false + false + 18 + 18 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 16 + 18 + 18 + No_ECC + false + false + false + Stand_Alone + kintex7 + + xc7k160t + fbg484 + VHDL + + MIXED + -1 + C + TRUE + TRUE + IP_Flow + 0 + TRUE + . + + . + 2015.3 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem5x18_xilinx/blockmem5x18_xilinx.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem5x18_xilinx/blockmem5x18_xilinx.xci new file mode 100644 index 0000000..12aeb40 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem5x18_xilinx/blockmem5x18_xilinx.xci @@ -0,0 +1,199 @@ + + + xilinx.com + xci + unknown + 1.0 + + + blockmem5x18_xilinx + + + 4096 + 5 + 5 + 1 + 4 + 0 + 1 + 9 + 1 + 1 + 0 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 3.10055 mW + kintex7 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + blockmem5x18_xilinx.mem + no_coe_file_loaded + 0 + 0 + 1 + 0 + 1 + 32 + 32 + 18 + 18 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 32 + 32 + NO_CHANGE + READ_FIRST + 18 + 18 + kintex7 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + true + 9 + NONE + no_coe_file_loaded + ALL + blockmem5x18_xilinx + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + false + no_mem_loaded + Simple_Dual_Port_RAM + NO_CHANGE + READ_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 100 + 100 + 0 + 8kx2 + false + false + 18 + 18 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 32 + 18 + 18 + No_ECC + false + false + false + Stand_Alone + kintex7 + + xc7k160t + fbg484 + VHDL + + MIXED + -1 + C + TRUE + TRUE + IP_Flow + 0 + TRUE + . + + . + 2015.3 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem_xilinx/blockmem_xilinx.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem_xilinx/blockmem_xilinx.xci new file mode 100644 index 0000000..11e0a88 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem_xilinx/blockmem_xilinx.xci @@ -0,0 +1,199 @@ + + + xilinx.com + xci + unknown + 1.0 + + + blockmem_xilinx + + + 4096 + 9 + 9 + 1 + 4 + 0 + 1 + 9 + 1 + 1 + 0 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 3.84935 mW + kintex7 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + blockmem_xilinx.mem + no_coe_file_loaded + 0 + 0 + 1 + 0 + 1 + 512 + 512 + 36 + 36 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 512 + 512 + NO_CHANGE + READ_FIRST + 36 + 36 + kintex7 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + true + 9 + NONE + no_coe_file_loaded + ALL + blockmem_xilinx + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + false + no_mem_loaded + Simple_Dual_Port_RAM + NO_CHANGE + READ_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 100 + 100 + 0 + 8kx2 + false + false + 36 + 36 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 512 + 36 + 36 + No_ECC + false + false + false + Stand_Alone + kintex7 + + xc7k160t + fbg484 + VHDL + + MIXED + -1 + C + TRUE + TRUE + IP_Flow + 0 + TRUE + . + + . + 2015.3 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/clock100to200/clock100to200.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/clock100to200/clock100to200.xci new file mode 100644 index 0000000..3cad49e --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/clock100to200/clock100to200.xci @@ -0,0 +1,517 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clock100to200 + + + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 100.0 + BUFG + 50.0 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + BUFG + 50.0 + 200.000 + 0.000 + 50.000 + 200.000 + 0.000 + 1 + 1 + BUFG + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + clk_out1 + clk_out2 + clk_out3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + dout + drdy + dwe + 0 + FDBK_AUTO + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_________100.000____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + OPTIMIZED + 10.000 + 0.000 + FALSE + 10.0 + 10.0 + 10.000 + 0.500 + 0.000 + FALSE + 5 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + ZHOLD + 1 + None + 0.010 + 0.010 + FALSE + 2 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + CLK_OUT1___100.000______0.000______50.0______130.958_____98.575 + CLK_OUT2___200.000______0.000______50.0______114.829_____98.575 + no_CLK_OUT3_output + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + UNKNOWN + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + clk_in1 + MMCM + AUTO + 100.000 + 0.010 + 10.000 + Global_buffer + psclk + psdone + psen + psincdec + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + clock100to200 + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 0.010 + 100.0 + 0.010 + BUFG + 130.958 + 98.575 + 50.000 + 100.000 + 0.000 + 1 + true + BUFG + 114.829 + 98.575 + 50.000 + 200.000 + 0.000 + 1 + true + BUFG + 0.0 + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + clk_out1 + false + clk_out2 + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + clock100to200 + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 10.000 + 0.000 + false + 10.0 + 10.0 + 10.000 + 0.500 + 0.000 + false + 5 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 1 + None + 0.010 + 0.010 + false + 2 + false + false + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + clk_in1 + MMCM + mmcm_adv + 100.000 + 0.010 + 10.000 + Global_buffer + psclk + psdone + psen + psincdec + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + false + false + false + false + false + false + false + true + false + false + false + false + false + false + true + false + false + false + false + false + kintex7 + + xc7k160t + fbg484 + VHDL + + MIXED + -1 + C + TRUE + TRUE + IP_Flow + 0 + TRUE + . + + . + 2015.3 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/clockmodule100to80M/clockmodule100to80M.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/clockmodule100to80M/clockmodule100to80M.xci new file mode 100644 index 0000000..0d23002 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/clockmodule100to80M/clockmodule100to80M.xci @@ -0,0 +1,549 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clockmodule100to80M + + + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 100.0 + BUFG + 50.0 + 40.000 + 0.000 + 50.000 + 40 + 0.00 + 1 + BUFG + 50.0 + 80.000 + 0.000 + 50.000 + 80 + 0.000 + 1 + 1 + BUFG + 50.0 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 1 + BUFG + 50.0 + 200.000 + 0.000 + 50.000 + 200.000 + 0.000 + 1 + 1 + BUFG + 50.0 + 66.667 + 0.000 + 50.000 + 65 + 0.000 + 1 + 1 + BUFG + 50.0 + 160.000 + 0.000 + 50.000 + 160 + 0.000 + 1 + 1 + BUFG + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + clk_out1 + clk_out2 + clk_out3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + dout + drdy + dwe + 0 + FDBK_AUTO + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_________100.000____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + OPTIMIZED + 8.000 + 0.000 + FALSE + 10.0 + 10.0 + 20.000 + 0.500 + 0.000 + FALSE + 10 + 0.500 + 0.000 + FALSE + 8 + 0.500 + 0.000 + FALSE + 4 + 0.500 + 0.000 + FALSE + FALSE + 12 + 0.500 + 0.000 + FALSE + 5 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + ZHOLD + 1 + None + 0.010 + 0.010 + FALSE + 6 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + CLK_OUT1____40.000______0.000______50.0______174.629____114.212 + CLK_OUT2____80.000______0.000______50.0______151.652____114.212 + CLK_OUT3___100.000______0.000______50.0______144.719____114.212 + CLK_OUT4___200.000______0.000______50.0______126.455____114.212 + CLK_OUT5____66.667______0.000______50.0______157.646____114.212 + CLK_OUT6___160.000______0.000______50.0______131.841____114.212 + no_CLK_OUT7_output + 0 + 0 + UNKNOWN + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + clk_in1 + MMCM + AUTO + 100.000 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + clockmodule100to80M + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 0.010 + 100.0 + 0.010 + BUFG + 174.629 + 114.212 + 50.000 + 40 + 0.00 + 1 + true + BUFG + 151.652 + 114.212 + 50.000 + 80 + 0.000 + 1 + true + BUFG + 144.719 + 114.212 + 50.000 + 100.000 + 0.000 + 1 + true + BUFG + 126.455 + 114.212 + 50.000 + 200.000 + 0.000 + 1 + true + BUFG + 157.646 + 114.212 + 50.000 + 65 + 0.000 + 1 + true + BUFG + 131.841 + 114.212 + 50.000 + 160 + 0.000 + 1 + true + BUFG + 0.0 + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + clk_out1 + false + clk_out2 + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + clockmodule100to80M + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 8.000 + 0.000 + false + 10.0 + 10.0 + 20.000 + 0.500 + 0.000 + false + 10 + 0.500 + 0.000 + false + 8 + 0.500 + 0.000 + false + 4 + 0.500 + 0.000 + false + false + 12 + 0.500 + 0.000 + false + 5 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 1 + None + 0.010 + 0.010 + false + 6 + false + false + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + clk_in1 + MMCM + mmcm_adv + 100.000 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + false + false + false + false + false + false + false + true + false + false + true + false + false + false + true + false + true + false + false + false + kintex7 + + xc7k160t + fbg484 + VHDL + + MIXED + -1 + C + TRUE + TRUE + IP_Flow + 0 + TRUE + . + + . + 2015.3 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/clockmodule40Mto80M_1/clockmodule40Mto80M.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/clockmodule40Mto80M_1/clockmodule40Mto80M.xci new file mode 100644 index 0000000..7d50fe6 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/clockmodule40Mto80M_1/clockmodule40Mto80M.xci @@ -0,0 +1,524 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clockmodule40Mto80M + + + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 250.0 + 100.0 + BUFG + 50.0 + 40.000 + 0.000 + 50.000 + 40 + 0.000 + 1 + BUFG + 50.0 + 80.000 + 0.000 + 50.000 + 80 + 0.000 + 1 + 1 + BUFG + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + clk_out1 + clk_out2 + clk_out3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + dout + drdy + dwe + 0 + FDBK_AUTO + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary______________40____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + OPTIMIZED + 24.000 + 0.000 + FALSE + 25.0 + 10.0 + 24.000 + 0.500 + 0.000 + FALSE + 12 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + ZHOLD + 1 + None + 0.010 + 0.010 + FALSE + 2 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + CLK_OUT1____40.000______0.000______50.0______247.096____196.976 + CLK_OUT2____80.000______0.000______50.0______200.412____196.976 + no_CLK_OUT3_output + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + UNKNOWN + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + clk_in1 + MMCM + AUTO + 40 + 0.010 + 10.000 + Global_buffer + psclk + psdone + psen + psincdec + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + clockmodule40Mto80M + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 250.0 + 0.010 + 100.0 + 0.010 + BUFG + 247.096 + 196.976 + 50.000 + 40 + 0.000 + 1 + true + BUFG + 200.412 + 196.976 + 50.000 + 80 + 0.000 + 1 + true + BUFG + 0.0 + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + clk_out1 + false + clk_out2 + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + clockmodule40Mto80M + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 24.000 + 0.000 + false + 25.0 + 10.0 + 24.000 + 0.500 + 0.000 + false + 12 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 1 + None + 0.010 + 0.010 + false + 2 + false + false + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + clk_in1 + MMCM + mmcm_adv + 40 + 0.010 + 10.000 + Global_buffer + psclk + psdone + psen + psincdec + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + false + false + false + false + false + false + false + true + false + false + true + false + false + false + true + false + true + false + false + false + kintex7 + + xc7k160t + fbg484 + VHDL + + MIXED + -1 + C + TRUE + TRUE + IP_Flow + 0 + TRUE + . + + . + 2015.3 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/gtxKintex7FEE80_clockmodule/gtxKintex7FEE80_clockmodule.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/gtxKintex7FEE80_clockmodule/gtxKintex7FEE80_clockmodule.xci new file mode 100644 index 0000000..29a5be7 --- /dev/null +++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/gtxKintex7FEE80_clockmodule/gtxKintex7FEE80_clockmodule.xci @@ -0,0 +1,521 @@ + + + xilinx.com + xci + unknown + 1.0 + + + gtxKintex7FEE80_clockmodule + + + gtxKintex7FEE80_clockmodule + MMCM + mmcm_adv + auto + true + false + true + false + false + false + No_Jitter + 80 + 10.000 + Units_MHz + Units_UI + REL_PRIMARY + false + 100.000 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + UI + 0.010 + 0.010 + 0.010 + 0.010 + 125.0 + 100.0 + true + true + false + false + false + false + false + 2 + false + false + false + false + false + false + false + clk_in1 + clk_out1 + clk_out2 + clk_out3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + daddr + dclk + drdy + dwe + din + dout + den + psclk + psen + psincdec + psdone + 100.000 + 0.000 + 50.000 + 200.000 + 0.000 + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 50.000 + false + false + Global_buffer + BUFG + BUFG + BUFG + BUFG + BUFG + BUFG + BUFG + FDBK_AUTO + SINGLE + clkfb_in + clkfb_in_p + clkfb_in_n + clkfb_out + clkfb_out_p + clkfb_out_n + UNKNOWN + empty + true + empty + true + false + false + false + false + false + false + reset + locked + power_down + CLK_VALID + STATUS + clk_in_sel + input_clk_stopped + clkfb_stopped + CENTER_HIGH + 250 + 0.004 + false + None + 1 + OPTIMIZED + 12.500 + 0.000 + false + 12.5 + 10.0 + false + false + ZHOLD + 0.010 + 0.010 + false + 10.000 + 0.500 + 0.000 + false + 5 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + None + OPTIMIZED + 4 + 0.000 + CLKFBOUT + 1 + 10.000 + SYSTEM_SYNCHRONOUS + 0.010 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + ACTIVE_HIGH + false + false + 1 + 1 + 1 + 1 + 1 + 1 + 1 + false + Custom + Custom + Custom + Custom + Custom + false + cddcdone + cddcreq + false + 600.000 + 136.213 + 100.585 + 119.661 + 100.585 + 0.0 + 0.0 + 0.0 + 0.0 + 0.0 + 0.0 + 0.0 + 0.0 + 0.0 + 0.0 + frequency + Enable_AXI + false + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + gtxKintex7FEE80_clockmodule + UNKNOWN + 1 + 1 + 0.010 + 0.010 + No_Jitter + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + AUTO + 0 + 80 + 10.000 + Units_MHz + 100.000 + 10.000 + FDBK_AUTO + Global_buffer + Single_ended_clock_capable_pin + SINGLE + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + BUFG + BUFG + BUFG + BUFG + BUFG + BUFG + BUFG + Input Clock Freq (MHz) Input Jitter (UI) + __primary______________80____________0.010 + no_secondary_input_clock + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + CLK_OUT1___100.000______0.000______50.0______136.213____100.585 + CLK_OUT2___200.000______0.000______50.0______119.661____100.585 + no_CLK_OUT3_output + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 100.000 + 200.000 + 100.000 + 100.000 + 100.000 + 100.000 + 100.000 + 0.000 + 0.000 + 0.000 + 0.000 + 0.000 + 0.000 + 0.000 + 50.000 + 50.000 + 50.000 + 50.000 + 50.000 + 50.000 + 50.000 + 100.000 + 200.000 + 100.000 + 100.000 + 100.000 + 100.000 + 100.000 + 0.000 + 0.000 + 0.000 + 0.000 + 0.000 + 0.000 + 0.000 + 50.0 + 50.0 + 50.000 + 50.000 + 50.000 + 50.000 + 50.000 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + None + OPTIMIZED + 12.500 + 12.5 + 10.0 + FALSE + FALSE + ZHOLD + 1 + 0.010 + 0.010 + FALSE + 10.000 + 5 + 1 + 1 + 1 + 1 + 1 + 0.500 + 0.500 + 0.500 + 0.500 + 0.500 + 0.500 + 0.500 + 0.000 + 0.000 + 0.000 + 0.000 + 0.000 + 0.000 + 0.000 + 0.000 + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + No notes + OPTIMIZED + CLKFBOUT + 1 + 1.000 + SYSTEM_SYNCHRONOUS + 1 + 0.010 + 1 + 1 + 1 + 1 + 1 + 1 + 0.500 + 0.500 + 0.500 + 0.500 + 0.500 + 0.500 + 0.000 + 0.000 + 0.000 + 0.000 + 0.000 + 0.000 + 0.000 + NA + 0 + 0 + clk_in1 + clk_in2 + clk_out1 + clk_out2 + clk_out3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + reset + locked + clkfb_in + clkfb_in_p + clkfb_in_n + clkfb_out + clkfb_out_p + clkfb_out_n + power_down + daddr + dclk + drdy + dwe + din + dout + den + psclk + psen + psincdec + psdone + CLK_VALID + STATUS + clk_in_sel + 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