From a07aae004975c28a6d8abe8da677ff7166c86661 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 10 Jul 2018 14:18:33 +0200 Subject: [PATCH] cleanup of unnecessary signals --- releases/tdc_v2.3/Channel.vhd | 40 ++++++++++++++-------------- releases/tdc_v2.3/Readout_record.vhd | 16 +++++------ releases/tdc_v2.3/TDC_record.vhd | 6 ++--- 3 files changed, 31 insertions(+), 31 deletions(-) diff --git a/releases/tdc_v2.3/Channel.vhd b/releases/tdc_v2.3/Channel.vhd index f6c96a3..f29d995 100644 --- a/releases/tdc_v2.3/Channel.vhd +++ b/releases/tdc_v2.3/Channel.vhd @@ -74,9 +74,9 @@ architecture Channel of Channel is -- debug signal hit_pulse_100 : std_logic; signal encoder_finished : std_logic; - signal encoder_finished_100 : std_logic; +-- signal encoder_finished_100 : std_logic; signal encoder_start : std_logic; - signal encoder_start_100 : std_logic; +-- signal encoder_start_100 : std_logic; signal fifo_write : std_logic; signal fifo_write_100 : std_logic; -- signal hit_detect_cntr : unsigned(30 downto 0); @@ -175,24 +175,24 @@ begin buf_empty_reg <= buf_empty when rising_edge(CLK_100); buf_data_valid <= rd_en_reg and not buf_empty_reg when rising_edge(CLK_100); - pulse_sync_encoder_start : pulse_sync - port map ( - CLK_A_IN => CLK_200, - RESET_A_IN => RESET_200, - PULSE_A_IN => encoder_start, - CLK_B_IN => CLK_100, - RESET_B_IN => RESET_100, - PULSE_B_OUT => encoder_start_100); - - pulse_sync_encoder_finished : pulse_sync - port map ( - CLK_A_IN => CLK_200, - RESET_A_IN => RESET_200, - PULSE_A_IN => encoder_finished, - CLK_B_IN => CLK_100, - RESET_B_IN => RESET_100, - PULSE_B_OUT => encoder_finished_100); - +-- pulse_sync_encoder_start : pulse_sync +-- port map ( +-- CLK_A_IN => CLK_200, +-- RESET_A_IN => RESET_200, +-- PULSE_A_IN => encoder_start, +-- CLK_B_IN => CLK_100, +-- RESET_B_IN => RESET_100, +-- PULSE_B_OUT => encoder_start_100); +-- +-- pulse_sync_encoder_finished : pulse_sync +-- port map ( +-- CLK_A_IN => CLK_200, +-- RESET_A_IN => RESET_200, +-- PULSE_A_IN => encoder_finished, +-- CLK_B_IN => CLK_100, +-- RESET_B_IN => RESET_100, +-- PULSE_B_OUT => encoder_finished_100); +-- pulse_sync_fifo_write : pulse_sync port map ( CLK_A_IN => CLK_200, diff --git a/releases/tdc_v2.3/Readout_record.vhd b/releases/tdc_v2.3/Readout_record.vhd index 005d88e..01aa97c 100644 --- a/releases/tdc_v2.3/Readout_record.vhd +++ b/releases/tdc_v2.3/Readout_record.vhd @@ -34,7 +34,7 @@ entity Readout_record is CLK_200 : in std_logic; HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 1); -- from the channels - CH_DATA_IN : in std_logic_vector_array_36(0 to CHANNEL_NUMBER); + CH_DATA_IN : in std_logic_vector_array_36(0 to CHANNEL_NUMBER-1); CH_DATA_VALID_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); CH_ALMOST_FULL_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); CH_EMPTY_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); @@ -87,9 +87,9 @@ architecture behavioral of Readout_record is -- signal trg_win_end_100_3r : std_logic; -- signal trg_win_end_100_4r : std_logic; -- channel signals - signal ch_data_r : std_logic_vector_array_36(0 to CHANNEL_NUMBER); - signal ch_data_2r : std_logic_vector_array_36(0 to CHANNEL_NUMBER); - signal ch_data_3r : std_logic_vector_array_36(0 to CHANNEL_NUMBER); + signal ch_data_r : std_logic_vector_array_36(0 to CHANNEL_NUMBER-1); + signal ch_data_2r : std_logic_vector_array_36(0 to CHANNEL_NUMBER-1); + signal ch_data_3r : std_logic_vector_array_36(0 to CHANNEL_NUMBER-1); signal ch_data_4r : std_logic_vector(31 downto 0); signal ch_hit_time : std_logic_vector(38 downto 0); signal ch_epoch_cntr : std_logic_vector(27 downto 0); @@ -135,8 +135,8 @@ architecture behavioral of Readout_record is signal fifo_nr_rd : integer range 0 to CHANNEL_NUMBER := 0; signal fifo_nr_wr : integer range 0 to CHANNEL_NUMBER := 0; signal fifo_nr_wr_r : integer range 0 to CHANNEL_NUMBER := 0; - signal fifo_nr_wr_2r : integer range 0 to CHANNEL_NUMBER := 0; - signal fifo_nr_wr_3r : integer range 0 to CHANNEL_NUMBER := 0; +-- signal fifo_nr_wr_2r : integer range 0 to CHANNEL_NUMBER := 0; +-- signal fifo_nr_wr_3r : integer range 0 to CHANNEL_NUMBER := 0; -- fifo read signal rd_en : std_logic_vector(CHANNEL_NUMBER-1 downto 0); -- data mux @@ -570,8 +570,8 @@ begin -- behavioral end process WR_FSM; fifo_nr_wr_r <= fifo_nr_wr when rising_edge(CLK_100); - fifo_nr_wr_2r <= fifo_nr_wr_r when rising_edge(CLK_100); - fifo_nr_wr_3r <= fifo_nr_wr_2r when rising_edge(CLK_100); +-- fifo_nr_wr_2r <= fifo_nr_wr_r when rising_edge(CLK_100); +-- fifo_nr_wr_3r <= fifo_nr_wr_2r when rising_edge(CLK_100); wr_ch_data_r <= wr_ch_data when rising_edge(CLK_100); ------------------------------------------------------------------------------- diff --git a/releases/tdc_v2.3/TDC_record.vhd b/releases/tdc_v2.3/TDC_record.vhd index 81a3b3c..11a8e02 100644 --- a/releases/tdc_v2.3/TDC_record.vhd +++ b/releases/tdc_v2.3/TDC_record.vhd @@ -100,7 +100,7 @@ architecture TDC_record of TDC_record is signal rd_en : std_logic_vector(CHANNEL_NUMBER-1 downto 0); signal trg_time : std_logic_vector(38 downto 0); -- From the channels - signal ch_data : std_logic_vector_array_36(0 to CHANNEL_NUMBER); + signal ch_data : std_logic_vector_array_36(0 to CHANNEL_NUMBER-1); signal ch_data_valid : std_logic_vector(CHANNEL_NUMBER-1 downto 0); signal ch_empty : std_logic_vector(CHANNEL_NUMBER-1 downto 0); signal ch_almost_full : std_logic_vector(CHANNEL_NUMBER-1 downto 0); @@ -458,7 +458,7 @@ begin Channel_200_DEBUG_OUT => ch_200_debug(i), Channel_DEBUG_OUT => ch_debug(i)); end generate GEN_Channels; - ch_data(CHANNEL_NUMBER) <= (others => '1'); +-- ch_data(CHANNEL_NUMBER) <= (others => '1'); ------------------------------------------------------------------------------- -- Trigger @@ -510,7 +510,7 @@ begin ------------------------------------------------------------------------------- -- Readout ------------------------------------------------------------------------------- - TheReadout : Readout_record + TheReadout : entity work.Readout_record generic map ( CHANNEL_NUMBER => CHANNEL_NUMBER, STATUS_REG_NR => STATUS_REG_NR) -- 2.43.0