From a0afd608f433680098f1ebd5a87ed68879526a89 Mon Sep 17 00:00:00 2001 From: Tobias Weber Date: Tue, 31 Jul 2018 10:58:06 +0200 Subject: [PATCH] some more piping. --- mupix/Mupix8/sources/Datapath/DataMux.vhd | 24 ++++--- .../Mupix8/sources/Datapath/MuPixUnpacker.vhd | 64 ++++++++++++------- .../Mupix8/sources/Simulation/DataOutput.vhd | 6 +- mupix/Mupix8/tb/MupixUnpackerTest.vhd | 2 +- mupix/Mupix8/trb3_periph.prj | 3 +- 5 files changed, 63 insertions(+), 36 deletions(-) diff --git a/mupix/Mupix8/sources/Datapath/DataMux.vhd b/mupix/Mupix8/sources/Datapath/DataMux.vhd index 7921ecf..0db163d 100644 --- a/mupix/Mupix8/sources/Datapath/DataMux.vhd +++ b/mupix/Mupix8/sources/Datapath/DataMux.vhd @@ -35,6 +35,7 @@ architecture RTL of FiFoDataMux is signal ticks_counter : unsigned(f_log2(g_clockspeed) - 1 downto 0) := (others => '0'); signal inword_counter : t_counter32_array(0 to g_inputs - 1) := (others => (others => '0')); signal increase_counter : std_logic_vector(g_inputs - 1 downto 0) := (others => '0'); + signal wordin_freq_i : std_logic_vector(32*g_inputs - 1 downto 0) := (others => '0'); signal fifo_full_i : std_logic; @@ -102,6 +103,7 @@ begin if rst = '1' then ticks_counter <= (others => '0'); inword_counter <= (others => (others => '0')); + wordin_freq_i <= (others => '0'); else if increase_counter(fifo_sel_reg) = '1' then inword_counter(fifo_sel_reg) <= inword_counter(fifo_sel_reg) + 1; @@ -111,7 +113,7 @@ begin if ticks_counter = g_clockspeed - 1 then inword_counter <= (others => (others => '0')); ticks_counter <= (others => '0'); - wordin_freq <= counter_array_to_stdvec(inword_counter); + wordin_freq_i <= counter_array_to_stdvec(inword_counter); else ticks_counter <= ticks_counter + 1; end if; @@ -144,7 +146,7 @@ begin end if; when wait_fifo => fifo_rden(fifo_sel_reg) <= '1'; - mux_fsm <= writedata; + mux_fsm <= writedata; when writedata => pause_cnt_i <= 0; dataout_i <= fifo_datain((fifo_sel_reg + 1)*g_datawidth - 1 downto g_datawidth*fifo_sel_reg); @@ -154,13 +156,13 @@ begin if fifo_empty(fifo_sel_reg) = '0' then mux_fsm <= writedata; else - mux_fsm <= pause; + mux_fsm <= pause; end if; when pause => -- wait in case filling clock is slower than reading -- clock - increase_counter <= (others => '0'); - pause_cnt_i <= pause_cnt_i + 1; - mux_fsm <= pause; + increase_counter <= (others => '0'); + pause_cnt_i <= pause_cnt_i + 1; + mux_fsm <= pause; if pause_cnt_i = 6 then mux_fsm <= idle; elsif fifo_empty(fifo_sel_reg) = '0' then @@ -176,11 +178,13 @@ begin begin -- process output_pipe if rising_edge(clk) then if rst = '1' then - dataout <= (others => '0'); - buff_wren <= '0'; + dataout <= (others => '0'); + buff_wren <= '0'; + wordin_freq <= (others => '0'); else - dataout <= dataout_i; - buff_wren <= buff_wren_i; + dataout <= dataout_i; + buff_wren <= buff_wren_i; + wordin_freq <= wordin_freq_i; end if; end if; end process output_pipe; diff --git a/mupix/Mupix8/sources/Datapath/MuPixUnpacker.vhd b/mupix/Mupix8/sources/Datapath/MuPixUnpacker.vhd index 96a25e0..558065e 100644 --- a/mupix/Mupix8/sources/Datapath/MuPixUnpacker.vhd +++ b/mupix/Mupix8/sources/Datapath/MuPixUnpacker.vhd @@ -33,17 +33,22 @@ architecture RTL of MupixUnpacker is type unpacker_fsm_type is (idle, receive_err, counter, link, data); signal unpacker_state : unpacker_fsm_type := idle; - signal data_i : std_logic_vector(31 downto 0) := (others => '0'); - signal errorcounter_i : unsigned(31 downto 0) := (others => '0'); - signal link_i : std_logic_vector(7 downto 0) := (others => '0'); - signal link_reg : std_logic_vector(7 downto 0) := (others => '0'); + signal data_i : std_logic_vector(31 downto 0) := (others => '0'); + signal errorcounter_i : unsigned(31 downto 0) := (others => '0'); + signal link_i : std_logic_vector(7 downto 0) := (others => '0'); + signal link_reg : std_logic_vector(7 downto 0) := (others => '0'); signal link_toggle : std_logic; signal data_mode : std_logic; - signal cnt4 : unsigned(1 downto 0) := (others => '0'); + signal cnt4 : unsigned(1 downto 0) := (others => '0'); signal counter_seen : std_logic; signal coarse_reg : std_logic; signal hit_reg : std_logic; signal link_flag_reg : std_logic; + signal hit_out_i : std_logic_vector(g_hitsize - 1 downto 0) := (others => '0'); + signal hit_enable_i : std_logic := '0'; + + signal inc_en_i : std_logic; + signal errorcounter_gray_i : std_logic_vector(31 downto 0); component Graycounter2 is generic ( @@ -54,11 +59,10 @@ architecture RTL of MupixUnpacker is inc_en : in std_logic; counter : out std_logic_vector(COUNTWIDTH - 1 downto 0)); end component Graycounter2; - signal inc_en_i : std_logic; + begin - errorcounter <= std_logic_vector(errorcounter_i); Graycounter2_1 : entity work.Graycounter2 generic map ( COUNTWIDTH => 32) @@ -66,7 +70,7 @@ begin clk => clk, reset => reset_counter, inc_en => inc_en_i, - counter => errorcounter_gray); + counter => errorcounter_gray_i); unpacker_proc : process (clk, reset) is begin -- process unpacker_proc @@ -74,11 +78,11 @@ begin if reset = '1' then unpacker_state <= idle; - hit_enable <= '0'; - hit_out <= (others => '0'); - data_i <= (others => '0'); - link_flag <= '0'; - link_flag_reg <= '0'; + hit_enable_i <= '0'; + hit_out_i <= (others => '0'); + data_i <= (others => '0'); + link_flag <= '0'; + link_flag_reg <= '0'; link_i <= (others => '0'); link_reg <= (others => '0'); @@ -96,18 +100,18 @@ begin errorcounter_i <= (others => '0'); end if; - link_flag_reg <= '0'; - coarse_reg <= '0'; - hit_reg <= '0'; - inc_en_i <= '0'; - hit_enable <= hit_reg or coarse_reg; - link_flag <= link_flag_reg; + link_flag_reg <= '0'; + coarse_reg <= '0'; + hit_reg <= '0'; + inc_en_i <= '0'; + hit_enable_i <= hit_reg or coarse_reg; + link_flag <= link_flag_reg; if coarse_reg = '1' then - hit_out <= x"3" & link_i(3 downto 0) & data_i(31 downto 0); + hit_out_i <= x"3" & link_i(3 downto 0) & data_i(31 downto 0); -- x"3" & link & binary counter elsif hit_reg = '1' then - hit_out <= link_i & data_i(7 downto 0) & data_i(15 downto 8) & data_i(21 downto 16) & data_i(31 downto 22); + hit_out_i <= link_i & data_i(7 downto 0) & data_i(15 downto 8) & data_i(21 downto 16) & data_i(31 downto 22); -- Link & Row & Col & Charge & TS end if; @@ -195,9 +199,25 @@ begin end if; end case; end if; - end if; end if; end process unpacker_proc; + output_pipe : process (clk) is + begin -- process output_pipe + if rising_edge(clk) then -- rising clock edge + if reset = '1' then -- synchronous reset (active low) + hit_out <= (others => '0'); + hit_enable <= '0'; + errorcounter <= (others => '0'); + errorcounter_gray <= (others => '0'); + else + hit_out <= hit_out_i; + hit_enable <= hit_enable_i; + errorcounter <= std_logic_vector(errorcounter_i); + errorcounter_gray <= errorcounter_gray_i; + end if; + end if; + end process output_pipe; + end architecture RTL; diff --git a/mupix/Mupix8/sources/Simulation/DataOutput.vhd b/mupix/Mupix8/sources/Simulation/DataOutput.vhd index c9e7f9b..a48ec57 100644 --- a/mupix/Mupix8/sources/Simulation/DataOutput.vhd +++ b/mupix/Mupix8/sources/Simulation/DataOutput.vhd @@ -24,7 +24,7 @@ architecture rtl of DataOutput is signal empty_i : std_logic := '0'; signal data_out_i : std_logic_vector(1 downto 0); - type output_fsm_type is (idle, readfifo, sending); + type output_fsm_type is (idle, readfifo, readfifo2, sending); signal output_state : output_fsm_type := idle; begin -- architecture rtl @@ -61,6 +61,8 @@ begin -- architecture rtl rden <= '1'; end if; when readfifo => + output_state <= readfifo2; + when readfifo2 => output_state <= sending; when sending => data_out_i <= datain_i((cnt5 + 1)*2 - 1 downto cnt5*2); @@ -71,7 +73,7 @@ begin -- architecture rtl cnt5 <= 0; end if; -- read fifo - if cnt5 = 3 then + if cnt5 = 2 then if empty = '0' then rden <= '1'; end if; diff --git a/mupix/Mupix8/tb/MupixUnpackerTest.vhd b/mupix/Mupix8/tb/MupixUnpackerTest.vhd index fabb6e9..597f923 100644 --- a/mupix/Mupix8/tb/MupixUnpackerTest.vhd +++ b/mupix/Mupix8/tb/MupixUnpackerTest.vhd @@ -61,7 +61,7 @@ architecture sim of MupixUnpackerTest is -- mupix state machine signal words : std_logic_vector(4 downto 0) := "00100"; - signal slowdown : std_logic_vector(15 downto 0) := x"000A"; + signal slowdown : std_logic_vector(15 downto 0) := x"FF0A"; signal wr_en : std_logic; signal data_out : std_logic_vector(9 downto 0); diff --git a/mupix/Mupix8/trb3_periph.prj b/mupix/Mupix8/trb3_periph.prj index 24a9196..56d7943 100644 --- a/mupix/Mupix8/trb3_periph.prj +++ b/mupix/Mupix8/trb3_periph.prj @@ -150,6 +150,7 @@ add_file -vhdl -lib "work" "cores/serdes_fifo.vhd" add_file -vhdl -lib "work" "cores/mupix_sim_pll.vhd" add_file -vhdl -lib "work" "cores/fifo_sim.vhd" add_file -vhdl -lib "work" "cores/RAM_DP_4096_32.vhd" +add_file -vhdl -lib "work" "cores/FIFO_40_512.vhd" #MuPix Files add_file -vhdl -lib "work" "trb3_periph.vhd" @@ -183,7 +184,7 @@ add_file -vhdl -lib "work" "sources/Datapath/MuPixDataLink_new.vhd" add_file -vhdl -lib "work" "sources/Datapath/TriggerHandler.vhd" add_file -vhdl -lib "work" "sources/Datapath/Arbiter.vhd" add_file -vhdl -lib "work" "sources/Datapath/DataMux.vhd" -add_file -vhdl -lib "work" "sources/DataWidthConversion.vhd" +add_file -vhdl -lib "work" "sources/Datapath/DataWidthConversion.vhd" add_file -vhdl -lib "work" "sources/Datapath/MuPixUnpacker.vhd" add_file -vhdl -lib "work" "sources/Datapath/LinkSynchronizer.vhd" -- 2.43.0