From a125f187e6fb8a17fdffd0dacfeb969dbf897f4e Mon Sep 17 00:00:00 2001 From: Adrian Weber Date: Tue, 14 Jul 2020 15:47:41 +0200 Subject: [PATCH] cleanup of code and deleted obsolet files --- combiner_cts/combiner.prj | 9 +- combiner_cts/cri/cri_data_receiver.vhd | 94 +- combiner_cts/cri/cri_data_sender.vhd | 879 ++++++++---- combiner_cts/cri/cri_data_sender3.vhd | 712 ---------- combiner_cts/cri/trb_net16_cri_interface.vhd | 411 +++--- combiner_cts/cri/trb_net16_cri_interface3.vhd | 991 ------------- ...16_cri_response_constructor_TrbNetData.vhd | 814 ----------- ...net16_hub_streaming_port_sctrl_cts_cri.vhd | 1228 ----------------- 8 files changed, 840 insertions(+), 4298 deletions(-) delete mode 100644 combiner_cts/cri/cri_data_sender3.vhd delete mode 100644 combiner_cts/cri/trb_net16_cri_interface3.vhd delete mode 100644 combiner_cts/cri/trb_net16_cri_response_constructor_TrbNetData.vhd delete mode 100644 combiner_cts/cri/trb_net16_hub_streaming_port_sctrl_cts_cri.vhd diff --git a/combiner_cts/combiner.prj b/combiner_cts/combiner.prj index 7ddbf09..336eca4 100644 --- a/combiner_cts/combiner.prj +++ b/combiner_cts/combiner.prj @@ -216,15 +216,10 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_rec add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" #CRI -add_file -vhdl -lib work "./cri/trb_net16_cri_interface3.vhd" +add_file -vhdl -lib work "./cri/trb_net16_cri_interface.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd" -add_file -vhdl -lib work "./cri/trb_net16_cri_response_constructor_TrbNetData.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd" -add_file -vhdl -lib work "./cri/cri_data_sender3.vhd" -add_file -vhdl -lib work "./cri/trb_net16_cri_ipu_interface.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd" +add_file -vhdl -lib work "./cri/cri_data_sender.vhd" #TDC Calibration #add_file -vhdl -lib work "./code/Calibration.vhd" diff --git a/combiner_cts/cri/cri_data_receiver.vhd b/combiner_cts/cri/cri_data_receiver.vhd index 30a35d4..64bf77a 100644 --- a/combiner_cts/cri/cri_data_receiver.vhd +++ b/combiner_cts/cri/cri_data_receiver.vhd @@ -32,7 +32,8 @@ end entity; architecture cri_data_receiver_arch of cri_data_receiver is - type state_t is (RECEIVE, PREPARE, REPLY); + constant localBuffer_Depth : integer := 8; + type state_t is (IDLE,RECEIVE, PREPARE, REPLY); signal state_num : std_logic_vector(3 downto 0) := x"0"; signal state : state_t; @@ -48,13 +49,20 @@ architecture cri_data_receiver_arch of cri_data_receiver is signal fifo_wr : std_logic; signal fifo_almFull : std_logic; + signal receive_cnt : std_logic_vector(15 downto 0) := x"0000"; + + type loc_buffer_t is array (0 to localBuffer_Depth) of std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal local_buffer : loc_buffer_t := (others => (others=> '0')); + + signal loc_buff_windowOffset : std_logic_vector(15 downto 0) := x"0000"; + begin PROC_STATE_MACHINE : process(CLK) begin if rising_edge(CLK) then if RESET = '1' then - state <= RECEIVE; + state <= IDLE; state_num <= x"0"; buf_APL_READ_OUT <= '0'; buf_APL_SHORT_TRANSFER_OUT <= '0'; @@ -64,23 +72,37 @@ PROC_STATE_MACHINE : process(CLK) buf_APL_SHORT_TRANSFER_OUT <= '0'; fifo_wr <= '0'; case state is + when IDLE => + state_num <= x"0"; + state <= RECEIVE; + buf_APL_SEND <= '0'; + receive_cnt <= (others => '0'); + when RECEIVE => state_num <= x"1"; buf_APL_SEND <= '0'; if APL_DATAREADY_IN = '1' and buf_APL_READ_OUT = '1' then if APL_TYP_IN = TYPE_TRM then -- end of event state <= PREPARE; + receive_cnt <= x"0000"; else case APL_PACKET_NUM_IN is - when c_F0 => null; --crc field, ignore + when c_F0 => receive_cnt <= receive_cnt + 1;--null; --crc field, ignore when c_F1 => buf_rec_data <= APL_DATA_IN; + receive_cnt <= receive_cnt + 1; fifo_wr <= '1'; when c_F2 => buf_rec_data <= APL_DATA_IN; - fifo_wr <= '1'; + receive_cnt <= receive_cnt + 1; + fifo_wr <= '1'; when c_F3 => buf_rec_data <= APL_DATA_IN; + receive_cnt <= receive_cnt + 1; fifo_wr <= '1'; - when others => null; + + when others => receive_cnt <= receive_cnt; end case; + if ((receive_cnt >= loc_buff_windowOffset) and ((receive_cnt - loc_buff_windowOffset) < localBuffer_Depth)) then + local_buffer(to_integer(unsigned(receive_cnt - loc_buff_windowOffset))) <= APL_DATA_IN; + end if; state <= RECEIVE; end if; end if; @@ -111,6 +133,25 @@ PROC_STATE_MACHINE : process(CLK) APL_READ_OUT <= buf_APL_READ_OUT; APL_SHORT_TRANSFER_OUT <= buf_APL_SHORT_TRANSFER_OUT; + + +-- THE_Local_Monitor_Cntr : process begin +-- wait until rising_edge(CLK); +-- +-- if RESET = '1' then +-- --local_buffer <= ("") +-- else +-- if (( state = RECEIVE) and APL_DATAREADY_IN = '1' and buf_APL_READ_OUT = '1') then +-- -- valid data at input +-- if ( (receive_cnt > 0) and (receive_cnt <= localBuffer_Depth) ) then +-- local_buffer(to_integer(unsigned(receive_cnt)-1)) <= buf_rec_data; +-- end if; +-- +-- end if; +-- end if; +-- +-- end process; + THE_Event_Cntr : process begin wait until rising_edge(CLK); @@ -175,11 +216,46 @@ THE_CRI_DATA_RECEIVER_DEBUG_HANDLER : process begin BUS_DBG_TX.ack <= '1'; end if; + if BUS_DBG_RX.addr(7 downto 0) = x"06" then + BUS_DBG_TX.data <= x"0000" & receive_cnt; + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"07" then + BUS_DBG_TX.data(15 downto 0) <= local_buffer(0); + BUS_DBG_TX.data(31 downto 16) <= local_buffer(1); + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"08" then + BUS_DBG_TX.data(15 downto 0) <= local_buffer(2); + BUS_DBG_TX.data(31 downto 16) <= local_buffer(3); + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"09" then + BUS_DBG_TX.data(15 downto 0) <= local_buffer(4); + BUS_DBG_TX.data(31 downto 16) <= local_buffer(5); + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"0A" then + BUS_DBG_TX.data(15 downto 0) <= local_buffer(6); + BUS_DBG_TX.data(31 downto 16) <= local_buffer(7); + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"0B" then + BUS_DBG_TX.data(15 downto 0) <= loc_buff_windowOffset; + BUS_DBG_TX.data(31 downto 16) <= (others => '0'); + BUS_DBG_TX.ack <= '1'; + end if; + elsif BUS_DBG_RX.write = '1' then - --if BUS_DBG_RX.addr( 7 downto 0) = x"0C" then - -- MUX_cal_sw <= BUS_DBG_RX.data(0); - --end if; - BUS_DBG_TX.ack <= '1'; + if BUS_DBG_RX.addr( 7 downto 0) = x"0B" then + loc_buff_windowOffset <= BUS_DBG_RX.data(15 downto 0); + BUS_DBG_TX.ack <= '1'; + end if; end if; end process; end architecture; diff --git a/combiner_cts/cri/cri_data_sender.vhd b/combiner_cts/cri/cri_data_sender.vhd index 621caae..98a691b 100644 --- a/combiner_cts/cri/cri_data_sender.vhd +++ b/combiner_cts/cri/cri_data_sender.vhd @@ -1,6 +1,6 @@ LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; +--USE IEEE.std_logic_ARITH.ALL; USE IEEE.std_logic_UNSIGNED.ALL; USE IEEE.numeric_std.ALL; library work; @@ -13,6 +13,9 @@ entity cri_data_sender is CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; + + ENABLE_TRANSPORT : in std_logic; + -- Port to API API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); @@ -35,378 +38,656 @@ entity cri_data_sender is MY_ADDRESS_IN : in std_logic_vector (15 downto 0); --data from event packer - CRI_DATA_IN : in std_logic_vector (8 downto 0); --8 is EOD - CRI_DATAREADY_IN : in std_logic; - --no more data, send TRM - CRI_READOUT_FINISHED_IN : in std_logic; --currently not used - CRI_READ_OUT : out std_logic; - CRI_LENGTH_IN : in std_logic_vector (15 downto 0); - - STAT_DEBUG : out std_logic_vector(31 downto 0) + CTS_NUMBER_IN : in std_logic_vector(15 downto 0); --not used; got it from FEE + CTS_CODE_IN : in std_logic_vector( 7 downto 0); --not used; got it from FEE + CTS_INFORMATION_IN : in std_logic_vector( 7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector( 3 downto 0); --not used; got it from FEE + CTS_START_READOUT_IN : in std_logic; + CTS_READ_IN : in std_logic; + CTS_DATA_OUT : out std_logic_vector(31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM + CTS_LENGTH_OUT : out std_logic_vector(15 downto 0); -- 0 terminated + CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- 0 terminated + -- Data from Frontends + FEE_DATA_IN : in std_logic_vector(15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; + FEE_BUSY_IN : in std_logic; + FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0); + + DEBUG_OUT : out std_logic_vector(191 downto 0) ); end entity; architecture cri_data_sender_arch of cri_data_sender is - type send_state_t is (IDLE, WAITING, SEND_DATA, READ_ANSWER); - signal send_state_current, send_state_next : send_state_t; - signal send_state_bits : std_logic_vector( 3 downto 0); - - attribute syn_encoding : string; + type save_states_t is (IDLE, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, SEND_TERM_PULSE, CLOSE, CLEANUP); + signal save_current_state, save_next_state : save_states_t; - type fifo_states is (IDLE, PREPARE_DATA, WAIT_FOR_READY, SAVE, CLOSE, WAIT_FOR_TRANS, DIVIDE, CLEANUP); - signal fifo_machine_current_state, fifo_machine_next_state : fifo_states; - attribute syn_encoding of fifo_machine_current_state : signal is "onehot"; - signal fifo_state_bits : std_logic_vector( 3 downto 0); + type data_sender_states_t is (IDLE, PREPARE_SEND, LOAD, FINISH_SEND, STOP_SEND, READ_ANSWER, FINISH_ACTION, CLEANUP); + signal send_state_current, send_state_next : data_sender_states_t; - type loc_buffer_t is array (0 to 15) of std_logic_vector(17 downto 0); - signal local_buffer : loc_buffer_t := (others => (others=> '0')); + constant loc_buff_depth : integer := 4; + type loc_buffer_t is array (0 to loc_buff_depth) of std_logic_vector(16 downto 0); + signal local_buffer : loc_buffer_t := (others => (others=> '0')); - signal fifo_wr_en : std_logic; - signal fifo_almFull : std_logic; - signal fifo_full : std_logic; - signal fifo_empty : std_logic; + signal rec_state, send_state_bits : std_logic_vector(3 downto 0); - signal local_end : std_logic_vector(15 downto 0); - signal fifo_rd_en : std_logic; - signal fifo_data_in : std_logic_vector(17 downto 0); - signal fifo_wcnt : std_logic_vector(11 downto 0); - signal fifo_data_out : std_logic_vector(17 downto 0); - - signal cri_rd : std_logic; - signal cri_rd_q : std_logic; - signal cri_rd_qq : std_logic; - signal cri_data_avail : std_logic; + signal df_wr_en_qq, df_wr_en_q, df_wr_en,df_rd_en : std_logic; + signal df_data : std_logic_vector(15 downto 0); + signal df_eos_q, df_eos : std_logic; + signal fifo_almFull : std_logic; + signal df_afull, df_full_real : std_logic; + signal df_empty : std_logic; + signal df_wcnt : std_logic_vector(11 downto 0); + signal df_rdy_q, df_rdy : std_logic; + signal data_out, df_q : std_logic_vector(15 downto 0); + signal load_eod : std_logic; + signal fifo_rd_en : std_logic; + signal eod_out : std_logic; + signal local_buf_empty : std_logic; - signal data_word_pos : std_logic; - signal local_buffer_empty : std_logic; + -- saving + signal cts_rnd, cts_trg : std_logic_vector(15 downto 0); + signal length_cnt : std_logic_vector(15 downto 0) := x"0000"; - signal data_ready_q : std_logic; - signal data_ready_qq : std_logic; - signal buf_data_ready : std_logic; - signal buf_data_out : std_logic_vector(15 downto 0); - signal buf_eod : std_logic_vector( 1 downto 0); + -- sending + signal cri_apl_reading : std_logic; + signal cri_apl_data : std_logic_vector(15 downto 0); + signal cri_apl_packet_num : std_logic_vector(2 downto 0); + signal cri_apl_dataready : std_logic; + signal cri_apl_read : std_logic; + signal data_trans_finished : std_logic; + signal load_data : std_logic; + signal tmp_data : std_logic_vector( 7 downto 0); + signal cri_apl_send : std_logic; + signal received_answer : std_logic; + signal cri_apl_run : std_logic; + + signal cri_event_cnt : std_logic_vector(15 downto 0) := x"0000"; - signal loc_sending_flag : std_logic; + signal cri_apl_answer_data : std_logic_vector(15 downto 0); + signal cri_apl_answer_packet_num : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal cri_apl_answer_typ : std_logic_vector( 2 downto 0); + signal cri_apl_answer_dataready : std_logic; + signal loaded_bytes : std_logic_vector(15 downto 0) := x"0000"; + signal cri_packet_num_cnt : std_logic_vector( 1 downto 0) := "00"; - signal buf_API_READ_OUT : std_logic; - signal buf_API_SEND_OUT : std_logic; - signal packet_number : std_logic_vector(2 downto 0); + signal data_save_cnt : std_logic_vector(15 downto 0); + signal fee_read_loc : std_logic; + + signal data_open : std_logic; -- for modelsim + type loc_buffer_dbg_t is array (0 to 7) of std_logic_vector(15 downto 0); + signal local_buffer_dbg : loc_buffer_dbg_t := (others => (others=> '0')); begin - ------------------------------------------------------------------ --- Receive finaly packed events ------------------------------------------------------------------ --- --- 8 bit words with all headers are reordered to 16 bit words for --- trbnet. The Fifo is buffering and the readout is controled by --- the status of trbnet and event packer. --- - - THE_CRI_BUFF : entity work.fifo_18x2k_oreg - port map ( - Data => fifo_data_in, - Clock => CLK, - WrEn => fifo_wr_en, - RdEn => fifo_rd_en, - Reset => RESET, - AmFullThresh => b"11111110000", - Q => fifo_data_out, - WCNT => fifo_wcnt, - Empty => fifo_empty, - Full => fifo_full, - AlmostFull => fifo_almFull - ); + CTS_LENGTH_OUT <= (others => '0'); + CTS_ERROR_PATTERN_OUT <= (others => '0'); - - FIFO_MACHINE_PROC : process(RESET, CLK) + SAVE_MACHINE_PROC : process(RESET, CLK) begin if RESET = '1' then - fifo_machine_current_state <= IDLE; + save_current_state <= IDLE; elsif rising_edge(CLK) then - fifo_machine_current_state <= fifo_machine_next_state; + save_current_state <= save_next_state; end if; - end process FIFO_MACHINE_PROC; - - - FIFO_MACHINE : process(fifo_machine_current_state, CRI_DATAREADY_IN, local_end, fifo_almFull) + end process; + + SAVE_MACHINE : process(save_current_state, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN) begin - fifo_state_bits <= x"0"; - case fifo_machine_current_state is + rec_state <= x"0"; + case (save_current_state) is when IDLE => - fifo_state_bits <= x"1"; - if (CRI_DATAREADY_IN = '1') then - fifo_machine_next_state <= PREPARE_DATA; - else - fifo_machine_next_state <= IDLE; - end if; - - when PREPARE_DATA => - fifo_state_bits <= x"2"; - if (fifo_almFull = '0') then - fifo_machine_next_state <= WAIT_FOR_READY; - else - fifo_machine_next_state <= PREPARE_DATA; - end if; - when WAIT_FOR_READY => - fifo_state_bits <= x"3"; - if (fifo_almFull = '0') then - fifo_machine_next_state <= SAVE; - else - fifo_machine_next_state <= WAIT_FOR_READY; - end if; - - when SAVE => - fifo_state_bits <= x"4"; - if (local_end = x"0000") then -- or look for DataIn(8) ?? - fifo_machine_next_state <= CLOSE; - else - if (fifo_almFull = '1') then - fifo_machine_next_state <= WAIT_FOR_READY; - else - fifo_machine_next_state <= SAVE; - end if; - end if; - + rec_state <= x"1"; + if (CTS_START_READOUT_IN = '1') then + save_next_state <= WAIT_FOR_DATA; + else + save_next_state <= IDLE; + end if; + + when WAIT_FOR_DATA => + rec_state <= x"2"; + if (FEE_BUSY_IN = '1') then + save_next_state <= SAVE_DATA; + else + save_next_state <= WAIT_FOR_DATA; + end if; + + when SAVE_DATA => + rec_state <= x"3"; + if (FEE_BUSY_IN = '0') then + save_next_state <= TERMINATE; + else + save_next_state <= SAVE_DATA; + end if; + + when TERMINATE => + rec_state <= x"5"; + if (CTS_READ_IN = '1') then + save_next_state <= SEND_TERM_PULSE; --CLOSE; + else + save_next_state <= TERMINATE; + end if; + + when SEND_TERM_PULSE => + rec_state <= x"6"; + save_next_state <= CLOSE; + when CLOSE => - fifo_state_bits <= x"5"; - fifo_machine_next_state <= IDLE; - + rec_state <= x"6"; + save_next_state <= ADD_SUBSUB1; + + when ADD_SUBSUB1 => + rec_state <= x"7"; + save_next_state <= ADD_SUBSUB2; + + when ADD_SUBSUB2 => + rec_state <= x"8"; + save_next_state <= ADD_SUBSUB3; + + when ADD_SUBSUB3 => + rec_state <= x"9"; + save_next_state <= ADD_SUBSUB4; + + when ADD_SUBSUB4 => + rec_state <= x"a"; + save_next_state <= CLEANUP; + + when CLEANUP => + rec_state <= x"c"; + if (CTS_START_READOUT_IN = '0') then + save_next_state <= IDLE; + else + save_next_state <= CLEANUP; + end if; + + when others => save_next_state <= IDLE; + end case; end process; - - - LOCAL_END_PROC : process begin - wait until rising_edge(CLK); - if (fifo_machine_current_state = IDLE and CRI_DATAREADY_IN = '1') then - local_end <= CRI_LENGTH_IN - x"1"; - --full_packet_size <= CRI_LENGTH_IN; - elsif (fifo_machine_current_state = SAVE) then - local_end <= local_end - x"1"; - --full_packet_size <= full_packet_size; - else - local_end <= local_end; - --full_packet_size <= full_packet_size; - end if; - end process; - - SYNC_PROC : process begin - wait until rising_edge(CLK); - cri_rd_q <= cri_rd; - cri_rd_qq <= cri_rd_q; - cri_data_avail <= cri_rd_qq; + + CTS_DATAREADY_PROC : process(CLK) + begin + if rising_edge(CLK) then + if (save_current_state = SAVE_DATA and FEE_BUSY_IN = '0') then + CTS_DATAREADY_OUT <= '1'; + elsif (save_current_state = TERMINATE) then + CTS_DATAREADY_OUT <= '1'; + else + CTS_DATAREADY_OUT <= '0'; + end if; + end if; end process; - - -- If a 8bit word is available, it is putt in the correct position of the - -- 16bit words with the EOD bit in the MSB positions - ARRANGE_DATA_WORDS_PROC : process begin - wait until rising_edge(CLK); - fifo_wr_en <= '0'; - if RESET = '1' then - data_word_pos <= '0'; - else - if cri_data_avail = '1' then - if data_word_pos = '0' then - fifo_data_in(7 downto 0) <= CRI_DATA_IN(7 downto 0); - fifo_data_in(16) <= CRI_DATA_IN(8); --16: mark lower 8 bit as end; - - data_word_pos <= '1'; - - -- case that event size is odd; - if (CRI_DATA_IN(8) = '1') then - fifo_data_in(15 downto 8) <= (others => '0'); - fifo_data_in(17) <= CRI_DATA_IN(8); --17: mark 16bit as EOD; - - fifo_wr_en <= '1'; - data_word_pos <= '0'; - end if; - - else - fifo_data_in(15 downto 8) <= CRI_DATA_IN(7 downto 0); - fifo_data_in(17) <= CRI_DATA_IN(8); - - data_word_pos <= '0'; - fifo_wr_en <= '1'; - end if; + CTS_READOUT_FINISHED_PROC : process(CLK) + begin + if rising_edge(CLK) then + if (save_current_state = CLEANUP) then + CTS_READOUT_FINISHED_OUT <= '1'; + else + CTS_READOUT_FINISHED_OUT <= '0'; end if; end if; end process; - cri_rd <= '1' when fifo_machine_current_state = SAVE else '0'; - CRI_READ_OUT <= cri_rd; - ------------------------------------------------------------------ ---XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX-- ------------------------------------------------------------------ - - ------------------------------------------------------------------ --- Send data to API for transfer to CRI ------------------------------------------------------------------ + CTS_DATA_PROC : process(CLK) + begin + if rising_edge(CLK) then + CTS_DATA_OUT <= "0001" & cts_rnd(11 downto 0) & cts_trg; + end if; + end process; + + CTS_RND_TRG_PROC : process(CLK) + begin + if rising_edge(CLK) then + if ((save_current_state = SAVE_DATA) and + (FEE_DATAREADY_IN = '1') and + (fee_read_loc = '1')) + then + if (length_cnt = x"0000") then + cts_rnd <= FEE_DATA_IN; + end if; + + if (length_cnt = x"0001") then + cts_trg <= FEE_DATA_IN; + end if; + else + cts_rnd <= cts_rnd; + cts_trg <= cts_trg; + end if; + end if; + end process; + + CTS_WORD_CNT : process(CLK) + begin + if rising_edge(CLK) then + if (save_current_state = IDLE) then + length_cnt <= (others => '0'); + elsif ((save_current_state = SAVE_DATA) and (FEE_DATAREADY_IN = '1') and (fee_read_loc = '1')) then + length_cnt <= length_cnt + 1; + else + length_cnt <= length_cnt; + end if; + end if; + end process; ---load data from fifo - fifo_rd_en <= API_READ_IN and (not fifo_empty) and local_buffer_empty and loc_sending_flag; + DATA_WRITE_PROC : process begin + wait until rising_edge(CLK); + if ((save_current_state = SAVE_DATA) and (FEE_DATAREADY_IN = '1') and (fee_read_loc = '1')) then + df_wr_en <= '1'; + elsif (save_current_state = ADD_SUBSUB1 or save_current_state = ADD_SUBSUB2 or save_current_state = ADD_SUBSUB3 or save_current_state = ADD_SUBSUB4) then + df_wr_en <= '1'; + else + df_wr_en <= '0'; + end if; + end process; + +-- FEE_READ_PROC : process(CLK) +-- begin +-- if rising_edge(CLK) then +-- if (save_current_state = SAVE_DATA) then +-- if (df_afull = '0') then +-- local_read <= '1'; +-- else +-- local_read <= '0'; +-- end if; +-- else +-- local_read <= '1'; +-- end if; +-- end if; +-- end process FEE_READ_PROC; + + SF_DATA_EOD_PROC : process begin + wait until rising_edge(CLK); + case (save_current_state) is + when SAVE_DATA => + df_data <= FEE_DATA_IN; + df_eos_q <= '0'; + + when ADD_SUBSUB1 => + df_data <= x"0001"; + df_eos_q <= '0'; + + when ADD_SUBSUB2 => + df_data <= x"5555"; + df_eos_q <= '0'; + + when ADD_SUBSUB3 => + df_data <= FEE_STATUS_BITS_IN(31 downto 16); + df_eos_q <= '0'; + + when ADD_SUBSUB4 => + df_data <= FEE_STATUS_BITS_IN(15 downto 0); + df_eos_q <= '1'; + + when others => + df_data <= df_data; + df_eos_q <= '0'; - FIFO_DATARDY_PROC : process begin + end case; + end process; + + FEE_READ_OUT <= fee_read_loc; + fee_read_loc <= not df_afull;--local_read; + +-- DATA_FIFO : entity work.fifo_64kx9_af_cnt +-- port map( +-- Data(15 downto 0) => df_data, +-- Data(16) => df_eos_q, +-- WrClock => CLK, +-- RdClock => CLK, +-- WrEn => df_wr_en, +-- RdEn => df_rd_en, +-- Reset => RESET, +-- RPReset => RESET, +-- Q(15 downto 0) => df_q, +-- Q(16) => load_eod, +-- Empty => df_empty, +-- Full => df_full_real, +-- AlmostFull => df_afull, +-- WCNT => df_wcnt +-- ); + + DATA_FIFO : entity work.fifo_18x2k_oreg + port map ( + Data(15 downto 0) => df_data, + Data(16) => df_eos_q, + Data(17) => '0', + Clock => CLK, + WrEn => df_wr_en, + RdEn => df_rd_en, + Reset => RESET, + AmFullThresh => b"11111111000", + Q(15 downto 0) => data_out,--df_q, --df_q if fifo is without outreg + Q(16) => eod_out,--load_eod, --load_eod if fifo is without outreg + Q(17) => data_open, + WCNT => df_wcnt, + Empty => df_empty, + Full => df_full_real, + AlmostFull => df_afull + ); + + --READ from FIFO to TrbNet API + + df_rd_en <= load_data and not df_empty and local_buf_empty; + + load_data <= '1' when send_state_current = LOAD else '0'; + + DATA_FIFO_CONTRL_PROC : process begin wait until rising_edge(CLK); if RESET = '1' then - data_ready_q <= '0'; - data_ready_qq <= '0'; + df_rdy_q <= '0'; + df_rdy <= '0'; + --data_out <= x"0000"; + --eod_out <= '0'; else - data_ready_q <= fifo_rd_en; - data_ready_qq <= data_ready_q; - end if; + df_rdy_q <= df_rd_en; + df_rdy <= df_rdy_q; -- delay from readout reg of fifo + + --data_out <= df_q; -- readout reg for fifo + --eod_out <= load_eod; + end if; end process; - - -- buffer words from fifo if the API FIFO is going full while we are reding from our fifo - local_buffer_process : process - variable wcnt : unsigned( 2 downto 0) := 0; + + + LOCAL_BUFF_PROC : process + variable buff_cnt : integer range 0 to loc_buff_depth := 0; begin wait until rising_edge(CLK); - - buf_data_ready <= '0'; - if RESET = '1' then - local_buffer_empty <= '1'; - packet_number <= c_F0; - wcnt := 0; - buf_eod <= "00"; + buff_cnt := 0; else - -- buffer if data is read and API FIFO is full OR buffer also if the transmission - -- has finished, but a few words are still coming from FIFO. - if (((data_ready_qq = '1') and (API_READ_IN = '0')) or - ((data_ready_qq = '1') and (loc_sending_flag = '0'))) - then - local_buffer(to_integer(wcnt)) <= fifo_data_out; - wcnt := wcnt + 1; - end if; - -- Data output to API: - if ((loc_sending_flag = '1') and (API_READ_IN = '1')) then - if (wcnt > 0) then - buf_data_ready <= '1'; - buf_data_out <= local_buffer(to_integer(wcnt-1))(15 downto 0); - buf_eod <= local_buffer(to_integer(wcnt-1))(17 downto 16); - wcnt := wcnt - 1; - else -- standard output from FIFO - buf_data_ready <= data_ready_qq; - buf_data_out <= fifo_data_out(15 downto 0); - buf_eod <= fifo_data_out(17 downto 16); - end if; - - -- Generate packet number - packet_number <= packet_number + 1; - if packet_number = c_F3 then - packet_number <= c_F0; - end if; + -- Data from sub is loaded; first data from following sub is (partialy) loaded + if (send_state_current /= LOAD) and (df_rdy = '1') then + local_buffer(buff_cnt) <= eod_out & data_out; + buff_cnt := buff_cnt + 1; + end if; + + -- first word in buffer is always in 0; is loaded in sending process. + if (send_state_current = LOAD) and (local_buf_empty = '0') then + local_buffer(0) <= local_buffer(1); + local_buffer(1) <= local_buffer(2); + local_buffer(2) <= local_buffer(3); + local_buffer(3) <= local_buffer(4); + local_buffer(4) <= (others => '0'); + buff_cnt := buff_cnt - 1; end if; - if wcnt = 0 then - local_buffer_empty <= '1'; + -- has to be atthis position, to garantee that buff_cnt won't be negative + if buff_cnt = 0 then + local_buf_empty <= '1'; else - local_buffer_empty <= '0'; + local_buf_empty <= '0'; end if; - end if; - end process; - - ---send loaded data to CRI - + end if; + end process; + + SEND_STATE_PROC : process(RESET, CLK) begin if RESET = '1' then send_state_current <= IDLE; - buf_API_READ_OUT <= '0'; - elsif rising_edge(CLK) then - send_state_current <= send_state_next; - buf_API_READ_OUT <= '1'; + else + if rising_edge(CLK) then + send_state_current <= send_state_next; + end if; end if; end process; - SEND_STATE_MACHINE : process(send_state_current, API_RUN_IN, fifo_empty, API_READ_IN, buf_eod) - begin + SEND_STATE_MACHINE : process(send_state_current, cri_apl_reading, ENABLE_TRANSPORT, eod_out, df_rdy,local_buf_empty,local_buffer(0)(8),data_trans_finished,received_answer,cri_apl_run) + begin send_state_bits <= x"0"; case send_state_current is when IDLE => - send_state_bits <= x"1"; - buf_API_SEND_OUT <= '0'; - loc_sending_flag <= '0'; - - if ((API_RUN_IN = '0') and (fifo_empty = '0')) then - send_state_next <= WAITING; - end if; - - when WAITING => - send_state_bits <= x"2"; - loc_sending_flag <= '0'; - if (fifo_empty = '0') and API_READ_IN = '1' then - -- read signal for DHDR - send_state_next <= SEND_DATA; - loc_sending_flag <= '1'; - end if; - - when SEND_DATA => -- send DHDR packet + send_state_bits <= x"1"; + send_state_next <= PREPARE_SEND; + + when PREPARE_SEND => + send_state_bits <= x"2"; + if cri_apl_reading = '1' and ENABLE_TRANSPORT = '1' then + send_state_next <= LOAD; + else + send_state_next <= PREPARE_SEND; + end if; + + when LOAD => send_state_bits <= x"3"; - loc_sending_flag <= '1'; - buf_API_SEND_OUT <= '1'; - if buf_eod(1) = '1' then --TO CHECK: is this to late? maybe one word too much send! - loc_sending_flag <= '0'; - send_state_next <= READ_ANSWER; + if ((eod_out = '1' and df_rdy = '1') or ( local_buf_empty = '0' and local_buffer(0)(8) = '1' )) then --last word of subevent is currently in data_out + send_state_next <= FINISH_SEND; + else + send_state_next <= LOAD; end if; - when READ_ANSWER => + when FINISH_SEND => send_state_bits <= x"4"; - buf_API_SEND_OUT <= '0'; - loc_sending_flag <= '0'; - if API_DATAREADY_IN = '1' and buf_API_READ_OUT = '1' and API_TYP_IN = TYPE_TRM then - case API_PACKET_NUM_IN is - when c_F0 => null; --crc field, ignore - when c_F1 => null; - when c_F2 => null; - when c_F3 => --buf_TYPE <= API_DATA_IN(3 downto 0); - null; - send_state_next <= IDLE; - when others => null; - end case; + if data_trans_finished = '1' then + send_state_next <= STOP_SEND; + else + send_state_next <= FINISH_SEND; + end if; + + when STOP_SEND => + send_state_bits <= x"5"; + send_state_next <= READ_ANSWER; + + when READ_ANSWER => + send_state_bits <= x"6"; + if received_answer = '1' then + send_state_next <= FINISH_ACTION; + else + send_state_next <= READ_ANSWER; + end if; + + when FINISH_ACTION => + send_state_bits <= x"7"; + if cri_apl_run = '0' then + send_state_next <= PREPARE_SEND; + else + send_state_next <= FINISH_ACTION; end if; when others => - send_state_bits <= x"5"; + send_state_bits <= x"8"; send_state_next <= IDLE; end case; - end process; - + end process; + + + + DATA_TRANSPORT_PROC : process + variable loc_tmp_data : std_logic_vector(15 downto 0); + variable loc_data_rdy : std_logic; + --variable pos_cnt : std_logic := '0'; + begin + wait until rising_edge(CLK); - + cri_apl_dataready <= '0'; + data_trans_finished <= '0'; ---------------------------------------------------------------------- ---Connect Outputs ---------------------------------------------------------------------- - - API_ERROR_PATTERN_OUT <= (others => '0'); - API_LENGTH_OUT <= (others => '0'); - API_READ_OUT <= buf_API_READ_OUT; - API_DATAREADY_OUT <= buf_data_ready; - API_DATA_OUT <= buf_data_out; - API_PACKET_NUM_OUT <= packet_number; - API_SEND_OUT <= buf_API_SEND_OUT; - API_SHORT_TRANSFER_OUT<= '0'; - API_DTYPE_OUT <= (others => '0');--buf_TYPE; + if RESET = '1' then + loc_tmp_data := x"0000"; + loc_data_rdy := '0'; + loaded_bytes <= (others => '0'); + else + --prepare data + loc_data_rdy := '0'; + if (send_state_current = LOAD) then -- load state data + -- get data from correct source + if (local_buf_empty = '0') then + loc_tmp_data := local_buffer(0)(15 downto 0); + loc_data_rdy := '1'; + else + loc_tmp_data := data_out; + loc_data_rdy := df_rdy; + end if; + end if; + + if (send_state_current = LOAD) then -- or (send_state_current = FINISH_SEND)) then + if loc_data_rdy = '1' then -- only process if data is valid/rdy + cri_apl_dataready <= '1'; + cri_packet_num_cnt <= cri_packet_num_cnt + 1; + loaded_bytes <= loaded_bytes + 1; + cri_apl_data <= loc_tmp_data;-- & tmp_data; --maybe wrong order! + cri_apl_packet_num <= '0' & std_logic_vector(cri_packet_num_cnt); + end if; -- end data rdy + end if;-- load state + + + -- finish the send process: + -- packet if last word in LOAD was not send, send it now. + if (send_state_current = FINISH_SEND) then + if (cri_packet_num_cnt = "00") then + data_trans_finished <= '1'; + cri_apl_packet_num <= '0' & std_logic_vector(cri_packet_num_cnt); + else + cri_packet_num_cnt <= cri_packet_num_cnt + 1; + cri_apl_packet_num <= '0' & std_logic_vector(cri_packet_num_cnt); + cri_apl_dataready <= '1'; + cri_apl_data <= x"AAAA"; + end if; + end if; -- FINISH_SEND + + -- to be sure that cntr is null in next data sending process. + if (data_trans_finished = '1') then + cri_packet_num_cnt <= "00"; + loaded_bytes <= (others => '0'); + end if; + + if ((loaded_bytes > x"0000") and (loaded_bytes < x"0009") and (cri_apl_dataready = '1')) then + local_buffer_dbg(to_integer( unsigned( loaded_bytes )-1) ) <= cri_apl_data; + end if; + + end if; + end process; ---------------------------------------------------------------------- ---Debugging ---------------------------------------------------------------------- - STAT_DEBUG( 2 downto 0) <= fifo_state_bits(2 downto 0); - STAT_DEBUG( 5 downto 3) <= send_state_bits(2 downto 0); - STAT_DEBUG(31 downto 6) <= (others => '0'); + + + -- handle the data sending flag to the trbnet APL + DATA_SEND_OUT_PROC : process begin + wait until rising_edge(CLK); + if RESET = '1' then + cri_apl_send <= '0'; + else + if ((send_state_current = PREPARE_SEND) or + (send_state_current = LOAD) or + (send_state_current = FINISH_SEND) or + (send_state_current = STOP_SEND)) + then + cri_apl_send <= '1'; + else + cri_apl_send <= '0'; + end if; + end if; + end process; + + -- handle the read flag to the trbnet APL + DATA_READ_OUT_PROC : process begin + wait until rising_edge(CLK); + if RESET = '1' then + cri_apl_read <= '0'; + else + --if ((send_state_current /= IDLE) then + if (( send_state_current = READ_ANSWER ) or + ( send_state_current = STOP_SEND )) + then + cri_apl_read <= '1'; + else + cri_apl_read <= '0'; + end if; + end if; + end process; + + + + -- handle the answer from CRI over trbnet + EVENT_CNT_PROC : process begin + wait until rising_edge(CLK); + if RESET = '1' then + received_answer <= '0'; + cri_event_cnt <= (others => '0'); + else + received_answer <= '0'; + if ((cri_apl_answer_dataready = '1') and (cri_apl_answer_typ = TYPE_TRM) and (cri_apl_answer_packet_num = c_F3)) then + --cri_data_send_cnt <= 0; + cri_event_cnt <= cri_event_cnt + 1; + received_answer <= '1'; + end if; + end if; + end process; + +-- DEBUG_OUT + DATA_SAVE_CNT_PROC : process begin + wait until rising_edge(CLK); + if RESET = '1' then + data_save_cnt <= (others => '0'); + else + if ((save_current_state = CLEANUP) and (CTS_START_READOUT_IN = '0')) then + data_save_cnt <= data_save_cnt + 1; + end if; + end if; + end process; + + + -- Data to CRI board + API_DATA_OUT <= cri_apl_data; + API_PACKET_NUM_OUT <= cri_apl_packet_num; + API_DATAREADY_OUT <= cri_apl_dataready; + cri_apl_reading <= API_READ_IN; + + API_SHORT_TRANSFER_OUT <= '0'; + API_DTYPE_OUT <= (others => '0'); + API_ERROR_PATTERN_OUT <= (others => '0'); + API_SEND_OUT <= cri_apl_send; + + cri_apl_answer_data <= API_DATA_IN; + cri_apl_answer_packet_num <= API_PACKET_NUM_IN; + cri_apl_answer_typ <= API_TYP_IN; + cri_apl_answer_dataready <= API_DATAREADY_IN; + + API_READ_OUT <= cri_apl_read; + -- APL Control port + cri_apl_run <= API_RUN_IN; + API_LENGTH_OUT <= (others => '0'); + + DEBUG_OUT(3 downto 0) <= rec_state; + DEBUG_OUT(7 downto 4) <= send_state_bits; + DEBUG_OUT( 8) <= df_empty; + DEBUG_OUT( 9) <= df_full_real; + DEBUG_OUT(10) <= df_afull; + DEBUG_OUT(11) <= '0'; + DEBUG_OUT(14 downto 12) <= cri_apl_packet_num; + DEBUG_OUT(15) <= '0'; + DEBUG_OUT(31 downto 16) <= cri_event_cnt; + + DEBUG_OUT( 47 downto 32) <= local_buffer_dbg(0); + DEBUG_OUT( 63 downto 48) <= local_buffer_dbg(1); + DEBUG_OUT( 79 downto 64) <= local_buffer_dbg(2); + DEBUG_OUT( 95 downto 80) <= local_buffer_dbg(3); + DEBUG_OUT(111 downto 96) <= local_buffer_dbg(4); + DEBUG_OUT(127 downto 112) <= local_buffer_dbg(5); + DEBUG_OUT(143 downto 128) <= local_buffer_dbg(6); + DEBUG_OUT(159 downto 144) <= local_buffer_dbg(7); + + DEBUG_OUT(175 downto 160) <= data_save_cnt; + DEBUG_OUT(176) <= local_buf_empty; + DEBUG_OUT(177) <= local_buffer(0)(8); + DEBUG_OUT(178) <= df_rdy; + DEBUG_OUT(179) <= eod_out; + DEBUG_OUT(180) <= data_trans_finished; + DEBUG_OUT(181) <= cri_apl_run; + DEBUG_OUT(182) <= cri_apl_dataready; + DEBUG_OUT(183) <= cri_apl_send; + DEBUG_OUT(184) <= cri_apl_read; + DEBUG_OUT(191 downto 185) <= cri_apl_data( 6 downto 0); + end architecture; diff --git a/combiner_cts/cri/cri_data_sender3.vhd b/combiner_cts/cri/cri_data_sender3.vhd deleted file mode 100644 index ba3fefa..0000000 --- a/combiner_cts/cri/cri_data_sender3.vhd +++ /dev/null @@ -1,712 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; ---USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; -USE IEEE.numeric_std.ALL; -library work; -use work.trb_net_std.all; - - -entity cri_data_sender is - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - ENABLE_TRANSPORT : in std_logic; - - -- Port to API - API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - API_DATAREADY_OUT : out std_logic; - API_READ_IN : in std_logic; - API_SHORT_TRANSFER_OUT : out std_logic; - API_DTYPE_OUT : out std_logic_vector (3 downto 0); - API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - API_SEND_OUT : out std_logic; - -- Receiver port - API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - API_TYP_IN : in std_logic_vector (2 downto 0); - API_DATAREADY_IN : in std_logic; - API_READ_OUT : out std_logic; - -- APL Control port - API_RUN_IN : in std_logic; - API_SEQNR_IN : in std_logic_vector (7 downto 0); - API_LENGTH_OUT : out std_logic_vector (15 downto 0); - MY_ADDRESS_IN : in std_logic_vector (15 downto 0); - - --data from event packer - CTS_NUMBER_IN : in std_logic_vector(15 downto 0); --not used; got it from FEE - CTS_CODE_IN : in std_logic_vector( 7 downto 0); --not used; got it from FEE - CTS_INFORMATION_IN : in std_logic_vector( 7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector( 3 downto 0); --not used; got it from FEE - CTS_START_READOUT_IN : in std_logic; - CTS_READ_IN : in std_logic; - CTS_DATA_OUT : out std_logic_vector(31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM - CTS_LENGTH_OUT : out std_logic_vector(15 downto 0); -- 0 terminated - CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- 0 terminated - -- Data from Frontends - FEE_DATA_IN : in std_logic_vector(15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; - FEE_BUSY_IN : in std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0); - - DEBUG_OUT : out std_logic_vector(191 downto 0) - ); -end entity; - -architecture cri_data_sender_arch of cri_data_sender is - - type save_states_t is (IDLE, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, SEND_TERM_PULSE, CLOSE, CLEANUP); - signal save_current_state, save_next_state : save_states_t; - - type data_sender_states_t is (IDLE, PREPARE_SEND, LOAD, FINISH_SEND, STOP_SEND, READ_ANSWER, FINISH_ACTION, CLEANUP); - signal send_state_current, send_state_next : data_sender_states_t; - - constant loc_buff_depth : integer := 4; - type loc_buffer_t is array (0 to loc_buff_depth) of std_logic_vector(16 downto 0); - signal local_buffer : loc_buffer_t := (others => (others=> '0')); - - signal rec_state, send_state_bits : std_logic_vector(3 downto 0); - - signal df_wr_en_qq, df_wr_en_q, df_wr_en,df_rd_en : std_logic; - signal df_data : std_logic_vector(15 downto 0); - signal df_eos_q, df_eos : std_logic; - signal fifo_almFull : std_logic; - signal df_afull, df_full_real : std_logic; - signal df_empty : std_logic; - signal df_wcnt : std_logic_vector(11 downto 0); - signal df_rdy_q, df_rdy : std_logic; - signal data_out, df_q : std_logic_vector(15 downto 0); - signal load_eod : std_logic; - signal fifo_rd_en : std_logic; - signal eod_out : std_logic; - signal local_buf_empty : std_logic; - - -- saving - signal cts_rnd, cts_trg : std_logic_vector(15 downto 0); - signal length_cnt : std_logic_vector(15 downto 0) := x"0000"; - - -- sending - signal cri_apl_reading : std_logic; - signal cri_apl_data : std_logic_vector(15 downto 0); - signal cri_apl_packet_num : std_logic_vector(2 downto 0); - signal cri_apl_dataready : std_logic; - signal cri_apl_read : std_logic; - signal data_trans_finished : std_logic; - signal load_data : std_logic; - signal tmp_data : std_logic_vector( 7 downto 0); - signal cri_apl_send : std_logic; - signal received_answer : std_logic; - signal cri_apl_run : std_logic; - - signal cri_event_cnt : std_logic_vector(15 downto 0) := x"0000"; - - signal cri_apl_answer_data : std_logic_vector(15 downto 0); - signal cri_apl_answer_packet_num : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal cri_apl_answer_typ : std_logic_vector( 2 downto 0); - signal cri_apl_answer_dataready : std_logic; - signal loaded_bytes : std_logic_vector(15 downto 0) := x"0000"; - signal cri_packet_num_cnt : std_logic_vector( 1 downto 0) := "00"; - - signal data_save_cnt : std_logic_vector(15 downto 0); - signal fee_read_loc : std_logic; - - signal data_open : std_logic; -- for modelsim - - type loc_buffer_dbg_t is array (0 to 7) of std_logic_vector(15 downto 0); - signal local_buffer_dbg : loc_buffer_dbg_t := (others => (others=> '0')); -begin - - CTS_LENGTH_OUT <= (others => '0'); - CTS_ERROR_PATTERN_OUT <= (others => '0'); - - SAVE_MACHINE_PROC : process(RESET, CLK) - begin - if RESET = '1' then - save_current_state <= IDLE; - elsif rising_edge(CLK) then - save_current_state <= save_next_state; - end if; - end process; - - SAVE_MACHINE : process(save_current_state, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN) - begin - rec_state <= x"0"; - case (save_current_state) is - when IDLE => - rec_state <= x"1"; - if (CTS_START_READOUT_IN = '1') then - save_next_state <= WAIT_FOR_DATA; - else - save_next_state <= IDLE; - end if; - - when WAIT_FOR_DATA => - rec_state <= x"2"; - if (FEE_BUSY_IN = '1') then - save_next_state <= SAVE_DATA; - else - save_next_state <= WAIT_FOR_DATA; - end if; - - when SAVE_DATA => - rec_state <= x"3"; - if (FEE_BUSY_IN = '0') then - save_next_state <= TERMINATE; - else - save_next_state <= SAVE_DATA; - end if; - - when TERMINATE => - rec_state <= x"5"; - if (CTS_READ_IN = '1') then - save_next_state <= SEND_TERM_PULSE; --CLOSE; - else - save_next_state <= TERMINATE; - end if; - - when SEND_TERM_PULSE => - rec_state <= x"6"; - save_next_state <= CLOSE; - - when CLOSE => - rec_state <= x"6"; - save_next_state <= ADD_SUBSUB1; - - when ADD_SUBSUB1 => - rec_state <= x"7"; - save_next_state <= ADD_SUBSUB2; - - when ADD_SUBSUB2 => - rec_state <= x"8"; - save_next_state <= ADD_SUBSUB3; - - when ADD_SUBSUB3 => - rec_state <= x"9"; - save_next_state <= ADD_SUBSUB4; - - when ADD_SUBSUB4 => - rec_state <= x"a"; - save_next_state <= CLEANUP; - - when CLEANUP => - rec_state <= x"c"; - if (CTS_START_READOUT_IN = '0') then - save_next_state <= IDLE; - else - save_next_state <= CLEANUP; - end if; - - when others => save_next_state <= IDLE; - - end case; - end process; - - CTS_DATAREADY_PROC : process(CLK) - begin - if rising_edge(CLK) then - if (save_current_state = SAVE_DATA and FEE_BUSY_IN = '0') then - CTS_DATAREADY_OUT <= '1'; - elsif (save_current_state = TERMINATE) then - CTS_DATAREADY_OUT <= '1'; - else - CTS_DATAREADY_OUT <= '0'; - end if; - end if; - end process; - - CTS_READOUT_FINISHED_PROC : process(CLK) - begin - if rising_edge(CLK) then - if (save_current_state = CLEANUP) then - CTS_READOUT_FINISHED_OUT <= '1'; - else - CTS_READOUT_FINISHED_OUT <= '0'; - end if; - end if; - end process; - - CTS_DATA_PROC : process(CLK) - begin - if rising_edge(CLK) then - CTS_DATA_OUT <= "0001" & cts_rnd(11 downto 0) & cts_trg; - end if; - end process; - - CTS_RND_TRG_PROC : process(CLK) - begin - if rising_edge(CLK) then - if ((save_current_state = SAVE_DATA) and - (FEE_DATAREADY_IN = '1') and - (fee_read_loc = '1')) - then - if (length_cnt = x"0000") then - cts_rnd <= FEE_DATA_IN; - end if; - - if (length_cnt = x"0001") then - cts_trg <= FEE_DATA_IN; - end if; - else - cts_rnd <= cts_rnd; - cts_trg <= cts_trg; - end if; - end if; - end process; - - CTS_WORD_CNT : process(CLK) - begin - if rising_edge(CLK) then - if (save_current_state = IDLE) then - length_cnt <= (others => '0'); - elsif ((save_current_state = SAVE_DATA) and (FEE_DATAREADY_IN = '1') and (fee_read_loc = '1')) then - length_cnt <= length_cnt + 1; - else - length_cnt <= length_cnt; - end if; - end if; - end process; - - - DATA_WRITE_PROC : process begin - wait until rising_edge(CLK); - if ((save_current_state = SAVE_DATA) and (FEE_DATAREADY_IN = '1') and (fee_read_loc = '1')) then - df_wr_en <= '1'; - elsif (save_current_state = ADD_SUBSUB1 or save_current_state = ADD_SUBSUB2 or save_current_state = ADD_SUBSUB3 or save_current_state = ADD_SUBSUB4) then - df_wr_en <= '1'; - else - df_wr_en <= '0'; - end if; - end process; - --- FEE_READ_PROC : process(CLK) --- begin --- if rising_edge(CLK) then --- if (save_current_state = SAVE_DATA) then --- if (df_afull = '0') then --- local_read <= '1'; --- else --- local_read <= '0'; --- end if; --- else --- local_read <= '1'; --- end if; --- end if; --- end process FEE_READ_PROC; - - SF_DATA_EOD_PROC : process begin - wait until rising_edge(CLK); - case (save_current_state) is - when SAVE_DATA => - df_data <= FEE_DATA_IN; - df_eos_q <= '0'; - - when ADD_SUBSUB1 => - df_data <= x"0001"; - df_eos_q <= '0'; - - when ADD_SUBSUB2 => - df_data <= x"5555"; - df_eos_q <= '0'; - - when ADD_SUBSUB3 => - df_data <= FEE_STATUS_BITS_IN(31 downto 16); - df_eos_q <= '0'; - - when ADD_SUBSUB4 => - df_data <= FEE_STATUS_BITS_IN(15 downto 0); - df_eos_q <= '1'; - - when others => - df_data <= df_data; - df_eos_q <= '0'; - - end case; - end process; - - FEE_READ_OUT <= fee_read_loc; - fee_read_loc <= not df_afull;--local_read; - --- DATA_FIFO : entity work.fifo_64kx9_af_cnt --- port map( --- Data(15 downto 0) => df_data, --- Data(16) => df_eos_q, --- WrClock => CLK, --- RdClock => CLK, --- WrEn => df_wr_en, --- RdEn => df_rd_en, --- Reset => RESET, --- RPReset => RESET, --- Q(15 downto 0) => df_q, --- Q(16) => load_eod, --- Empty => df_empty, --- Full => df_full_real, --- AlmostFull => df_afull, --- WCNT => df_wcnt --- ); - - DATA_FIFO : entity work.fifo_18x2k_oreg - port map ( - Data(15 downto 0) => df_data, - Data(16) => df_eos_q, - Data(17) => '0', - Clock => CLK, - WrEn => df_wr_en, - RdEn => df_rd_en, - Reset => RESET, - AmFullThresh => b"11111111000", - Q(15 downto 0) => data_out,--df_q, --df_q if fifo is without outreg - Q(16) => eod_out,--load_eod, --load_eod if fifo is without outreg - Q(17) => data_open, - WCNT => df_wcnt, - Empty => df_empty, - Full => df_full_real, - AlmostFull => df_afull - ); - - --READ from FIFO to TrbNet API - - df_rd_en <= load_data and not df_empty and local_buf_empty; - - load_data <= '1' when send_state_current = LOAD else '0'; - - DATA_FIFO_CONTRL_PROC : process begin - wait until rising_edge(CLK); - if RESET = '1' then - df_rdy_q <= '0'; - df_rdy <= '0'; - --data_out <= x"0000"; - --eod_out <= '0'; - else - df_rdy_q <= df_rd_en; - df_rdy <= df_rdy_q; -- delay from readout reg of fifo - - --data_out <= df_q; -- readout reg for fifo - --eod_out <= load_eod; - end if; - end process; - - - LOCAL_BUFF_PROC : process - variable buff_cnt : integer range 0 to loc_buff_depth := 0; - begin - wait until rising_edge(CLK); - if RESET = '1' then - buff_cnt := 0; - else - - -- Data from sub is loaded; first data from following sub is (partialy) loaded - if (send_state_current /= LOAD) and (df_rdy = '1') then - local_buffer(buff_cnt) <= eod_out & data_out; - buff_cnt := buff_cnt + 1; - end if; - - -- first word in buffer is always in 0; is loaded in sending process. - if (send_state_current = LOAD) and (local_buf_empty = '0') then - local_buffer(0) <= local_buffer(1); - local_buffer(1) <= local_buffer(2); - local_buffer(2) <= local_buffer(3); - local_buffer(3) <= local_buffer(4); - local_buffer(4) <= (others => '0'); - buff_cnt := buff_cnt - 1; - end if; - - -- has to be atthis position, to garantee that buff_cnt won't be negative - if buff_cnt = 0 then - local_buf_empty <= '1'; - else - local_buf_empty <= '0'; - end if; - - end if; - end process; - - - SEND_STATE_PROC : process(RESET, CLK) - begin - if RESET = '1' then - send_state_current <= IDLE; - else - if rising_edge(CLK) then - send_state_current <= send_state_next; - end if; - end if; - end process; - - - SEND_STATE_MACHINE : process(send_state_current, cri_apl_reading, ENABLE_TRANSPORT, eod_out, df_rdy,local_buf_empty,local_buffer(0)(8),data_trans_finished,received_answer,cri_apl_run) - begin - send_state_bits <= x"0"; - case send_state_current is - when IDLE => - send_state_bits <= x"1"; - send_state_next <= PREPARE_SEND; - - when PREPARE_SEND => - send_state_bits <= x"2"; - if cri_apl_reading = '1' and ENABLE_TRANSPORT = '1' then - send_state_next <= LOAD; - else - send_state_next <= PREPARE_SEND; - end if; - - when LOAD => - send_state_bits <= x"3"; - if (eod_out = '1' and df_rdy = '1') then--or ( local_buf_empty = '0' and local_buffer(0)(8) = '1' )) then --last word of subevent is currently in data_out - send_state_next <= FINISH_SEND; - else - send_state_next <= LOAD; - end if; - - when FINISH_SEND => - send_state_bits <= x"4"; - if data_trans_finished = '1' then - send_state_next <= STOP_SEND; - else - send_state_next <= FINISH_SEND; - end if; - - when STOP_SEND => - send_state_bits <= x"5"; - send_state_next <= READ_ANSWER; - - when READ_ANSWER => - send_state_bits <= x"6"; - if received_answer = '1' then - send_state_next <= FINISH_ACTION; - else - send_state_next <= READ_ANSWER; - end if; - - when FINISH_ACTION => - send_state_bits <= x"7"; - if cri_apl_run = '0' then - send_state_next <= PREPARE_SEND; - else - send_state_next <= FINISH_ACTION; - end if; - - when others => - send_state_bits <= x"8"; - send_state_next <= IDLE; - - end case; - end process; - - - - DATA_TRANSPORT_PROC : process - variable loc_tmp_data : std_logic_vector(15 downto 0); - variable loc_data_rdy : std_logic; - --variable pos_cnt : std_logic := '0'; - begin - wait until rising_edge(CLK); - - cri_apl_dataready <= '0'; - data_trans_finished <= '0'; - - if RESET = '1' then - loc_tmp_data := x"0000"; - loc_data_rdy := '0'; - --tmp_data <= x"00"; - --pos_cnt := '0'; - loaded_bytes <= (others => '0'); - else - --prepare data - loc_data_rdy := '0'; - if (send_state_current = LOAD) then -- load state data - -- get data from correct source - if (local_buf_empty = '0') then - loc_tmp_data := local_buffer(0)(15 downto 0); - loc_data_rdy := '1'; - else - loc_tmp_data := data_out; - loc_data_rdy := df_rdy; - end if; - end if; - - if (send_state_current = LOAD) then -- or (send_state_current = FINISH_SEND)) then - -- put data in 16 bits - if loc_data_rdy = '1' then -- only process if data is valid/rdy --- if (pos_cnt = '1') then - cri_apl_dataready <= '1'; - cri_packet_num_cnt <= cri_packet_num_cnt + 1; - loaded_bytes <= loaded_bytes + 1; --- pos_cnt := '0'; --- else --- tmp_data <= loc_tmp_data; --- pos_cnt := '1'; --- end if; - cri_apl_data <= loc_tmp_data;-- & tmp_data; --maybe wrong order! - cri_apl_packet_num <= '0' & std_logic_vector(cri_packet_num_cnt); - end if; -- end data rdy - end if;-- load state - - - -- finish the send process: - -- packet if last word in LOAD was not send, send it now. - if (send_state_current = FINISH_SEND) then - -- one word was loaded, but never send out! - --if (pos_cnt = '1') then - -- cri_apl_dataready <= '1'; - -- cri_packet_num_cnt <= cri_packet_num_cnt + 1; - -- loaded_bytes <= loaded_bytes + 1; - -- cri_apl_data <= loc_tmp_data & x"00"; --maybe wrong order! - -- cri_apl_packet_num <= '0' & std_logic_vector(cri_packet_num_cnt); - --else - if (cri_packet_num_cnt = "00") then - data_trans_finished <= '1'; - cri_apl_packet_num <= '0' & std_logic_vector(cri_packet_num_cnt); - else - cri_packet_num_cnt <= cri_packet_num_cnt + 1; - cri_apl_packet_num <= '0' & std_logic_vector(cri_packet_num_cnt); - cri_apl_dataready <= '1'; - cri_apl_data <= x"BBBB"; - end if; - --end if; - --pos_cnt := '0'; - end if; -- FINISH_SEND - - -- to be sure that cntr is null in next data sending process. - if (data_trans_finished = '1') then - cri_packet_num_cnt <= "00"; - loaded_bytes <= (others => '0'); - end if; - - if ((loaded_bytes > x"0000") and (loaded_bytes < x"0009") and (cri_apl_dataready = '1')) then - local_buffer_dbg(to_integer( unsigned( loaded_bytes )-1) ) <= cri_apl_data; - end if; - - end if; - end process; - - - - -- handle the data sending flag to the trbnet APL - DATA_SEND_OUT_PROC : process begin - wait until rising_edge(CLK); - if RESET = '1' then - cri_apl_send <= '0'; - else - if ((send_state_current = PREPARE_SEND) or - (send_state_current = LOAD) or - (send_state_current = FINISH_SEND) or - (send_state_current = STOP_SEND)) - then - cri_apl_send <= '1'; - else - cri_apl_send <= '0'; - end if; - end if; - end process; - - - - -- handle the read flag to the trbnet APL - DATA_READ_OUT_PROC : process begin - wait until rising_edge(CLK); - if RESET = '1' then - cri_apl_read <= '0'; - else - --if ((send_state_current /= IDLE) then - if (( send_state_current = READ_ANSWER ) or - ( send_state_current = STOP_SEND )) - then - cri_apl_read <= '1'; - else - cri_apl_read <= '0'; - end if; - end if; - end process; - - - - -- handle the answer from CRI over trbnet - EVENT_CNT_PROC : process begin - wait until rising_edge(CLK); - if RESET = '1' then - received_answer <= '0'; - cri_event_cnt <= (others => '0'); - else - received_answer <= '0'; - if ((cri_apl_answer_dataready = '1') and (cri_apl_answer_typ = TYPE_TRM) and (cri_apl_answer_packet_num = c_F3)) then - --cri_data_send_cnt <= 0; - cri_event_cnt <= cri_event_cnt + 1; - received_answer <= '1'; - end if; - end if; - end process; - - --- DEBUG_OUT - DATA_SAVE_CNT_PROC : process begin - wait until rising_edge(CLK); - if RESET = '1' then - data_save_cnt <= (others => '0'); - else - if ((save_current_state = CLEANUP) and (CTS_START_READOUT_IN = '0')) then - data_save_cnt <= data_save_cnt + 1; - end if; - end if; - end process; - - - -- Data to CRI board - API_DATA_OUT <= cri_apl_data; - API_PACKET_NUM_OUT <= cri_apl_packet_num; - API_DATAREADY_OUT <= cri_apl_dataready; - cri_apl_reading <= API_READ_IN; - - API_SHORT_TRANSFER_OUT <= '0'; - API_DTYPE_OUT <= (others => '0'); - API_ERROR_PATTERN_OUT <= (others => '0'); - API_SEND_OUT <= cri_apl_send; - - cri_apl_answer_data <= API_DATA_IN; - cri_apl_answer_packet_num <= API_PACKET_NUM_IN; - cri_apl_answer_typ <= API_TYP_IN; - cri_apl_answer_dataready <= API_DATAREADY_IN; - - API_READ_OUT <= cri_apl_read; - -- APL Control port - cri_apl_run <= API_RUN_IN; - API_LENGTH_OUT <= (others => '0'); - - DEBUG_OUT(3 downto 0) <= rec_state; - DEBUG_OUT(7 downto 4) <= send_state_bits; - DEBUG_OUT( 8) <= df_empty; - DEBUG_OUT( 9) <= df_full_real; - DEBUG_OUT(10) <= df_afull; - DEBUG_OUT(11) <= '0'; - DEBUG_OUT(14 downto 12) <= cri_apl_packet_num; - DEBUG_OUT(15) <= '0'; - DEBUG_OUT(31 downto 16) <= cri_event_cnt; - - DEBUG_OUT( 47 downto 32) <= local_buffer_dbg(0); - DEBUG_OUT( 63 downto 48) <= local_buffer_dbg(1); - DEBUG_OUT( 79 downto 64) <= local_buffer_dbg(2); - DEBUG_OUT( 95 downto 80) <= local_buffer_dbg(3); - DEBUG_OUT(111 downto 96) <= local_buffer_dbg(4); - DEBUG_OUT(127 downto 112) <= local_buffer_dbg(5); - DEBUG_OUT(143 downto 128) <= local_buffer_dbg(6); - DEBUG_OUT(159 downto 144) <= local_buffer_dbg(7); - - DEBUG_OUT(175 downto 160) <= data_save_cnt; - DEBUG_OUT(176) <= local_buf_empty; - DEBUG_OUT(177) <= local_buffer(0)(8); - DEBUG_OUT(178) <= df_rdy; - DEBUG_OUT(179) <= eod_out; - DEBUG_OUT(180) <= data_trans_finished; - DEBUG_OUT(181) <= cri_apl_run; - DEBUG_OUT(182) <= cri_apl_dataready; - DEBUG_OUT(183) <= cri_apl_send; - DEBUG_OUT(184) <= cri_apl_read; - DEBUG_OUT(191 downto 185) <= cri_apl_data( 6 downto 0); - -end architecture; diff --git a/combiner_cts/cri/trb_net16_cri_interface.vhd b/combiner_cts/cri/trb_net16_cri_interface.vhd index 49f4517..0a10412 100644 --- a/combiner_cts/cri/trb_net16_cri_interface.vhd +++ b/combiner_cts/cri/trb_net16_cri_interface.vhd @@ -1,6 +1,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.numeric_std.all; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; library work; use work.version.all; @@ -182,13 +183,35 @@ architecture arch of trb_net16_cri_interface is signal dbg_api_fifo_to_int : std_logic_vector(31 downto 0); signal dbg_api_fifo_to_api : std_logic_vector(31 downto 0); - signal dbg_start_data_send : std_logic; + signal dbg_start_data_send : std_logic := '0'; signal dbg_io_dataready_cnt_2 : unsigned(15 downto 0); signal dbg_io_dataready_cnt_3 : unsigned(15 downto 0); signal dbg_io_dataready_cnt_6 : unsigned(15 downto 0); signal dbg_io_dataready_cnt_7 : unsigned(15 downto 0); + signal resp_ready_q : std_logic := '0'; + signal resp_ready_qq : std_logic := '0'; + signal resp_ready_3q : std_logic := '0'; + signal resp_ready_4q : std_logic := '0'; + signal resp_ready_5q : std_logic := '0'; + signal resp_ready_6q : std_logic := '0'; + + signal tc_data_rdy : std_logic; + + signal tmp_data, ipu_data : std_logic_vector( 7 downto 0); + + signal ipu_wr_en, ipu_wr_en_q, ipu_wr_en_qq, ipu_wr_en_qqq : std_logic; + signal ipu_sos_out_q, ipu_sos_out_qq, ipu_sos_out_qqq : std_logic; + signal ipu_eod_out_q, ipu_eod_out_qq, ipu_eod_out_qqq : std_logic; + signal ipu_data_start, ipu_data_end : std_logic; + signal ipu_sub_size : std_logic_vector(31 downto 0); + + signal ipu_ready_in : std_logic; + signal ipu_start_rdy : std_logic; + signal loaded_bytes : std_logic_vector(15 downto 0); + + signal debug_sender :std_logic_vector(191 downto 0); begin --------------------------------------------------------------------- @@ -245,238 +268,83 @@ begin --------------------------------------------------------------------- trbnet_gen : if INCLUDE_READOUT = 1 generate - TrbNetData : entity work.trb_net16_cri_response_constructor_TrbNetData - generic map( - RX_PATH_ENABLE => 0, - DO_SIMULATION => 0, - READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE - ) - port map( - CLK => CLK, - RESET => reset_i_mux_io, - - -- INTERFACE - MY_MAC_IN => (others => '0'), - MY_IP_IN => (others => '0'), - PS_DATA_IN => (others => '0'), - PS_WR_EN_IN => '0', - PS_ACTIVATE_IN => '0', - PS_RESPONSE_READY_OUT => resp_ready, -- TODO: make use of it - PS_BUSY_OUT => resp_busy,--busy(3), -- TODO: make use of it - PS_SELECTED_IN => '1', - PS_SRC_MAC_ADDRESS_IN => (others => '0'), - PS_DEST_MAC_ADDRESS_IN => (others => '0'), - PS_SRC_IP_ADDRESS_IN => (others => '0'), - PS_DEST_IP_ADDRESS_IN => (others => '0'), - PS_SRC_UDP_PORT_IN => (others => '0'), - PS_DEST_UDP_PORT_IN => (others => '0'), - - -- BEGIN TODO : Connect this to the ouside world. Now data is just thrown away - TC_RD_EN_IN => tc_rd_en,--'1',--TC_RD_EN_IN, - TC_DATA_OUT => tc_data,--tc_data(4 * 9 - 1 downto 3 * 9), - TC_FRAME_SIZE_OUT => tc_size,--tc_size(4 * 16 - 1 downto 3 * 16), - TC_FRAME_TYPE_OUT => open,--tc_type(4 * 16 - 1 downto 3 * 16), - TC_IP_PROTOCOL_OUT => open,--tc_ip_proto(4 * 8 - 1 downto 3 * 8), - TC_IDENT_OUT => open,--tc_ident(4 * 16 - 1 downto 3 * 16), - -- END TODO - - TC_DEST_MAC_OUT => open, - TC_DEST_IP_OUT => open, - TC_DEST_UDP_OUT => open, - TC_SRC_MAC_OUT => open, - TC_SRC_IP_OUT => open, - TC_SRC_UDP_OUT => open, - STAT_DATA_OUT => open, - STAT_ADDR_OUT => open, - STAT_DATA_RDY_OUT => open, - STAT_DATA_ACK_IN => '0', -- not used in code - DEBUG_OUT => debug_resp_control,--MONITOR_SELECT_GEN_DBG_OUT(4 * 64 - 1 downto 3 * 64), - -- END OF INTERFACE - - -- CTS interface - CTS_NUMBER_IN => CTS_NUMBER_IN, - CTS_CODE_IN => CTS_CODE_IN, - CTS_INFORMATION_IN => CTS_INFORMATION_IN, - CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, - CTS_START_READOUT_IN => CTS_START_READOUT_IN, - CTS_DATA_OUT => open, - CTS_DATAREADY_OUT => open, - CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, - CTS_READ_IN => '1', - CTS_LENGTH_OUT => open, - CTS_ERROR_PATTERN_OUT => CTS_STATUS_BITS_OUT, - -- Data payload interface - FEE_DATA_IN => FEE_DATA_IN, - FEE_DATAREADY_IN => FEE_DATAREADY_IN, - FEE_READ_OUT => FEE_READ_OUT, - FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, - FEE_BUSY_IN => FEE_BUSY_IN, - -- ip configurator - SLV_ADDR_IN => (others => '0'), - SLV_READ_IN => '0', - SLV_WRITE_IN => '0', - SLV_BUSY_OUT => open, - SLV_ACK_OUT => open, - SLV_DATA_IN => (others => '0'), - SLV_DATA_OUT => open, - CFG_GBE_ENABLE_IN => cfg_gbe_enable, - CFG_IPU_ENABLE_IN => cfg_ipu_enable, - CFG_MULT_ENABLE_IN => cfg_mult_enable, - CFG_SUBEVENT_ID_IN => cfg_subevent_id, - CFG_SUBEVENT_DEC_IN => cfg_subevent_dec, - CFG_QUEUE_DEC_IN => cfg_queue_dec, - CFG_READOUT_CTR_IN => cfg_readout_ctr, - CFG_READOUT_CTR_VALID_IN => cfg_readout_ctr_valid, - CFG_INSERT_TTYPE_IN => cfg_insert_ttype, - CFG_MAX_SUB_IN => cfg_max_sub, - CFG_MAX_QUEUE_IN => cfg_max_queue, - CFG_MAX_SUBS_IN_QUEUE_IN => cfg_max_subs_in_queue, - CFG_MAX_SINGLE_SUB_IN => cfg_max_single_sub, - CFG_AUTO_THROTTLE_IN => '0', - CFG_THROTTLE_PAUSE_IN => (others => '0'), - MONITOR_SELECT_REC_OUT => open, - MONITOR_SELECT_REC_BYTES_OUT => open, - MONITOR_SELECT_SENT_BYTES_OUT => open, - MONITOR_SELECT_SENT_OUT => open, - MONITOR_SELECT_DROP_OUT_OUT => open, - MONITOR_SELECT_DROP_IN_OUT => open, - DATA_HIST_OUT => open,--DATA_HIST_OUT - - BUS_DBG_RX => BUS_DBG_RX, - BUS_DBG_TX => BUS_DBG_TX, - - --debuging for TrbNet Transfer - dbg_event_cnt => cri_event_cnt, - dbg_data_send_cnt => cri_data_send_cnt, - dbg_api_fifo_to_int => dbg_api_fifo_to_int, - dbg_api_fifo_to_api => dbg_api_fifo_to_api, - dbg_start_data_send => dbg_start_data_send, - - dbg_io_datardy_data(15 downto 0) => std_logic_vector(dbg_io_dataready_cnt_2), - dbg_io_datardy_data(31 downto 16) => std_logic_vector(dbg_io_dataready_cnt_3), - - dbg_io_datardy_slwc(15 downto 0) => std_logic_vector(dbg_io_dataready_cnt_6), - dbg_io_datardy_slwc(31 downto 16) => std_logic_vector(dbg_io_dataready_cnt_7) - ); - - - THE_CRI_READOUT_CONTROL : process begin - wait until rising_edge(CLK); - if RESET = '1' then - --tc_rd_en <= '0'; - cri_packet_num_cnt <= 0; - cri_data_send_cnt <= 0; - cri_event_cnt <= 0; - - dbg_io_dataready_cnt_2 <= 0; - dbg_io_dataready_cnt_3 <= 0; - dbg_io_dataready_cnt_6 <= 0; - dbg_io_dataready_cnt_7 <= 0; - - else --- if resp_ready = '1' then --maybe not good in timing; then maybe event_bytes != loaded_bytes for ever --- tc_rd_en <= '1'; --- else --- tc_rd_en <= '0'; --includes also busy state --- end if; - -- Test of readout - if (debug_resp_control(35 downto 32) <= x"2") then - -- if (resp_busy = '0') then - tc_rd_en <= '0'; - else - tc_rd_en <= '1'; - end if; - -- END Test of readout - - - --Test of data Sending - --TODO: FRIDAY 7.3.: STart over slowcontrol; monitor dataout on data channel to multiplexer! DONE - 2020-07-6 - if dbg_start_data_send = '1' then - if (cri_data_send_cnt < 32 ) then - cri_send <= '1'; - else - cri_send <= '0'; - --if (cri_apl_run_out = '0') then -- data transfer has finished and the reply is in - if cri_apl_dataready_out = '1' and cri_apl_read_in = '1' and cri_apl_typ_out = TYPE_TRM then - cri_data_send_cnt <= 0; - cri_event_cnt <= cri_event_cnt + 1; - end if; - end if; - - -- Write only if buffer in api is not full - if cri_apl_read_out = '1' and cri_send = '1' then --TODO: add fifo dataready for real dataflow - cri_apl_dataready_in <= '1'; - cri_apl_data_in <= x"1234"; - cri_apl_packet_num_in <= '0' & std_logic_vector(cri_packet_num_cnt); - cri_packet_num_cnt <= cri_packet_num_cnt + 1; - cri_apl_send_in <= '1'; - cri_data_send_cnt <= cri_data_send_cnt + 1; - else - cri_apl_send_in <= '0'; - cri_apl_dataready_in <= '0'; - end if; - cri_apl_read_in <= '1'; - end if; - --END Test of data Sending - - if io_dataready_out(2) = '1' then - dbg_io_dataready_cnt_2 <= dbg_io_dataready_cnt_2 + 1; - end if; - - if io_dataready_out(3) = '1' then - dbg_io_dataready_cnt_3 <= dbg_io_dataready_cnt_3 + 1; - end if; - - if io_dataready_out(6) = '1' then - dbg_io_dataready_cnt_6 <= dbg_io_dataready_cnt_6 + 1; - end if; - - if io_dataready_out(7) = '1' then - dbg_io_dataready_cnt_7 <= dbg_io_dataready_cnt_7 + 1; - end if; - end if; - end process; - --- THE_CRI_DATA_SENDER : entity work.cri_data_sender --- port map( --- -- Misc --- CLK => CLK, --- RESET => reset_i, --- CLK_EN => '1', --- -- Port to API --- API_DATA_OUT => cri_apl_data_in, --- API_PACKET_NUM_OUT => cri_apl_packet_num_in, --- API_DATAREADY_OUT => cri_apl_dataready_in, --- API_READ_IN => cri_apl_read_out, --- API_SHORT_TRANSFER_OUT => open, --- API_DTYPE_OUT => open, --- API_ERROR_PATTERN_OUT => open, --- API_SEND_OUT => cri_apl_send_in, --- -- Receiver port --- API_DATA_IN => cri_apl_data_out, --- API_PACKET_NUM_IN => cri_apl_packet_num_out, --- API_TYP_IN => cri_apl_typ_out, --- API_DATAREADY_IN => cri_apl_dataready_out, --- API_READ_OUT => cri_apl_read_in, --- -- APL Control port --- API_RUN_IN => cri_apl_run_out, --- API_SEQNR_IN => (others => '0'), --- API_LENGTH_OUT => open, --- MY_ADDRESS_IN => MY_ADDRESS_IN, --- --- --data from event packer --- CRI_DATA_IN => tc_data, --8 is EOD --- CRI_DATAREADY_IN => resp_ready, --- --no more data, send TRM --- CRI_READOUT_FINISHED_IN => cri_readout_finished_in, --currently not used --- CRI_READ_OUT => tc_rd_en, --- CRI_LENGTH_IN => tc_size, --- --- STAT_DEBUG => open --- ); --- --- cri_readout_finished_in <= resp_busy and not resp_ready; - + THE_CRI_DATA_SENDER : entity work.cri_data_sender + port map( + -- Misc + CLK => CLK, + RESET => reset_i, + CLK_EN => '1', + + ENABLE_TRANSPORT => '1',--dbg_start_data_send, + + -- Port to API + API_DATA_OUT => cri_apl_data_in, + API_PACKET_NUM_OUT => cri_apl_packet_num_in, + API_DATAREADY_OUT => cri_apl_dataready_in, + API_READ_IN => cri_apl_read_out, + API_SHORT_TRANSFER_OUT => open, + API_DTYPE_OUT => open, + API_ERROR_PATTERN_OUT => open, + API_SEND_OUT => cri_apl_send_in, + -- Receiver port + API_DATA_IN => cri_apl_data_out, + API_PACKET_NUM_IN => cri_apl_packet_num_out, + API_TYP_IN => cri_apl_typ_out, + API_DATAREADY_IN => cri_apl_dataready_out, + API_READ_OUT => cri_apl_read_in, + -- APL Control port + API_RUN_IN => cri_apl_run_out, + API_SEQNR_IN => (others => '0'), + API_LENGTH_OUT => open, + MY_ADDRESS_IN => MY_ADDRESS_IN, + + CTS_NUMBER_IN => CTS_NUMBER_IN, + CTS_CODE_IN => CTS_CODE_IN, + CTS_INFORMATION_IN => CTS_INFORMATION_IN, + CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, + CTS_START_READOUT_IN => CTS_START_READOUT_IN, + CTS_READ_IN => '1', + CTS_DATA_OUT => open, + CTS_DATAREADY_OUT => open, + CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, + CTS_LENGTH_OUT => open, + CTS_ERROR_PATTERN_OUT => CTS_STATUS_BITS_OUT, + -- Data from Frontends + FEE_DATA_IN => FEE_DATA_IN, + FEE_DATAREADY_IN => FEE_DATAREADY_IN, + FEE_READ_OUT => FEE_READ_OUT, + FEE_BUSY_IN => FEE_BUSY_IN, + FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, + + DEBUG_OUT => debug_sender + ); + + THE_CRI_DATARDY_DBG : process begin + wait until rising_edge(CLK); + if RESET = '1' then + dbg_io_dataready_cnt_2 <= 0; + dbg_io_dataready_cnt_3 <= 0; + dbg_io_dataready_cnt_6 <= 0; + dbg_io_dataready_cnt_7 <= 0; + else + if io_dataready_out(2) = '1' then + dbg_io_dataready_cnt_2 <= dbg_io_dataready_cnt_2 + 1; + end if; + + if io_dataready_out(3) = '1' then + dbg_io_dataready_cnt_3 <= dbg_io_dataready_cnt_3 + 1; + end if; + + if io_dataready_out(6) = '1' then + dbg_io_dataready_cnt_6 <= dbg_io_dataready_cnt_6 + 1; + end if; + + if io_dataready_out(7) = '1' then + dbg_io_dataready_cnt_7 <= dbg_io_dataready_cnt_7 + 1; + end if; + end if; + end process; + --------------------------------------------------------------------- -- active API for Data Channel --------------------------------------------------------------------- @@ -691,10 +559,7 @@ begin MONITOR_OUT => open, DEBUG_OUT => open ); --- --Clean Data Output --- CTS_READOUT_FINISHED_OUT <= '1'; --- CTS_STATUS_BITS_OUT <= (others => '0'); --- FEE_READ_OUT <= '0'; --maybe high if idle? + end generate no_readout_gen; @@ -998,6 +863,76 @@ begin end if; end process; end generate debug_gen; + +debug_gen : if INCLUDE_READOUT = 1 generate + + + THE_CRI_READOUT_DEBUG : process begin + wait until rising_edge(CLK); + BUS_DBG_TX.ack <= '0'; + BUS_DBG_TX.nack <= '0'; + BUS_DBG_TX.unknown <= '0'; + + if BUS_DBG_RX.read = '1' then + if BUS_DBG_RX.addr(7 downto 0) = x"00" then + BUS_DBG_TX.data <= debug_sender(31 downto 0); + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"01" then + BUS_DBG_TX.data(0) <= dbg_start_data_send; + BUS_DBG_tX.data(31 downto 1) <= (others => '0'); + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"02" then + BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(dbg_io_dataready_cnt_2); + BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(dbg_io_dataready_cnt_3); + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"03" then + BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(dbg_io_dataready_cnt_6); + BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(dbg_io_dataready_cnt_7); + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"04" then + BUS_DBG_TX.data <= debug_sender(63 downto 32); + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"05" then + BUS_DBG_TX.data <= debug_sender(95 downto 64); + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"06" then + BUS_DBG_TX.data <= debug_sender(127 downto 96); + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"07" then + BUS_DBG_TX.data <= debug_sender(159 downto 128); + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"08" then + BUS_DBG_TX.data <= debug_sender(191 downto 160); + BUS_DBG_TX.ack <= '1'; + end if; + + elsif BUS_DBG_RX.write = '1' then + + if BUS_DBG_RX.addr( 7 downto 0) = x"01" then + dbg_start_data_send <= BUS_DBG_RX.data(0); + BUS_DBG_TX.ack <= '1'; + end if; + + + end if; + end process; + end generate debug_gen; end architecture; diff --git a/combiner_cts/cri/trb_net16_cri_interface3.vhd b/combiner_cts/cri/trb_net16_cri_interface3.vhd deleted file mode 100644 index 7f43572..0000000 --- a/combiner_cts/cri/trb_net16_cri_interface3.vhd +++ /dev/null @@ -1,991 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.version.all; -use work.config.all; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb3_components.all; -use work.trb_net16_hub_func.all; -use work.trb_net_gbe_components.all; -use work.trb_net_gbe_protocols.all; -use work.med_sync_define.all; - -entity trb_net16_cri_interface is - generic( - INCLUDE_READOUT : integer range 0 to 1 := 1; - INCLUDE_SLOWCTRL : integer range 0 to 1 := 1; - READOUT_BUFFER_SIZE : integer range 1 to 4 := 1 - ); - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - --Media Interface - MEDIA_MED2INT : in med2int_array_t(0 to 0); - MEDIA_INT2MED : out int2med_array_t(0 to 0); - - MY_ADDRESS_IN : in std_logic_vector(15 downto 0); - - --Event information coming from CTS for CRI - CTS_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_CODE_IN : in std_logic_vector (7 downto 0); - CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_START_READOUT_IN : in std_logic; - - --Information sent to CTS - CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM - CTS_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); - - --Data from Frontends - FEE_DATA_IN : in std_logic_vector (15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; --must be high when idle, otherwise you will never get a dataready - FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - FEE_BUSY_IN : in std_logic; - - --Gbe Sctrl Input - GSC_INIT_DATAREADY_OUT : out std_logic; - GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); - GSC_INIT_PACKET_NUM_OUT : out std_logic_vector( 2 downto 0); - GSC_INIT_READ_IN : in std_logic; - GSC_REPLY_DATAREADY_IN : in std_logic; - GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); - GSC_REPLY_PACKET_NUM_IN : in std_logic_vector( 2 downto 0); - GSC_REPLY_READ_OUT : out std_logic; - GSC_BUSY_IN : in std_logic; - - -- Registers config - BUS_REG_RX : in CTRLBUS_RX; - BUS_REG_TX : out CTRLBUS_TX; - - BUS_DBG_RX : in CTRLBUS_RX; - BUS_DBG_TX : out CTRLBUS_TX; - - TIMER_TICKS_IN : in std_logic_vector( 1 downto 0) - ); -end entity; - -architecture arch of trb_net16_cri_interface is - - signal reset_i, reset_i_mux_io : std_logic; - - signal gbe_cts_number : std_logic_vector(15 downto 0); - signal gbe_cts_code : std_logic_vector(7 downto 0); - signal gbe_cts_information : std_logic_vector(7 downto 0); - signal gbe_cts_start_readout : std_logic; - signal gbe_cts_readout_type : std_logic_vector(3 downto 0); - signal gbe_cts_readout_finished : std_logic; - signal gbe_cts_status_bits : std_logic_vector(31 downto 0); - signal gbe_fee_data : std_logic_vector(15 downto 0); - signal gbe_fee_dataready : std_logic; - signal gbe_fee_read : std_logic; - signal gbe_fee_status_bits : std_logic_vector(31 downto 0); - signal gbe_fee_busy : std_logic; - - signal io_dataready_out : std_logic_vector(7 downto 0); - signal io_data_out : std_logic_vector(127 downto 0); - signal io_packet_num_out : std_logic_vector(23 downto 0); - signal io_read_in : std_logic_vector(7 downto 0); - - signal io_dataready_in : std_logic_vector(3 downto 0); - signal io_read_out : std_logic_vector(3 downto 0); - signal io_data_in : std_logic_vector(4*16-1 downto 0); - signal io_packet_num_in : std_logic_vector(4*3-1 downto 0); - signal io_error_in : std_logic_vector(2 downto 0); - - signal cfg_gbe_enable : std_logic; - signal cfg_ipu_enable : std_logic; - signal cfg_mult_enable : std_logic; - signal cfg_subevent_id : std_logic_vector(31 downto 0); - signal cfg_subevent_dec : std_logic_vector(31 downto 0); - signal cfg_queue_dec : std_logic_vector(31 downto 0); - signal cfg_readout_ctr : std_logic_vector(23 downto 0); - signal cfg_readout_ctr_valid : std_logic; - signal cfg_insert_ttype : std_logic; - signal cfg_max_sub : std_logic_vector(15 downto 0); - signal cfg_max_queue : std_logic_vector(15 downto 0); - signal cfg_max_subs_in_queue : std_logic_vector(15 downto 0); - signal cfg_max_single_sub : std_logic_vector(15 downto 0); - signal cfg_additional_hdr : std_logic; - signal cfg_soft_rst : std_logic; - signal cfg_allow_rx : std_logic; - signal cfg_max_frame : std_logic_vector(15 downto 0); - - signal tc_rd_en : std_logic := '0'; - signal tc_data : std_logic_vector( 8 downto 0); - signal tc_size : std_logic_vector(15 downto 0); - signal resp_ready : std_logic := '0'; - signal resp_busy : std_logic := '0'; - signal cri_readout_finished_in : std_logic; - - signal cri_init_dataready_out : std_logic; - signal cri_init_data_out : std_logic_vector(15 downto 0); - signal cri_init_packet_num_out : std_logic_vector( 2 downto 0); - signal cri_init_read_in : std_logic; - - signal cri_reply_dataready_in : std_logic; - signal cri_reply_data_in : std_logic_vector(15 downto 0); - signal cri_reply_packet_num_in : std_logic_vector( 2 downto 0); - signal cri_reply_read_out : std_logic; - - --API data Transmitter to CRI - signal cri_apl_data_in : std_logic_vector(15 downto 0); - signal cri_apl_packet_num_in : std_logic_vector( 2 downto 0); - signal cri_apl_dataready_in : std_logic; - signal cri_apl_read_out : std_logic; - signal cri_apl_send_in : std_logic; - - --API data Receiver from CRI - signal cri_apl_data_out : std_logic_vector(15 downto 0); - signal cri_apl_packet_num_out : std_logic_vector( 2 downto 0); - signal cri_apl_typ_out : std_logic_vector( 2 downto 0); - signal cri_apl_dataready_out : std_logic; - signal cri_apl_read_in : std_logic; - - --API data controller - signal cri_apl_run_out : std_logic; - signal cri_packet_num_cnt : unsigned( 1 downto 0) := 0; - signal cri_data_send_cnt : unsigned(15 downto 0) := 0; - signal cri_send : std_logic; - - signal cri_event_cnt : unsigned(15 downto 0) := 0; - - --DEBUG SIGNALS: - signal debug_resp_control : std_logic_vector(63 downto 0); - signal readout_finished_cnt, readout_start_cnt : unsigned(15 downto 0); - signal last_cts_readout_finished, last_cts_readout_start : std_logic; - - signal dbg_pc_wr_en : std_logic; - signal dbg_pc_data : std_logic_vector( 7 downto 0); - signal dbg_pc_sos : std_logic; - signal dbg_pc_eos : std_logic; - signal dbg_pc_eoq : std_logic; - signal dbg_pc_sub_size : std_logic_vector(31 downto 0); - signal dbg_pc_trig_nr : std_logic_vector(31 downto 0); - signal dbg_pc_trig_type : std_logic_vector( 3 downto 0); - - signal last_dbg_pc_wr_en : std_logic; - signal last_dbg_pc_sos : std_logic; - signal last_dbg_pc_eos : std_logic; - signal last_dbg_pc_eoq : std_logic; - - signal dbg_pc_wr_en_cnt : unsigned(15 downto 0); - signal dbg_pc_sos_cnt : unsigned(15 downto 0); - signal dbg_pc_eos_cnt : unsigned(15 downto 0); - signal dbg_pc_eoq_cnt : unsigned(15 downto 0); - - signal dbg_api_fifo_to_int : std_logic_vector(31 downto 0); - signal dbg_api_fifo_to_api : std_logic_vector(31 downto 0); - - signal dbg_start_data_send : std_logic := '0'; - - signal dbg_io_dataready_cnt_2 : unsigned(15 downto 0); - signal dbg_io_dataready_cnt_3 : unsigned(15 downto 0); - signal dbg_io_dataready_cnt_6 : unsigned(15 downto 0); - signal dbg_io_dataready_cnt_7 : unsigned(15 downto 0); - - signal resp_ready_q : std_logic := '0'; - signal resp_ready_qq : std_logic := '0'; - signal resp_ready_3q : std_logic := '0'; - signal resp_ready_4q : std_logic := '0'; - signal resp_ready_5q : std_logic := '0'; - signal resp_ready_6q : std_logic := '0'; - - signal tc_data_rdy : std_logic; - - signal tmp_data, ipu_data : std_logic_vector( 7 downto 0); - - signal ipu_wr_en, ipu_wr_en_q, ipu_wr_en_qq, ipu_wr_en_qqq : std_logic; - signal ipu_sos_out_q, ipu_sos_out_qq, ipu_sos_out_qqq : std_logic; - signal ipu_eod_out_q, ipu_eod_out_qq, ipu_eod_out_qqq : std_logic; - signal ipu_data_start, ipu_data_end : std_logic; - signal ipu_sub_size : std_logic_vector(31 downto 0); - - signal ipu_ready_in : std_logic; - signal ipu_start_rdy : std_logic; - signal loaded_bytes : std_logic_vector(15 downto 0); - - signal debug_sender :std_logic_vector(191 downto 0); -begin - ---------------------------------------------------------------------- --- Reset ---------------------------------------------------------------------- ---13: reset sequence received ---14: not connected ---15: send reset sequence - - SYNC_RESET_MUX_IO : process(CLK) - begin - if rising_edge(CLK) then - reset_i <= RESET; - reset_i_mux_io <= MEDIA_MED2INT(0).stat_op(14) or reset_i; - end if; - end process; - - - - - ---------------------------------------------------------------------- --- I/O Buffers ---------------------------------------------------------------------- --- iobuf of Trigger channel -> As CTS is part of Combiner, this channel is --- not used anymore in this place - --- channel 0 - THE_IOBUF_0 : trb_net16_term_buf - port map ( - -- Misc - CLK => CLK , - RESET => reset_i_mux_io, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => io_dataready_out(0), - MED_INIT_DATA_OUT => io_data_out(15 downto 0), - MED_INIT_PACKET_NUM_OUT => io_packet_num_out(2 downto 0), - MED_INIT_READ_IN => io_read_in(0), - - MED_REPLY_DATAREADY_OUT => io_dataready_out(1), - MED_REPLY_DATA_OUT => io_data_out(31 downto 16), - MED_REPLY_PACKET_NUM_OUT=> io_packet_num_out(5 downto 3), - MED_REPLY_READ_IN => io_read_in(1), - - MED_DATAREADY_IN => io_dataready_in(0), - MED_DATA_IN => io_data_in(15 downto 0), - MED_PACKET_NUM_IN => io_packet_num_in(2 downto 0), - MED_READ_OUT => io_read_out(0) - ); - ---------------------------------------------------------------------- --- TrbNet Data Readout ---------------------------------------------------------------------- - trbnet_gen : if INCLUDE_READOUT = 1 generate - - THE_CRI_DATA_SENDER : entity work.cri_data_sender - port map( - -- Misc - CLK => CLK, - RESET => reset_i, - CLK_EN => '1', - - ENABLE_TRANSPORT => dbg_start_data_send, - - -- Port to API - API_DATA_OUT => cri_apl_data_in, - API_PACKET_NUM_OUT => cri_apl_packet_num_in, - API_DATAREADY_OUT => cri_apl_dataready_in, - API_READ_IN => cri_apl_read_out, - API_SHORT_TRANSFER_OUT => open, - API_DTYPE_OUT => open, - API_ERROR_PATTERN_OUT => open, - API_SEND_OUT => cri_apl_send_in, - -- Receiver port - API_DATA_IN => cri_apl_data_out, - API_PACKET_NUM_IN => cri_apl_packet_num_out, - API_TYP_IN => cri_apl_typ_out, - API_DATAREADY_IN => cri_apl_dataready_out, - API_READ_OUT => cri_apl_read_in, - -- APL Control port - API_RUN_IN => cri_apl_run_out, - API_SEQNR_IN => (others => '0'), - API_LENGTH_OUT => open, - MY_ADDRESS_IN => MY_ADDRESS_IN, - - CTS_NUMBER_IN => CTS_NUMBER_IN, - CTS_CODE_IN => CTS_CODE_IN, - CTS_INFORMATION_IN => CTS_INFORMATION_IN, - CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, - CTS_START_READOUT_IN => CTS_START_READOUT_IN, - CTS_READ_IN => '1', - CTS_DATA_OUT => open, - CTS_DATAREADY_OUT => open, - CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, - CTS_LENGTH_OUT => open, - CTS_ERROR_PATTERN_OUT => CTS_STATUS_BITS_OUT, - -- Data from Frontends - FEE_DATA_IN => FEE_DATA_IN, - FEE_DATAREADY_IN => FEE_DATAREADY_IN, - FEE_READ_OUT => FEE_READ_OUT, - FEE_BUSY_IN => FEE_BUSY_IN, - FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, - - DEBUG_OUT => debug_sender - ); - --- THE_IPU_INTERFACE : entity work.trb_net16_cri_ipu_interface --- port map ( --- CLK_IPU => CLK, --- CLK_CRI => CLK, --- RESET => reset_i, --- -- IPU interface directed toward the CTS --- CTS_NUMBER_IN => CTS_NUMBER_IN, --- CTS_CODE_IN => CTS_CODE_IN, --- CTS_INFORMATION_IN => CTS_INFORMATION_IN, --- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, --- CTS_START_READOUT_IN => CTS_START_READOUT_IN, --- CTS_READ_IN => '1', --- CTS_DATA_OUT => open, --- CTS_DATAREADY_OUT => open, --- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, --- CTS_LENGTH_OUT => open, --- CTS_ERROR_PATTERN_OUT => CTS_STATUS_BITS_OUT, --- -- Data from Frontends --- FEE_DATA_IN => FEE_DATA_IN, --- FEE_DATAREADY_IN => FEE_DATAREADY_IN, --- FEE_READ_OUT => FEE_READ_OUT, --- FEE_BUSY_IN => FEE_BUSY_IN, --- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, --- -- slow control interface --- DATA_IPU_ENABLE_IN => '1', --- MULT_EVT_ENABLE_IN => '0', --- MAX_SUBEVENT_SIZE_IN => (others => '1'), --- MAX_QUEUE_SIZE_IN => (others => '1'), --- MAX_SUBS_IN_QUEUE_IN => (others => '1'), --- MAX_SINGLE_SUB_SIZE_IN => (others => '1'), --- READOUT_CTR_IN => (others => '0'), --- READOUT_CTR_VALID_IN => '0', --- -- PacketConstructor interface --- PC_WR_EN_OUT => ipu_wr_en, --- PC_DATA_OUT => ipu_data, --- PC_READY_IN => ipu_ready_in, --- PC_SOS_OUT => ipu_data_start, --- PC_EOS_OUT => open, --- PC_EOQ_OUT => ipu_data_end, --- PC_SUB_SIZE_OUT => ipu_sub_size, --- PC_TRIG_NR_OUT => open, --- PC_TRIGGER_TYPE_OUT => open, --- --- MONITOR_OUT => open, --- DEBUG_OUT => open --- ); - - - THE_CRI_DATARDY_DBG : process begin - wait until rising_edge(CLK); - if RESET = '1' then - dbg_io_dataready_cnt_2 <= 0; - dbg_io_dataready_cnt_3 <= 0; - dbg_io_dataready_cnt_6 <= 0; - dbg_io_dataready_cnt_7 <= 0; - else - if io_dataready_out(2) = '1' then - dbg_io_dataready_cnt_2 <= dbg_io_dataready_cnt_2 + 1; - end if; - - if io_dataready_out(3) = '1' then - dbg_io_dataready_cnt_3 <= dbg_io_dataready_cnt_3 + 1; - end if; - - if io_dataready_out(6) = '1' then - dbg_io_dataready_cnt_6 <= dbg_io_dataready_cnt_6 + 1; - end if; - - if io_dataready_out(7) = '1' then - dbg_io_dataready_cnt_7 <= dbg_io_dataready_cnt_7 + 1; - end if; - end if; - end process; - ---------------------------------------------------------------------- --- active API for Data Channel ---------------------------------------------------------------------- - TRG_CHANNEL_API: trb_net16_api_base - generic map ( - API_TYPE => c_API_ACTIVE, - FIFO_TO_INT_DEPTH => 6, - FIFO_TO_APL_DEPTH => 6, - FORCE_REPLY => 1, - SBUF_VERSION => 0, - USE_VENDOR_CORES => c_YES, - SECURE_MODE_TO_APL => c_YES, - SECURE_MODE_TO_INT => c_YES, - APL_WRITE_ALL_WORDS=> c_YES - ) - port map ( - -- Misc - CLK => CLK, - RESET => reset_i, - CLK_EN => '1', - -- APL Transmitter port - APL_DATA_IN => cri_apl_data_in, - APL_PACKET_NUM_IN => cri_apl_packet_num_in, - APL_DATAREADY_IN => cri_apl_dataready_in, -- almostfullflag ; daten in fifo von 8 auf 16 bit packen - APL_READ_OUT => cri_apl_read_out, - APL_SHORT_TRANSFER_IN => '0', - APL_DTYPE_IN => (others => '0'), - APL_ERROR_PATTERN_IN => (others => '0'), - APL_SEND_IN => cri_apl_send_in, -- 1 till end of Datastream - APL_TARGET_ADDRESS_IN => (others => '1'), - -- Receiver port - APL_DATA_OUT => cri_apl_data_out, - APL_PACKET_NUM_OUT => cri_apl_packet_num_out, - APL_TYP_OUT => cri_apl_typ_out, - APL_DATAREADY_OUT => cri_apl_dataready_out, - APL_READ_IN => cri_apl_read_in, - -- APL Control port - APL_RUN_OUT => cri_apl_run_out, - APL_MY_ADDRESS_IN => MY_ADDRESS_IN, - APL_SEQNR_OUT => open, - APL_LENGTH_IN => (others => '0'), - APL_FIFO_COUNT_OUT => open, - - -- Internal direction port - INT_MASTER_DATAREADY_OUT => cri_init_dataready_out, - INT_MASTER_DATA_OUT => cri_init_data_out, - INT_MASTER_PACKET_NUM_OUT=> cri_init_packet_num_out, - INT_MASTER_READ_IN => cri_init_read_in, - INT_MASTER_DATAREADY_IN => '0', - INT_MASTER_DATA_IN => (others => '0'), - INT_MASTER_PACKET_NUM_IN => "000", - INT_MASTER_READ_OUT => open, - INT_SLAVE_DATAREADY_OUT => open, - INT_SLAVE_DATA_OUT => open, - INT_SLAVE_PACKET_NUM_OUT => open, - INT_SLAVE_READ_IN => '1', - INT_SLAVE_DATAREADY_IN => cri_reply_dataready_in, - INT_SLAVE_DATA_IN => cri_reply_data_in, - INT_SLAVE_PACKET_NUM_IN => cri_reply_packet_num_in, - INT_SLAVE_READ_OUT => cri_reply_read_out, - -- Status and control port - CTRL_SEQNR_RESET => '0',--common_ctrl(10), --TO BE IMPLEMENTED - STAT_FIFO_TO_INT => dbg_api_fifo_to_int, - STAT_FIFO_TO_APL => dbg_api_fifo_to_api - ); - - --iobuf on streaming api, towards CRI, data channel - THE_IOBUF_1 : trb_net16_iobuf - generic map( - IBUF_DEPTH => 6, - USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(1), - USE_CHECKSUM => cfg_USE_CHECKSUM(1), - INIT_CAN_SEND_DATA => c_YES, - INIT_CAN_RECEIVE_DATA => c_NO, - REPLY_CAN_SEND_DATA => c_NO, - REPLY_CAN_RECEIVE_DATA => c_YES - ) - port map( - -- Misc - CLK => CLK, - RESET => reset_i_mux_io, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => io_dataready_out(2), - MED_INIT_DATA_OUT => io_data_out(47 downto 32), - MED_INIT_PACKET_NUM_OUT => io_packet_num_out(8 downto 6), - MED_INIT_READ_IN => io_read_in(2), - - MED_REPLY_DATAREADY_OUT => io_dataready_out(3), - MED_REPLY_DATA_OUT => io_data_out(63 downto 48), - MED_REPLY_PACKET_NUM_OUT => io_packet_num_out(11 downto 9), - MED_REPLY_READ_IN => io_read_in(3), - - MED_DATAREADY_IN => io_dataready_in(1), - MED_DATA_IN => io_data_in(31 downto 16), - MED_PACKET_NUM_IN => io_packet_num_in(5 downto 3), - MED_READ_OUT => io_read_out(1), - MED_ERROR_IN => io_error_in, - - -- Internal direction port - - INT_INIT_DATAREADY_OUT => open, - INT_INIT_DATA_OUT => open, - INT_INIT_PACKET_NUM_OUT => open, - INT_INIT_READ_IN => '1', - - INT_INIT_DATAREADY_IN => cri_init_dataready_out, - INT_INIT_DATA_IN => cri_init_data_out, -- gbe like data to CRI - INT_INIT_PACKET_NUM_IN => cri_init_packet_num_out, - INT_INIT_READ_OUT => cri_init_read_in, - - INT_REPLY_DATAREADY_OUT => cri_reply_dataready_in, - INT_REPLY_DATA_OUT => cri_reply_data_in, -- answer from CRI - INT_REPLY_PACKET_NUM_OUT => cri_reply_packet_num_in, - INT_REPLY_READ_IN => cri_reply_read_out, - - INT_REPLY_DATAREADY_IN => '0', - INT_REPLY_DATA_IN => (others => '0'), - INT_REPLY_PACKET_NUM_IN => (others => '0'), - INT_REPLY_READ_OUT => open, - - -- Status and control port - STAT_GEN => open, - STAT_IBUF_BUFFER => open, - CTRL_GEN => (others => '0'), - STAT_INIT_OBUF_DEBUG => open, - STAT_REPLY_OBUF_DEBUG => open, - TIMER_TICKS_IN => TIMER_TICKS_IN - ); - end generate trbnet_gen; - - - - - no_readout_gen : if INCLUDE_READOUT = 0 generate - -- terminate data channel if no readout - THE_IOBUF_1 : trb_net16_term_buf - port map ( - -- Misc - CLK => CLK, - RESET => reset_i_mux_io, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => io_dataready_out(2), - MED_INIT_DATA_OUT => io_data_out(47 downto 32), - MED_INIT_PACKET_NUM_OUT => io_packet_num_out(8 downto 6), - MED_INIT_READ_IN => io_read_in(2), - - MED_REPLY_DATAREADY_OUT => io_dataready_out(3), - MED_REPLY_DATA_OUT => io_data_out(63 downto 48), - MED_REPLY_PACKET_NUM_OUT=> io_packet_num_out(11 downto 9), - MED_REPLY_READ_IN => io_read_in(3), - - MED_DATAREADY_IN => io_dataready_in(1), - MED_DATA_IN => io_data_in(31 downto 16), - MED_PACKET_NUM_IN => io_packet_num_in(5 downto 3), - MED_READ_OUT => io_read_out(1) - ); - - --Terminate Data - THE_TrbNetData : entity work.trb_net16_gbe_ipu_interface - generic map( - DO_SIMULATION => 0 - ) - port map ( - CLK_IPU => CLK, - CLK_GBE => CLK, - RESET => reset_i_mux_io, - - CTS_NUMBER_IN => CTS_NUMBER_IN, - CTS_CODE_IN => CTS_CODE_IN, - CTS_INFORMATION_IN => CTS_INFORMATION_IN, - CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, - CTS_START_READOUT_IN => CTS_START_READOUT_IN, - CTS_READ_IN => '1', - CTS_DATA_OUT => open, - CTS_DATAREADY_OUT => open, - CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, - CTS_LENGTH_OUT => open, - CTS_ERROR_PATTERN_OUT => CTS_STATUS_BITS_OUT, - -- Data from Frontends - FEE_DATA_IN => FEE_DATA_IN, - FEE_DATAREADY_IN => FEE_DATAREADY_IN, - FEE_READ_OUT => FEE_READ_OUT, - FEE_BUSY_IN => FEE_BUSY_IN, - FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, - -- slow control interface - START_CONFIG_OUT => open, - BANK_SELECT_OUT => open, - CONFIG_DONE_IN => '1', - DATA_GBE_ENABLE_IN => cfg_gbe_enable, - DATA_IPU_ENABLE_IN => cfg_ipu_enable, -- never used in code - MULT_EVT_ENABLE_IN => cfg_mult_enable, - MAX_SUBEVENT_SIZE_IN => cfg_max_sub, - MAX_QUEUE_SIZE_IN => cfg_max_queue, - MAX_SUBS_IN_QUEUE_IN => cfg_max_subs_in_queue, - MAX_SINGLE_SUB_SIZE_IN => cfg_max_single_sub, - READOUT_CTR_IN => cfg_readout_ctr, - READOUT_CTR_VALID_IN => cfg_readout_ctr_valid, - CFG_AUTO_THROTTLE_IN => '0', - CFG_THROTTLE_PAUSE_IN => (others => '0'), - -- PacketConstructor interface - PC_WR_EN_OUT => dbg_pc_wr_en, - PC_DATA_OUT => dbg_pc_data, - PC_READY_IN => '1', - PC_SOS_OUT => dbg_pc_sos, - PC_EOS_OUT => dbg_pc_eos, - PC_EOQ_OUT => dbg_pc_eoq, - PC_SUB_SIZE_OUT => dbg_pc_sub_size, - PC_TRIG_NR_OUT => dbg_pc_trig_nr, - PC_TRIGGER_TYPE_OUT => dbg_pc_trig_type, - MONITOR_OUT => open, - DEBUG_OUT => open - ); --- --Clean Data Output --- CTS_READOUT_FINISHED_OUT <= '1'; --- CTS_STATUS_BITS_OUT <= (others => '0'); --- FEE_READ_OUT <= '0'; --maybe high if idle? - end generate no_readout_gen; - - ---who cares about an unused channel? - THE_IOBUF_2 : trb_net16_term_buf - port map ( - -- Misc - CLK => CLK , - RESET => reset_i_mux_io, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => io_dataready_out(4), - MED_INIT_DATA_OUT => io_data_out(79 downto 64), - MED_INIT_PACKET_NUM_OUT => io_packet_num_out(14 downto 12), - MED_INIT_READ_IN => io_read_in(4), - - MED_REPLY_DATAREADY_OUT => io_dataready_out(5), - MED_REPLY_DATA_OUT => io_data_out(95 downto 80), - MED_REPLY_PACKET_NUM_OUT=> io_packet_num_out(17 downto 15), - MED_REPLY_READ_IN => io_read_in(5), - - MED_DATAREADY_IN => io_dataready_in(2), - MED_DATA_IN => io_data_in(47 downto 32), - MED_PACKET_NUM_IN => io_packet_num_in(8 downto 6), - MED_READ_OUT => io_read_out(2) - ); - ---iobuf towards slow control channel - THE_IOBUF_3 : trb_net16_iobuf - generic map( - IBUF_DEPTH => 6, - USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(3), - USE_CHECKSUM => cfg_USE_CHECKSUM(3), - INIT_CAN_SEND_DATA => c_NO,--MII_IS_DOWNLINK(mii), - INIT_CAN_RECEIVE_DATA => c_YES,--MII_IS_UPLINK(mii), - REPLY_CAN_SEND_DATA => c_YES,--MII_IS_UPLINK(mii), - REPLY_CAN_RECEIVE_DATA => c_NO--MII_IS_DOWNLINK(mii) - ) - port map( - -- Misc - CLK => CLK, - RESET => reset_i_mux_io, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => io_dataready_out(6), - MED_INIT_DATA_OUT => io_data_out(111 downto 96), - MED_INIT_PACKET_NUM_OUT => io_packet_num_out(20 downto 18), - MED_INIT_READ_IN => io_read_in(6), - - MED_REPLY_DATAREADY_OUT => io_dataready_out(7), - MED_REPLY_DATA_OUT => io_data_out(127 downto 112), - MED_REPLY_PACKET_NUM_OUT => io_packet_num_out(23 downto 21), - MED_REPLY_READ_IN => io_read_in(7), - - MED_DATAREADY_IN => io_dataready_in(3), - MED_DATA_IN => io_data_in(63 downto 48), - MED_PACKET_NUM_IN => io_packet_num_in(11 downto 9), - MED_READ_OUT => io_read_out(3), - MED_ERROR_IN => io_error_in, - - -- Internal direction port - - INT_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT, - INT_INIT_DATA_OUT => GSC_INIT_DATA_OUT, - INT_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT, - INT_INIT_READ_IN => GSC_INIT_READ_IN, - - INT_INIT_DATAREADY_IN => '0', - INT_INIT_DATA_IN => (others => '0'), - INT_INIT_PACKET_NUM_IN => (others => '0'), - INT_INIT_READ_OUT => open, - - INT_REPLY_DATAREADY_OUT => open, - INT_REPLY_DATA_OUT => open, - INT_REPLY_PACKET_NUM_OUT => open, - INT_REPLY_READ_IN => '1', - - INT_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN, - INT_REPLY_DATA_IN => GSC_REPLY_DATA_IN, - INT_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN, - INT_REPLY_READ_OUT => GSC_REPLY_READ_OUT, - - -- Status and control port - STAT_GEN => open, - STAT_IBUF_BUFFER => open, - CTRL_GEN => (others => '0'), - STAT_INIT_OBUF_DEBUG => open, - STAT_REPLY_OBUF_DEBUG => open, - TIMER_TICKS_IN => TIMER_TICKS_IN - ); - - ---------------------------------------------------------------------- --- Multiplexer ---------------------------------------------------------------------- - MPLEX: trb_net16_io_multiplexer - port map ( - CLK => CLK, - RESET => reset_i_mux_io, - CLK_EN => CLK_EN, - MED_DATAREADY_IN => MEDIA_MED2INT(0).dataready, - MED_DATA_IN => MEDIA_MED2INT(0).data, - MED_PACKET_NUM_IN => MEDIA_MED2INT(0).packet_num, - MED_READ_OUT => open, - MED_DATAREADY_OUT => MEDIA_INT2MED(0).dataready, - MED_DATA_OUT => MEDIA_INT2MED(0).data, - MED_PACKET_NUM_OUT => MEDIA_INT2MED(0).packet_num, - MED_READ_IN => MEDIA_MED2INT(0).tx_read, - INT_DATAREADY_OUT => io_dataready_in, - INT_DATA_OUT => io_data_in, - INT_PACKET_NUM_OUT => io_packet_num_in, - INT_READ_IN => io_read_out, - INT_DATAREADY_IN => io_dataready_out, - INT_DATA_IN => io_data_out, - INT_PACKET_NUM_IN => io_packet_num_out, - INT_READ_OUT => io_read_in, - CTRL => (others => '0'), - STAT => open - ); - io_error_in <= MEDIA_MED2INT(0).stat_op(2 downto 0); - - - SETUP : gbe_setup - port map( - CLK => CLK, - RESET => reset_i_mux_io, - - -- interface to regio bus - BUS_ADDR_IN => BUS_REG_RX.addr(7 downto 0), - BUS_DATA_IN => BUS_REG_RX.data, - BUS_DATA_OUT => BUS_REG_TX.data, - BUS_WRITE_EN_IN => BUS_REG_RX.write, - BUS_READ_EN_IN => BUS_REG_RX.read, - BUS_ACK_OUT => BUS_REG_TX.ack, - - -- output to gbe_buf - GBE_SUBEVENT_ID_OUT => cfg_subevent_id, - GBE_SUBEVENT_DEC_OUT => cfg_subevent_dec, - GBE_QUEUE_DEC_OUT => cfg_queue_dec, - GBE_MAX_FRAME_OUT => cfg_max_frame, - GBE_USE_GBE_OUT => cfg_gbe_enable, - GBE_USE_TRBNET_OUT => cfg_ipu_enable, - GBE_USE_MULTIEVENTS_OUT => cfg_mult_enable, - GBE_READOUT_CTR_OUT => cfg_readout_ctr, - GBE_READOUT_CTR_VALID_OUT => cfg_readout_ctr_valid, - GBE_ALLOW_RX_OUT => cfg_allow_rx, - GBE_ADDITIONAL_HDR_OUT => cfg_additional_hdr, - GBE_INSERT_TTYPE_OUT => cfg_insert_ttype, - GBE_SOFT_RESET_OUT => cfg_soft_rst, - GBE_MAX_REPLY_OUT => open, -- is for SLWCNTR - GBE_MAX_SUB_OUT => cfg_max_sub, - GBE_MAX_QUEUE_OUT => cfg_max_queue, - GBE_MAX_SUBS_IN_QUEUE_OUT => cfg_max_subs_in_queue, - GBE_MAX_SINGLE_SUB_OUT => cfg_max_single_sub, - GBE_AUTOTHROTTLE_OUT => open, - GBE_THROTTLE_PAUSE_OUT => open, - MONITOR_RX_BYTES_IN => (others => '0'), --sum_rx_bytes, - MONITOR_RX_FRAMES_IN => (others => '0'), --sum_rx_frames, - MONITOR_TX_BYTES_IN => (others => '0'), --sum_tx_bytes, - MONITOR_TX_FRAMES_IN => (others => '0'), --sum_tx_frames, - MONITOR_TX_PACKETS_IN => (others => '0'), --sum_tx_packets, - MONITOR_DROPPED_IN => (others => '0'), --sum_dropped, - MONITOR_SELECT_REC_IN => (others => '0'), --dbg_select_rec, - MONITOR_SELECT_REC_BYTES_IN => (others => '0'), --dbg_select_rec_bytes, - MONITOR_SELECT_SENT_BYTES_IN => (others => '0'), --dbg_select_sent_bytes, - MONITOR_SELECT_SENT_IN => (others => '0'), --dbg_select_sent, - MONITOR_SELECT_DROP_IN_IN => (others => '0'), --dbg_select_drop_in, - MONITOR_SELECT_DROP_OUT_IN => (others => '0'), --dbg_select_drop_out, - MONITOR_SELECT_GEN_DBG_IN => (others => '0'), --monitor_gen_dbg, --dbg_select_gen, - - DUMMY_EVENT_SIZE_OUT => open,--dummy_event, - DUMMY_TRIGGERED_MODE_OUT => open, - DATA_HIST_IN => (others => (others => '0')), --dbg_hist, - SCTRL_HIST_IN => (others => (others => '0')) --dbg_hist2 - ); - - - debug_gen : if INCLUDE_READOUT = 0 generate - - THE_CTS_READOUT_FINISHED_CNT : process begin - wait until rising_edge(CLK); - - if RESET = '1' then - last_cts_readout_finished <= '0'; - last_cts_readout_start <= '0'; - - last_dbg_pc_wr_en <= '0'; - last_dbg_pc_sos <= '0'; - last_dbg_pc_eos <= '0'; - last_dbg_pc_eoq <= '0'; - - readout_finished_cnt <= 0; - readout_start_cnt <= 0; - - dbg_pc_wr_en_cnt <= 0; - dbg_pc_sos_cnt <= 0; - dbg_pc_eos_cnt <= 0; - dbg_pc_eoq_cnt <= 0; - else - last_cts_readout_finished <= CTS_READOUT_FINISHED_OUT; - last_cts_readout_start <= CTS_START_READOUT_IN; - if ((CTS_READOUT_FINISHED_OUT and (not last_cts_readout_finished)) = '1') then - readout_finished_cnt <= readout_finished_cnt + 1; - end if; - - if ((CTS_START_READOUT_IN and (not last_cts_readout_start)) = '1') then - readout_start_cnt <= readout_start_cnt + 1; - end if; - - ------------------- - - last_dbg_pc_wr_en <= dbg_pc_wr_en; - if ((dbg_pc_wr_en and (not last_dbg_pc_wr_en)) = '1') then - dbg_pc_wr_en_cnt <= dbg_pc_wr_en_cnt + 1; - end if; - - last_dbg_pc_sos <= dbg_pc_sos; - if ((dbg_pc_sos and (not last_dbg_pc_sos)) = '1') then - dbg_pc_sos_cnt <= dbg_pc_sos_cnt + 1; - end if; - - last_dbg_pc_eos <= dbg_pc_eos; - if ((dbg_pc_eos and (not last_dbg_pc_eos)) = '1') then - dbg_pc_eos_cnt <= dbg_pc_eos_cnt + 1; - end if; - - last_dbg_pc_eoq <= dbg_pc_eoq; - if ((dbg_pc_eoq and (not last_dbg_pc_eoq)) = '1') then - dbg_pc_eoq_cnt <= dbg_pc_eoq_cnt + 1; - end if; - - ------------------- - end if; - end process; - - - THE_CRI_READOUT_DEBUG : process begin - wait until rising_edge(CLK); - BUS_DBG_TX.ack <= '0'; - BUS_DBG_TX.nack <= '0'; - BUS_DBG_TX.unknown <= '0'; - - if BUS_DBG_RX.read = '1' then - if BUS_DBG_RX.addr(7 downto 0) = x"00" then - BUS_DBG_TX.data <= debug_resp_control(31 downto 0); - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"01" then - BUS_DBG_TX.data <= debug_resp_control(63 downto 32); - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"02" then - BUS_DBG_TX.data(15 downto 0) <= CTS_NUMBER_IN; - BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(readout_finished_cnt); - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"03" then - BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(readout_start_cnt); - BUS_DBG_TX.data(19 downto 16) <= "000" & cfg_gbe_enable; - BUS_DBG_TX.data(23 downto 20) <= "000" & cfg_ipu_enable; - BUS_DBG_TX.data(27 downto 24) <= "000" & cfg_mult_enable; - BUS_DBG_TX.data(31 downto 28) <= "0000"; - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"04" then - BUS_DBG_TX.data(7 downto 0) <= dbg_pc_data; - BUS_DBG_TX.data(15 downto 8) <= x"00"; - BUS_DBG_TX.data(19 downto 16) <= dbg_pc_trig_type; - BUS_DBG_TX.data(23 downto 20) <= x"0"; - BUS_DBG_TX.data(24) <= dbg_pc_wr_en; - BUS_DBG_TX.data(25) <= dbg_pc_sos; - BUS_DBG_TX.data(26) <= dbg_pc_eos; - BUS_DBG_TX.data(27) <= dbg_pc_eoq; - BUS_DBG_TX.data(31 downto 28) <= x"0"; - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"05" then - BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(dbg_pc_wr_en_cnt); - BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(dbg_pc_sos_cnt); - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"06" then - BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(dbg_pc_eos_cnt); - BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(dbg_pc_eoq_cnt); - BUS_DBG_TX.ack <= '1'; - end if; - - elsif BUS_DBG_RX.write = '1' then - --- if BUS_DBG_RX.addr( 7 downto 0) = x"00" then --- dbg_start_data_send <= BUS_DBG_RX.data(0); --- end if; --- --- BUS_DBG_TX.ack <= '1'; - end if; - end process; - end generate debug_gen; - -debug_gen : if INCLUDE_READOUT = 1 generate - - - THE_CRI_READOUT_DEBUG : process begin - wait until rising_edge(CLK); - BUS_DBG_TX.ack <= '0'; - BUS_DBG_TX.nack <= '0'; - BUS_DBG_TX.unknown <= '0'; - - if BUS_DBG_RX.read = '1' then - if BUS_DBG_RX.addr(7 downto 0) = x"00" then - BUS_DBG_TX.data <= debug_sender(31 downto 0); - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"01" then - BUS_DBG_TX.data(0) <= dbg_start_data_send; - BUS_DBG_tX.data(31 downto 1) <= (others => '0'); - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"02" then - BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(dbg_io_dataready_cnt_2); - BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(dbg_io_dataready_cnt_3); - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"03" then - BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(dbg_io_dataready_cnt_6); - BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(dbg_io_dataready_cnt_7); - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"04" then - BUS_DBG_TX.data <= debug_sender(63 downto 32); - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"05" then - BUS_DBG_TX.data <= debug_sender(95 downto 64); - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"06" then - BUS_DBG_TX.data <= debug_sender(127 downto 96); - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"07" then - BUS_DBG_TX.data <= debug_sender(159 downto 128); - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"08" then - BUS_DBG_TX.data <= debug_sender(191 downto 160); - BUS_DBG_TX.ack <= '1'; - end if; - - elsif BUS_DBG_RX.write = '1' then - - if BUS_DBG_RX.addr( 7 downto 0) = x"01" then - dbg_start_data_send <= BUS_DBG_RX.data(0); - BUS_DBG_TX.ack <= '1'; - end if; - - - end if; - end process; - end generate debug_gen; - -end architecture; - - - diff --git a/combiner_cts/cri/trb_net16_cri_response_constructor_TrbNetData.vhd b/combiner_cts/cri/trb_net16_cri_response_constructor_TrbNetData.vhd deleted file mode 100644 index 4bae5f5..0000000 --- a/combiner_cts/cri/trb_net16_cri_response_constructor_TrbNetData.vhd +++ /dev/null @@ -1,814 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - -use work.trb_net_gbe_components.all; -use work.trb_net_gbe_protocols.all; - -entity trb_net16_cri_response_constructor_TrbNetData is - generic( - RX_PATH_ENABLE : integer range 0 to 1 := 1; - DO_SIMULATION : integer range 0 to 1 := 0; - READOUT_BUFFER_SIZE : integer range 1 to 4 := 1 - ); - port( - CLK : in std_logic; -- system clock - RESET : in std_logic; - - -- INTERFACE - MY_MAC_IN : in std_logic_vector(47 downto 0); - MY_IP_IN : in std_logic_vector(31 downto 0); - PS_DATA_IN : in std_logic_vector(8 downto 0); - PS_WR_EN_IN : in std_logic; - PS_ACTIVATE_IN : in std_logic; - PS_RESPONSE_READY_OUT : out std_logic; - PS_BUSY_OUT : out std_logic; - PS_SELECTED_IN : in std_logic; - PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - TC_RD_EN_IN : in std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - TC_IDENT_OUT : out std_logic_vector(15 downto 0); - STAT_DATA_OUT : out std_logic_vector(31 downto 0); - STAT_ADDR_OUT : out std_logic_vector(7 downto 0); - STAT_DATA_RDY_OUT : out std_logic; - STAT_DATA_ACK_IN : in std_logic; - DEBUG_OUT : out std_logic_vector(63 downto 0); - -- END OF INTERFACE - - -- CTS interface - CTS_NUMBER_IN : in std_logic_vector(15 downto 0); - CTS_CODE_IN : in std_logic_vector(7 downto 0); - CTS_INFORMATION_IN : in std_logic_vector(7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector(3 downto 0); - CTS_START_READOUT_IN : in std_logic; - CTS_DATA_OUT : out std_logic_vector(31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; - CTS_READ_IN : in std_logic; - CTS_LENGTH_OUT : out std_logic_vector(15 downto 0); - CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); - -- Data payload interface - FEE_DATA_IN : in std_logic_vector(15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0); - FEE_BUSY_IN : in std_logic; - -- ip configurator - SLV_ADDR_IN : in std_logic_vector(7 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - CFG_GBE_ENABLE_IN : in std_logic; - CFG_IPU_ENABLE_IN : in std_logic; - CFG_MULT_ENABLE_IN : in std_logic; - CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0); - CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0); - CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); - CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0); - CFG_READOUT_CTR_VALID_IN : in std_logic; - CFG_INSERT_TTYPE_IN : in std_logic; - CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0); - CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0); - CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0); - CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0); - CFG_AUTO_THROTTLE_IN : in std_logic; - CFG_THROTTLE_PAUSE_IN : in std_logic_vector(15 downto 0); - MONITOR_SELECT_REC_OUT : out std_logic_vector(31 downto 0); - MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(31 downto 0); - MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(31 downto 0); - MONITOR_SELECT_SENT_OUT : out std_logic_vector(31 downto 0); - MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(31 downto 0); - MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(31 downto 0); - DATA_HIST_OUT : out hist_array; - - BUS_DBG_RX : in CTRLBUS_RX; - BUS_DBG_TX : out CTRLBUS_TX; - - dbg_event_cnt : in unsigned(15 downto 0); - dbg_data_send_cnt : in unsigned(15 downto 0); - dbg_api_fifo_to_int : in std_logic_vector(31 downto 0); - dbg_api_fifo_to_api : in std_logic_vector(31 downto 0); - dbg_start_data_send : out std_logic; - - dbg_io_datardy_data : in std_logic_vector(31 downto 0); - dbg_io_datardy_slwc : in std_logic_vector(31 downto 0) - ); -end trb_net16_cri_response_constructor_TrbNetData; - -architecture trb_net16_cri_response_constructor_TrbNetData of trb_net16_cri_response_constructor_TrbNetData is - attribute syn_encoding : string; - - signal ip_cfg_start : std_logic; - signal ip_cfg_bank : std_logic_vector(3 downto 0); - signal ip_cfg_done : std_logic; - signal ip_cfg_mem_addr : std_logic_vector(7 downto 0); - signal ip_cfg_mem_data : std_logic_vector(31 downto 0); - signal ip_cfg_mem_clk : std_logic; - - signal ic_dest_mac, ic_dest_mac_shift : std_logic_vector(47 downto 0); - signal ic_dest_ip, ic_dest_ip_shift : std_logic_vector(31 downto 0); - signal ic_dest_udp, ic_dest_udp_shift : std_logic_vector(15 downto 0); - signal ic_src_mac, ic_src_mac_shift : std_logic_vector(47 downto 0); - signal ic_src_ip, ic_src_ip_shift : std_logic_vector(31 downto 0); - signal ic_src_udp, ic_src_udp_shift : std_logic_vector(15 downto 0); - - signal pc_wr_en : std_logic; - signal pc_data : std_logic_vector(7 downto 0); - signal pc_eoq : std_logic; - signal pc_sos : std_logic; - signal pc_ready : std_logic; - signal pc_sub_size : std_logic_vector(31 downto 0); - signal pc_trig_nr : std_logic_vector(31 downto 0); - signal pc_eos : std_logic; - - signal tc_rd_en : std_logic; - signal tc_data : std_logic_vector(8 downto 0); - signal tc_size : std_logic_vector(15 downto 0); - signal tc_sod : std_logic; - signal pc_trig_type, pc_trig_type_shift : std_logic_vector(3 downto 0); - - type dissect_states is (IDLE, WAIT_FOR_LOAD, LOAD, CLEANUP); - signal dissect_current_state, dissect_next_state : dissect_states; - attribute syn_encoding of dissect_current_state : signal is "onehot"; - - signal event_bytes : std_logic_vector(15 downto 0); - signal loaded_bytes : std_logic_vector(15 downto 0); - signal sent_packets : std_logic_vector(15 downto 0); - - signal mon_sent_frames, mon_sent_bytes : std_logic_vector(31 downto 0); - signal ipu_dbg : std_logic_vector(383 downto 0); - signal constr_dbg : std_logic_vector(63 downto 0); - - signal hist_inst : hist_array; - signal tc_sod_flag : std_logic; - signal reset_all_hist : std_logic_vector(31 downto 0); - signal ipu_monitor : std_logic_vector(223 downto 0); - - -- JUST FOR DEBUGING PURPOSE - type sim_check_states is (IDLE, SAVE_HDR, GO_OVER_DATA, SAVE_TLR, GET_ONE_MORE, GET_SECOND_MORE, CLEANUP); - signal sim_check_current, sim_check_next : sim_check_states; - - signal hdr, tlr : std_logic_vector(255 downto 0); - - --debug - signal readout_finished_cnt, readout_start_cnt : unsigned(15 downto 0); - signal last_cts_readout_finished, last_cts_readout_start : std_logic; - - signal last_pc_wr_en : std_logic; - signal last_pc_sos : std_logic; - signal last_pc_eos : std_logic; - signal last_pc_eoq : std_logic; - - signal pc_wr_en_cnt : unsigned(15 downto 0); - signal pc_sos_cnt : unsigned(15 downto 0); - signal pc_eos_cnt : unsigned(15 downto 0); - signal pc_eoq_cnt : unsigned(15 downto 0); - - signal constr_state_cnt : unsigned(15 downto 0); - signal constr_state_sub_cnt : unsigned(15 downto 0); - signal last_constr_state : std_logic_vector(3 downto 0); - -begin - sim_check_gen : if DO_SIMULATION = 1 generate - process(RESET, CLK) - begin - if RESET = '1' then - sim_check_current <= IDLE; - elsif rising_edge(CLK) then - sim_check_current <= sim_check_next; - end if; - end process; - - process(sim_check_current, tc_sod, loaded_bytes, tc_size, hdr, tlr, event_bytes) - begin - case (sim_check_current) is - when IDLE => - if (tc_sod = '1') then - sim_check_next <= SAVE_HDR; - else - sim_check_next <= IDLE; - end if; - - when SAVE_HDR => - if (loaded_bytes = x"001f" + x"0002") then - sim_check_next <= GO_OVER_DATA; - else - sim_check_next <= SAVE_HDR; - end if; - - when GO_OVER_DATA => - if (loaded_bytes = tc_size + x"0001") then - sim_check_next <= SAVE_TLR; - else - sim_check_next <= GO_OVER_DATA; - end if; - - when SAVE_TLR => - if (loaded_bytes = event_bytes) then - sim_check_next <= GET_ONE_MORE; - else - sim_check_next <= SAVE_TLR; - end if; - - when GET_ONE_MORE => - sim_check_next <= GET_SECOND_MORE; - - when GET_SECOND_MORE => - sim_check_next <= CLEANUP; - - when CLEANUP => - - --assert (hdr = tlr) report "--------- >>>> Header Trailer mismatch" severity failure; - - sim_check_next <= IDLE; - - end case; - end process; - - process(CLK) - begin - if rising_edge(CLK) then - if (sim_check_current = SAVE_HDR and loaded_bytes > x"0001") then - hdr((to_integer(unsigned(loaded_bytes - x"0002") * 8)) + 7 downto (to_integer(unsigned(loaded_bytes - x"0002")) * 8)) <= tc_data(7 downto 0); - else - hdr <= hdr; - end if; - end if; - end process; - - process(CLK) - begin - if rising_edge(CLK) then - if (sim_check_current = SAVE_TLR) then - tlr((to_integer(unsigned(loaded_bytes - tc_size - 2) * 8)) + 7 downto (to_integer(unsigned(loaded_bytes - tc_size - 2)) * 8)) <= tc_data(7 downto 0); - elsif (sim_check_current = GET_ONE_MORE) then - tlr((to_integer(unsigned(loaded_bytes - tc_size - 1) * 8)) + 7 downto (to_integer(unsigned(loaded_bytes - tc_size - 1)) * 8)) <= tc_data(7 downto 0); - elsif (sim_check_current = GET_ONE_MORE) then - tlr((to_integer(unsigned(loaded_bytes - tc_size) * 8)) + 7 downto (to_integer(unsigned(loaded_bytes - tc_size)) * 8)) <= tc_data(7 downto 0); - else - tlr <= tlr; - end if; - end if; - end process; - - end generate sim_check_gen; - --- THE_IP_CONFIGURATOR : ip_configurator --- port map( --- CLK => CLK, --- RESET => RESET, --- -- configuration interface --- START_CONFIG_IN => ip_cfg_start, --- BANK_SELECT_IN => ip_cfg_bank, --- CONFIG_DONE_OUT => ip_cfg_done, --- MEM_ADDR_OUT => ip_cfg_mem_addr, --- MEM_DATA_IN => ip_cfg_mem_data, --- MEM_CLK_OUT => ip_cfg_mem_clk, --- -- information for IP cores --- DEST_MAC_OUT => ic_dest_mac, --- DEST_IP_OUT => ic_dest_ip, --- DEST_UDP_OUT => ic_dest_udp, --- SRC_MAC_OUT => ic_src_mac, --- SRC_IP_OUT => ic_src_ip, --- SRC_UDP_OUT => ic_src_udp, --- MTU_OUT => open, --- -- Debug --- DEBUG_OUT => open --- ); --- --- MB_IP_CONFIG : slv_mac_memory --- port map( --- CLK => CLK, --- RESET => RESET, --- BUSY_IN => '0', --- -- Slave bus --- SLV_ADDR_IN => SLV_ADDR_IN, --- SLV_READ_IN => SLV_READ_IN, --- SLV_WRITE_IN => SLV_WRITE_IN, --- SLV_BUSY_OUT => SLV_BUSY_OUT, --- SLV_ACK_OUT => SLV_ACK_OUT, --- SLV_DATA_IN => SLV_DATA_IN, --- SLV_DATA_OUT => SLV_DATA_OUT, --- -- I/O to the backend --- MEM_CLK_IN => ip_cfg_mem_clk, --- MEM_ADDR_IN => ip_cfg_mem_addr, --- MEM_DATA_OUT => ip_cfg_mem_data, --- -- Status lines --- STAT => open --- ); - - THE_IPU_INTERFACE : entity work.trb_net16_gbe_ipu_interface - generic map( - DO_SIMULATION => DO_SIMULATION - ) - port map( - CLK_IPU => CLK, - CLK_GBE => CLK, - RESET => RESET, - --Event information coming from CTS - CTS_NUMBER_IN => CTS_NUMBER_IN, - CTS_CODE_IN => CTS_CODE_IN, - CTS_INFORMATION_IN => CTS_INFORMATION_IN, - CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, - CTS_START_READOUT_IN => CTS_START_READOUT_IN, - --Information sent to CTS - --status data, equipped with DHDR - CTS_DATA_OUT => CTS_DATA_OUT, - CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, - CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, - CTS_READ_IN => CTS_READ_IN, - CTS_LENGTH_OUT => CTS_LENGTH_OUT, - CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, - -- Data from Frontends - FEE_DATA_IN => FEE_DATA_IN, - FEE_DATAREADY_IN => FEE_DATAREADY_IN, - FEE_READ_OUT => FEE_READ_OUT, - FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, - FEE_BUSY_IN => FEE_BUSY_IN, - -- slow control interface - START_CONFIG_OUT => ip_cfg_start, -- just to shift Trigger for packer - BANK_SELECT_OUT => ip_cfg_bank, -- not used - CONFIG_DONE_IN => ip_cfg_done, -- just to shift Trigger for packer - DATA_GBE_ENABLE_IN => CFG_GBE_ENABLE_IN, - DATA_IPU_ENABLE_IN => CFG_IPU_ENABLE_IN, - MULT_EVT_ENABLE_IN => CFG_MULT_ENABLE_IN, - MAX_SUBEVENT_SIZE_IN => CFG_MAX_SUB_IN, - MAX_QUEUE_SIZE_IN => CFG_MAX_QUEUE_IN, - MAX_SUBS_IN_QUEUE_IN => CFG_MAX_SUBS_IN_QUEUE_IN, - MAX_SINGLE_SUB_SIZE_IN => CFG_MAX_SINGLE_SUB_IN, - READOUT_CTR_IN => CFG_READOUT_CTR_IN, - READOUT_CTR_VALID_IN => CFG_READOUT_CTR_VALID_IN, - CFG_AUTO_THROTTLE_IN => CFG_AUTO_THROTTLE_IN, - CFG_THROTTLE_PAUSE_IN => CFG_THROTTLE_PAUSE_IN, - - -- PacketConstructor interface - PC_WR_EN_OUT => pc_wr_en, - PC_DATA_OUT => pc_data, - PC_READY_IN => pc_ready, - PC_SOS_OUT => pc_sos, - PC_EOS_OUT => pc_eos, - PC_EOQ_OUT => pc_eoq, - PC_SUB_SIZE_OUT => pc_sub_size, - PC_TRIG_NR_OUT => pc_trig_nr, - PC_TRIGGER_TYPE_OUT => pc_trig_type, - MONITOR_OUT => ipu_monitor, - DEBUG_OUT => ipu_dbg - ); - - MONITOR_SELECT_DROP_OUT_OUT <= ipu_monitor(31 downto 0); - - PACKET_CONSTRUCTOR : entity work.trb_net16_gbe_event_constr - generic map( - READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE, - DO_SIMULATION => DO_SIMULATION - ) - port map( - CLK => CLK, - RESET => RESET, - PC_WR_EN_IN => pc_wr_en, - PC_DATA_IN => pc_data, - PC_READY_OUT => pc_ready, - PC_START_OF_SUB_IN => pc_sos, - PC_END_OF_SUB_IN => pc_eos, - PC_END_OF_QUEUE_IN => pc_eoq, - PC_SUB_SIZE_IN => pc_sub_size, - PC_DECODING_IN => CFG_SUBEVENT_DEC_IN, - PC_EVENT_ID_IN => CFG_SUBEVENT_ID_IN, - PC_TRIG_NR_IN => pc_trig_nr, - PC_TRIGGER_TYPE_IN => pc_trig_type_shift, - PC_QUEUE_DEC_IN => CFG_QUEUE_DEC_IN, - PC_INSERT_TTYPE_IN => CFG_INSERT_TTYPE_IN, - TC_RD_EN_IN => tc_rd_en, - TC_DATA_OUT => tc_data, - TC_EVENT_SIZE_OUT => tc_size, - TC_SOD_OUT => tc_sod, - DEBUG_OUT => constr_dbg - ); - - tc_rd_en <= '1' when PS_SELECTED_IN = '1' and TC_RD_EN_IN = '1' else '0'; - - DISSECT_MACHINE_PROC : process(RESET, CLK) - begin - if RESET = '1' then - dissect_current_state <= IDLE; - elsif rising_edge(CLK) then - dissect_current_state <= dissect_next_state; - end if; - end process DISSECT_MACHINE_PROC; - - DISSECT_MACHINE : process(dissect_current_state, tc_sod, event_bytes, loaded_bytes, PS_SELECTED_IN) - begin - case dissect_current_state is - when IDLE => - if (tc_sod = '1') then - dissect_next_state <= WAIT_FOR_LOAD; - else - dissect_next_state <= IDLE; - end if; - - when WAIT_FOR_LOAD => - if (PS_SELECTED_IN = '1') then - dissect_next_state <= LOAD; - else - dissect_next_state <= WAIT_FOR_LOAD; - end if; - - when LOAD => - if (event_bytes = loaded_bytes) then - dissect_next_state <= CLEANUP; - else - dissect_next_state <= LOAD; - end if; - - when CLEANUP => - dissect_next_state <= IDLE; - - end case; - end process DISSECT_MACHINE; - - PS_BUSY_OUT <= '0' when dissect_current_state = IDLE else '1'; - PS_RESPONSE_READY_OUT <= '1' when (dissect_current_state = LOAD) or (dissect_current_state = WAIT_FOR_LOAD) else '0'; - - TC_DATA_OUT <= tc_data; - - EVENT_BYTES_PROC : process(clk) is - begin - if rising_edge(clk) then - if dissect_current_state = IDLE and tc_sod = '1' then - event_bytes <= tc_size + x"20"; -- adding termination bytes - else - event_bytes <= event_bytes; - end if; - end if; - end process EVENT_BYTES_PROC; - - LOADED_BYTES_PROC : process(clk) is - begin - if rising_edge(clk) then - if (dissect_current_state = IDLE) then - loaded_bytes <= (others => '0'); - elsif (dissect_current_state = LOAD and TC_RD_EN_IN = '1') then - loaded_bytes <= loaded_bytes + x"1"; - else - loaded_bytes <= loaded_bytes; - end if; - end if; - end process LOADED_BYTES_PROC; - - TC_FRAME_SIZE_OUT <= event_bytes; - TC_FRAME_TYPE_OUT <= x"0008"; - - TC_DEST_MAC_OUT <= x"c4e870211b00"; --ic_dest_mac; - TC_DEST_IP_OUT <= x"0300a8c0"; --ic_dest_ip; - TC_DEST_UDP_OUT <= x"c35c"; --ic_dest_udp; - - --TC_DEST_MAC_OUT <= x"87883c290c00"; --ic_dest_mac; - --TC_DEST_IP_OUT <= x"0188a8c0"; --ic_dest_ip; - --TC_DEST_UDP_OUT <= x"c35b"; --ic_dest_udp; - - process(CLK) - begin - if rising_edge(CLK) then - ip_cfg_done <= '0'; - if (ip_cfg_start = '1') then - ip_cfg_done <= '1'; --- ic_dest_mac_shift <= ic_dest_mac; --- ic_dest_ip_shift <= ic_dest_ip; --- ic_dest_udp_shift <= ic_dest_udp; --- --- ic_src_mac_shift <= ic_src_mac; --- ic_src_ip_shift <= ic_src_ip; --- ic_src_udp_shift <= ic_src_udp; - - pc_trig_type_shift <= pc_trig_type; - else --- ic_dest_mac_shift <= ic_dest_mac_shift; --- ic_dest_ip_shift <= ic_dest_ip_shift; --- ic_dest_udp_shift <= ic_dest_udp_shift; --- --- ic_src_mac_shift <= ic_src_mac_shift; --- ic_src_ip_shift <= ic_src_ip_shift; --- ic_src_udp_shift <= ic_src_udp_shift; - - pc_trig_type_shift <= pc_trig_type_shift; - end if; - end if; - end process; - - rx_enable_gen : if (RX_PATH_ENABLE = 1) generate - TC_SRC_MAC_OUT <= MY_MAC_IN; - TC_SRC_IP_OUT <= MY_IP_IN; - end generate rx_enable_gen; - - rx_disable_gen : if (RX_PATH_ENABLE = 0) generate - TC_SRC_MAC_OUT <= MY_MAC_IN; - TC_SRC_IP_OUT <= ic_src_ip_shift; - end generate rx_disable_gen; - - TC_SRC_UDP_OUT <= ic_src_udp_shift; - TC_IP_PROTOCOL_OUT <= x"11"; - TC_IDENT_OUT <= x"4" & sent_packets(11 downto 0); - - SENT_PACKETS_PROC : process(CLK) - begin - if rising_edge(CLK) then - if (RESET = '1') then - sent_packets <= (others => '0'); - elsif (dissect_current_state = IDLE and tc_sod = '1') then - sent_packets <= sent_packets + x"1"; - end if; - end if; - end process SENT_PACKETS_PROC; - - -- monitoring - - - process(CLK) - begin - if rising_edge(CLK) then - if (tc_sod = '1' and tc_sod_flag = '0') then - tc_sod_flag <= '1'; - elsif (tc_sod = '0') then - tc_sod_flag <= '0'; - else - tc_sod_flag <= tc_sod_flag; - end if; - end if; - end process; - - hist_ctrs_gen : for i in 0 to 31 generate - process(CLK) - begin - if rising_edge(CLK) then - if (RESET = '1') then - reset_all_hist(i) <= '1'; - elsif (hist_inst(i) = x"ffff_ffff") then - reset_all_hist(i) <= '1'; - else - reset_all_hist(i) <= '0'; - end if; - end if; - end process; - - HIST_PROC : process(CLK) - begin - if rising_edge(CLK) then - if (RESET = '1') or (reset_all_hist /= x"0000_0000") then - hist_inst(i) <= (others => '0'); - elsif (tc_sod = '1' and tc_sod_flag = '0' and i = to_integer(unsigned(event_bytes(15 downto 11)))) then - hist_inst(i) <= hist_inst(i) + x"1"; - else - hist_inst(i) <= hist_inst(i); - end if; - end if; - end process; - end generate hist_ctrs_gen; - - DATA_HIST_OUT <= hist_inst; - - process(CLK) - begin - if rising_edge(CLK) then - if (RESET = '1') then - mon_sent_frames <= (others => '0'); - elsif (dissect_current_state = LOAD and event_bytes = loaded_bytes) then - mon_sent_frames <= mon_sent_frames + x"1"; - else - mon_sent_frames <= mon_sent_frames; - end if; - end if; - end process; - MONITOR_SELECT_SENT_OUT <= mon_sent_frames; - - process(CLK) - begin - if rising_edge(CLK) then - if (RESET = '1') then - mon_sent_bytes <= (others => '0'); - elsif (tc_rd_en = '1') then - mon_sent_bytes <= mon_sent_bytes + x"1"; - else - mon_sent_bytes <= mon_sent_bytes; - end if; - end if; - end process; - - MONITOR_SELECT_SENT_BYTES_OUT <= mon_sent_bytes; - - MONITOR_SELECT_REC_BYTES_OUT <= (others => '0'); - MONITOR_SELECT_REC_OUT <= (others => '0'); - - DEBUG_OUT(31 downto 0) <= ipu_dbg(31 downto 0); - DEBUG_OUT(63 downto 32) <= constr_dbg(31 downto 0); - - -THE_CTS_READOUT_FINISHED_CNT : process begin - wait until rising_edge(CLK); - - if RESET = '1' then - last_cts_readout_finished <= '0'; - last_cts_readout_start <= '0'; - - last_pc_wr_en <= '0'; - last_pc_sos <= '0'; - last_pc_eos <= '0'; - last_pc_eoq <= '0'; - - readout_finished_cnt <= 0; - readout_start_cnt <= 0; - - pc_wr_en_cnt <= 0; - pc_sos_cnt <= 0; - pc_eos_cnt <= 0; - pc_eoq_cnt <= 0; - - constr_state_cnt <= 0; - constr_state_sub_cnt <= 0; - - last_constr_state <= x"0"; - else - last_cts_readout_finished <= CTS_READOUT_FINISHED_OUT; - last_cts_readout_start <= CTS_START_READOUT_IN; - if ((CTS_READOUT_FINISHED_OUT and (not last_cts_readout_finished)) = '1') then - readout_finished_cnt <= readout_finished_cnt + 1; - end if; - - if ((CTS_START_READOUT_IN and (not last_cts_readout_start)) = '1') then - readout_start_cnt <= readout_start_cnt + 1; - end if; - - ------------------- - - last_pc_wr_en <= pc_wr_en; - if ((pc_wr_en and (not last_pc_wr_en)) = '1') then - pc_wr_en_cnt <= pc_wr_en_cnt + 1; - end if; - - last_pc_sos <= pc_sos; - if ((pc_sos and (not last_pc_sos)) = '1') then - pc_sos_cnt <= pc_sos_cnt + 1; - end if; - - last_pc_eos <= pc_eos; - if ((pc_eos and (not last_pc_eos)) = '1') then - pc_eos_cnt <= pc_eos_cnt + 1; - end if; - - last_pc_eoq <= pc_eoq; - if ((pc_eoq and (not last_pc_eoq)) = '1') then - pc_eoq_cnt <= pc_eoq_cnt + 1; - end if; - - last_constr_state <= constr_dbg(3 downto 0); - if (last_constr_state /= constr_dbg(3 downto 0)) then - constr_state_cnt <= constr_state_cnt + 1; - if (constr_dbg(3 downto 0) = x"2") then - constr_state_sub_cnt <= constr_state_sub_cnt + 1; - end if; - end if; - - - ------------------- - end if; -end process; - - -THE_CRI_READOUT_DEBUG : process begin - wait until rising_edge(CLK); - BUS_DBG_TX.ack <= '0'; - BUS_DBG_TX.nack <= '0'; - BUS_DBG_TX.unknown <= '0'; - - if BUS_DBG_RX.read = '1' then - if BUS_DBG_RX.addr(7 downto 0) = x"00" then - BUS_DBG_TX.data <= ipu_dbg(31 downto 0); - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"01" then - BUS_DBG_TX.data <= constr_dbg(31 downto 0); - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"02" then - BUS_DBG_TX.data(15 downto 0) <= CTS_NUMBER_IN; - BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(readout_finished_cnt); - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"03" then - BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(readout_start_cnt); - BUS_DBG_TX.data(19 downto 16) <= "000" & CFG_GBE_ENABLE_IN; - BUS_DBG_TX.data(23 downto 20) <= "000" & CFG_IPU_ENABLE_IN; - BUS_DBG_TX.data(27 downto 24) <= "000" & CFG_MULT_ENABLE_IN; - BUS_DBG_TX.data(31 downto 28) <= "0000"; - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"04" then - BUS_DBG_TX.data(7 downto 0) <= pc_data; - BUS_DBG_TX.data(15 downto 8) <= x"00"; - BUS_DBG_TX.data(19 downto 16) <= pc_trig_type; - BUS_DBG_TX.data(23 downto 20) <= x"0"; - BUS_DBG_TX.data(24) <= pc_wr_en; - BUS_DBG_TX.data(25) <= pc_sos; - BUS_DBG_TX.data(26) <= pc_eos; - BUS_DBG_TX.data(27) <= pc_eoq; - BUS_DBG_TX.data(31 downto 28) <= x"0"; - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"05" then - BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(pc_wr_en_cnt); - BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(pc_sos_cnt); - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"06" then - BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(pc_eos_cnt); - BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(pc_eoq_cnt); - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"07" then - BUS_DBG_TX.data( 8 downto 0) <= tc_data; - BUS_DBG_TX.data(11 downto 9) <= (others => '0'); - BUS_DBG_TX.data(15 downto 12) <= "000" & tc_sod; - BUS_DBG_TX.data(31 downto 16) <= tc_size; - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"08" then - BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(constr_state_cnt); - BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(constr_state_sub_cnt); - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"09" then - BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(dbg_event_cnt); - BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(dbg_data_send_cnt); - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"0a" then - BUS_DBG_TX.data <= dbg_api_fifo_to_int; - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"0b" then - BUS_DBG_TX.data <= dbg_api_fifo_to_api; - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"0C" then - BUS_DBG_TX.data(0) <= dbg_start_data_send; - BUS_DBG_TX.data(31 downto 1) <= (others => '0'); - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"0D" then - BUS_DBG_TX.data <= dbg_io_datardy_data; - BUS_DBG_TX.ack <= '1'; - end if; - - if BUS_DBG_RX.addr(7 downto 0) = x"0E" then - BUS_DBG_TX.data <= dbg_io_datardy_slwc; - BUS_DBG_TX.ack <= '1'; - end if; - - elsif BUS_DBG_RX.write = '1' then - - if BUS_DBG_RX.addr( 7 downto 0) = x"0C" then - dbg_start_data_send <= BUS_DBG_RX.data(0); - end if; - - BUS_DBG_TX.ack <= '1'; - end if; - end process; - -end trb_net16_cri_response_constructor_TrbNetData; - - diff --git a/combiner_cts/cri/trb_net16_hub_streaming_port_sctrl_cts_cri.vhd b/combiner_cts/cri/trb_net16_hub_streaming_port_sctrl_cts_cri.vhd deleted file mode 100644 index 54eb7ef..0000000 --- a/combiner_cts/cri/trb_net16_hub_streaming_port_sctrl_cts_cri.vhd +++ /dev/null @@ -1,1228 +0,0 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.trb_net16_hub_func.all; - ---Ports: --- LVL1/IPU SCtrl --- 0 FPGA 1 FPGA 1 --- 1 FPGA 2 FPGA 2 --- 2 FPGA 3 FPGA 3 --- 3 FPGA 4 FPGA 4 --- 4 opt. link opt. link --- 5 CTS read-out internal 0 1 - X X O --downlink only --- 6 CTS TRG Sctrl GbE 2 3 4 X X X --uplink only - --- MII_NUMBER => 5, --- INT_NUMBER => 5, --- INT_CHANNELS => (0,1,0,1,3), - --- No trigger sent to optical link, slow control receiving possible --- MII_IS_UPLINK => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0); --- MII_IS_DOWNLINK => (1,1,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0); --- MII_IS_UPLINK_ONLY => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0); - --- Trigger sent to optical link, slow control receiving possible --- MII_IS_UPLINK => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0); --- MII_IS_DOWNLINK => (1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0); --- MII_IS_UPLINK_ONLY => (0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0); --- & disable port 4 in c0 and c1 -- no triggers from/to optical link - ---Slow Control --- 0 - 7 Readout endpoint common status --- 80 - AF Hub status registers --- C0 - CF Hub control registers --- 4000 - 40FF Hub status registers --- 7000 - 72FF Readout endpoint registers --- 8100 - 83FF GbE configuration & status --- A000 - A1FF CTS configuration & status --- D000 - D13F Flash Programming - - - -entity trb_net16_hub_streaming_port_sctrl_cts_cri is - generic( - --hub control - INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F3C0"; - INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0'); - COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - INCLUDED_FEATURES : std_logic_vector(63 downto 0) := (others => '0'); - HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"9000CE00"; - INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0005"; - BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"7E"; - CLOCK_FREQUENCY : integer range 1 to 200 := 100; - USE_ONEWIRE : integer range 0 to 2 := c_YES; - BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF"; - RDO_ADDITIONAL_PORT : integer range 1 to 7 := 2; -- real limit to be explored - RDO_DATA_BUFFER_DEPTH : integer range 9 to 14 := 9; - RDO_DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-2 := 2**8; - RDO_HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9; - RDO_HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-2 := 2**8; - --media interfaces & hub ports - MII_NUMBER : integer range 1 to c_MAX_MII_PER_HUB := 5; - MII_IS_UPLINK : hub_mii_config_t := (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0); - MII_IS_DOWNLINK : hub_mii_config_t := (1,1,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0); - MII_IS_UPLINK_ONLY : hub_mii_config_t := (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0); - INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := - x"00000000_00000000_00000000_00000000" & - x"00000000_00000000_00000000_00000000" & - x"00000000_00000000_000050FF_00000000" & - x"FFFFFFFF_00000000_FFFFFFFF_FFFFFFFF" - ); - - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - --- Media Interfaces ---------------------------------------------------------------- - MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0); - MED_DATA_OUT : out std_logic_vector (MII_NUMBER*16-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector (MII_NUMBER*3-1 downto 0); - MED_READ_IN : in std_logic_vector (MII_NUMBER-1 downto 0); - MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0); - MED_DATA_IN : in std_logic_vector (MII_NUMBER*16-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*3-1 downto 0); - MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0); - MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0); - MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0); - --- Gbe Read-out Path --------------------------------------------------------------- - --Event information coming from CTS for GbE - GBE_CTS_NUMBER_OUT : out std_logic_vector (15 downto 0); - GBE_CTS_CODE_OUT : out std_logic_vector (7 downto 0); - GBE_CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0); - GBE_CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); - GBE_CTS_START_READOUT_OUT : out std_logic; - --Information sent to CTS - GBE_CTS_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM - GBE_CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - -- Data from Frontends - GBE_FEE_DATA_OUT : out std_logic_vector (15 downto 0); - GBE_FEE_DATAREADY_OUT : out std_logic; - GBE_FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready - GBE_FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); - GBE_FEE_BUSY_OUT : out std_logic; - --- Gbe Sctrl Input ----------------------------------------------------------------- - GSC_INIT_DATAREADY_IN : in std_logic; - GSC_INIT_DATA_IN : in std_logic_vector (15 downto 0); - GSC_INIT_PACKET_NUM_IN : in std_logic_vector (2 downto 0); - GSC_INIT_READ_OUT : out std_logic; - GSC_REPLY_DATAREADY_OUT : out std_logic; - GSC_REPLY_DATA_OUT : out std_logic_vector (15 downto 0); - GSC_REPLY_PACKET_NUM_OUT : out std_logic_vector (2 downto 0); - GSC_REPLY_READ_IN : in std_logic; - GSC_BUSY_OUT : out std_logic; - --- CTS Request Sending ------------------------------------------------------------- - --LVL1 trigger - CTS_TRG_SEND_IN : in std_logic; - CTS_TRG_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_TRG_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_TRG_INFORMATION_IN : in std_logic_vector (23 downto 0); - CTS_TRG_RND_CODE_IN : in std_logic_vector (7 downto 0); - CTS_TRG_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); - CTS_TRG_BUSY_OUT : out std_logic; - --IPU Channel - CTS_IPU_SEND_IN : in std_logic; - CTS_IPU_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_IPU_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_IPU_INFORMATION_IN : in std_logic_vector (7 downto 0); - CTS_IPU_RND_CODE_IN : in std_logic_vector (7 downto 0); - -- Receiver port - CTS_IPU_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); - CTS_IPU_BUSY_OUT : out std_logic; - --- CTS Data Readout ---------------------------------------------------------------- - --Trigger In - RDO_TRIGGER_IN : in std_logic; - RDO_TRG_DATA_VALID_OUT : out std_logic; - RDO_VALID_TIMING_TRG_OUT : out std_logic; - RDO_VALID_NOTIMING_TRG_OUT : out std_logic; - RDO_INVALID_TRG_OUT : out std_logic; - - RDO_TRG_TYPE_OUT : out std_logic_vector(3 downto 0); - RDO_TRG_CODE_OUT : out std_logic_vector(7 downto 0); - RDO_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0); - RDO_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); - - --Data out - RDO_TRG_STATUSBITS_IN : in std_logic_vector (31 downto 0) := (others => '0'); - RDO_DATA_IN : in std_logic_vector (31 downto 0) := (others => '0'); - RDO_DATA_WRITE_IN : in std_logic := '0'; - RDO_DATA_FINISHED_IN : in std_logic := '0'; - - RDO_ADDITIONAL_DATA : in std_logic_vector(RDO_ADDITIONAL_PORT*32-1 downto 0); - RDO_ADDITIONAL_WRITE : in std_logic_vector(RDO_ADDITIONAL_PORT-1 downto 0); - RDO_ADDITIONAL_FINISHED : in std_logic_vector(RDO_ADDITIONAL_PORT-1 downto 0); - RDO_ADDITIONAL_STATUSBITS_IN : in std_logic_vector(RDO_ADDITIONAL_PORT*32-1 downto 0) := (others => '0'); - --- Slow Control -------------------------------------------------------------------- - COMMON_STAT_REGS : out std_logic_vector (std_COMSTATREG*32-1 downto 0); --Status of common STAT regs - COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs - ONEWIRE : inout std_logic; - ONEWIRE_MONITOR_IN : in std_logic; - ONEWIRE_MONITOR_OUT : out std_logic; - MY_ADDRESS_OUT : out std_logic_vector (15 downto 0); - UNIQUE_ID_OUT : out std_logic_vector (63 downto 0); - --REGIO INTERFACE (0x8000 - 0xFFFF) - REGIO_ADDR_OUT : out std_logic_vector (16-1 downto 0); - REGIO_READ_ENABLE_OUT : out std_logic; - REGIO_WRITE_ENABLE_OUT : out std_logic; - REGIO_DATA_OUT : out std_logic_vector (32-1 downto 0); - REGIO_DATA_IN : in std_logic_vector (32-1 downto 0) := (others => '0'); - REGIO_DATAREADY_IN : in std_logic := '0'; - REGIO_NO_MORE_DATA_IN : in std_logic := '0'; - REGIO_WRITE_ACK_IN : in std_logic := '0'; - REGIO_UNKNOWN_ADDR_IN : in std_logic := '0'; - REGIO_TIMEOUT_OUT : out std_logic; - EXTERNAL_SEND_RESET : in std_logic := '0'; - TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); - TEMPERATURE_OUT : out std_logic_vector (11 downto 0); - --- Debug and Status Ports ---------------------------------------------------------- - HUB_STAT_CHANNEL : out std_logic_vector (4*16-1 downto 0); - HUB_STAT_GEN : out std_logic_vector (31 downto 0); - MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0); - MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0); - STAT_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom STAT regs - STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs - --Debugging registers - STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging - CTRL_DEBUG : in std_logic_vector (31 downto 0) --free control regs for debugging - ); -end entity; - - -architecture trb_net16_hub_streaming_arch of trb_net16_hub_streaming_port_sctrl_cts_cri is - -constant mii : integer := MII_NUMBER; -constant DATA_INTERFACE_NUMBER : integer := RDO_ADDITIONAL_PORT + 1; - -signal hub_init_dataready_out : std_logic_vector(5 downto 0); -signal hub_reply_dataready_out : std_logic_vector(5 downto 0); -signal hub_init_dataready_in : std_logic_vector(5 downto 0); -signal hub_reply_dataready_in : std_logic_vector(5 downto 0); -signal hub_init_read_out : std_logic_vector(5 downto 0); -signal hub_reply_read_out : std_logic_vector(5 downto 0); -signal hub_init_read_in : std_logic_vector(5 downto 0); -signal hub_reply_read_in : std_logic_vector(5 downto 0); -signal hub_init_data_out : std_logic_vector(80 downto 0); -signal hub_reply_data_out : std_logic_vector(80 downto 0); -signal hub_init_data_in : std_logic_vector(80 downto 0); -signal hub_reply_data_in : std_logic_vector(80 downto 0); -signal hub_init_packet_num_out : std_logic_vector(15 downto 0); -signal hub_reply_packet_num_out : std_logic_vector(15 downto 0); -signal hub_init_packet_num_in : std_logic_vector(15 downto 0); -signal hub_reply_packet_num_in : std_logic_vector(15 downto 0); - --- signal cts_init_data_out : std_logic_vector(15 downto 0); --- signal cts_init_dataready_out : std_logic; --- signal cts_init_packet_num_out : std_logic_vector(2 downto 0); --- signal cts_init_read_in : std_logic; - --- signal cts_reply_data_in : std_logic_vector(15 downto 0); --- signal cts_reply_dataready_in : std_logic; --- signal cts_reply_packet_num_in : std_logic_vector(2 downto 0); --- signal cts_reply_read_out : std_logic; - -signal common_ctrl : std_logic_vector(std_COMCTRLREG*32-1 downto 0); -signal common_stat : std_logic_vector(std_COMSTATREG*32-1 downto 0); -signal common_ctrl_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); -signal common_stat_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); -signal my_address : std_logic_vector(15 downto 0); - --- signal io_dataready_out : std_logic_vector(7 downto 0); --- signal io_data_out : std_logic_vector(127 downto 0); --- signal io_packet_num_out : std_logic_vector(23 downto 0); --- signal io_read_in : std_logic_vector(7 downto 0); --- --- signal io_dataready_in : std_logic_vector(3 downto 0); --- signal io_read_out : std_logic_vector(3 downto 0); --- signal io_data_in : std_logic_vector(4*16-1 downto 0); --- signal io_packet_num_in : std_logic_vector(4*3-1 downto 0); - -signal reset_i : std_logic; - -signal HUB_MED_CTRL_OP : std_logic_vector(mii*16-1 downto 0); -signal reset_i_mux_io : std_logic; - -signal hub_make_network_reset : std_logic; --- signal hub_got_network_reset : std_logic; -signal timer_ticks : std_logic_vector(1 downto 0); -signal hub_ctrl_debug : std_logic_vector(31 downto 0); -signal buf_HUB_STAT_GEN : std_logic_vector(31 downto 0); - -signal trg_apl_data_out : std_logic_vector(15 downto 0); -signal trg_apl_dataready_out : std_logic; -signal trg_apl_error_pattern_in : std_logic_vector(31 downto 0); -signal trg_apl_packet_num_out : std_logic_vector(2 downto 0); -signal trg_apl_read_in : std_logic; -signal trg_apl_run_out : std_logic; -signal trg_apl_typ_out : std_logic_vector(2 downto 0); -signal tmp_hub_init_data_in : std_logic_vector(15 downto 0); -signal reg_ext_trg_information : std_logic_vector(15 downto 0); - -signal lvl1_error_pattern : std_logic_vector(31 downto 0); -signal lvl1_handler_error_pattern : std_logic_vector(31 downto 0); -signal lvl1_trg_code : std_logic_vector(7 downto 0); -signal lvl1_trg_information : std_logic_vector(23 downto 0); -signal lvl1_trg_number : std_logic_vector(15 downto 0); -signal lvl1_trg_received : std_logic; -signal lvl1_trg_release : std_logic; -signal lvl1_handler_trg_release : std_logic; -signal lvl1_trg_type : std_logic_vector(3 downto 0); -signal lvl1_valid_i : std_logic; -signal lvl1_valid_notiming_i: std_logic; -signal lvl1_valid_timing_i : std_logic; -signal lvl1_invalid_i : std_logic; -signal lvl1_data_valid_i : std_logic; -signal reset_ipu_i : std_logic; - --- signal int_spike_detected : std_logic; --- signal int_lvl1_spurious_trg : std_logic; --- signal int_lvl1_timeout_detected : std_logic; --- signal int_multiple_trg : std_logic; --- signal int_lvl1_missing_tmg_trg : std_logic; --- signal int_lvl1_long_trg : std_logic; -signal int_trigger_num : std_logic_vector(15 downto 0); -signal int_lvl1_delay : std_logic_vector(15 downto 0); -signal stat_lvl1_handler : std_logic_vector(63 downto 0); -signal stat_counters_lvl1_handler : std_logic_vector(79 downto 0); - -signal dummy : std_logic_vector(300 downto 0); -signal write_enable : std_logic_vector(6 downto 0); -signal read_enable : std_logic_vector(6 downto 0); -signal last_write_enable : std_logic_vector(6 downto 0); -signal last_read_enable : std_logic_vector(6 downto 0); - -signal stat_buffer_i : std_logic_vector(31 downto 0); -signal stat_buffer_unknown : std_logic; -signal stat_buffer_read : std_logic; -signal stat_buffer_ready : std_logic; -signal stat_buffer_address : std_logic_vector(4 downto 0); -signal stat_handler_i : std_logic_vector(127 downto 0); -signal stat_data_buffer_level : std_logic_vector (DATA_INTERFACE_NUMBER*32-1 downto 0); -signal stat_header_buffer_level: std_logic_vector (31 downto 0); - -signal ipu_number_i : std_logic_vector (15 downto 0); -signal ipu_readout_type_i : std_logic_vector ( 3 downto 0); -signal ipu_information_i : std_logic_vector ( 7 downto 0); -signal ipu_start_readout_i : std_logic; -signal ipu_data_i : std_logic_vector (31 downto 0); -signal ipu_dataready_i : std_logic; -signal ipu_readout_finished_i : std_logic; -signal ipu_read_i : std_logic; -signal ipu_length_i : std_logic_vector (15 downto 0); -signal ipu_error_pattern_i : std_logic_vector (31 downto 0); - - -signal rdo_apl_data_in : std_logic_vector(15 downto 0); -signal rdo_apl_packet_num_in : std_logic_vector(2 downto 0); -signal rdo_apl_dataready_in : std_logic; -signal rdo_apl_read_out : std_logic; -signal rdo_apl_short_transfer_in : std_logic; -signal rdo_apl_dtype_in : std_logic_vector(3 downto 0); -signal rdo_apl_error_pattern_in : std_logic_vector(31 downto 0); -signal rdo_apl_send_in : std_logic; -signal rdo_apl_data_out : std_logic_vector(15 downto 0); -signal rdo_apl_packet_num_out : std_logic_vector(2 downto 0); -signal rdo_apl_typ_out : std_logic_vector(2 downto 0); -signal rdo_apl_dataready_out : std_logic; -signal rdo_apl_read_in : std_logic; -signal rdo_apl_run_out : std_logic; -signal rdo_apl_seqnr_out : std_logic_vector(7 downto 0); -signal rdo_apl_length_in : std_logic_vector(15 downto 0); - - -signal dbuf_addr : std_logic_vector(3 downto 0); -signal dbuf_data_in : std_logic_vector(31 downto 0); -signal dbuf_dataready : std_logic; -signal dbuf_read_enable : std_logic; -signal dbuf_unknown_addr : std_logic; -signal tbuf_dataready : std_logic; -signal tbuf_read_enable : std_logic; - -signal regio_addr_i : std_logic_vector(15 downto 0); -signal regio_data_out_i : std_logic_vector(31 downto 0); -signal regio_data_in_i : std_logic_vector(31 downto 0); -signal regio_read_enable_i : std_logic; -signal regio_write_enable_i: std_logic; -signal regio_timeout_i : std_logic; -signal regio_dataready_i : std_logic; -signal regio_write_ack_i : std_logic; -signal regio_no_more_data_i: std_logic; -signal regio_unknown_addr_i: std_logic; -signal external_send_reset_long : std_logic; -signal external_send_reset_timer : std_logic; - -signal max_event_size : std_logic_vector(15 downto 0); -signal min_event_size : std_logic_vector( 7 downto 0); -signal buffer_disable : std_logic_vector(15 downto 0); -signal new_max_size : std_logic_vector(15 downto 0); - - signal info_rd_nack : std_logic; - signal info_wr_nack : std_logic; - -signal info_registers : std_logic_vector_array_32(0 to 4); - -signal info_rx : CTRLBUS_RX; -signal info_tx : CTRLBUS_TX; - -signal info_tx_ack_or_info_tx_rack : std_logic; -signal info_tx_ack_or_info_tx_wack : std_logic; - -begin - -info_tx_ack_or_info_tx_rack <= info_tx.ack or info_tx.rack; -info_tx_ack_or_info_tx_wack <= info_tx.ack or info_tx.wack; - ---------------------------------------------------------------------- --- Reset ---------------------------------------------------------------------- ---13: reset sequence received ---14: not connected ---15: send reset sequence - - SYNC_RESET_MUX_IO : process(CLK) - begin - if rising_edge(CLK) then - reset_i <= RESET; - reset_i_mux_io <= RESET; --MED_STAT_OP(mii*16+14) or - end if; - end process; - - ---generate media resync - gen_resync : for i in 0 to mii-1 generate - MED_CTRL_OP(14+i*16 downto i*16) <= HUB_MED_CTRL_OP(14+i*16 downto i*16); - MED_CTRL_OP(15+i*16) <= hub_make_network_reset or HUB_MED_CTRL_OP(15+i*16); - end generate; --- MED_CTRL_OP(13+mii*16 downto mii*16) <= (others => '0'); --- MED_CTRL_OP(14+mii*16) <= '0'; --- MED_CTRL_OP(15+mii*16) <= hub_make_network_reset; - - - hub_make_network_reset <= external_send_reset_long;-- or MED_STAT_OP(15+4*16); --MED_STAT_OP(15) or MED_STAT_OP(15+(mii-1)*16); - - make_gbe_reset : process begin - wait until rising_edge(CLK); - if(EXTERNAL_SEND_RESET = '1') then - external_send_reset_long <= '1'; - external_send_reset_timer <= '1'; - end if; - if timer_ticks(0) = '1' then - external_send_reset_timer <= '0'; - external_send_reset_long <= external_send_reset_timer; - end if; - end process; - ---------------------------------------------------------------------- --- Connecting I/O ---------------------------------------------------------------------- - - COMMON_CTRL_REGS <= common_ctrl; - MY_ADDRESS_OUT <= my_address; - - ---------------------------------------------------------------------- --- The Hub ---------------------------------------------------------------------- - THE_HUB : trb_net16_hub_base - generic map ( - --hub control - HUB_CTRL_CHANNELNUM => c_SLOW_CTRL_CHANNEL, - HUB_CTRL_DEPTH => c_FIFO_BRAM, - HUB_USED_CHANNELS => (c_YES,c_YES,c_NO,c_YES), - USE_CHECKSUM => (c_NO,c_YES,c_YES,c_YES), - USE_VENDOR_CORES => c_YES, - IBUF_SECURE_MODE => c_NO, - INIT_ADDRESS => INIT_ADDRESS, - INIT_UNIQUE_ID => INIT_UNIQUE_ID, - INIT_CTRL_REGS => INIT_CTRL_REGS, - COMPILE_TIME => COMPILE_TIME, - INCLUDED_FEATURES => INCLUDED_FEATURES, - HARDWARE_VERSION => HARDWARE_VERSION, - HUB_CTRL_BROADCAST_BITMASK => BROADCAST_BITMASK, - CLOCK_FREQUENCY => CLOCK_FREQUENCY, - USE_ONEWIRE => USE_ONEWIRE, - BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, - MII_NUMBER => mii, - MII_IBUF_DEPTH => std_HUB_IBUF_DEPTH, - MII_IS_UPLINK => MII_IS_UPLINK, - MII_IS_DOWNLINK => MII_IS_DOWNLINK, - MII_IS_UPLINK_ONLY => MII_IS_UPLINK_ONLY, - INIT_ENDPOINT_ID => INIT_ENDPOINT_ID, - INT_NUMBER => 5, - INT_CHANNELS => (0=>0,1=>1,2=>0,3=>1,4=>3,others=>0) - ) - port map ( - CLK => CLK, - RESET => reset_i, - CLK_EN => CLK_EN, - - --Media interfacces - MED_DATAREADY_OUT => med_dataready_out(mii-1 downto 0), - MED_DATA_OUT => med_data_out(mii*16-1 downto 0), - MED_PACKET_NUM_OUT=> med_packet_num_out(mii*3-1 downto 0), - MED_READ_IN => med_read_in(mii-1 downto 0), - MED_DATAREADY_IN => med_dataready_in(mii-1 downto 0), - MED_DATA_IN => med_data_in(mii*16-1 downto 0), - MED_PACKET_NUM_IN => med_packet_num_in(mii*3-1 downto 0), - MED_READ_OUT => med_read_out(mii-1 downto 0), - MED_STAT_OP => med_stat_op(mii*16-1 downto 0), - MED_CTRL_OP => HUB_MED_CTRL_OP(mii*16-1 downto 0), - - INT_INIT_DATAREADY_OUT => hub_init_dataready_out, - INT_INIT_DATA_OUT => hub_init_data_out, - INT_INIT_PACKET_NUM_OUT => hub_init_packet_num_out, - INT_INIT_READ_IN => hub_init_read_in, - INT_INIT_DATAREADY_IN => hub_init_dataready_in, - INT_INIT_DATA_IN => hub_init_data_in, - INT_INIT_PACKET_NUM_IN => hub_init_packet_num_in, - INT_INIT_READ_OUT => hub_init_read_out, - INT_REPLY_DATAREADY_OUT => hub_reply_dataready_out, - INT_REPLY_DATA_OUT => hub_reply_data_out, - INT_REPLY_PACKET_NUM_OUT => hub_reply_packet_num_out, - INT_REPLY_READ_IN => hub_reply_read_in, - INT_REPLY_DATAREADY_IN => hub_reply_dataready_in, - INT_REPLY_DATA_IN => hub_reply_data_in, - INT_REPLY_PACKET_NUM_IN => hub_reply_packet_num_in, - INT_REPLY_READ_OUT => hub_reply_read_out, - --REGIO INTERFACE - REGIO_ADDR_OUT => regio_addr_i, - REGIO_READ_ENABLE_OUT => regio_read_enable_i, - REGIO_WRITE_ENABLE_OUT => regio_write_enable_i, - REGIO_DATA_OUT => regio_data_out_i, - REGIO_DATA_IN => regio_data_in_i, - REGIO_DATAREADY_IN => regio_dataready_i, - REGIO_NO_MORE_DATA_IN => regio_no_more_data_i, - REGIO_WRITE_ACK_IN => regio_write_ack_i, - REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_i, - REGIO_TIMEOUT_OUT => regio_timeout_i, - TIMER_TICKS_OUT => timer_ticks, - TEMPERATURE_OUT => TEMPERATURE_OUT, - ONEWIRE => ONEWIRE, - ONEWIRE_MONITOR_IN => ONEWIRE_MONITOR_IN, - ONEWIRE_MONITOR_OUT=> ONEWIRE_MONITOR_OUT, - MY_ADDRESS_OUT => my_address, - UNIQUE_ID_OUT => UNIQUE_ID_OUT, - COMMON_CTRL_REGS => common_ctrl, - COMMON_STAT_REGS => common_stat, - COMMON_CTRL_REG_STROBE => common_ctrl_strobe, - COMMON_STAT_REG_STROBE => common_stat_strobe, - MPLEX_CTRL => (others => '0'), - CTRL_DEBUG => hub_ctrl_debug, - STAT_DEBUG => STAT_DEBUG, - HUB_STAT_GEN => buf_HUB_STAT_GEN - ); - - hub_ctrl_debug(2 downto 0) <= not ERROR_OK; - hub_ctrl_debug(31 downto 3) <= (others => '0'); - HUB_STAT_GEN <= buf_HUB_STAT_GEN; - - - --------------------------------------------------------------------- --- Trigger Channel Sender ---------------------------------------------------------------------- - TRG_CHANNEL_API: trb_net16_api_base - generic map ( - API_TYPE => c_API_ACTIVE, - FIFO_TO_INT_DEPTH => 6, - FIFO_TO_APL_DEPTH => 6, - FORCE_REPLY => 1, - SBUF_VERSION => 0, - USE_VENDOR_CORES => c_YES, - SECURE_MODE_TO_APL => c_YES, - SECURE_MODE_TO_INT => c_YES, - APL_WRITE_ALL_WORDS=> c_YES - ) - port map ( - -- Misc - CLK => CLK, - RESET => reset_i, - CLK_EN => CLK_EN, - -- APL Transmitter port - APL_DATA_IN => (others => '0'), - APL_PACKET_NUM_IN => "000", - APL_DATAREADY_IN => '0', - APL_READ_OUT => open, - APL_SHORT_TRANSFER_IN => '1', - APL_DTYPE_IN => CTS_TRG_TYPE_IN, - APL_ERROR_PATTERN_IN => trg_apl_error_pattern_in(31 downto 0), - APL_SEND_IN => CTS_TRG_SEND_IN, - APL_TARGET_ADDRESS_IN => (others => '0'), - -- Receiver port - APL_DATA_OUT => trg_apl_data_out(15 downto 0), - APL_PACKET_NUM_OUT=> trg_apl_packet_num_out(2 downto 0), - APL_TYP_OUT => trg_apl_typ_out(2 downto 0), - APL_DATAREADY_OUT => trg_apl_dataready_out, - APL_READ_IN => trg_apl_read_in, - -- APL Control port - APL_RUN_OUT => trg_apl_run_out, - APL_MY_ADDRESS_IN => my_address, - APL_SEQNR_OUT => open, - APL_LENGTH_IN => (others => '0'), - -- Internal direction port - INT_MASTER_DATAREADY_OUT => hub_init_dataready_in(2), - INT_MASTER_DATA_OUT => tmp_hub_init_data_in, - INT_MASTER_PACKET_NUM_OUT=> hub_init_packet_num_in(8 downto 6), - INT_MASTER_READ_IN => hub_init_read_out(2), - INT_MASTER_DATAREADY_IN => '0', - INT_MASTER_DATA_IN => (others => '0'), - INT_MASTER_PACKET_NUM_IN => "000", - INT_MASTER_READ_OUT => open, - INT_SLAVE_DATAREADY_OUT => open, - INT_SLAVE_DATA_OUT => open, - INT_SLAVE_PACKET_NUM_OUT => open, - INT_SLAVE_READ_IN => '1', - INT_SLAVE_DATAREADY_IN => hub_reply_dataready_out(2), - INT_SLAVE_DATA_IN => hub_reply_data_out(47 downto 32), - INT_SLAVE_PACKET_NUM_IN=> hub_reply_packet_num_out(8 downto 6), - INT_SLAVE_READ_OUT => hub_reply_read_in(2), - -- Status and control port - CTRL_SEQNR_RESET => common_ctrl(10), - STAT_FIFO_TO_INT => open, - STAT_FIFO_TO_APL => open - ); - - trg_apl_error_pattern_in(15 downto 0) <= CTS_TRG_NUMBER_IN; - trg_apl_error_pattern_in(23 downto 16) <= CTS_TRG_RND_CODE_IN; - trg_apl_error_pattern_in(31 downto 24) <= CTS_TRG_INFORMATION_IN(7 downto 0); - CTS_TRG_BUSY_OUT <= trg_apl_run_out; - - hub_reply_dataready_in(2) <= '0'; - hub_reply_data_in(47 downto 32) <= (others => '0'); - hub_reply_packet_num_in(8 downto 6) <= (others => '0'); - hub_init_read_in(2) <= '0'; - - trg_apl_read_in <= '1'; - - PROC_TRG_STATUS_BITS : process(CLK) - begin - if rising_edge(CLK) then - if trg_apl_packet_num_out = c_F1 and trg_apl_typ_out = TYPE_TRM then - CTS_TRG_STATUS_BITS_OUT(31 downto 16) <= trg_apl_data_out; - end if; - if trg_apl_packet_num_out = c_F2 and trg_apl_typ_out = TYPE_TRM then - CTS_TRG_STATUS_BITS_OUT(15 downto 0) <= trg_apl_data_out; - end if; - end if; - end process; - - proc_add_trigger_info : process(hub_init_packet_num_in, reg_ext_trg_information, tmp_hub_init_data_in) - begin - if hub_init_packet_num_in(8 downto 6) = c_F0 then - hub_init_data_in(47 downto 32) <= reg_ext_trg_information; - else - hub_init_data_in(47 downto 32) <= tmp_hub_init_data_in; - end if; - end process; - - proc_save_trigger_info : process(CLK) - begin - if rising_edge(CLK) then - if CTS_TRG_SEND_IN = '1' then - reg_ext_trg_information <= CTS_TRG_INFORMATION_IN(23 downto 8); - end if; - end if; - end process; - - - ---------------------------------------------------------------------- --- IPU Channel Sender ---------------------------------------------------------------------- - - hub_reply_data_in(63 downto 48) <= (others => '0'); - hub_reply_packet_num_in(11 downto 9) <= (others => '0'); - hub_reply_dataready_in(3) <= '0'; - hub_init_read_in(3) <= '1'; - - THE_STREAMING : trb_net16_api_ipu_streaming_internal - port map( - CLK => CLK, - RESET => reset_i, - CLK_EN => CLK_EN, - - -- Internal direction port - FEE_INIT_DATA_OUT => hub_init_data_in(63 downto 48), - FEE_INIT_DATAREADY_OUT => hub_init_dataready_in(3), - FEE_INIT_PACKET_NUM_OUT => hub_init_packet_num_in(11 downto 9), - FEE_INIT_READ_IN => hub_init_read_out(3), - FEE_REPLY_DATA_IN => hub_reply_data_out(63 downto 48), - FEE_REPLY_DATAREADY_IN => hub_reply_dataready_out(3), - FEE_REPLY_PACKET_NUM_IN => hub_reply_packet_num_out(11 downto 9), - FEE_REPLY_READ_OUT => hub_reply_read_in(3), - - --from CTS - CTS_SEND_IN => CTS_IPU_SEND_IN, - CTS_NUMBER_IN => CTS_IPU_NUMBER_IN, - CTS_CODE_IN => CTS_IPU_RND_CODE_IN, - CTS_INFORMATION_IN => CTS_IPU_INFORMATION_IN, - CTS_READOUT_TYPE_IN => CTS_IPU_TYPE_IN, - - --to CTS - CTS_STATUS_BITS_OUT => CTS_IPU_STATUS_BITS_OUT, - CTS_BUSY_OUT => CTS_IPU_BUSY_OUT, - - --from APL to GbE - GBE_FEE_DATA_OUT => GBE_FEE_DATA_OUT, - GBE_FEE_DATAREADY_OUT => GBE_FEE_DATAREADY_OUT, - GBE_FEE_READ_IN => GBE_FEE_READ_IN, - GBE_FEE_STATUS_BITS_OUT => GBE_FEE_STATUS_BITS_OUT, - GBE_FEE_BUSY_OUT => GBE_FEE_BUSY_OUT, - - GBE_CTS_NUMBER_OUT => GBE_CTS_NUMBER_OUT, - GBE_CTS_CODE_OUT => GBE_CTS_CODE_OUT, - GBE_CTS_INFORMATION_OUT => GBE_CTS_INFORMATION_OUT, - GBE_CTS_READOUT_TYPE_OUT => GBE_CTS_READOUT_TYPE_OUT, - GBE_CTS_START_READOUT_OUT => GBE_CTS_START_READOUT_OUT, - - --from GbE to CTS - GBE_READOUT_FINISHED_IN => GBE_CTS_READOUT_FINISHED_IN, - GBE_STATUS_BITS_IN => GBE_CTS_STATUS_BITS_IN, - - MY_ADDRESS_IN => my_address, - CTRL_SEQNR_RESET => common_ctrl(10) - ); - - - ---------------------------------------------------------------------- --- Trigger Channel read-out ---------------------------------------------------------------------- - RDO_READOUT_TRG : trb_net16_trigger - port map( - CLK => CLK, - RESET => reset_i, - CLK_EN => CLK_EN, - INT_DATAREADY_OUT => hub_reply_dataready_in(0), - INT_DATA_OUT => hub_reply_data_in(15 downto 0), - INT_PACKET_NUM_OUT => hub_reply_packet_num_in(2 downto 0), - INT_READ_IN => hub_reply_read_out(0), - INT_DATAREADY_IN => hub_init_dataready_out(0), - INT_DATA_IN => hub_init_data_out(15 downto 0), - INT_PACKET_NUM_IN => hub_init_packet_num_out(2 downto 0), - INT_READ_OUT => hub_init_read_in(0), - TRG_RECEIVED_OUT => lvl1_trg_received, - TRG_TYPE_OUT => lvl1_trg_type, - TRG_NUMBER_OUT => lvl1_trg_number, - TRG_CODE_OUT => lvl1_trg_code, - TRG_INFORMATION_OUT => lvl1_trg_information, - TRG_RELEASE_IN => lvl1_handler_trg_release, - TRG_ERROR_PATTERN_IN => lvl1_handler_error_pattern - ); - - hub_init_dataready_in(0) <= '0'; - hub_init_data_in(15 downto 0) <= (others => '0'); - hub_init_packet_num_in(2 downto 0) <= (others => '0'); - hub_reply_read_in(0) <= '0'; - - RDO_LVL1_HANDLER : handler_lvl1 - generic map ( - TIMING_TRIGGER_RAW => c_NO - ) - port map( - RESET => reset_i, - RESET_FLAGS_IN => common_ctrl(4), - RESET_STATS_IN => common_ctrl(5), - CLOCK => CLK, - --Timing Trigger - LVL1_TIMING_TRG_IN => RDO_TRIGGER_IN, - LVL1_PSEUDO_TMG_TRG_IN => common_ctrl(16), - --LVL1_handler connection - LVL1_TRG_RECEIVED_IN => lvl1_trg_received, - LVL1_TRG_TYPE_IN => lvl1_trg_type, - LVL1_TRG_NUMBER_IN => lvl1_trg_number, - LVL1_TRG_CODE_IN => lvl1_trg_code, - LVL1_TRG_INFORMATION_IN => lvl1_trg_information, - LVL1_ERROR_PATTERN_OUT => lvl1_handler_error_pattern, - LVL1_TRG_RELEASE_OUT => lvl1_handler_trg_release, - - LVL1_INT_TRG_NUMBER_OUT => int_trigger_num, - LVL1_INT_TRG_LOAD_IN => common_ctrl_strobe(1), - LVL1_INT_TRG_COUNTER_IN => common_ctrl(47 downto 32), - - --FEE logic / Data Handler - LVL1_TRG_DATA_VALID_OUT => lvl1_data_valid_i, - LVL1_VALID_TIMING_TRG_OUT => lvl1_valid_timing_i, - LVL1_VALID_NOTIMING_TRG_OUT => lvl1_valid_notiming_i, - LVL1_INVALID_TRG_OUT => lvl1_invalid_i, - LVL1_DELAY_OUT => int_lvl1_delay, - - LVL1_ERROR_PATTERN_IN => lvl1_error_pattern, - LVL1_TRG_RELEASE_IN => lvl1_trg_release, - - --Stat/Control - STATUS_OUT => stat_lvl1_handler, - TRG_ENABLE_IN => '1', - TRG_INVERT_IN => '0', - COUNTERS_STATUS_OUT => stat_counters_lvl1_handler, - --Debug - DEBUG_OUT => open - ); - - ---------------------------------------------------------------------- --- IPU Channel read-out ---------------------------------------------------------------------- - - RDO_IPU_API : trb_net16_api_base - generic map ( - API_TYPE => c_API_PASSIVE, - APL_WRITE_ALL_WORDS => c_YES, - ADDRESS_MASK => x"FFFF", - BROADCAST_BITMASK => BROADCAST_BITMASK, - BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR - ) - port map ( - -- Misc - CLK => CLK, - RESET => reset_i, - CLK_EN => CLK_EN, - -- APL Transmitter port - APL_DATA_IN => rdo_apl_data_in, - APL_PACKET_NUM_IN => rdo_apl_packet_num_in, - APL_DATAREADY_IN => rdo_apl_dataready_in, - APL_READ_OUT => rdo_apl_read_out, - APL_SHORT_TRANSFER_IN => rdo_apl_short_transfer_in, - APL_DTYPE_IN => rdo_apl_dtype_in, - APL_ERROR_PATTERN_IN => rdo_apl_error_pattern_in, - APL_SEND_IN => rdo_apl_send_in, - APL_TARGET_ADDRESS_IN => (others => '0'), - -- Receiver port - APL_DATA_OUT => rdo_apl_data_out, - APL_PACKET_NUM_OUT=> rdo_apl_packet_num_out, - APL_TYP_OUT => rdo_apl_typ_out, - APL_DATAREADY_OUT => rdo_apl_dataready_out, - APL_READ_IN => rdo_apl_read_in, - -- APL Control port - APL_RUN_OUT => rdo_apl_run_out, - APL_MY_ADDRESS_IN => my_address, - APL_SEQNR_OUT => rdo_apl_seqnr_out, - APL_LENGTH_IN => rdo_apl_length_in, - -- Internal direction port - INT_MASTER_DATAREADY_OUT => hub_reply_dataready_in(1), - INT_MASTER_DATA_OUT => hub_reply_data_in(31 downto 16), - INT_MASTER_PACKET_NUM_OUT=> hub_reply_packet_num_in(5 downto 3), - INT_MASTER_READ_IN => hub_reply_read_out(1), - INT_MASTER_DATAREADY_IN => '0', - INT_MASTER_DATA_IN => (others => '0'), - INT_MASTER_PACKET_NUM_IN => (others => '0'), - INT_MASTER_READ_OUT => open, - INT_SLAVE_DATAREADY_OUT => open, - INT_SLAVE_DATA_OUT => open, - INT_SLAVE_PACKET_NUM_OUT => open, - INT_SLAVE_READ_IN => '1', - INT_SLAVE_DATAREADY_IN => hub_init_dataready_out(1), - INT_SLAVE_DATA_IN => hub_init_data_out(31 downto 16), - INT_SLAVE_PACKET_NUM_IN=> hub_init_packet_num_out(5 downto 3), - INT_SLAVE_READ_OUT => hub_init_read_in(1), - -- Status and control port - CTRL_SEQNR_RESET => common_ctrl(10), - STAT_FIFO_TO_INT => open, - STAT_FIFO_TO_APL => open - ); - - hub_init_dataready_in(1) <= '0'; - hub_init_data_in(31 downto 16) <= (others => '0'); - hub_init_packet_num_in(5 downto 3) <= (others => '0'); - hub_reply_read_in(1) <= '0'; - - RDO_IPUDATA_APL : trb_net16_ipudata - port map( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - API_DATA_OUT => rdo_apl_data_in, - API_PACKET_NUM_OUT => rdo_apl_packet_num_in, - API_DATAREADY_OUT => rdo_apl_dataready_in, - API_READ_IN => rdo_apl_read_out, - API_SHORT_TRANSFER_OUT => rdo_apl_short_transfer_in, - API_DTYPE_OUT => rdo_apl_dtype_in, - API_ERROR_PATTERN_OUT => rdo_apl_error_pattern_in, - API_SEND_OUT => rdo_apl_send_in, - API_DATA_IN => rdo_apl_data_out, - API_PACKET_NUM_IN => rdo_apl_packet_num_out, - API_TYP_IN => rdo_apl_typ_out, - API_DATAREADY_IN => rdo_apl_dataready_out, - API_READ_OUT => rdo_apl_read_in, - API_RUN_IN => rdo_apl_run_out, - API_SEQNR_IN => rdo_apl_seqnr_out, - API_LENGTH_OUT => rdo_apl_length_in, - MY_ADDRESS_IN => my_address, - IPU_NUMBER_OUT => ipu_number_i, - IPU_READOUT_TYPE_OUT => ipu_readout_type_i, - IPU_INFORMATION_OUT => ipu_information_i, - IPU_START_READOUT_OUT => ipu_start_readout_i, - IPU_DATA_IN => ipu_data_i, - IPU_DATAREADY_IN => ipu_dataready_i, - IPU_READOUT_FINISHED_IN=> ipu_readout_finished_i, - IPU_READ_OUT => ipu_read_i, - IPU_LENGTH_IN => ipu_length_i, - IPU_ERROR_PATTERN_IN => ipu_error_pattern_i, - STAT_DEBUG => open - ); - - ---------------------------------------------------------------------- --- Read-out data handler ---------------------------------------------------------------------- - - RDO_HANDLER_TRIGGER_DATA : handler_trigger_and_data - generic map( - DATA_INTERFACE_NUMBER => DATA_INTERFACE_NUMBER, - DATA_BUFFER_DEPTH => RDO_DATA_BUFFER_DEPTH, - DATA_BUFFER_WIDTH => 32, - DATA_BUFFER_FULL_THRESH => RDO_DATA_BUFFER_FULL_THRESH, - TRG_RELEASE_AFTER_DATA => c_YES, - HEADER_BUFFER_DEPTH => RDO_HEADER_BUFFER_DEPTH, - HEADER_BUFFER_FULL_THRESH => RDO_HEADER_BUFFER_FULL_THRESH - ) - port map( - CLOCK => CLK, - RESET => reset_i, - RESET_IPU => reset_ipu_i, - --LVL1 channel - LVL1_VALID_TRIGGER_IN => lvl1_valid_i, - LVL1_INT_TRG_NUMBER_IN => int_trigger_num, - LVL1_TRG_DATA_VALID_IN => lvl1_data_valid_i, - LVL1_TRG_TYPE_IN => lvl1_trg_type, - LVL1_TRG_NUMBER_IN => lvl1_trg_number, - LVL1_TRG_CODE_IN => lvl1_trg_code, - LVL1_TRG_INFORMATION_IN => lvl1_trg_information, - LVL1_ERROR_PATTERN_OUT => lvl1_error_pattern, - LVL1_TRG_RELEASE_OUT => lvl1_trg_release, - - --IPU channel - IPU_NUMBER_IN => ipu_number_i, - IPU_INFORMATION_IN => ipu_information_i, - IPU_READOUT_TYPE_IN => ipu_readout_type_i, - IPU_START_READOUT_IN => ipu_start_readout_i, - IPU_DATA_OUT => ipu_data_i, - IPU_DATAREADY_OUT => ipu_dataready_i, - IPU_READOUT_FINISHED_OUT => ipu_readout_finished_i, - IPU_READ_IN => ipu_read_i, - IPU_LENGTH_OUT => ipu_length_i, - IPU_ERROR_PATTERN_OUT => ipu_error_pattern_i, - - --FEE Input - FEE_TRG_RELEASE_IN(0) => RDO_DATA_FINISHED_IN, - FEE_TRG_RELEASE_IN(RDO_ADDITIONAL_PORT downto 1) => RDO_ADDITIONAL_FINISHED, - FEE_TRG_STATUSBITS_IN(31 downto 0) => RDO_TRG_STATUSBITS_IN, - FEE_TRG_STATUSBITS_IN(RDO_ADDITIONAL_PORT*32+31 downto 32) => RDO_ADDITIONAL_STATUSBITS_IN, - FEE_DATA_IN(31 downto 0) => RDO_DATA_IN, - FEE_DATA_IN(RDO_ADDITIONAL_PORT*32+31 downto 32) => RDO_ADDITIONAL_DATA, - FEE_DATA_WRITE_IN(0) => RDO_DATA_WRITE_IN, - FEE_DATA_WRITE_IN(RDO_ADDITIONAL_PORT downto 1) => RDO_ADDITIONAL_WRITE, - FEE_DATA_FINISHED_IN(0) => RDO_DATA_FINISHED_IN, - FEE_DATA_FINISHED_IN(RDO_ADDITIONAL_PORT downto 1) => RDO_ADDITIONAL_FINISHED, - FEE_DATA_ALMOST_FULL_OUT => open, - - TMG_TRG_ERROR_IN => '0', - MAX_EVENT_SIZE_IN => max_event_size, - MIN_EVENT_SIZE_IN => min_event_size, - BUFFER_DISABLE_IN => buffer_disable, - - --Status Registers - STAT_DATA_BUFFER_LEVEL => stat_data_buffer_level, - STAT_HEADER_BUFFER_LEVEL => stat_header_buffer_level, - STATUS_OUT => stat_handler_i, - TIMER_TICKS_IN => timer_ticks, - STATISTICS_DATA_OUT => stat_buffer_i, - STATISTICS_UNKNOWN_OUT => stat_buffer_unknown, - STATISTICS_READY_OUT => stat_buffer_ready, - STATISTICS_READ_IN => stat_buffer_read, - STATISTICS_ADDR_IN => stat_buffer_address, - --Debug - DEBUG_DATA_HANDLER_OUT => open, - DEBUG_IPU_HANDLER_OUT => open - - ); - - reset_ipu_i <= reset_i or common_ctrl(2); - lvl1_valid_i <= lvl1_valid_timing_i or lvl1_valid_notiming_i or lvl1_invalid_i; - - RDO_VALID_TIMING_TRG_OUT <= lvl1_valid_timing_i; - RDO_VALID_NOTIMING_TRG_OUT <= lvl1_valid_notiming_i; - RDO_INVALID_TRG_OUT <= lvl1_invalid_i; - RDO_TRG_DATA_VALID_OUT <= lvl1_data_valid_i; - - RDO_TRG_TYPE_OUT <= lvl1_trg_type; - RDO_TRG_CODE_OUT <= lvl1_trg_code; - RDO_TRG_INFORMATION_OUT <= lvl1_trg_information; - RDO_TRG_NUMBER_OUT <= lvl1_trg_number; - - - proc_buf_status : process(CLK) - variable tmp : integer range 0 to 15; - begin - if rising_edge(CLK) then - dbuf_unknown_addr <= '0'; - dbuf_dataready <= '0'; - --tbuf_dataready <= tbuf_read_enable; - if dbuf_read_enable = '1' then - tmp := to_integer(unsigned(dbuf_addr)); - if tmp < DATA_INTERFACE_NUMBER then - dbuf_data_in <= stat_data_buffer_level(tmp*32+31 downto tmp*32); - dbuf_dataready <= '1'; - else - dbuf_data_in <= (others => '0'); - dbuf_unknown_addr <= '1'; - end if; - end if; - end if; - end process; - - - - --- process(REGIO_COMMON_STAT_REG_IN, debug_ipu_handler_i,common_ctrl_reg_i, common_stat_reg_i) --- begin --- common_stat_reg_i(8 downto 0) <= REGIO_COMMON_STAT_REG_IN(8 downto 0); --- common_stat_reg_i(47 downto 12) <= REGIO_COMMON_STAT_REG_IN(47 downto 12); --- common_stat_reg_i(6) <= debug_ipu_handler_i(15) or REGIO_COMMON_STAT_REG_IN(6); --- --- if rising_edge(CLK) then --- if common_ctrl_reg_i(4) = '1' then --- common_stat_reg_i(11 downto 9) <= "000"; --- else --- common_stat_reg_i(9) <= debug_ipu_handler_i(12) or REGIO_COMMON_STAT_REG_IN(9) or common_stat_reg_i(9); --- common_stat_reg_i(10) <= debug_ipu_handler_i(13) or REGIO_COMMON_STAT_REG_IN(10) or common_stat_reg_i(10); --- common_stat_reg_i(11) <= debug_ipu_handler_i(14) or REGIO_COMMON_STAT_REG_IN(11) or common_stat_reg_i(11); --- end if; --- end if; --- common_stat_reg_i(159 downto 64) <= REGIO_COMMON_STAT_REG_IN(159 downto 64); --- end process; --- --- process(CLK) --- begin --- if rising_edge(CLK) then --- if ipu_start_readout_i = '1' then --- common_stat_reg_i(63 downto 48) <= ipu_number_i; --- end if; --- end if; --- end process; - ---------------------------------------------------------------------- --- Slowcontrol injection via GbE ---------------------------------------------------------------------- - hub_init_dataready_in(4) <= GSC_INIT_DATAREADY_IN; - hub_init_data_in(79 downto 64) <= GSC_INIT_DATA_IN; - hub_init_packet_num_in(14 downto 12) <= GSC_INIT_PACKET_NUM_IN; - GSC_INIT_READ_OUT <= hub_init_read_out(4); - GSC_REPLY_DATAREADY_OUT <= hub_reply_dataready_out(4); - GSC_REPLY_DATA_OUT <= hub_reply_data_out(79 downto 64); - GSC_REPLY_PACKET_NUM_OUT <= hub_reply_packet_num_out(14 downto 12); - hub_reply_read_in(4) <= GSC_REPLY_READ_IN; - GSC_BUSY_OUT <= buf_HUB_STAT_GEN(3); - - hub_reply_dataready_in(4) <= '0'; - hub_reply_data_in(79 downto 64) <= (others => '0'); - hub_reply_packet_num_in(14 downto 12) <= (others => '0'); - hub_init_read_in(4) <= '1'; - - -------------------------------------------------- --- Common Status Register -------------------------------------------------- - proc_gen_common_stat_regs : process(stat_lvl1_handler, lvl1_trg_information, - lvl1_trg_type, lvl1_trg_number, lvl1_trg_code, - stat_counters_lvl1_handler, int_trigger_num) - begin - common_stat(47 downto 0) <= (others => '0'); - common_stat(std_COMSTATREG*32-1 downto 64) <= (others => '0'); - - common_stat(4) <= stat_lvl1_handler(12); - common_stat(13) <= stat_lvl1_handler(7); - common_stat(47 downto 32) <= int_trigger_num; - common_stat(127 downto 64) <= stat_lvl1_handler; - common_stat(175 downto 160) <= lvl1_trg_information(15 downto 0); - common_stat(179 downto 176) <= lvl1_trg_type; - common_stat(183 downto 180) <= lvl1_trg_number(3 downto 0); - common_stat(191 downto 184) <= lvl1_trg_code; - common_stat(271 downto 192) <= stat_counters_lvl1_handler; - end process; - - process(CLK) - begin - if rising_edge(CLK) then - if ipu_start_readout_i = '1' then - common_stat(63 downto 48) <= ipu_number_i; - end if; - end if; - end process; - -COMMON_STAT_REGS <= common_stat; - ---------------------------------------------------------------------------- --- RegIO Bus Handler ---------------------------------------------------------------------------- - THE_INTERNAL_BUS_HANDLER : trb_net16_regio_bus_handler - generic map( - PORT_NUMBER => 7, - PORT_ADDRESSES => (0 => x"8000", 1 => x"7100", 2 => x"7110", 3 => x"7200", 4 => x"7201", 5 => x"7202", 6 => x"7300", others => x"0000"), - PORT_ADDR_MASK => (0 => 15, 1 => 4, 2 => 3, 3 => 0, 4 => 0, 5 => 0, 6 => 5, others => 0) - ) - port map( - CLK => CLK, - RESET => reset_i, - - DAT_ADDR_IN => regio_addr_i, - DAT_DATA_IN => regio_data_out_i, - DAT_DATA_OUT => regio_data_in_i, - DAT_READ_ENABLE_IN => regio_read_enable_i, - DAT_WRITE_ENABLE_IN => regio_write_enable_i, - DAT_TIMEOUT_IN => regio_timeout_i, - DAT_DATAREADY_OUT => regio_dataready_i, - DAT_WRITE_ACK_OUT => regio_write_ack_i, - DAT_NO_MORE_DATA_OUT => regio_no_more_data_i, - DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_i, ---Fucking Modelsim wants it like this... - BUS_READ_ENABLE_OUT(0) => REGIO_READ_ENABLE_OUT, - BUS_READ_ENABLE_OUT(1) => dbuf_read_enable, - BUS_READ_ENABLE_OUT(2) => info_rx.read,--tbuf_read_enable, - BUS_READ_ENABLE_OUT(3) => read_enable(3), - BUS_READ_ENABLE_OUT(4) => read_enable(4), - BUS_READ_ENABLE_OUT(5) => read_enable(5), - BUS_READ_ENABLE_OUT(6) => stat_buffer_read, - BUS_WRITE_ENABLE_OUT(0) => REGIO_WRITE_ENABLE_OUT, - BUS_WRITE_ENABLE_OUT(1) => dummy(0), - BUS_WRITE_ENABLE_OUT(2) => info_rx.write,--write_enable(2), - BUS_WRITE_ENABLE_OUT(3) => write_enable(3), - BUS_WRITE_ENABLE_OUT(4) => write_enable(4), - BUS_WRITE_ENABLE_OUT(5) => write_enable(5), - BUS_WRITE_ENABLE_OUT(6) => write_enable(6), - BUS_DATA_OUT(31 downto 0) => REGIO_DATA_OUT, - BUS_DATA_OUT(63 downto 32) => dummy(33 downto 2), - BUS_DATA_OUT(95 downto 64) => info_rx.data,--dummy(65 downto 34), - BUS_DATA_OUT(191 downto 96) => dummy(191 downto 96), - BUS_DATA_OUT(223 downto 192)=> dummy(291 downto 260), - BUS_ADDR_OUT(15 downto 0) => REGIO_ADDR_OUT, - BUS_ADDR_OUT(19 downto 16) => dbuf_addr, - BUS_ADDR_OUT(31 downto 20) => dummy(77 downto 66), - BUS_ADDR_OUT(47 downto 32) => info_rx.addr,--dummy(93 downto 78), - BUS_ADDR_OUT(95 downto 48) => dummy(242 downto 195), - BUS_ADDR_OUT(100 downto 96)=> stat_buffer_address, - BUS_ADDR_OUT(111 downto 101)=> dummy(259 downto 249), - BUS_TIMEOUT_OUT(0) => REGIO_TIMEOUT_OUT, - BUS_TIMEOUT_OUT(1) => dummy(94), - BUS_TIMEOUT_OUT(2) => info_rx.timeout,--dummy(95), - BUS_TIMEOUT_OUT(3) => dummy(192), - BUS_TIMEOUT_OUT(4) => dummy(193), - BUS_TIMEOUT_OUT(5) => dummy(194), - BUS_TIMEOUT_OUT(6) => dummy(243), - BUS_DATA_IN(31 downto 0) => REGIO_DATA_IN, - BUS_DATA_IN(63 downto 32) => dbuf_data_in, - BUS_DATA_IN(95 downto 64) => info_tx.data,--stat_header_buffer_level, - BUS_DATA_IN(191 downto 96) => stat_handler_i(95 downto 0), - BUS_DATA_IN(223 downto 192)=> stat_buffer_i, - BUS_DATAREADY_IN(0) => REGIO_DATAREADY_IN, - BUS_DATAREADY_IN(1) => dbuf_dataready, - BUS_DATAREADY_IN(2) => info_tx_ack_or_info_tx_rack,--tbuf_dataready, - BUS_DATAREADY_IN(3) => last_read_enable(3), - BUS_DATAREADY_IN(4) => last_read_enable(4), - BUS_DATAREADY_IN(5) => last_read_enable(5), - BUS_DATAREADY_IN(6) => stat_buffer_ready, - BUS_WRITE_ACK_IN(0) => REGIO_WRITE_ACK_IN, - BUS_WRITE_ACK_IN(1) => '0', - BUS_WRITE_ACK_IN(2) => info_tx_ack_or_info_tx_wack,--'0', - BUS_WRITE_ACK_IN(3) => '0', - BUS_WRITE_ACK_IN(4) => '0', - BUS_WRITE_ACK_IN(5) => '0', - BUS_WRITE_ACK_IN(6) => '0', - BUS_NO_MORE_DATA_IN(0) => REGIO_NO_MORE_DATA_IN, - BUS_NO_MORE_DATA_IN(1) => '0', - BUS_NO_MORE_DATA_IN(2) => info_tx.nack,--'0', - BUS_NO_MORE_DATA_IN(3) => '0', - BUS_NO_MORE_DATA_IN(4) => '0', - BUS_NO_MORE_DATA_IN(5) => '0', - BUS_NO_MORE_DATA_IN(6) => '0', - BUS_UNKNOWN_ADDR_IN(0) => REGIO_UNKNOWN_ADDR_IN, - BUS_UNKNOWN_ADDR_IN(1) => dbuf_unknown_addr, - BUS_UNKNOWN_ADDR_IN(2) => info_tx.unknown,--last_write_enable(2), - BUS_UNKNOWN_ADDR_IN(3) => last_write_enable(3), - BUS_UNKNOWN_ADDR_IN(4) => last_write_enable(4), - BUS_UNKNOWN_ADDR_IN(5) => last_write_enable(5), - BUS_UNKNOWN_ADDR_IN(6) => stat_buffer_unknown - ); - - last_write_enable <= write_enable when rising_edge(CLK); - last_read_enable <= read_enable when rising_edge(CLK); - - TIMER_TICKS_OUT <= timer_ticks; - ---------------------------------------------------------------------------- --- registers 0x7110 ff. ---------------------------------------------------------------------------- - - THE_HANDLER_INFO_REGS : bus_register_handler - generic map( - BUS_LENGTH => 5 - ) - port map( - RESET => RESET, - CLK => CLK, - DATA_IN => info_registers, - READ_EN_IN => info_rx.read, - WRITE_EN_IN => '0', - ADDR_IN(2 downto 0) => info_rx.addr(2 downto 0), - ADDR_IN(6 downto 3) => "0000", - DATA_OUT => info_tx.data, - DATAREADY_OUT => info_tx.rack, - UNKNOWN_ADDR_OUT => info_rd_nack - ); - - info_tx.unknown <= info_rd_nack or info_wr_nack; - info_registers(0) <= stat_header_buffer_level; - info_registers(1) <= std_logic_vector(to_unsigned((2**RDO_DATA_BUFFER_DEPTH-RDO_DATA_BUFFER_FULL_THRESH-1),16)) & max_event_size; - info_registers(2) <= std_logic_vector(to_unsigned(RDO_DATA_BUFFER_FULL_THRESH,16)) - & std_logic_vector(to_unsigned(RDO_DATA_BUFFER_DEPTH,8)) - & std_logic_vector(to_unsigned(DATA_INTERFACE_NUMBER,8)); - info_registers(3) <= std_logic_vector(to_unsigned(c_YES,1)) --TRIGGER_RELEASE_AFTER_DATA - & "0000000" - & std_logic_vector(to_unsigned(RDO_HEADER_BUFFER_FULL_THRESH,16)) - & std_logic_vector(to_unsigned(RDO_HEADER_BUFFER_DEPTH,8)); - info_registers(4) <= x"00" & min_event_size & buffer_disable; - - proc_maxeventsize : process begin - wait until rising_edge(CLK); - info_tx.wack <= '0'; - info_wr_nack <= info_rx.write; - if RESET = '1' then - max_event_size <= std_logic_vector(to_unsigned((2**RDO_DATA_BUFFER_DEPTH-RDO_DATA_BUFFER_FULL_THRESH-1),16)); - buffer_disable <= (others => '0'); - min_event_size <= (others => '0'); - elsif info_rx.write = '1' and info_rx.addr(2 downto 0) = "001" then - max_event_size <= info_rx.data(15 downto 0); - info_tx.wack <= '1'; - info_wr_nack <= '0'; - elsif info_rx.write = '1' and info_rx.addr(2 downto 0) = "100" then - buffer_disable <= info_rx.data(15 downto 0); - min_event_size <= info_rx.data(23 downto 16); - info_tx.wack <= '1'; - info_wr_nack <= '0'; - end if; - end process; - ---------------------------------------------------------------------- --- Debug ---------------------------------------------------------------------- --- STAT_DEBUG(0) <= cts_reply_dataready_in; --- STAT_DEBUG(1) <= cts_reply_read_out; --- STAT_DEBUG(2) <= cts_init_dataready_out; --- STAT_DEBUG(3) <= cts_reply_read_out; --- STAT_DEBUG(4) <= io_dataready_out(2); --- STAT_DEBUG(5) <= io_dataready_out(3); --- STAT_DEBUG(6) <= '0'; --- STAT_DEBUG(7) <= '0'; - - -end architecture; -- 2.43.0