From a18a186b764c1d2b717eca31c3fde9355bdbc6e3 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 2 Aug 2013 14:16:55 +0200 Subject: [PATCH] changed all 'commands' to normal accesses --- vhdl/code/jtag_cmd_m26c.vhd | 489 +++++++++++++---------------------- vhdl/code/jtag_constants.vhd | 75 +++--- 2 files changed, 213 insertions(+), 351 deletions(-) diff --git a/vhdl/code/jtag_cmd_m26c.vhd b/vhdl/code/jtag_cmd_m26c.vhd index 6a07de1..2ae1ad8 100644 --- a/vhdl/code/jtag_cmd_m26c.vhd +++ b/vhdl/code/jtag_cmd_m26c.vhd @@ -119,10 +119,9 @@ constant RAM_ERROR_COUNTS_DEPTH : integer := MAX_REGISTERS_PLUS_TWO_LD+2+MAX_NUM -signal data_register, data_register_next : std_logic_vector(31 downto 0); -signal jtag_refresh_active, jtag_refresh_active_next : std_logic; -signal jtag_check1_active, jtag_check1_active_next : std_logic; -signal jtag_refresh_active_last, jtag_refresh_active_last_next : std_logic; +signal jtag_refresh_active : std_logic; +signal jtag_check1_active : std_logic; +signal jtag_refresh_active_last : std_logic; -- has to fit number of 32 bit words needed to represent the status register --signal status_register_pos, status_register_pos_next : std_logic_vector(MAX_NUMCHIPS_LD+2+MAX_REGISTERS_LD-5 downto 0); @@ -144,7 +143,7 @@ signal crc_status_register, crc_status_register_next : std_logic_vector(MAX_NUMC -- contains a "1" at the positions of deactivated sensors -signal removed_chips, removed_chips_next : std_logic_vector(MAX_NUMCHIPS -1 downto 0); +signal removed_chips : std_logic_vector(MAX_NUMCHIPS -1 downto 0); signal last_not_removed, last_not_removed_next : unsigned(MAX_NUMCHIPS_LD - 1 downto 0); signal first_not_removed, first_not_removed_next : unsigned(MAX_NUMCHIPS_LD - 1 downto 0); @@ -157,7 +156,7 @@ signal cc_state, cc_state_next : CC_STATE_TYPE; signal ram1a_a2 : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); signal ram1a_dout2 : std_logic_vector(31 downto 0); -signal ram1a_a1_base_addr, ram1a_a1_base_addr_next : std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0); +signal ram1a_a1_base_addr : std_logic_vector(MAX_NUMCHIPS_LD-1 downto 0); signal ram1a_a1_rel_addr : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-MAX_NUMCHIPS_LD-1 downto 0); signal ram1a_a1 : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); signal ram1a_din1 : std_logic_vector(31 downto 0); @@ -229,7 +228,7 @@ signal jtag_tdo_compare_count_ram_wr : std_logic; signal idle_out_signal, idle_out_signal_next : std_logic; -signal numchips_configured, numchips_configured_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0); +signal numchips_configured : unsigned(MAX_NUMCHIPS_LD-1 downto 0); signal numchips_active, numchips_active_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0); signal numchips_active_acc, numchips_active_acc_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0); @@ -278,13 +277,9 @@ signal bus2_control_addr_out : std_logic_vector(15 downto 0); signal bus2_control_data_out : std_logic_vector(31 downto 0); signal bus2_control_read_enable_out : std_logic; signal bus2_control_write_enable_out : std_logic; -signal bus2_control_timeout_out : std_logic; - -signal bus2_control_data_in, bus2_control_data_in_next : std_logic_vector(31 downto 0); -signal bus2_control_dataready_in, bus2_control_dataready_in_next : std_logic; -signal bus2_control_write_ack_in, bus2_control_write_ack_in_next : std_logic; -signal bus2_control_no_more_data_in, bus2_control_no_more_data_in_next : std_logic; -signal bus2_control_unknown_addr_in, bus2_control_unknown_addr_in_next : std_logic; +signal bus2_control_data_in : std_logic_vector(31 downto 0); +signal bus2_control_ack_in : std_logic; +signal bus2_control_nack_in : std_logic; --signal bus2_debug_addr_out : std_logic_vector(4 downto 0); signal bus2_debug_addr_out : std_logic_vector(15 downto 0); @@ -347,13 +342,13 @@ signal jtag_bypassreg_last_tck_cycle : std_logic; signal jtag_bypassreg_tms : std_logic; signal jtag_bypassreg_tdi : std_logic; -- begin: global_jtag_counter settings -signal jtag_clock_cycle_length, jtag_clock_cycle_length_next : unsigned(9 downto 0); -- 10 bit linear adjustment of tck cycle length (10ns-10us) -signal jtag_clock_time1, jtag_clock_time1_next : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution -signal jtag_clock_time2, jtag_clock_time2_next : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution -signal jtag_sample_time1, jtag_sample_time1_next : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution -signal jtag_sample_time2, jtag_sample_time2_next : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution -signal jtag_sample_time3, jtag_sample_time3_next : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution -signal jtag_set_data_time, jtag_set_data_time_next : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution +signal jtag_clock_cycle_length : unsigned(9 downto 0); -- 10 bit linear adjustment of tck cycle length (10ns-10us) +signal jtag_clock_time1 : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution +signal jtag_clock_time2 : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution +signal jtag_sample_time1 : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution +signal jtag_sample_time2 : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution +signal jtag_sample_time3 : unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution +signal jtag_set_data_time: unsigned(9 downto 0); -- 10 bit linear adjustment within tck cycle with system clock resolution -- begin: periodic pulses, periodic with global_jtag_counter signal begin_jtag_bitcalc : std_logic; signal jtag_sample_pulse1 : std_logic; @@ -434,7 +429,7 @@ signal m26cs_state, m26cs_state_next : M26CS_STATE_TYPE; --signal write_count, write_count_next : std_logic_vector(31 downto 0); signal m26cs_stopped : std_logic; signal m26cs_firstrun, m26cs_firstrun_next : std_logic; -signal breakpoint_active, breakpoint_active_next : std_logic_vector(9 downto 0); +signal breakpoint_active : std_logic_vector(9 downto 0); -- chain_status: -- bit 0: chain broken -- bit 1: CRC_error(s) @@ -448,14 +443,14 @@ signal trigger_copy_ram3, trigger_copy_ram3_next : std_logic; signal run_counter, run_counter_next : unsigned(31 downto 0); signal jtag_status2_copy_requested, jtag_status2_copy_requested_next : std_logic; -signal jtag_status2_copy_request_strobe, jtag_status2_copy_request_strobe_next : std_logic; +signal jtag_status2_copy_request_strobe : std_logic; type CPS2_STATE_TYPE is (CPS2_IDLE, CPS2_COPY_BEGIN, CPS2_COPY_WAIT); signal cps2_state, cps2_state_next : CPS2_STATE_TYPE; signal jtag_clock_pulse1 : std_logic; signal jtag_clock_pulse2 : std_logic; signal jtag_tck : std_logic; -signal jtag_pulses_reset, jtag_pulses_reset_next : std_logic; +signal jtag_pulses_reset : std_logic; signal jtag_pulses_reset_complete : std_logic; signal jtag_chain_broken_counter, jtag_chain_broken_counter_next : unsigned(JTAG_CHAIN_BROKEN_COUNTER_BITS-1 downto 0); @@ -466,7 +461,7 @@ signal trigger_check_crc_ram1a, trigger_check_crc_ram1a_next : std_logic; signal trigger_init_ram1b, trigger_init_ram1b_next : std_logic; signal jtag_init_ram1b_idle : std_logic; -signal ram1b1c_copy_trigger_strobe, ram1b1c_copy_trigger_strobe_next : std_logic_vector(3 downto 0); +signal ram1b1c_copy_trigger_strobe : std_logic_vector(3 downto 0); signal trigger_copy_ram1b1c : std_logic; signal copy_ram1b1c_ram1b_a : std_logic_vector(RAM_JTAG_REGISTERS_DEPTH-1 downto 0); signal copy_ram1b1c_ram1b_dout : std_logic_vector(31 downto 0); @@ -528,8 +523,8 @@ signal sDATA_CHANGED_COUNT_OUT : std_logic_vector(COUNTER_WIDTHS-1 downto 0); -- INSERTLABEL: signals -signal m26csoptions, m26csoptions_next : std_logic_vector(0 downto 0); -signal jtag_delay_expvalues, jtag_delay_expvalues_next : std_logic_vector(JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD-1 downto 0); +signal m26csoptions : std_logic_vector(0 downto 0); +signal jtag_delay_expvalues : std_logic_vector(JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD-1 downto 0); signal request_reset, request_reset_next : std_logic; signal reset_wait, reset_wait_next : unsigned(7 downto 0); @@ -539,7 +534,14 @@ signal run_requested, run_requested_next : std_logic; signal write_once_requested, write_once_requested_next : std_logic; signal write_once_count, write_once_count_next : unsigned(COUNTER_WIDTHS-1 downto 0); - +signal bus_command_ack : std_logic; +signal bus_command_addr : std_logic_vector(15 downto 0); +signal bus_command_data_in : std_logic_vector(31 downto 0); +signal bus_command_data_out: std_logic_vector(31 downto 0); +signal bus_command_nack : std_logic; +signal bus_command_write : std_logic; +signal bus_command_read : std_logic; +signal bus_command_retry : std_logic; begin @@ -570,9 +572,9 @@ REQUEST_RESET_OUT <= request_reset; the_bus_handler : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 5, - PORT_ADDRESSES => (0 => x"0000", 1 => x"0100", 2 => x"0120", 3 => x"0140", 4 => x"0160", others => (others => '0')), - PORT_ADDR_MASK => (0 => 8, 1 => 5, 2 => 5, 3 => 5, 4 => 5, others => 0) + PORT_NUMBER => 6, + PORT_ADDRESSES => (0 => x"0000", 1 => x"0100", 2 => x"0120", 3 => x"0140", 4 => x"0160", 5 => x"0200", others => (others => '0')), + PORT_ADDR_MASK => (0 => 8, 1 => 5, 2 => 5, 3 => 5, 4 => 5, 5 => 8, others => 0) ) port map( CLK => CLK_IN, @@ -598,52 +600,57 @@ the_bus_handler : trb_net16_regio_bus_handler --BUS_ADDR_OUT(3*16+15 downto 3*16+5) => open, BUS_ADDR_OUT(3*16+15 downto 3*16) => bus2_debug_addr_out, BUS_ADDR_OUT(4*16+15 downto 4*16) => bus2_status2_addr_out, + BUS_ADDR_OUT(5*16+15 downto 5*16) => bus_command_addr, BUS_DATA_OUT(0*32+31 downto 0*32) => bus2_ram_data_out, BUS_DATA_OUT(1*32+31 downto 1*32) => bus2_status_data_out, BUS_DATA_OUT(2*32+31 downto 2*32) => bus2_control_data_out, BUS_DATA_OUT(3*32+31 downto 3*32) => bus2_debug_data_out, BUS_DATA_OUT(4*32+31 downto 4*32) => bus2_status2_data_out, + BUS_DATA_OUT(5*32+31 downto 5*32) => bus_command_data_out, BUS_READ_ENABLE_OUT(0) => bus2_ram_read_enable_out, BUS_READ_ENABLE_OUT(1) => bus2_status_read_enable_out, BUS_READ_ENABLE_OUT(2) => bus2_control_read_enable_out, BUS_READ_ENABLE_OUT(3) => bus2_debug_read_enable_out, BUS_READ_ENABLE_OUT(4) => bus2_status2_read_enable_out, + BUS_READ_ENABLE_OUT(5) => bus_command_read, BUS_WRITE_ENABLE_OUT(0) => bus2_ram_write_enable_out, BUS_WRITE_ENABLE_OUT(1) => bus2_status_write_enable_out, BUS_WRITE_ENABLE_OUT(2) => bus2_control_write_enable_out, BUS_WRITE_ENABLE_OUT(3) => bus2_debug_write_enable_out, BUS_WRITE_ENABLE_OUT(4) => bus2_status2_write_enable_out, - BUS_TIMEOUT_OUT(0) => open, - BUS_TIMEOUT_OUT(1) => open, - BUS_TIMEOUT_OUT(2) => bus2_control_timeout_out, - BUS_TIMEOUT_OUT(3) => open, - BUS_TIMEOUT_OUT(4) => open, + BUS_WRITE_ENABLE_OUT(5) => bus_command_write, + BUS_TIMEOUT_OUT => open, BUS_DATA_IN(0*32+31 downto 0*32) => bus2_ram_data_in, BUS_DATA_IN(1*32+31 downto 1*32) => bus2_status_data_in, BUS_DATA_IN(2*32+31 downto 2*32) => bus2_control_data_in, BUS_DATA_IN(3*32+31 downto 3*32) => bus2_debug_data_in, BUS_DATA_IN(4*32+31 downto 4*32) => bus2_status2_data_in, + BUS_DATA_IN(5*32+31 downto 5*32) => bus_command_data_in, BUS_DATAREADY_IN(0) => bus2_ram_ack_in, BUS_DATAREADY_IN(1) => bus2_status_ack_in, - BUS_DATAREADY_IN(2) => bus2_control_dataready_in, + BUS_DATAREADY_IN(2) => bus2_control_ack_in, BUS_DATAREADY_IN(3) => bus2_debug_ack_in, BUS_DATAREADY_IN(4) => bus2_status2_ack_in, + BUS_DATAREADY_IN(5) => bus_command_ack, BUS_WRITE_ACK_IN(0) => bus2_ram_ack_in, BUS_WRITE_ACK_IN(1) => bus2_status_ack_in, - BUS_WRITE_ACK_IN(2) => bus2_control_write_ack_in, + BUS_WRITE_ACK_IN(2) => bus2_control_ack_in, BUS_WRITE_ACK_IN(3) => bus2_debug_ack_in, BUS_WRITE_ACK_IN(4) => bus2_status2_ack_in, + BUS_WRITE_ACK_IN(5) => bus_command_ack, BUS_NO_MORE_DATA_IN(0) => bus2_ram_nack_in, BUS_NO_MORE_DATA_IN(1) => '0', - BUS_NO_MORE_DATA_IN(2) => bus2_control_no_more_data_in, + BUS_NO_MORE_DATA_IN(2) => bus2_control_nack_in, BUS_NO_MORE_DATA_IN(3) => '0', BUS_NO_MORE_DATA_IN(4) => '0', + BUS_NO_MORE_DATA_IN(5) => '0', BUS_UNKNOWN_ADDR_IN(0) => '0', BUS_UNKNOWN_ADDR_IN(1) => bus2_status_nack_in, - BUS_UNKNOWN_ADDR_IN(2) => bus2_control_unknown_addr_in, + BUS_UNKNOWN_ADDR_IN(2) => bus_command_nack, BUS_UNKNOWN_ADDR_IN(3) => bus2_debug_nack_in, - BUS_UNKNOWN_ADDR_IN(4) => bus2_status2_nack_in + BUS_UNKNOWN_ADDR_IN(4) => bus2_status2_nack_in, + BUS_UNKNOWN_ADDR_IN(5) => bus_command_retry ); @@ -1300,85 +1307,35 @@ SEQUENTIAL : process (CLK_IN) begin if (rising_edge(CLK_IN)) then if(RESET_IN = '1') then - data_register <= x"00000000"; - jtag_refresh_active <= '0'; - jtag_check1_active <= '0'; - jtag_refresh_active_last <= '0'; idle_out_signal <= '0'; crc_status_register <= (others => '0'); - removed_chips <= (others => '0'); - numchips_configured <= (others => '0'); chip_counter_start <= '0'; - bus2_control_data_in <= (others =>'0'); - bus2_control_dataready_in <= '0'; - bus2_control_write_ack_in <= '0'; - bus2_control_no_more_data_in <= '0'; - bus2_control_unknown_addr_in <= '0'; prog_jtag_finished <= '0'; -- NEW SIGNALS - ram1a_a1_base_addr <= (others =>'0'); jtag_status2_copy_requested <= '0'; - jtag_status2_copy_request_strobe <= '0'; cps2_state <= CPS2_IDLE; status2_run_counter <= (others =>'0'); status2_chain_status <= (others =>'0'); - jtag_clock_cycle_length <= (others =>'0'); - jtag_clock_time1 <= (others =>'0'); - jtag_clock_time2 <= (others =>'0'); - jtag_sample_time1 <= (others =>'0'); - jtag_sample_time2 <= (others =>'0'); - jtag_sample_time3 <= (others =>'0'); - jtag_set_data_time <= (others => '0'); - jtag_pulses_reset <= '0'; jtag_sample_pulse3_d1 <= '0'; - breakpoint_active <= (others => '0'); - m26csoptions <= (others => '0'); - jtag_delay_expvalues <= (others => '0'); crc_error_on_last_check <= '0'; last_run_successful <= '0'; last_run_successful_tmp <= '0'; else - data_register <= data_register_next; - jtag_refresh_active <= jtag_refresh_active_next; - jtag_check1_active <= jtag_check1_active_next; - jtag_refresh_active_last <= jtag_refresh_active_last_next; idle_out_signal <= idle_out_signal_next; crc_status_register <= crc_status_register_next; - removed_chips <= removed_chips_next; - numchips_configured <= numchips_configured_next; chip_counter_start <= chip_counter_start_next; - bus2_control_data_in <= bus2_control_data_in_next; - bus2_control_dataready_in <= bus2_control_dataready_in_next; - bus2_control_write_ack_in <= bus2_control_write_ack_in_next; - bus2_control_no_more_data_in <= bus2_control_no_more_data_in_next; - bus2_control_unknown_addr_in <= bus2_control_unknown_addr_in_next; prog_jtag_finished <= prog_jtag_finished_next; --last_write_successful <= last_write_successful_next; -- NEW SIGNALS - ram1a_a1_base_addr <= ram1a_a1_base_addr_next; jtag_status2_copy_requested <= jtag_status2_copy_requested_next; - jtag_status2_copy_request_strobe <= jtag_status2_copy_request_strobe_next; cps2_state <= cps2_state_next; status2_run_counter <= status2_run_counter_next; status2_chain_status <= status2_chain_status_next; - jtag_clock_cycle_length <= jtag_clock_cycle_length_next; - jtag_clock_time1 <= jtag_clock_time1_next; - jtag_clock_time2 <= jtag_clock_time2_next ; - jtag_sample_time1 <= jtag_sample_time1_next; - jtag_sample_time2 <= jtag_sample_time2_next; - jtag_sample_time3 <= jtag_sample_time3_next; - jtag_set_data_time <= jtag_set_data_time_next; - jtag_pulses_reset <= jtag_pulses_reset_next; jtag_sample_pulse3_d1 <= jtag_sample_pulse3_d1_next; - breakpoint_active <= breakpoint_active_next; - - ram1b1c_copy_trigger_strobe <= ram1b1c_copy_trigger_strobe_next; - m26csoptions <= m26csoptions_next; - jtag_delay_expvalues <= jtag_delay_expvalues_next; crc_error_on_last_check <= crc_error_on_last_check_next; last_run_successful <= last_run_successful_next; last_run_successful_tmp <= last_run_successful_tmp_next; @@ -1468,7 +1425,7 @@ end process; -- delay one clock cycle -jtag_refresh_active_last_next <= jtag_refresh_active; +jtag_refresh_active_last <= jtag_refresh_active when rising_edge(CLK_IN); -- monitoring @@ -2104,235 +2061,155 @@ BUS2_STATUS_R : process begin end process; ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ -BUS2_CONTROL_RW : process (bus2_control_addr_out, bus2_control_data_out, bus2_control_read_enable_out, - bus2_control_write_enable_out, bus2_control_data_in, jtag_refresh_active, - ram1a_a1_base_addr, data_register, jtag_check1_active, numchips_configured, - removed_chips, jtag_clock_cycle_length, jtag_clock_time1, jtag_clock_time2, - jtag_sample_time1, jtag_sample_time2, jtag_sample_time3, jtag_set_data_time, - breakpoint_active, run_counter, debug_trigger_counter, last_not_removed, - m26cs_stopped, numchips_active, m26csoptions, jtag_delay_expvalues -) -begin - bus2_control_data_in_next <= bus2_control_data_in; - bus2_control_dataready_in_next <= '0'; - bus2_control_write_ack_in_next <= '0'; - bus2_control_no_more_data_in_next <= '0'; - bus2_control_unknown_addr_in_next <= '0'; - jtag_refresh_active_next <= jtag_refresh_active; - ram1a_a1_base_addr_next <= ram1a_a1_base_addr; - data_register_next <= data_register; - jtag_status2_copy_request_strobe_next <= '0'; - jtag_check1_active_next <= jtag_check1_active; - numchips_configured_next <= numchips_configured; - removed_chips_next <= removed_chips; - jtag_clock_cycle_length_next <= jtag_clock_cycle_length; - jtag_clock_time1_next <= jtag_clock_time1; - jtag_clock_time2_next <= jtag_clock_time2; - jtag_sample_time1_next <= jtag_sample_time1; - jtag_sample_time2_next <= jtag_sample_time2; - jtag_sample_time3_next <= jtag_sample_time3; - jtag_set_data_time_next <= jtag_set_data_time; - jtag_pulses_reset_next <= '0'; - breakpoint_active_next <= breakpoint_active; - ram1b1c_copy_trigger_strobe_next <= (others => '0'); - m26csoptions_next <= m26csoptions; - jtag_delay_expvalues_next <= jtag_delay_expvalues; +BUS2_COMMAND_RW : process begin + wait until rising_edge(CLK_IN); + bus_command_ack <= '0'; + bus_command_nack <= '0'; + bus_command_retry <= '0'; + bus_command_data_in <= (others => '0'); + jtag_pulses_reset <= '0'; + jtag_status2_copy_request_strobe <= '0'; + ram1b1c_copy_trigger_strobe <= (others => '0'); - if(bus2_control_write_enable_out='1') then - -- CONTROL registers layout: - -- ADDR_CONTROL_CMD - -- ADDR_CONTROL_RAM_BASEADDR - -- bits i*32+31 downto i*32: bits 0: JTAG_ERROR, 1: WRITE_ERROR, 2: WRITE_ERROR2, 3: READ_ERROR, 4: READ_ERROR2, - -- 5: DATA_CHANGED, 6: reserved, 7: reserved - if(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_CMD) then - bus2_control_write_ack_in_next <= '1'; - if(bus2_control_data_out(7 downto 0) = M26C_CMD_START) then - jtag_refresh_active_next <= '1'; - elsif(bus2_control_data_out(7 downto 0) =M26C_CMD_START_CHECK1) then - jtag_check1_active_next <= '1'; - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_STOP) then - jtag_refresh_active_next <= '0'; - jtag_check1_active_next <= '0'; - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_REMOVE_SENSOR ) then - -- only signal ack if really written - bus2_control_write_ack_in_next <= '0'; - bus2_control_no_more_data_in_next <= '1'; - -- only allowed to change removed chips when not writing to JTAG interface! - if(m26cs_stopped = '1') then - if(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0)) + bus_command_data_in(0) <= jtag_refresh_active; + bus_command_data_in(1) <= jtag_check1_active; + when M26C_CMD_REMOVE_SENSOR => + bus_command_data_in(MAX_NUMCHIPS -1 downto 0) <= removed_chips; + when M26C_CMD_INSERT_SENSOR => + bus_command_data_in(MAX_NUMCHIPS -1 downto 0) <= removed_chips; + when M26C_CMD_SET_NUMCHIPS_CONFIGURED => + bus_command_data_in(MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(numchips_configured); + when M26C_CMD_GET_NUMCHIPS_ACTIVE => + bus_command_data_in(MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(numchips_active); + when M26C_CMD_GET_TRIGGER_COUNT => + bus_command_data_in <= std_logic_vector(debug_trigger_counter); + when M26C_CMD_GET_LAST_NOT_REMOVED => + bus_command_data_in(MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(last_not_removed); + when M26C_CMD_SET_BREAKPOINTS => + bus_command_data_in(9 downto 0) <= breakpoint_active; + when M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH => + bus_command_data_in(9 downto 0) <= std_logic_vector(jtag_clock_cycle_length); + when M26C_CMD_SET_JTAG_CLOCK_TIME1 => + bus_command_data_in(9 downto 0) <= std_logic_vector(jtag_clock_time1); + when M26C_CMD_SET_JTAG_CLOCK_TIME2 => + bus_command_data_in(9 downto 0) <= std_logic_vector(jtag_clock_time2); + when M26C_CMD_SET_JTAG_SAMPLE_TIME1 => + bus_command_data_in(9 downto 0) <= std_logic_vector(jtag_sample_time1); + when M26C_CMD_SET_JTAG_SAMPLE_TIME2 => + bus_command_data_in(9 downto 0) <= std_logic_vector(jtag_sample_time2); + when M26C_CMD_SET_JTAG_SAMPLE_TIME3 => + bus_command_data_in(9 downto 0) <= std_logic_vector(jtag_sample_time3); + when M26C_CMD_SET_JTAG_SET_DATA_TIME => + bus_command_data_in(9 downto 0) <= std_logic_vector(jtag_set_data_time); + when M26C_CMD_GET_RUN_COUNT => + bus_command_data_in(31 downto 0) <= std_logic_vector(run_counter); + when M26C_CMD_SET_CSOPTIONS => + bus_command_data_in(0 downto 0) <= m26csoptions(0 downto 0); -- bit 0 => skip bypassreg chaintest + when M26C_CMD_SET_DELAY_EXPECTED_VALUES => + bus_command_data_in(JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD-1 downto 0) <= jtag_delay_expvalues; + when others => + bus_command_ack <= '0'; + bus_command_nack <= '1'; + end case; + + + elsif bus_command_write = '1' then + bus_command_ack <= '1'; + case bus_command_addr(7 downto 0) is + when M26C_CMD_START => + jtag_refresh_active <= bus_command_data_out(0); + jtag_check1_active <= bus_command_data_out(1); + when M26C_CMD_REMOVE_SENSOR => + if m26cs_stopped = '1' then + if(unsigned(bus_command_data_out) + if m26cs_stopped = '1' then + if(unsigned(bus_command_data_out) '0'); --- data_register_next(15 downto 0) <= driver_speed; --- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_REACTIVATE_SENSOR) then --- if(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0)) '0'); - data_register_next(MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(numchips_configured); - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_NUMCHIPS_ACTIVE) then - data_register_next(31 downto MAX_NUMCHIPS_LD) <= (others => '0'); - data_register_next(MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(numchips_active); - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_TRIGGER_COUNT) then - data_register_next <= std_logic_vector(debug_trigger_counter); --- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_DISABLE_WRITE) then --- data_register_next(31 downto 1) <= (others => '0'); --- data_register_next(0) <= disable_write; --- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_DISABLE_WRITE) then --- disable_write_next <= data_register(0); --- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_LAST_NOT_REMOVED) then - data_register_next(31 downto MAX_NUMCHIPS_LD) <= (others => '0'); - data_register_next(MAX_NUMCHIPS_LD-1 downto 0) <= std_logic_vector(last_not_removed); - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_REMOVED) then - data_register_next(31 downto 1) <= (others => '0'); - data_register_next(0) <= removed_chips(to_integer(unsigned(data_register(MAX_NUMCHIPS_LD-1 downto 0)))); - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_REMOVED32) then - data_register_next(31 downto MYMIN(MAX_NUMCHIPS-1, 31)) <= (others => '0'); - data_register_next(MYMIN(MAX_NUMCHIPS-1, 31) downto 0) <= removed_chips(MYMIN(MAX_NUMCHIPS-1, 31) downto 0); --- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_REACTIVATE_SENSOR32) then --- data_register_next(31 downto 0) <= reactivate_sensor(31 downto 0); --- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_DEACTIVATE_SENSOR32) then --- data_register_next(31 downto 0) <= deactivate_sensor(31 downto 0); --- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_M26_DEV_ID) then --- data_register_next <= JTAG_M26_DEV_ID; - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_NUMCHIPS_CONFIGURED) then - numchips_configured_next <= unsigned(data_register(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0)); --- elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_NUMCHIPS) then --- data_register_next(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0) <= std_logic_vector(numchips_configured); --- data_register_next(31 downto MAX_NUMCHIPS_PLUS_ONE_LD) <= (others => '0'); - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_BREAKPOINTS) then - breakpoint_active_next <= data_register(9 downto 0); - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_BREAKPOINTS) then - data_register_next(9 downto 0) <= breakpoint_active; - data_register_next(31 downto 10) <= (others => '0'); - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH) then - jtag_clock_cycle_length_next <= unsigned(data_register(9 downto 0)); - jtag_pulses_reset_next <= '1'; -- reset counter (because maximum value of counter could be exceeded) - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_CLOCK_CYCLE_LENGTH) then - data_register_next(9 downto 0) <= std_logic_vector(jtag_clock_cycle_length); - data_register_next(31 downto 10) <= (others => '0'); - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_CLOCK_TIME1) then - jtag_clock_time1_next <= unsigned(data_register(9 downto 0)); - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_CLOCK_TIME1) then - data_register_next(9 downto 0) <= std_logic_vector(jtag_clock_time1); - data_register_next(31 downto 10) <= (others => '0'); - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_CLOCK_TIME2) then - jtag_clock_time2_next <= unsigned(data_register(9 downto 0)); - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_CLOCK_TIME2) then - data_register_next(9 downto 0) <= std_logic_vector(jtag_clock_time2); - data_register_next(31 downto 10) <= (others => '0'); - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_SAMPLE_TIME1) then - jtag_sample_time1_next <= unsigned(data_register(9 downto 0)); - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_SAMPLE_TIME1) then - data_register_next(9 downto 0) <= std_logic_vector(jtag_sample_time1); - data_register_next(31 downto 10) <= (others => '0'); - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_SAMPLE_TIME2) then - jtag_sample_time2_next <= unsigned(data_register(9 downto 0)); - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_SAMPLE_TIME2) then - data_register_next(9 downto 0) <= std_logic_vector(jtag_sample_time2); - data_register_next(31 downto 10) <= (others => '0'); - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_SAMPLE_TIME3) then - jtag_sample_time3_next <= unsigned(data_register(9 downto 0)); - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_SAMPLE_TIME3) then - data_register_next(9 downto 0) <= std_logic_vector(jtag_sample_time3); - data_register_next(31 downto 10) <= (others => '0'); - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_JTAG_SET_DATA_TIME) then - jtag_set_data_time_next <= unsigned(data_register(9 downto 0)); - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_JTAG_SET_DATA_TIME) then - data_register_next(9 downto 0) <= std_logic_vector(jtag_set_data_time); - data_register_next(31 downto 10) <= (others => '0'); - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_RUN_COUNT) then - data_register_next(31 downto 0) <= std_logic_vector(run_counter); - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_COPY_TO_STATUS2) then - jtag_status2_copy_request_strobe_next <= '1'; - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER) then - ram1b1c_copy_trigger_strobe_next(3 downto 0) <= data_register(3 downto 0); -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_READ_ERROR) then - ram1b1c_copy_trigger_strobe_next(0) <= '1'; -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_WRITE_ERROR) then - ram1b1c_copy_trigger_strobe_next(1) <= '1'; -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_DATA_CHANGED) then - ram1b1c_copy_trigger_strobe_next(2) <= '1'; -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_NOW) then - ram1b1c_copy_trigger_strobe_next(3) <= '1'; -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_CSOPTIONS) then - m26csoptions_next(0 downto 0) <= data_register(0 downto 0); -- bit 0 => skip bypassreg chaintest - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_CSOPTIONS) then - data_register_next(0 downto 0) <= m26csoptions(0 downto 0); -- bit 0 => skip bypassreg chaintest - data_register_next(31 downto 0+1) <= (others => '0'); - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_SET_DELAY_EXPECTED_VALUES) then - jtag_delay_expvalues_next(JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD-1 downto 0) <= data_register(JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD-1 downto 0); - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_DELAY_EXPECTED_VALUES) then - data_register_next(JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD-1 downto 0) <= jtag_delay_expvalues(JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD-1 downto 0); - data_register_next(31 downto JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD) <= (others => '0'); - elsif(bus2_control_data_out(7 downto 0) = M26C_CMD_GET_ACTIVITY) then - data_register_next(0) <= jtag_refresh_active; - data_register_next(1) <= jtag_check1_active; - data_register_next(31 downto 2) <= (others => '0'); - else - -- revoke write_ack, which was set preliminary before "if" - bus2_control_write_ack_in_next <= '0'; - bus2_control_unknown_addr_in_next <= '1'; - end if; - elsif(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_RAM_BASEADDR) then - ram1a_a1_base_addr_next <= bus2_control_data_out(MAX_NUMCHIPS_LD-1 downto 0); - bus2_control_write_ack_in_next <= '1'; - elsif(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_DATA_REGISTER) then - data_register_next <= bus2_control_data_out; - bus2_control_write_ack_in_next <= '1'; + when M26C_CMD_SET_NUMCHIPS_CONFIGURED => + numchips_configured <= unsigned(bus_command_data_out(MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0)); + when M26C_CMD_SET_BREAKPOINTS => + breakpoint_active <= bus_command_data_out(9 downto 0); + when M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH => + jtag_clock_cycle_length <= unsigned(bus_command_data_out(9 downto 0)); + jtag_pulses_reset <= '1'; -- reset counter (because maximum value of counter could be exceeded) + when M26C_CMD_SET_JTAG_CLOCK_TIME1 => + jtag_clock_time1 <= unsigned(bus_command_data_out(9 downto 0)); + when M26C_CMD_SET_JTAG_CLOCK_TIME2 => + jtag_clock_time2 <= unsigned(bus_command_data_out(9 downto 0)); + when M26C_CMD_SET_JTAG_SAMPLE_TIME1 => + jtag_sample_time1 <= unsigned(bus_command_data_out(9 downto 0)); + when M26C_CMD_SET_JTAG_SAMPLE_TIME2 => + jtag_sample_time2 <= unsigned(bus_command_data_out(9 downto 0)); + when M26C_CMD_SET_JTAG_SAMPLE_TIME3 => + jtag_sample_time3 <= unsigned(bus_command_data_out(9 downto 0)); + when M26C_CMD_SET_JTAG_SET_DATA_TIME => + jtag_set_data_time <= unsigned(bus_command_data_out(9 downto 0)); + when M26C_CMD_COPY_TO_STATUS2 => + jtag_status2_copy_request_strobe <= '1'; + when M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER => + ram1b1c_copy_trigger_strobe(3 downto 0) <= bus_command_data_out(3 downto 0); + -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed, 3=>next run + when M26C_CMD_SET_CSOPTIONS => + m26csoptions(0 downto 0) <= bus_command_data_out(0 downto 0); -- bit 0 => skip bypassreg chaintest + when M26C_CMD_SET_DELAY_EXPECTED_VALUES => + jtag_delay_expvalues <= bus_command_data_out(JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD-1 downto 0); + when others => + bus_command_ack <= '0'; + bus_command_nack <= '1'; + end case; + end if; + if RESET_IN = '1' then + jtag_refresh_active <= '0'; + jtag_check1_active <= '0'; + breakpoint_active <= (others => '0'); + numchips_configured <= (others => '0'); + m26csoptions <= (others => '0'); + end if; +end process; + + + +BUS2_CONTROL_RW : process begin + wait until rising_edge(CLK_IN); + bus2_control_ack_in <= '0'; + bus2_control_nack_in <= '0'; + bus2_control_data_in <= (others => '0'); + + if(bus2_control_write_enable_out='1') then + if(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_RAM_BASEADDR) then + ram1a_a1_base_addr <= bus2_control_data_out(MAX_NUMCHIPS_LD-1 downto 0); + bus2_control_ack_in <= '1'; else - bus2_control_unknown_addr_in_next <= '1'; + bus2_control_nack_in <= '1'; end if; elsif(bus2_control_read_enable_out='1') then - if(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_CMD) then - bus2_control_data_in_next <= (others => '0'); - bus2_control_dataready_in_next <= '1'; - elsif(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_RAM_BASEADDR) then - bus2_control_data_in_next(31 downto RAM_JTAG_REGISTERS_DEPTH-8) <= (others => '0'); - bus2_control_data_in_next(MAX_NUMCHIPS_LD-1 downto 0) <= ram1a_a1_base_addr; - bus2_control_dataready_in_next <= '1'; - elsif(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_DATA_REGISTER) then - bus2_control_data_in_next <= data_register; - bus2_control_dataready_in_next <= '1'; + if(bus2_control_addr_out(4 downto 0) = ADDR_CONTROL_RAM_BASEADDR) then + bus2_control_data_in(MAX_NUMCHIPS_LD-1 downto 0) <= ram1a_a1_base_addr; + bus2_control_ack_in <= '1'; else - bus2_control_unknown_addr_in_next <= '1'; + bus2_control_nack_in <= '1'; end if; end if; end process; ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ - - BUS2_DEBUG_R : process begin wait until rising_edge(CLK_IN); bus2_debug_ack_in <= '0'; diff --git a/vhdl/code/jtag_constants.vhd b/vhdl/code/jtag_constants.vhd index 6dff623..96a8664 100644 --- a/vhdl/code/jtag_constants.vhd +++ b/vhdl/code/jtag_constants.vhd @@ -13,68 +13,53 @@ constant CMD_UPDATE_IR : std_logic_vector (3 downto 0) := x"5"; constant CMD_UPDATE_DR : std_logic_vector (3 downto 0) := x"6"; constant CMD_RESET_JTAG : std_logic_vector (3 downto 0) := x"7"; constant CMD_READ_TDO : std_logic_vector (3 downto 0) := x"8"; -constant M26C_CMD_NONE : std_logic_vector (7 downto 0) := x"00"; +-- constant M26C_CMD_NONE : std_logic_vector (7 downto 0) := x"00"; constant M26C_CMD_START : std_logic_vector (7 downto 0) := x"09"; -constant M26C_CMD_STOP : std_logic_vector (7 downto 0) := x"0A"; +-- constant M26C_CMD_STOP : std_logic_vector (7 downto 0) := x"0A"; constant M26C_CMD_REMOVE_SENSOR : std_logic_vector (7 downto 0) := x"10"; constant M26C_CMD_INSERT_SENSOR : std_logic_vector (7 downto 0) := x"11"; ---constant M26C_CMD_REACTIVATE_SENSOR : std_logic_vector (7 downto 0) := x"10"; ---constant M26C_CMD_DEACTIVATE_SENSOR : std_logic_vector (7 downto 0) := x"11"; -constant M26C_CMD_GET_NUMCHIPS_CONFIGURED:std_logic_vector (7 downto 0) := x"12"; +-- constant M26C_CMD_GET_NUMCHIPS_CONFIGURED:std_logic_vector (7 downto 0) := x"12"; constant M26C_CMD_GET_NUMCHIPS_ACTIVE : std_logic_vector (7 downto 0) := x"13"; constant M26C_CMD_GET_TRIGGER_COUNT : std_logic_vector (7 downto 0) := x"14"; ---constant M26C_CMD_GET_DISABLE_WRITE : std_logic_vector (7 downto 0) := x"15"; ---constant M26C_CMD_SET_DISABLE_WRITE : std_logic_vector (7 downto 0) := x"16"; ---constant M26C_CMD_GET_DISABLE_WRITEERROR_FOR_REMOVE : std_logic_vector (7 downto 0) := x"17"; ---constant M26C_CMD_SET_DISABLE_WRITEERROR_FOR_REMOVE : std_logic_vector (7 downto 0) := x"18"; ---constant M26C_CMD_GET_DISABLE_REMOVE : std_logic_vector (7 downto 0) := x"19"; ---constant M26C_CMD_SET_DISABLE_REMOVE : std_logic_vector (7 downto 0) := x"1a"; ---constant M26C_CMD_DEBUG_ONE_REMOVE : std_logic_vector (7 downto 0) := x"1b"; --- constant M26C_CMD_GET_LAST_NOT_REMOVED : std_logic_vector (7 downto 0) := x"1c"; ---constant M26C_CMD_GET_REACTIVATE_SENSOR32 : std_logic_vector (7 downto 0) := x"1d"; ---constant M26C_CMD_GET_DEACTIVATE_SENSOR32 : std_logic_vector (7 downto 0) := x"1e"; -constant M26C_CMD_GET_REMOVED : std_logic_vector (7 downto 0) := x"1d"; -constant M26C_CMD_GET_REMOVED32 : std_logic_vector (7 downto 0) := x"1e"; -constant M26C_CMD_GET_WRITE_ERROR_COUNTER :std_logic_vector (7 downto 0) := x"20"; -constant M26C_CMD_GET_WRITE_ERROR_OVER_THRESHOLD_COUNTER :std_logic_vector (7 downto 0) := x"21"; -constant M26C_CMD_GET_WRITE_DATA_CHANGED_COUNTER :std_logic_vector (7 downto 0) := x"22"; -constant M26C_CMD_GET_READ_ERROR_COUNTER :std_logic_vector (7 downto 0) := x"23"; -constant M26C_CMD_GET_READ_ERROR_OVER_THRESHOLD_COUNTER :std_logic_vector (7 downto 0) := x"24"; -constant M26C_CMD_GET_JTAG_M26_DEV_ID :std_logic_vector (7 downto 0) := x"30"; ---constant M26C_CMD_GET_NUMCHIPS : std_logic_vector (7 downto 0) := x"32"; +constant M26C_CMD_GET_LAST_NOT_REMOVED : std_logic_vector (7 downto 0) := x"1c"; +-- constant M26C_CMD_GET_REMOVED : std_logic_vector (7 downto 0) := x"1d"; +-- constant M26C_CMD_GET_REMOVED32 : std_logic_vector (7 downto 0) := x"1e"; +-- constant M26C_CMD_GET_WRITE_ERROR_COUNTER :std_logic_vector (7 downto 0) := x"20"; +-- constant M26C_CMD_GET_WRITE_ERROR_OVER_THRESHOLD_COUNTER :std_logic_vector (7 downto 0) := x"21"; +-- constant M26C_CMD_GET_WRITE_DATA_CHANGED_COUNTER :std_logic_vector (7 downto 0) := x"22"; +-- constant M26C_CMD_GET_READ_ERROR_COUNTER :std_logic_vector (7 downto 0) := x"23"; +-- constant M26C_CMD_GET_READ_ERROR_OVER_THRESHOLD_COUNTER :std_logic_vector (7 downto 0) := x"24"; +-- constant M26C_CMD_GET_JTAG_M26_DEV_ID :std_logic_vector (7 downto 0) := x"30"; constant M26C_CMD_SET_NUMCHIPS_CONFIGURED : std_logic_vector (7 downto 0) := x"33"; constant M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH : std_logic_vector (7 downto 0) := x"40"; -constant M26C_CMD_GET_JTAG_CLOCK_CYCLE_LENGTH : std_logic_vector (7 downto 0) := x"41"; +-- constant M26C_CMD_GET_JTAG_CLOCK_CYCLE_LENGTH : std_logic_vector (7 downto 0) := x"41"; constant M26C_CMD_SET_JTAG_CLOCK_TIME1 : std_logic_vector (7 downto 0) := x"42"; -constant M26C_CMD_GET_JTAG_CLOCK_TIME1 : std_logic_vector (7 downto 0) := x"43"; +-- constant M26C_CMD_GET_JTAG_CLOCK_TIME1 : std_logic_vector (7 downto 0) := x"43"; constant M26C_CMD_SET_JTAG_CLOCK_TIME2 : std_logic_vector (7 downto 0) := x"44"; -constant M26C_CMD_GET_JTAG_CLOCK_TIME2 : std_logic_vector (7 downto 0) := x"45"; +-- constant M26C_CMD_GET_JTAG_CLOCK_TIME2 : std_logic_vector (7 downto 0) := x"45"; constant M26C_CMD_SET_JTAG_SAMPLE_TIME1 : std_logic_vector (7 downto 0) := x"46"; -constant M26C_CMD_GET_JTAG_SAMPLE_TIME1 : std_logic_vector (7 downto 0) := x"47"; +-- constant M26C_CMD_GET_JTAG_SAMPLE_TIME1 : std_logic_vector (7 downto 0) := x"47"; constant M26C_CMD_SET_JTAG_SAMPLE_TIME2 : std_logic_vector (7 downto 0) := x"48"; -constant M26C_CMD_GET_JTAG_SAMPLE_TIME2 : std_logic_vector (7 downto 0) := x"49"; +-- constant M26C_CMD_GET_JTAG_SAMPLE_TIME2 : std_logic_vector (7 downto 0) := x"49"; constant M26C_CMD_SET_JTAG_SAMPLE_TIME3 : std_logic_vector (7 downto 0) := x"4a"; -constant M26C_CMD_GET_JTAG_SAMPLE_TIME3 : std_logic_vector (7 downto 0) := x"4b"; +-- constant M26C_CMD_GET_JTAG_SAMPLE_TIME3 : std_logic_vector (7 downto 0) := x"4b"; constant M26C_CMD_SET_JTAG_SET_DATA_TIME : std_logic_vector (7 downto 0) := x"4c"; -constant M26C_CMD_GET_JTAG_SET_DATA_TIME : std_logic_vector (7 downto 0) := x"4d"; +-- constant M26C_CMD_GET_JTAG_SET_DATA_TIME : std_logic_vector (7 downto 0) := x"4d"; constant M26C_CMD_GET_RUN_COUNT : std_logic_vector(7 downto 0) := x"50"; -constant M26C_CMD_GET_BREAKPOINTS : std_logic_vector(7 downto 0) := x"52"; +-- constant M26C_CMD_GET_BREAKPOINTS : std_logic_vector(7 downto 0) := x"52"; constant M26C_CMD_SET_BREAKPOINTS : std_logic_vector(7 downto 0) := x"53"; -constant M26C_CMD_START_CHECK1 : std_logic_vector (7 downto 0) := x"60"; +-- constant M26C_CMD_START_CHECK1 : std_logic_vector (7 downto 0) := x"60"; constant M26C_CMD_COPY_TO_STATUS2 : std_logic_vector (7 downto 0) := x"63"; constant M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER : std_logic_vector (7 downto 0) := x"64"; -- trigger on: bit 0 => read error, 1 => write error, 2 => data changed -constant M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_READ_ERROR : std_logic_vector (7 downto 0) := x"6a"; -- -constant M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_WRITE_ERROR : std_logic_vector (7 downto 0) := x"6b"; -- -constant M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_DATA_CHANGED : std_logic_vector (7 downto 0) := x"6c"; -- -constant M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_NOW : std_logic_vector (7 downto 0) := x"6d"; -- +-- constant M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_READ_ERROR : std_logic_vector (7 downto 0) := x"6a"; -- +-- constant M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_WRITE_ERROR : std_logic_vector (7 downto 0) := x"6b"; -- +-- constant M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_DATA_CHANGED : std_logic_vector (7 downto 0) := x"6c"; -- +-- constant M26C_CMD_COPY_RAM1B1C_SINGLE_TRIGGER_NOW : std_logic_vector (7 downto 0) := x"6d"; -- constant M26C_CMD_SET_CSOPTIONS : std_logic_vector (7 downto 0) := x"65"; -- bit 0 => skip BYPASS CHAINTEST -constant M26C_CMD_GET_CSOPTIONS : std_logic_vector (7 downto 0) := x"66"; -- bit 0 => skip BYPASS CHAINTEST +-- constant M26C_CMD_GET_CSOPTIONS : std_logic_vector (7 downto 0) := x"66"; -- bit 0 => skip BYPASS CHAINTEST constant M26C_CMD_SET_DELAY_EXPECTED_VALUES : std_logic_vector (7 downto 0) := x"67"; -- bits 1 downto 0 as unsigned number of TCK clocks expected values are delayed -constant M26C_CMD_GET_DELAY_EXPECTED_VALUES : std_logic_vector (7 downto 0) := x"68"; -constant M26C_CMD_GET_ACTIVITY : std_logic_vector (7 downto 0) := x"69"; -- bit 0 => jtag_refresh_active, bit 1 => jtag_check1_active. ---constant M26C_CMD_REG_GET_STATUS : std_logic_vector (3 downto 0) := x"B"; ---constant M26C_CMD_CRC_GET_STATUS : std_logic_vector (3 downto 0) := x"C"; ---constant M26C_CMD_SET_RAM_BASE_ADDR : std_logic_vector (3 downto 0) := x"D"; +-- constant M26C_CMD_GET_DELAY_EXPECTED_VALUES : std_logic_vector (7 downto 0) := x"68"; +-- constant M26C_CMD_GET_ACTIVITY : std_logic_vector (7 downto 0) := x"69"; -- bit 0 => jtag_refresh_active, bit 1 => jtag_check1_active. -- 0xb100 - 0xb2ff -- RAM: 0xb000 - 0xb0ff @@ -87,9 +72,9 @@ constant ADDR_CONTROL : std_logic_vector (15 downto 0) := x"b120"; constant ADDR_DEBUG : std_logic_vector (15 downto 0) := x"b140"; constant ADDR_STATUS2 : std_logic_vector (15 downto 0) := x"b160"; -constant ADDR_CONTROL_CMD : std_logic_vector (4 downto 0) := "00000"; +-- constant ADDR_CONTROL_CMD : std_logic_vector (4 downto 0) := "00000"; constant ADDR_CONTROL_RAM_BASEADDR : std_logic_vector (4 downto 0) := "00001"; -constant ADDR_CONTROL_DATA_REGISTER : std_logic_vector (4 downto 0) := "00010"; +-- constant ADDR_CONTROL_DATA_REGISTER : std_logic_vector (4 downto 0) := "00010"; constant ADDR_DEBUG_TEST : std_logic_vector(4 downto 0) := "00000"; constant ADDR_DEBUG_M26CS_STATE : std_logic_vector(4 downto 0) := "00001"; -- 2.43.0