From a1c9eef459317130aabbc9d64902550512a98323 Mon Sep 17 00:00:00 2001 From: hadaq Date: Thu, 24 Aug 2006 16:20:00 +0000 Subject: [PATCH] moved testbenches in special dir, Ingo --- testbench/trb_net_fifo_testbench.vhd | 133 ++++++++++++++++++++++ testbench/trb_net_ibuf_testbench.vhd | 161 +++++++++++++++++++++++++++ trb_net_std.vhd | 15 +++ 3 files changed, 309 insertions(+) create mode 100644 testbench/trb_net_fifo_testbench.vhd create mode 100644 testbench/trb_net_ibuf_testbench.vhd diff --git a/testbench/trb_net_fifo_testbench.vhd b/testbench/trb_net_fifo_testbench.vhd new file mode 100644 index 0000000..d92caec --- /dev/null +++ b/testbench/trb_net_fifo_testbench.vhd @@ -0,0 +1,133 @@ +-- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetFifo + +library ieee; + +use ieee.std_logic_1164.all; + +USE ieee.std_logic_signed.ALL; + +USE ieee.std_logic_arith.ALL; + +USE std.textio.ALL; +USE ieee.std_logic_textio.ALL; + +entity trb_net_fifo_testbench is + +end trb_net_fifo_testbench; + +architecture trb_net_fifo_testbench_arch of trb_net_fifo_testbench is + + signal clk : std_logic := '0'; + signal reset : std_logic := '1'; + signal mydata_input: std_logic_vector(3 downto 0) := x"0"; + signal mywrite : std_logic := '1'; + signal myread : std_logic := '0'; + signal mydata_output: std_logic_vector(3 downto 0) := x"0"; + signal myfull: std_logic := '0'; + signal myempty: std_logic := '0'; + signal mydepth: std_logic_vector(7 downto 0) := x"00"; + + component trb_net_fifo + + generic (WIDTH : integer := 8; -- FIFO word width + DEPTH : integer := 4); -- Depth of the FIFO, 2^(n+1) + + port (CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data + WRITE_ENABLE_IN : in std_logic; + DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Output data + READ_ENABLE_IN : in std_logic; + FULL_OUT : out std_logic; -- Full Flag + EMPTY_OUT : out std_logic; + DEPTH_OUT : out std_logic_vector(7 downto 0) + ); + end component; + +begin + + FIFO : trb_net_fifo + generic map ( + WIDTH => 4, + DEPTH => 3) + port map ( + CLK => clk, + RESET => reset, + CLK_EN => '1', + DATA_IN => mydata_input, + WRITE_ENABLE_IN => mywrite, + READ_ENABLE_IN => myread, + DATA_OUT => mydata_output, + FULL_OUT => myfull, + EMPTY_OUT => myempty, + DEPTH_OUT => mydepth); + + clk <= not clk after 10ns; + + DO_RESET : process + begin + reset <= '1'; + wait for 30ns; + reset <= '0'; + wait; + end process DO_RESET; + + STIMULI: process (clk) + file protokoll : text open read_mode is "in_fifo.txt"; + variable myoutline : line; + variable leer : character; + variable var1, var2 : std_logic; + variable varx : std_logic_vector(3 downto 0); + begin + if falling_edge(CLK) then + if (not endfile(protokoll)) then + readline(protokoll,myoutline); + read(myoutline,var1); + mywrite <= var1; + read(myoutline,leer); + read(myoutline,var2); + myread <= var2; + read(myoutline,leer); + read(myoutline,varx); + mydata_input <= varx; + end if; + end if; + end process STIMULI; + + + RESPONSE: process (clk) + file protokoll : text open write_mode is "out_fifo.txt"; + variable myoutline : line; + + begin -- process RESPONSE + if rising_edge(CLK) then -- rising clock edge + + hwrite (myoutline, mydepth); + writeline(protokoll, myoutline); + end if; + end process RESPONSE; + + +end trb_net_fifo_testbench_arch; + + +-- fuse -prj trb_net_fifo_testbench_beh.prj -top trb_net_fifo_testbench -o trb_net_fifo_testbench + +-- vhdl work "/home/hadaq/acromag/design/DX2002test/trbnet/trb_net_std.vhd" +-- vhdl work "/home/hadaq/acromag/design/DX2002test/trbnet/trb_net_fifo.vhd" +-- vhdl work "/home/hadaq/acromag/design/DX2002test/trbnet/xilinx/arch_trb_net_fifo.vhd" +-- vhdl work "/home/hadaq/acromag/design/DX2002test/trbnet/xilinx/generic_fifo.vhd" +-- vhdl work "/home/hadaq/acromag/design/DX2002test/trbnet/xilinx/generic_shift.vhd" +-- vhdl work "/home/hadaq/acromag/design/DX2002test/trbnet/trb_net_fifo_testbench.vhd" + +-- trb_net_fifo_testbench -tclbatch testsim.tcl + +-- ntrace select -o on -m / -l this +-- ntrace start +-- run 1000 ns +-- quit + +-- isimwave isimwavedata.xwv + diff --git a/testbench/trb_net_ibuf_testbench.vhd b/testbench/trb_net_ibuf_testbench.vhd new file mode 100644 index 0000000..fb65f25 --- /dev/null +++ b/testbench/trb_net_ibuf_testbench.vhd @@ -0,0 +1,161 @@ +library ieee; + +use ieee.std_logic_1164.all; + +USE ieee.std_logic_signed.ALL; + +USE ieee.std_logic_arith.ALL; + +USE std.textio.ALL; +USE ieee.std_logic_textio.ALL; + +entity trb_net_ibuf_testbench is + +end trb_net_ibuf_testbench; + +architecture trb_net_ibuf_testbench_arch of trb_net_ibuf_testbench is + + signal clk : std_logic := '0'; + signal reset : std_logic := '1'; + + signal med_dataready_in: std_logic := '0'; + signal med_data_in : std_logic_vector(50 downto 0) := (others => '0'); + signal med_read_out : std_logic := '0'; + + signal int_header_in : std_logic := '0'; + signal int_dataready_out: std_logic := '0'; + signal int_data_out : std_logic_vector(50 downto 0) := (others => '0'); + signal int_read_in : std_logic := '0'; + + signal read_type : std_logic_vector(2 downto 0) := (others => '0'); + signal read_f2 : std_logic_vector(3 downto 0) := (others => '0'); + signal stat_buffer : std_logic_vector(31 downto 0) := (others => '0'); + + + component trb_net_ibuf + + generic (DEPTH : integer := 3); -- Depth of the FIFO, 2^(n+1) + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media (the IOBUF MUST read) + MED_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word + MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media + MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits + -- Internal direction port + INT_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last header + INT_DATAREADY_OUT: out STD_LOGIC; + INT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_READ_IN: in STD_LOGIC; + INT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits + -- Status and control port + STAT_LOCKED: out STD_LOGIC_VECTOR (15 downto 0); + CTRL_LOCKED: in STD_LOGIC_VECTOR (15 downto 0); + STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0) + ); + end component; + +begin + + IBUF : trb_net_ibuf + port map ( + CLK => clk, + RESET => reset, + CLK_EN => '1', + + MED_DATAREADY_IN => med_dataready_in, + MED_DATA_IN => med_data_in, + MED_READ_OUT => med_read_out, + MED_ERROR_IN => (others => '0'), + INT_HEADER_IN => int_header_in, + INT_DATAREADY_OUT =>int_dataready_out, + INT_DATA_OUT => int_data_out, + INT_READ_IN => int_read_in, + CTRL_LOCKED => (others => '0'), + STAT_BUFFER => stat_buffer + ); + + clk <= not clk after 10ns; + --med_data_in <= (50 downto 48 => read_type, 35 downto 32 => read_f1, others => '0'); + --med_data_in <= (others => '0'); + med_data_in(50 downto 48) <= read_type; + med_data_in(19 downto 16) <= read_f2; + + + + + DO_RESET : process + begin + reset <= '1'; + wait for 30ns; + reset <= '0'; + wait; + end process DO_RESET; + + STIMULI: process (clk) + file protokoll : text open read_mode is "in_ibuf.txt"; + variable myoutline : line; + variable leer : character; + variable var1, var2 : std_logic; + variable varx1 : std_logic_vector(2 downto 0); + variable varx2 : std_logic_vector(3 downto 0); + begin + if falling_edge(CLK) then + if (not endfile(protokoll)) then + readline(protokoll,myoutline); + + read(myoutline,var1); + med_dataready_in <= var1; + read(myoutline,leer); + + read(myoutline,varx1); + read_type <= varx1; + read(myoutline,leer); + + read(myoutline,varx2); + read_f2 <= varx2; +-- read(myoutline,leer); + + end if; + end if; + end process STIMULI; + + +-- RESPONSE: process (clk) +-- file protokoll : text open write_mode is "out_ibuf.txt"; +-- variable myoutline : line; + +-- begin -- process RESPONSE +-- if rising_edge(CLK) then -- rising clock edge + +-- hwrite (myoutline, mydepth); +-- writeline(protokoll, myoutline); +-- end if; +-- end process RESPONSE; + + +end trb_net_ibuf_testbench_arch; + + +-- fuse -prj trb_net_fifo_testbench_beh.prj -top trb_net_fifo_testbench -o trb_net_fifo_testbench + +-- vhdl work "/home/hadaq/acromag/design/DX2002test/trbnet/trb_net_std.vhd" +-- vhdl work "/home/hadaq/acromag/design/DX2002test/trbnet/trb_net_fifo.vhd" +-- vhdl work "/home/hadaq/acromag/design/DX2002test/trbnet/xilinx/arch_trb_net_fifo.vhd" +-- vhdl work "/home/hadaq/acromag/design/DX2002test/trbnet/xilinx/generic_fifo.vhd" +-- vhdl work "/home/hadaq/acromag/design/DX2002test/trbnet/xilinx/generic_shift.vhd" +-- vhdl work "/home/hadaq/acromag/design/DX2002test/trbnet/trb_net_fifo_testbench.vhd" + +-- trb_net_fifo_testbench -tclbatch testsim.tcl + +-- ntrace select -o on -m / -l this +-- ntrace start +-- run 1000 ns +-- quit + +-- isimwave isimwavedata.xwv + diff --git a/trb_net_std.vhd b/trb_net_std.vhd index 22b565b..1679b57 100644 --- a/trb_net_std.vhd +++ b/trb_net_std.vhd @@ -12,6 +12,21 @@ package trb_net_std is return std_logic; function all_zero (arg : std_logic_vector) return std_logic; + + subtype TYPE_POSITION is integer range 50 downto 48; + constant TYPE_HDR : std_logic_vector(2 downto 0) := "001"; + constant TYPE_TRM : std_logic_vector(2 downto 0) := "010"; + constant TYPE_EOB : std_logic_vector(2 downto 0) := "011"; + constant TYPE_DAT : std_logic_vector(2 downto 0) := "100"; + constant TYPE_ACK : std_logic_vector(2 downto 0) := "101"; + + subtype F1_POSITION is integer range 47 downto 32; + subtype F2_POSITION is integer range 31 downto 16; + subtype F3_POSITION is integer range 15 downto 0; + + constant F1_CHECK_ACK : std_logic_vector(15 downto 0) := x"0000"; + subtype BUFFER_SIZE_POSITION is integer range 19 downto 16; + end package trb_net_std; -- 2.43.0