From a23681ecc280bde9bd551af3a5b4d9f436c9367b Mon Sep 17 00:00:00 2001
From: Jan Michel <j.michel@gsi.de>
Date: Wed, 10 Jun 2020 10:43:07 +0200
Subject: [PATCH] fix automatic test signal generation

---
 code/fee_signals.vhd | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/code/fee_signals.vhd b/code/fee_signals.vhd
index d62bfa6..14e2f29 100644
--- a/code/fee_signals.vhd
+++ b/code/fee_signals.vhd
@@ -130,9 +130,8 @@ PROC_TESTSIG : process begin
   wait until rising_edge(CLK);
   if start = '1' then
     timer <= unsigned(timer_reg);
-    TEST_SIG_OUT <= not invert_reg;
-  end if;
-  if timer > 0 then
+    TEST_SIG_OUT <= (invert_reg xor select_reg);
+  elsif timer > 0 then
     timer <= timer - 1 ;
   else
     TEST_SIG_OUT <= invert_reg;
-- 
2.43.0