From a2ec1c670d9f564e09007d6644e890a31f9bb15b Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Mon, 5 Mar 2012 17:57:56 +0000 Subject: [PATCH] *** empty log message *** --- cts.tex | 1 + slowcontrol.tex | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/cts.tex b/cts.tex index 60acccb..f5da192 100644 --- a/cts.tex +++ b/cts.tex @@ -8,6 +8,7 @@ Register addresses from 0xA000 to 0xA0ef is SCM FPGA (1) \\ Register addresses from 0xA0f0 to 0xA0ff is ECP2M FPGA (2) \\ + Register addresses from 0xA100 to 0xA100 + 26*500 (500 is number of samples per beam structure), the histograms are created in the SCM FPGA (1) see fig. \ref{ctsbeam}. First 8 is START next 8 is also START but perpendicular stripes. Next 8 is Veto and for the last two the source is selected by 0xA0C2 register. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% diff --git a/slowcontrol.tex b/slowcontrol.tex index 88b956d..95fb3d6 100755 --- a/slowcontrol.tex +++ b/slowcontrol.tex @@ -488,7 +488,8 @@ A detailed bit definition can be found in table~\ref{CommonCtrlReg2}. 29 & invert timing trigger \\ 28 & Single Event Upset Detection enable \\ 27 & Enable error correction in media interface \\ -26 -- 24 & reserved \\ +26 & Enable automatic reboot at network reset \\ +25 -- 24 & reserved \\ 23 -- 20 & data format \\ 19 -- 16 & reserved \\ 15 -- 0 & enable frontends \\ -- 2.43.0