From a32131bf953083ac49eda9a5489f21a9169cd7a8 Mon Sep 17 00:00:00 2001 From: Peter Lemmens Date: Wed, 20 Aug 2014 08:36:25 +0200 Subject: [PATCH] Disabled unused ports on trb_hub. All SYSCLK now to rx_half_clk, except SPI_RELOAD !! Minor clock rename in media_interface --- code/med_ecp3_sfp_4_sync_down.vhd | 2 +- code/med_ecp3_sfp_sync_up.vhd | 42 ++-- code/trb3_periph_sodahub.vhd | 19 +- soda_hub.ldf | 358 ++++++++++++++++++++++++++++++ 4 files changed, 390 insertions(+), 31 deletions(-) create mode 100644 soda_hub.ldf diff --git a/code/med_ecp3_sfp_4_sync_down.vhd b/code/med_ecp3_sfp_4_sync_down.vhd index d7fbf0a..33e1489 100644 --- a/code/med_ecp3_sfp_4_sync_down.vhd +++ b/code/med_ecp3_sfp_4_sync_down.vhd @@ -471,7 +471,7 @@ generated_logic : for i in 0 to 3 generate ------------------------------------------------- THE_RX_CONTROL : rx_control port map( - CLK_200 => rx_full_clk(i), --clk_200_i(i), --PL! + CLK_200 => clk_200_txdata, --clk_200_i(i), --PL! CLK_100 => SYSCLK, RESET_IN => rst(i), --CLEAR, PL! diff --git a/code/med_ecp3_sfp_sync_up.vhd b/code/med_ecp3_sfp_sync_up.vhd index 353c15f..99cce96 100644 --- a/code/med_ecp3_sfp_sync_up.vhd +++ b/code/med_ecp3_sfp_sync_up.vhd @@ -98,10 +98,10 @@ end component; --signal clk_200_i : std_logic; --signal clk_200_internal : std_logic; signal clk_200_osc : std_logic; -signal rx_full_clk_ch3 : std_logic; -signal rx_half_clk_ch3 : std_logic; -signal tx_full_clk_ch3 : std_logic; -signal tx_half_clk_ch3 : std_logic; +signal rx_full_clk : std_logic; +signal rx_half_clk : std_logic; +signal tx_full_clk : std_logic; +signal tx_half_clk : std_logic; signal tx_data : std_logic_vector(7 downto 0); signal tx_k : std_logic; @@ -199,10 +199,10 @@ begin clk_200_osc <= OSCCLK; -RX_HALF_CLK_OUT <= rx_half_clk_ch3; -RX_FULL_CLK_OUT <= rx_full_clk_ch3; -TX_HALF_CLK_OUT <= tx_half_clk_ch3; -TX_FULL_CLK_OUT <= tx_full_clk_ch3; +RX_HALF_CLK_OUT <= rx_half_clk; +RX_FULL_CLK_OUT <= rx_full_clk; +TX_HALF_CLK_OUT <= tx_half_clk; +TX_FULL_CLK_OUT <= tx_full_clk; RX_CDR_LOL_OUT <= rx_cdr_lol; -- !PL14082014 SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready @@ -216,7 +216,7 @@ rst <= (CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigg --gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate --- clk_200_i <= rx_full_clk_ch3; +-- clk_200_i <= rx_full_clk; --end generate; --gen_master_clock : if IS_SYNC_SLAVE = c_NO generate @@ -233,11 +233,11 @@ THE_SERDES : entity work.serdes_sync_upstream hdinn_ch3 => SD_RXD_N_IN, hdoutp_ch3 => SD_TXD_P_OUT, hdoutn_ch3 => SD_TXD_N_OUT, - txiclk_ch3 => rx_full_clk_ch3, --clk_200_i, - rx_full_clk_ch3 => rx_full_clk_ch3, - rx_half_clk_ch3 => rx_half_clk_ch3, - tx_full_clk_ch3 => tx_full_clk_ch3, - tx_half_clk_ch3 => tx_half_clk_ch3, + txiclk_ch3 => rx_full_clk, --clk_200_i, + rx_full_clk_ch3 => rx_full_clk, + rx_half_clk_ch3 => rx_half_clk, + tx_full_clk_ch3 => tx_full_clk, + tx_half_clk_ch3 => tx_half_clk, fpga_rxrefclk_ch3 => clk_200_osc, --clk_200_internal, txdata_ch3 => tx_data, tx_k_ch3 => tx_k, @@ -268,7 +268,7 @@ THE_SERDES : entity work.serdes_sync_upstream SCI_RD => sci_read_i, SCI_WRN => sci_write_i, - fpga_txrefclk => rx_full_clk_ch3, --clk_200_osc, --clk_200_i, + fpga_txrefclk => rx_full_clk, --clk_200_osc, --clk_200_i, tx_serdes_rst_c => tx_serdes_rst, tx_pll_lol_qd_s => tx_pll_lol, rst_qd_c => rst_qd, @@ -295,7 +295,7 @@ THE_RX_FSM : rx_reset_fsm THE_TX_FSM : tx_reset_fsm port map( RST_N => rst_n, - TX_REFCLK => rx_full_clk_ch3, --clk_200_osc, --clk_200_internal, -- allways running PL! 18-06 was clk_200_i + TX_REFCLK => rx_full_clk, --clk_200_osc, --clk_200_internal, -- allways running PL! 18-06 was clk_200_i TX_PLL_LOL_QD_S => tx_pll_lol, RST_QD_C => rst_qd, TX_PCS_RST_CH_C => tx_pcs_rst, @@ -308,7 +308,7 @@ wa_position_rx <= wa_position when (IS_SYNC_SLAVE = c_YES) else x"0000"; --Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable PROC_ALLOW : process begin - wait until rising_edge(rx_full_clk_ch3); --clk_200_osc); --clk_200_i); + wait until rising_edge(rx_full_clk); --clk_200_osc); --clk_200_i); if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then rx_allow <= '1'; else @@ -325,9 +325,9 @@ rx_allow_q <= rx_allow when rising_edge(SYSCLK); tx_allow_q <= tx_allow when rising_edge(SYSCLK); -PROC_START_TIMER : process(rx_full_clk_ch3) --clk_200_osc) --clk_200_i) +PROC_START_TIMER : process(rx_full_clk) --clk_200_osc) --clk_200_i) begin - if rising_edge(rx_full_clk_ch3) then --clk_200_osc) then + if rising_edge(rx_full_clk) then --clk_200_osc) then if got_link_ready_i = '1' then watchdog_timer <= (others => '0'); if start_timer(start_timer'left) = '0' then @@ -353,7 +353,7 @@ end process; ------------------------------------------------- THE_TX : soda_tx_control port map( - CLK_200 => rx_full_clk_ch3, --clk_200_osc, --clk_200_i, + CLK_200 => rx_full_clk, --clk_200_osc, --clk_200_i, CLK_100 => SYSCLK, RESET_IN => rst, --CLEAR, PL! @@ -390,7 +390,7 @@ LINK_PHASE_OUT <= link_phase_S; --PL! ------------------------------------------------- THE_RX_CONTROL : rx_control port map( - CLK_200 => rx_full_clk_ch3, --clk_200_i, PL! + CLK_200 => rx_full_clk, --clk_200_i, PL! CLK_100 => SYSCLK, RESET_IN => rst, --CLEAR, PL! diff --git a/code/trb3_periph_sodahub.vhd b/code/trb3_periph_sodahub.vhd index 21b88a7..7d8c29e 100644 --- a/code/trb3_periph_sodahub.vhd +++ b/code/trb3_periph_sodahub.vhd @@ -263,7 +263,7 @@ begin CLEAR_IN => '0', -- reset input (high active, async) CLEAR_N_IN => '1', -- reset input (low active, async) CLK_IN => clk_200_osc, -- raw master clock, NOT from PLL/DLL! - SYSCLK_IN => clk_100_osc, -- PLL/DLL remastered clock + SYSCLK_IN => rxup_half_clk, --clk_100_osc, -- PLL/DLL remastered clock PLL_LOCKED_IN => GSR_N, --pll_lock, -- master PLL lock signal (async) !PL 14082014 RESET_IN => '0', --general_reset_i, -- '0', -- general reset signal (SYSCLK) --peter schakel TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) @@ -397,7 +397,7 @@ begin THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch port map( - CLK_IN => clk_100_osc, --clk_sys_i, + CLK_IN => clk_100_osc, RESET_IN => reset_i, BUS_ADDR_IN => spimem_addr, @@ -431,8 +431,8 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up IS_SYNC_SLAVE => c_YES ) port map( - OSCCLK => clk_200_osc, --clk_200_i, - SYSCLK => clk_100_osc, --clk_sys_i, + OSCCLK => clk_200_osc, + SYSCLK => clk_100_osc, -- rx_half_clk is selectively used inside med_ecp3_sfp_sync_down.vhd RESET => reset_i, CLEAR => clear_i, --Internal Connection for TrbNet data -> not used a.t.m. @@ -490,9 +490,8 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up A_SODA_HUB : soda_hub port map( - SYSCLK => rxup_half_clk, --clk_100_osc, --clk_sys_i, - SODACLK => rxup_full_clk, --clk_soda_i, --- SODA_OUT_CLK => txdn_full_clk, -- This is 4 clocks !! + SYSCLK => rxup_half_clk, + SODACLK => rxup_full_clk, RESET => reset_i, CLEAR => clear_i, CLK_EN => '1', @@ -534,8 +533,8 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up ) port map( OSC_CLK => clk_200_osc, - TX_DATACLK => rxup_full_clk, --clk_soda_i, --clk_raw_internal, --clk_200_i, - SYSCLK => clk_100_osc, --clk_sys_i, + TX_DATACLK => rxup_full_clk, + SYSCLK => clk_100_osc, -- rx_half_clk is selectively used inside med_ecp3_sfp_4_sync_down.vhd RESET => downlink_reset, CLEAR => downlink_clear, --------------------------------------------------------------------------------------------------------------------------------------------------------- @@ -694,6 +693,8 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up --------------------------------------------------------------------------- -- TRB-Hub --------------------------------------------------------------------------- + med_stat_op(3*16+15 downto 3*16) <= x"0007"; -- !PL telling the hub that this board is inactive 08192014 + med_stat_op(5*16+15 downto 5*16) <= x"0007"; -- !PL telling the hub that this board is inactive 08192014 TRB_HUB : trb_net16_hub_base generic map ( diff --git a/soda_hub.ldf b/soda_hub.ldf new file mode 100644 index 0000000..e628cc1 --- /dev/null +++ b/soda_hub.ldf @@ -0,0 +1,358 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- 2.43.0