From a357990451cde6241c74af7ff0f38453b85eb9ba Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 7 Aug 2012 14:57:12 +0000 Subject: [PATCH] *** empty log message *** --- wasa/.cvsignore | 12 + wasa/compile_panda_dirc_wasa_frankfurt.pl | 161 ++ wasa/cores/.cvsignore | 12 + wasa/cores/flash.ipx | 8 + wasa/cores/flash.lpc | 86 ++ wasa/cores/flash.vhd | 200 +++ wasa/cores/oddr16.ipx | 8 + wasa/cores/oddr16.lpc | 49 + wasa/cores/oddr16.vhd | 291 ++++ wasa/panda_dirc_wasa.prj | 71 + wasa/panda_dirc_wasa.vhd | 255 +++ wasa/sim/machxo.mpf | 1715 +++++++++++++++++++++ wasa/source/.cvsignore | 12 + wasa/source/pwm.vhd | 59 + wasa/source/spi_slave.vhd | 152 ++ wasa/source/tb/.cvsignore | 12 + wasa/source/tb/full_tb.vhd | 175 +++ wasa/source/tb/pwm_tb.vhd | 65 + 18 files changed, 3343 insertions(+) create mode 100644 wasa/.cvsignore create mode 100755 wasa/compile_panda_dirc_wasa_frankfurt.pl create mode 100644 wasa/cores/.cvsignore create mode 100644 wasa/cores/flash.ipx create mode 100644 wasa/cores/flash.lpc create mode 100644 wasa/cores/flash.vhd create mode 100644 wasa/cores/oddr16.ipx create mode 100644 wasa/cores/oddr16.lpc create mode 100644 wasa/cores/oddr16.vhd create mode 100644 wasa/panda_dirc_wasa.prj create mode 100644 wasa/panda_dirc_wasa.vhd create mode 100644 wasa/sim/machxo.mpf create mode 100644 wasa/source/.cvsignore create mode 100644 wasa/source/pwm.vhd create mode 100644 wasa/source/spi_slave.vhd create mode 100644 wasa/source/tb/.cvsignore create mode 100644 wasa/source/tb/full_tb.vhd create mode 100644 wasa/source/tb/pwm_tb.vhd diff --git a/wasa/.cvsignore b/wasa/.cvsignore new file mode 100644 index 0000000..c36ae2e --- /dev/null +++ b/wasa/.cvsignore @@ -0,0 +1,12 @@ +*.log +*.rpt +stdout.log +workdir +version.vhd +*.jhd +*.naf +*.sort +*.srp +*.sym +*tmpl.vhd +*.log diff --git a/wasa/compile_panda_dirc_wasa_frankfurt.pl b/wasa/compile_panda_dirc_wasa_frankfurt.pl new file mode 100755 index 0000000..cf6dead --- /dev/null +++ b/wasa/compile_panda_dirc_wasa_frankfurt.pl @@ -0,0 +1,161 @@ +#!/usr/bin/perl +use Data::Dumper; +use warnings; +use strict; + + + + +################################################################################### +#Settings for this project +my $TOPNAME = "panda_dirc_wasa"; #Name of top-level entity +my $lattice_path = '/d/jspc29/lattice/diamond/1.4.2.105'; +my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/'; +my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; +my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; +################################################################################### + + + + +# +# set_option -technology MACHXO2 +# set_option -part LCMXO2_4000HC +# set_option -package FTG256C +# set_option -speed_grade -6 +# set_option -part_companion "" + + + +use FileHandle; + +$ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; + + + + +my $FAMILYNAME="MACHXO2"; +my $DEVICENAME="LCMXO2-4000HC"; +my $PACKAGE="FTBGA256"; +my $SPEEDGRADE="6"; + + +#create full lpf file +system("cp ../base/".$TOPNAME."1.lpf workdir/$TOPNAME.lpf"); +system("cat ".$TOPNAME."1_constraints.lpf >> workdir/$TOPNAME.lpf"); + + +#set -e +#set -o errexit + +#generate timestamp +my $t=time; +my $fh = new FileHandle(">version.vhd"); +die "could not open file" if (! defined $fh); +print $fh <close; + +system("env| grep LM_"); +my $r = ""; + +my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; +$r=execute($c, "do_not_exit" ); + + +chdir "workdir"; +$fh = new FileHandle("<$TOPNAME".".srr"); +my @a = <$fh>; +$fh -> close; + + + +foreach (@a) +{ + if(/\@E:/) + { + print "\n"; + $c="cat $TOPNAME.srr | grep \"\@E\""; + system($c); + print "\n\n"; + exit 129; + } +} + + +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; + + +$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; +execute($c); + +my $tpmap = $TOPNAME . "_map" ; + +$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; +execute($c); + +system("rm $TOPNAME.ncd"); + + +$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +execute($c); + +# IOR IO Timing Report +# $c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; +# execute($c); + +# TWR Timing Report +$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +# $c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; +# execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.jed $TOPNAME.prf|; +# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +chdir ".."; + +exit; + +sub execute { + my ($c, $op) = @_; + #print "option: $op \n"; + $op = "" if(!$op); + print "\n\ncommand to execute: $c \n"; + $r=system($c); + if($r) { + print "$!"; + if($op ne "do_not_exit") { + exit; + } + } + + return $r; + +} diff --git a/wasa/cores/.cvsignore b/wasa/cores/.cvsignore new file mode 100644 index 0000000..c36ae2e --- /dev/null +++ b/wasa/cores/.cvsignore @@ -0,0 +1,12 @@ +*.log +*.rpt +stdout.log +workdir +version.vhd +*.jhd +*.naf +*.sort +*.srp +*.sym +*tmpl.vhd +*.log diff --git a/wasa/cores/flash.ipx b/wasa/cores/flash.ipx new file mode 100644 index 0000000..cf60b63 --- /dev/null +++ b/wasa/cores/flash.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/wasa/cores/flash.lpc b/wasa/cores/flash.lpc new file mode 100644 index 0000000..effaaf2 --- /dev/null +++ b/wasa/cores/flash.lpc @@ -0,0 +1,86 @@ +[Device] +Family=machxo2 +PartType=LCMXO2-4000HC +PartName=LCMXO2-4000HC-6FTG256C +SpeedGrade=6 +Package=FTBGA256 +OperatingCondition=COM +Status=S + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=EFB +CoreRevision=1.0 +ModuleName=flash +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/03/2012 +Time=15:05:55 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +freq= +i2c1=0 +i2c1_addr=7-Bit Addressing +i2c1_ce=0 +i2c1_freq=100 +i2c1_sa=10000 +i2c1_we=0 +i2c2=0 +i2c2_addr=7-Bit Addressing +i2c2_ce=0 +i2c2_freq=100 +i2c2_sa=10000 +i2c2_we=0 +ufm_addr=7-Bit Addressing +ufm_sa=10000 +pll=0 +pll_cnt=1 +spi=0 +spi_clkinv=0 +spi_cs=1 +spi_en=0 +spi_freq=1 +spi_lsb=0 +spi_mode=Slave +spi_ib=0 +spi_ph=0 +spi_hs=0 +spi_rxo=0 +spi_rxr=0 +spi_txo=0 +spi_txr=0 +spi_we=0 +static_tc=Static +tc=0 +tc_clkinv=PCLOCK +tc_ctr=1 +tc_div=1 +tc_ipcap=0 +tc_mode=CTCM +tc_ocr=32767 +tc_oflow=1 +tc_o=TOGGLE +tc_opcomp=0 +tc_osc=0 +tc_sa_oflow=0 +tc_top=65535 +ufm=1 +wb_clk_freq=133 +ufm_usage=SHARED_EBR_TAG +ufm_ebr=751 +ufm_remain= +mem_size=16 +ufm_start= +ufm_init=0 +memfile= +ufm_dt=hex +wb=1 diff --git a/wasa/cores/flash.vhd b/wasa/cores/flash.vhd new file mode 100644 index 0000000..99ff252 --- /dev/null +++ b/wasa/cores/flash.vhd @@ -0,0 +1,200 @@ +-- VHDL netlist generated by SCUBA Diamond_1.4_Production (87) +-- Module Version: 1.0 +--/d/jspc29/lattice/diamond/1.4.2.105/ispfpga/bin/lin/scuba -w -n flash -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 133 -ufm -ufm_ebr 751 -mem_size 16 -ufm_0 -wb -dev 4000 -e + +-- Fri Aug 3 15:05:55 2012 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library MACHXO2; +use MACHXO2.components.all; +-- synopsys translate_on + +entity flash is + port ( + wb_clk_i: in std_logic; + wb_rst_i: in std_logic; + wb_cyc_i: in std_logic; + wb_stb_i: in std_logic; + wb_we_i: in std_logic; + wb_adr_i: in std_logic_vector(7 downto 0); + wb_dat_i: in std_logic_vector(7 downto 0); + wb_dat_o: out std_logic_vector(7 downto 0); + wb_ack_o: out std_logic; + wbc_ufm_irq: out std_logic); +end flash; + +architecture Structure of flash is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component EFB + generic (EFB_I2C1 : in String; EFB_I2C2 : in String; + EFB_SPI : in String; EFB_TC : in String; + EFB_TC_PORTMODE : in String; EFB_UFM : in String; + EFB_WB_CLK_FREQ : in String; DEV_DENSITY : in String; + UFM_INIT_PAGES : in Integer; + UFM_INIT_START_PAGE : in Integer; + UFM_INIT_ALL_ZEROS : in String; + UFM_INIT_FILE_NAME : in String; + UFM_INIT_FILE_FORMAT : in String; + I2C1_ADDRESSING : in String; I2C2_ADDRESSING : in String; + I2C1_SLAVE_ADDR : in String; I2C2_SLAVE_ADDR : in String; + I2C1_BUS_PERF : in String; I2C2_BUS_PERF : in String; + I2C1_CLK_DIVIDER : in Integer; + I2C2_CLK_DIVIDER : in Integer; I2C1_GEN_CALL : in String; + I2C2_GEN_CALL : in String; I2C1_WAKEUP : in String; + I2C2_WAKEUP : in String; SPI_MODE : in String; + SPI_CLK_DIVIDER : in Integer; SPI_LSB_FIRST : in String; + SPI_CLK_INV : in String; SPI_PHASE_ADJ : in String; + SPI_SLAVE_HANDSHAKE : in String; + SPI_INTR_TXRDY : in String; SPI_INTR_RXRDY : in String; + SPI_INTR_TXOVR : in String; SPI_INTR_RXOVR : in String; + SPI_WAKEUP : in String; TC_MODE : in String; + TC_SCLK_SEL : in String; TC_CCLK_SEL : in Integer; + GSR : in String; TC_TOP_SET : in Integer; + TC_OCR_SET : in Integer; TC_OC_MODE : in String; + TC_RESETN : in String; TC_TOP_SEL : in String; + TC_OV_INT : in String; TC_OCR_INT : in String; + TC_ICR_INT : in String; TC_OVERFLOW : in String; + TC_ICAPTURE : in String); + port (WBCLKI: in std_logic; WBRSTI: in std_logic; + WBCYCI: in std_logic; WBSTBI: in std_logic; + WBWEI: in std_logic; WBADRI7: in std_logic; + WBADRI6: in std_logic; WBADRI5: in std_logic; + WBADRI4: in std_logic; WBADRI3: in std_logic; + WBADRI2: in std_logic; WBADRI1: in std_logic; + WBADRI0: in std_logic; WBDATI7: in std_logic; + WBDATI6: in std_logic; WBDATI5: in std_logic; + WBDATI4: in std_logic; WBDATI3: in std_logic; + WBDATI2: in std_logic; WBDATI1: in std_logic; + WBDATI0: in std_logic; PLL0DATI7: in std_logic; + PLL0DATI6: in std_logic; PLL0DATI5: in std_logic; + PLL0DATI4: in std_logic; PLL0DATI3: in std_logic; + PLL0DATI2: in std_logic; PLL0DATI1: in std_logic; + PLL0DATI0: in std_logic; PLL0ACKI: in std_logic; + PLL1DATI7: in std_logic; PLL1DATI6: in std_logic; + PLL1DATI5: in std_logic; PLL1DATI4: in std_logic; + PLL1DATI3: in std_logic; PLL1DATI2: in std_logic; + PLL1DATI1: in std_logic; PLL1DATI0: in std_logic; + PLL1ACKI: in std_logic; I2C1SCLI: in std_logic; + I2C1SDAI: in std_logic; I2C2SCLI: in std_logic; + I2C2SDAI: in std_logic; SPISCKI: in std_logic; + SPIMISOI: in std_logic; SPIMOSII: in std_logic; + SPISCSN: in std_logic; TCCLKI: in std_logic; + TCRSTN: in std_logic; TCIC: in std_logic; + UFMSN: in std_logic; WBDATO7: out std_logic; + WBDATO6: out std_logic; WBDATO5: out std_logic; + WBDATO4: out std_logic; WBDATO3: out std_logic; + WBDATO2: out std_logic; WBDATO1: out std_logic; + WBDATO0: out std_logic; WBACKO: out std_logic; + PLLCLKO: out std_logic; PLLRSTO: out std_logic; + PLL0STBO: out std_logic; PLL1STBO: out std_logic; + PLLWEO: out std_logic; PLLADRO4: out std_logic; + PLLADRO3: out std_logic; PLLADRO2: out std_logic; + PLLADRO1: out std_logic; PLLADRO0: out std_logic; + PLLDATO7: out std_logic; PLLDATO6: out std_logic; + PLLDATO5: out std_logic; PLLDATO4: out std_logic; + PLLDATO3: out std_logic; PLLDATO2: out std_logic; + PLLDATO1: out std_logic; PLLDATO0: out std_logic; + I2C1SCLO: out std_logic; I2C1SCLOEN: out std_logic; + I2C1SDAO: out std_logic; I2C1SDAOEN: out std_logic; + I2C2SCLO: out std_logic; I2C2SCLOEN: out std_logic; + I2C2SDAO: out std_logic; I2C2SDAOEN: out std_logic; + I2C1IRQO: out std_logic; I2C2IRQO: out std_logic; + SPISCKO: out std_logic; SPISCKEN: out std_logic; + SPIMISOO: out std_logic; SPIMISOEN: out std_logic; + SPIMOSIO: out std_logic; SPIMOSIEN: out std_logic; + SPIMCSN7: out std_logic; SPIMCSN6: out std_logic; + SPIMCSN5: out std_logic; SPIMCSN4: out std_logic; + SPIMCSN3: out std_logic; SPIMCSN2: out std_logic; + SPIMCSN1: out std_logic; SPIMCSN0: out std_logic; + SPICSNEN: out std_logic; SPIIRQO: out std_logic; + TCINT: out std_logic; TCOC: out std_logic; + WBCUFMIRQ: out std_logic; CFGWAKE: out std_logic; + CFGSTDBY: out std_logic); + end component; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + EFBInst_0: EFB + generic map (UFM_INIT_FILE_FORMAT=> "HEX", UFM_INIT_FILE_NAME=> "NONE", + UFM_INIT_ALL_ZEROS=> "ENABLED", UFM_INIT_START_PAGE=> 751, + UFM_INIT_PAGES=> 16, DEV_DENSITY=> "4000L", EFB_UFM=> "ENABLED", + TC_ICAPTURE=> "DISABLED", TC_OVERFLOW=> "DISABLED", TC_ICR_INT=> "OFF", + TC_OCR_INT=> "OFF", TC_OV_INT=> "OFF", TC_TOP_SEL=> "OFF", + TC_RESETN=> "ENABLED", TC_OC_MODE=> "TOGGLE", TC_OCR_SET=> 32767, + TC_TOP_SET=> 65535, GSR=> "ENABLED", TC_CCLK_SEL=> 1, TC_MODE=> "CTCM", + TC_SCLK_SEL=> "PCLOCK", EFB_TC_PORTMODE=> "WB", EFB_TC=> "DISABLED", + SPI_WAKEUP=> "DISABLED", SPI_INTR_RXOVR=> "DISABLED", + SPI_INTR_TXOVR=> "DISABLED", SPI_INTR_RXRDY=> "DISABLED", + SPI_INTR_TXRDY=> "DISABLED", SPI_SLAVE_HANDSHAKE=> "DISABLED", + SPI_PHASE_ADJ=> "DISABLED", SPI_CLK_INV=> "DISABLED", + SPI_LSB_FIRST=> "DISABLED", SPI_CLK_DIVIDER=> 1, SPI_MODE=> "MASTER", + EFB_SPI=> "DISABLED", I2C2_WAKEUP=> "DISABLED", I2C2_GEN_CALL=> "DISABLED", + I2C2_CLK_DIVIDER=> 1, I2C2_BUS_PERF=> "100kHz", I2C2_SLAVE_ADDR=> "0b0011001", + I2C2_ADDRESSING=> "7BIT", EFB_I2C2=> "DISABLED", I2C1_WAKEUP=> "DISABLED", + I2C1_GEN_CALL=> "DISABLED", I2C1_CLK_DIVIDER=> 1, I2C1_BUS_PERF=> "100kHz", + I2C1_SLAVE_ADDR=> "0b0011001", I2C1_ADDRESSING=> "7BIT", + EFB_I2C1=> "DISABLED", EFB_WB_CLK_FREQ=> "133.0") + port map (WBCLKI=>wb_clk_i, WBRSTI=>wb_rst_i, WBCYCI=>wb_cyc_i, + WBSTBI=>wb_stb_i, WBWEI=>wb_we_i, WBADRI7=>wb_adr_i(7), + WBADRI6=>wb_adr_i(6), WBADRI5=>wb_adr_i(5), + WBADRI4=>wb_adr_i(4), WBADRI3=>wb_adr_i(3), + WBADRI2=>wb_adr_i(2), WBADRI1=>wb_adr_i(1), + WBADRI0=>wb_adr_i(0), WBDATI7=>wb_dat_i(7), + WBDATI6=>wb_dat_i(6), WBDATI5=>wb_dat_i(5), + WBDATI4=>wb_dat_i(4), WBDATI3=>wb_dat_i(3), + WBDATI2=>wb_dat_i(2), WBDATI1=>wb_dat_i(1), + WBDATI0=>wb_dat_i(0), PLL0DATI7=>scuba_vlo, + PLL0DATI6=>scuba_vlo, PLL0DATI5=>scuba_vlo, + PLL0DATI4=>scuba_vlo, PLL0DATI3=>scuba_vlo, + PLL0DATI2=>scuba_vlo, PLL0DATI1=>scuba_vlo, + PLL0DATI0=>scuba_vlo, PLL0ACKI=>scuba_vlo, + PLL1DATI7=>scuba_vlo, PLL1DATI6=>scuba_vlo, + PLL1DATI5=>scuba_vlo, PLL1DATI4=>scuba_vlo, + PLL1DATI3=>scuba_vlo, PLL1DATI2=>scuba_vlo, + PLL1DATI1=>scuba_vlo, PLL1DATI0=>scuba_vlo, + PLL1ACKI=>scuba_vlo, I2C1SCLI=>scuba_vlo, + I2C1SDAI=>scuba_vlo, I2C2SCLI=>scuba_vlo, + I2C2SDAI=>scuba_vlo, SPISCKI=>scuba_vlo, SPIMISOI=>scuba_vlo, + SPIMOSII=>scuba_vlo, SPISCSN=>scuba_vlo, TCCLKI=>scuba_vlo, + TCRSTN=>scuba_vlo, TCIC=>scuba_vlo, UFMSN=>scuba_vhi, + WBDATO7=>wb_dat_o(7), WBDATO6=>wb_dat_o(6), + WBDATO5=>wb_dat_o(5), WBDATO4=>wb_dat_o(4), + WBDATO3=>wb_dat_o(3), WBDATO2=>wb_dat_o(2), + WBDATO1=>wb_dat_o(1), WBDATO0=>wb_dat_o(0), WBACKO=>wb_ack_o, + PLLCLKO=>open, PLLRSTO=>open, PLL0STBO=>open, PLL1STBO=>open, + PLLWEO=>open, PLLADRO4=>open, PLLADRO3=>open, PLLADRO2=>open, + PLLADRO1=>open, PLLADRO0=>open, PLLDATO7=>open, + PLLDATO6=>open, PLLDATO5=>open, PLLDATO4=>open, + PLLDATO3=>open, PLLDATO2=>open, PLLDATO1=>open, + PLLDATO0=>open, I2C1SCLO=>open, I2C1SCLOEN=>open, + I2C1SDAO=>open, I2C1SDAOEN=>open, I2C2SCLO=>open, + I2C2SCLOEN=>open, I2C2SDAO=>open, I2C2SDAOEN=>open, + I2C1IRQO=>open, I2C2IRQO=>open, SPISCKO=>open, + SPISCKEN=>open, SPIMISOO=>open, SPIMISOEN=>open, + SPIMOSIO=>open, SPIMOSIEN=>open, SPIMCSN7=>open, + SPIMCSN6=>open, SPIMCSN5=>open, SPIMCSN4=>open, + SPIMCSN3=>open, SPIMCSN2=>open, SPIMCSN1=>open, + SPIMCSN0=>open, SPICSNEN=>open, SPIIRQO=>open, TCINT=>open, + TCOC=>open, WBCUFMIRQ=>wbc_ufm_irq, CFGWAKE=>open, + CFGSTDBY=>open); + +end Structure; diff --git a/wasa/cores/oddr16.ipx b/wasa/cores/oddr16.ipx new file mode 100644 index 0000000..372444e --- /dev/null +++ b/wasa/cores/oddr16.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/wasa/cores/oddr16.lpc b/wasa/cores/oddr16.lpc new file mode 100644 index 0000000..cd403f7 --- /dev/null +++ b/wasa/cores/oddr16.lpc @@ -0,0 +1,49 @@ +[Device] +Family=machxo2 +PartType=LCMXO2-4000HC +PartName=LCMXO2-4000HC-6FTG256C +SpeedGrade=6 +Package=FTBGA256 +OperatingCondition=COM +Status=S + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=DDR_GENERIC +CoreRevision=5.2 +ModuleName=oddr16 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/03/2012 +Time=16:02:24 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +mode=Transmit +io_type=LVTTL33 +num_int=8 +width=16 +freq_in=133 +bandwidth=4256 +aligned=Edge-to-Edge +pre-configuration=DISABLED +mode2=Transmit +io_type2=LVTTL33 +freq_in2=133 +gear=1x +aligned2=Edge-to-Edge +num_int2=8 +width2=16 +Interface=GDDRX1_TX.SCLK.Aligned +Delay=Bypass +DelVal= +UsePll= +GenPll=0 diff --git a/wasa/cores/oddr16.vhd b/wasa/cores/oddr16.vhd new file mode 100644 index 0000000..b12bcfd --- /dev/null +++ b/wasa/cores/oddr16.vhd @@ -0,0 +1,291 @@ +-- VHDL netlist generated by SCUBA Diamond_1.4_Production (87) +-- Module Version: 5.2 +--/d/jspc29/lattice/diamond/1.4.2.105/ispfpga/bin/lin/scuba -w -n oddr16 -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type iol -mode out -io_type LVTTL33 -width 16 -freq_in 133 -gear 1 -clk sclk -aligned -del -1 -e + +-- Fri Aug 3 16:02:24 2012 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library MACHXO2; +use MACHXO2.components.all; +-- synopsys translate_on + +entity oddr16 is + port ( + clk: in std_logic; + clkout: out std_logic; + reset: in std_logic; + sclk: out std_logic; + dataout: in std_logic_vector(31 downto 0); + dout: out std_logic_vector(15 downto 0)); + attribute dont_touch : boolean; + attribute dont_touch of oddr16 : entity is true; +end oddr16; + +architecture Structure of oddr16 is + + -- internal signal declarations + signal db15: std_logic; + signal da15: std_logic; + signal db14: std_logic; + signal da14: std_logic; + signal db13: std_logic; + signal da13: std_logic; + signal db12: std_logic; + signal da12: std_logic; + signal db11: std_logic; + signal da11: std_logic; + signal db10: std_logic; + signal da10: std_logic; + signal db9: std_logic; + signal da9: std_logic; + signal db8: std_logic; + signal da8: std_logic; + signal db7: std_logic; + signal da7: std_logic; + signal db6: std_logic; + signal da6: std_logic; + signal db5: std_logic; + signal da5: std_logic; + signal db4: std_logic; + signal da4: std_logic; + signal db3: std_logic; + signal da3: std_logic; + signal db2: std_logic; + signal da2: std_logic; + signal db1: std_logic; + signal da1: std_logic; + signal db0: std_logic; + signal da0: std_logic; + signal buf_clkout: std_logic; + signal scuba_vlo: std_logic; + signal scuba_vhi: std_logic; + signal clkos: std_logic; + signal clkop: std_logic; + signal buf_douto15: std_logic; + signal buf_douto14: std_logic; + signal buf_douto13: std_logic; + signal buf_douto12: std_logic; + signal buf_douto11: std_logic; + signal buf_douto10: std_logic; + signal buf_douto9: std_logic; + signal buf_douto8: std_logic; + signal buf_douto7: std_logic; + signal buf_douto6: std_logic; + signal buf_douto5: std_logic; + signal buf_douto4: std_logic; + signal buf_douto3: std_logic; + signal buf_douto2: std_logic; + signal buf_douto1: std_logic; + signal buf_douto0: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component OB + port (I: in std_logic; O: out std_logic); + end component; + component ODDRXE + port (D0: in std_logic; D1: in std_logic; SCLK: in std_logic; + RST: in std_logic; Q: out std_logic); + end component; + attribute IO_TYPE : string; + attribute IO_TYPE of Inst1_OB15 : label is "LVTTL33"; + attribute IO_TYPE of Inst1_OB14 : label is "LVTTL33"; + attribute IO_TYPE of Inst1_OB13 : label is "LVTTL33"; + attribute IO_TYPE of Inst1_OB12 : label is "LVTTL33"; + attribute IO_TYPE of Inst1_OB11 : label is "LVTTL33"; + attribute IO_TYPE of Inst1_OB10 : label is "LVTTL33"; + attribute IO_TYPE of Inst1_OB9 : label is "LVTTL33"; + attribute IO_TYPE of Inst1_OB8 : label is "LVTTL33"; + attribute IO_TYPE of Inst1_OB7 : label is "LVTTL33"; + attribute IO_TYPE of Inst1_OB6 : label is "LVTTL33"; + attribute IO_TYPE of Inst1_OB5 : label is "LVTTL33"; + attribute IO_TYPE of Inst1_OB4 : label is "LVTTL33"; + attribute IO_TYPE of Inst1_OB3 : label is "LVTTL33"; + attribute IO_TYPE of Inst1_OB2 : label is "LVTTL33"; + attribute IO_TYPE of Inst1_OB1 : label is "LVTTL33"; + attribute IO_TYPE of Inst1_OB0 : label is "LVTTL33"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + +begin + -- component instantiation statements + Inst3_ODDRXE15: ODDRXE + port map (D0=>da15, D1=>db15, SCLK=>clkop, RST=>reset, + Q=>buf_douto15); + + Inst3_ODDRXE14: ODDRXE + port map (D0=>da14, D1=>db14, SCLK=>clkop, RST=>reset, + Q=>buf_douto14); + + Inst3_ODDRXE13: ODDRXE + port map (D0=>da13, D1=>db13, SCLK=>clkop, RST=>reset, + Q=>buf_douto13); + + Inst3_ODDRXE12: ODDRXE + port map (D0=>da12, D1=>db12, SCLK=>clkop, RST=>reset, + Q=>buf_douto12); + + Inst3_ODDRXE11: ODDRXE + port map (D0=>da11, D1=>db11, SCLK=>clkop, RST=>reset, + Q=>buf_douto11); + + Inst3_ODDRXE10: ODDRXE + port map (D0=>da10, D1=>db10, SCLK=>clkop, RST=>reset, + Q=>buf_douto10); + + Inst3_ODDRXE9: ODDRXE + port map (D0=>da9, D1=>db9, SCLK=>clkop, RST=>reset, + Q=>buf_douto9); + + Inst3_ODDRXE8: ODDRXE + port map (D0=>da8, D1=>db8, SCLK=>clkop, RST=>reset, + Q=>buf_douto8); + + Inst3_ODDRXE7: ODDRXE + port map (D0=>da7, D1=>db7, SCLK=>clkop, RST=>reset, + Q=>buf_douto7); + + Inst3_ODDRXE6: ODDRXE + port map (D0=>da6, D1=>db6, SCLK=>clkop, RST=>reset, + Q=>buf_douto6); + + Inst3_ODDRXE5: ODDRXE + port map (D0=>da5, D1=>db5, SCLK=>clkop, RST=>reset, + Q=>buf_douto5); + + Inst3_ODDRXE4: ODDRXE + port map (D0=>da4, D1=>db4, SCLK=>clkop, RST=>reset, + Q=>buf_douto4); + + Inst3_ODDRXE3: ODDRXE + port map (D0=>da3, D1=>db3, SCLK=>clkop, RST=>reset, + Q=>buf_douto3); + + Inst3_ODDRXE2: ODDRXE + port map (D0=>da2, D1=>db2, SCLK=>clkop, RST=>reset, + Q=>buf_douto2); + + Inst3_ODDRXE1: ODDRXE + port map (D0=>da1, D1=>db1, SCLK=>clkop, RST=>reset, + Q=>buf_douto1); + + Inst3_ODDRXE0: ODDRXE + port map (D0=>da0, D1=>db0, SCLK=>clkop, RST=>reset, + Q=>buf_douto0); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + Inst2_ODDRXE: ODDRXE + port map (D0=>scuba_vhi, D1=>scuba_vlo, SCLK=>clkos, RST=>reset, + Q=>buf_clkout); + + Inst1_OB15: OB + port map (I=>buf_douto15, O=>dout(15)); + + Inst1_OB14: OB + port map (I=>buf_douto14, O=>dout(14)); + + Inst1_OB13: OB + port map (I=>buf_douto13, O=>dout(13)); + + Inst1_OB12: OB + port map (I=>buf_douto12, O=>dout(12)); + + Inst1_OB11: OB + port map (I=>buf_douto11, O=>dout(11)); + + Inst1_OB10: OB + port map (I=>buf_douto10, O=>dout(10)); + + Inst1_OB9: OB + port map (I=>buf_douto9, O=>dout(9)); + + Inst1_OB8: OB + port map (I=>buf_douto8, O=>dout(8)); + + Inst1_OB7: OB + port map (I=>buf_douto7, O=>dout(7)); + + Inst1_OB6: OB + port map (I=>buf_douto6, O=>dout(6)); + + Inst1_OB5: OB + port map (I=>buf_douto5, O=>dout(5)); + + Inst1_OB4: OB + port map (I=>buf_douto4, O=>dout(4)); + + Inst1_OB3: OB + port map (I=>buf_douto3, O=>dout(3)); + + Inst1_OB2: OB + port map (I=>buf_douto2, O=>dout(2)); + + Inst1_OB1: OB + port map (I=>buf_douto1, O=>dout(1)); + + Inst1_OB0: OB + port map (I=>buf_douto0, O=>dout(0)); + + sclk <= clkop; + db15 <= dataout(31); + db14 <= dataout(30); + db13 <= dataout(29); + db12 <= dataout(28); + db11 <= dataout(27); + db10 <= dataout(26); + db9 <= dataout(25); + db8 <= dataout(24); + db7 <= dataout(23); + db6 <= dataout(22); + db5 <= dataout(21); + db4 <= dataout(20); + db3 <= dataout(19); + db2 <= dataout(18); + db1 <= dataout(17); + db0 <= dataout(16); + da15 <= dataout(15); + da14 <= dataout(14); + da13 <= dataout(13); + da12 <= dataout(12); + da11 <= dataout(11); + da10 <= dataout(10); + da9 <= dataout(9); + da8 <= dataout(8); + da7 <= dataout(7); + da6 <= dataout(6); + da5 <= dataout(5); + da4 <= dataout(4); + da3 <= dataout(3); + da2 <= dataout(2); + da1 <= dataout(1); + da0 <= dataout(0); + clkout <= buf_clkout; + clkos <= clk; + clkop <= clk; +end Structure; + +-- synopsys translate_off +library MACHXO2; +configuration Structure_CON of oddr16 is + for Structure + for all:VHI use entity MACHXO2.VHI(V); end for; + for all:VLO use entity MACHXO2.VLO(V); end for; + for all:OB use entity MACHXO2.OB(V); end for; + for all:ODDRXE use entity MACHXO2.ODDRXE(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/wasa/panda_dirc_wasa.prj b/wasa/panda_dirc_wasa.prj new file mode 100644 index 0000000..163b484 --- /dev/null +++ b/wasa/panda_dirc_wasa.prj @@ -0,0 +1,71 @@ +#-- Synopsys, Inc. +#-- Version F-2012.03-SP1 +#-- Project file /local/trb/cvs/trb3/wasa/panda_dirc_wasa/panda_dirc_wasa_syn.prj +#-- Written on Mon Aug 6 18:53:10 2012 + + +#project files +add_file -vhdl -lib work "/d/jspc29/lattice/diamond/1.4.2.105/cae_library/synthesis/vhdl/machxo2.vhd" +add_file -vhdl -lib work "/local/trb/cvs/trb3/wasa/panda_dirc_wasa.vhd" +add_file -vhdl -lib work "/local/trb/cvs/trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "/local/trb/cvs/trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "/local/trb/cvs/trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "/local/trb/cvs/trb3/wasa/source/spi_slave.vhd" +add_file -vhdl -lib work "/local/trb/cvs/trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "/local/trb/cvs/trb3/wasa/version.vhd" +add_file -vhdl -lib work "/local/trb/cvs/trb3/wasa/cores/oddr16.vhd" +add_file -vhdl -lib work "/local/trb/cvs/trb3/wasa/source/pwm.vhd" + + +#implementation: "panda_dirc_wasa" +impl -add workdir -type fpga + +# +#implementation attributes + +set_option -vlog_std sysv +set_option -project_relative_includes 1 + +#device options +set_option -technology MACHXO2 +set_option -part LCMXO2_4000HC +set_option -package FTG256C +set_option -speed_grade -6 +set_option -part_companion "" + +#compilation/mapping options + +# mapper_options +set_option -frequency auto +set_option -write_verilog 0 +set_option -write_vhdl 0 + +# Lattice XP +set_option -maxfan 1000 +set_option -disable_io_insertion 0 +set_option -retiming 0 +set_option -pipe 1 +set_option -forcegsr no +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -update_models_cp 0 + +# NFilter +set_option -popfeed 0 +set_option -constprop 0 +set_option -createhierarchy 0 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 +set_option -multi_file_compilation_unit 1 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "workdir/panda_dirc_wasa.edf" +impl -active "workdir" diff --git a/wasa/panda_dirc_wasa.vhd b/wasa/panda_dirc_wasa.vhd new file mode 100644 index 0000000..1ba53d0 --- /dev/null +++ b/wasa/panda_dirc_wasa.vhd @@ -0,0 +1,255 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.version.all; + +library machxo2; +use machxo2.all; + + +entity panda_dirc_wasa is + port( + CON : out std_logic_vector(16 downto 1); + INP : in std_logic_vector(16 downto 1); + PWM : out std_logic_vector(16 downto 1); + SPARE_LINE : out std_logic_vector(5 downto 0); + LED_GREEN : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_YELLOW : out std_logic; + SPI_CLK : in std_logic; + SPI_CS : in std_logic; + SPI_IN : in std_logic; + SPI_OUT : out std_logic; + TEMP_LINE : inout std_logic; + TEST_LINE : out std_logic_vector(15 downto 0) + ); +end entity; + +architecture panda_dirc_wasa_arch of panda_dirc_wasa is + +component OSCH +-- synthesis translate_off + generic (NOM_FREQ: string := "133.00"); +-- synthesis translate_on + port ( + STDBY :IN std_logic; + OSC :OUT std_logic; + SEDSTDBY :OUT std_logic + ); +end component; + +component oddr16 is + port ( + clk: in std_logic; + clkout: out std_logic; + reset: in std_logic; + sclk: out std_logic; + dataout: in std_logic_vector(31 downto 0); + dout: out std_logic_vector(15 downto 0)); +end component; + +component spi_slave + port( + CLK : in std_logic; + SPI_CLK : in std_logic; + SPI_CS : in std_logic; + SPI_IN : in std_logic; + SPI_OUT : out std_logic; + + DATA_OUT : out std_logic_vector(15 downto 0); + REG00_IN : in std_logic_vector(15 downto 0); + REG10_IN : in std_logic_vector(15 downto 0); + REG20_IN : in std_logic_vector(15 downto 0); + REG40_IN : in std_logic_vector(15 downto 0); + + OPERATION_OUT : out std_logic_vector(3 downto 0); + CHANNEL_OUT : out std_logic_vector(7 downto 0); + WRITE_OUT : out std_logic_vector(15 downto 0); + + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end component; + + +component pwm_generator + port( + CLK : in std_logic; + DATA_IN : in std_logic_vector(15 downto 0); + DATA_OUT : out std_logic_vector(15 downto 0); + WRITE_IN : in std_logic; + ADDR_IN : in std_logic_vector(3 downto 0); + PWM : out std_logic_vector(31 downto 0) + ); +end component; + +attribute NOM_FREQ : string; +attribute NOM_FREQ of clk_source : label is "133.00"; +signal clk_i : std_logic; + +signal reset_i : std_logic := '1'; +signal reset_cnt : unsigned(3 downto 0) := x"0"; +signal id_data_i : std_logic_vector(15 downto 0); +signal id_addr_i : std_logic_vector(2 downto 0); +signal id_write_i: std_logic; +signal ram_write_i : std_logic; +signal ram_data_i: std_logic_vector(15 downto 0); +signal ram_data_o: std_logic_vector(15 downto 0); +signal ram_addr_i: integer range 0 to 15; +signal temperature_i : std_logic_vector(11 downto 0); + +type ram_t is array(0 to 15) of std_logic_vector(15 downto 0); +signal idram : ram_t; +signal ram : ram_t; + +signal pwm_i : std_logic_vector(31 downto 0); + +signal spi_reg00_i : std_logic_vector(15 downto 0); +signal spi_reg10_i : std_logic_vector(15 downto 0); +signal spi_reg20_i : std_logic_vector(15 downto 0); +signal spi_reg40_i : std_logic_vector(15 downto 0); +signal spi_data_i : std_logic_vector(15 downto 0); +signal spi_operation_i : std_logic_vector(3 downto 0); +signal spi_channel_i : std_logic_vector(7 downto 0); +signal spi_write_i : std_logic_vector(15 downto 0); + +begin + +PROC_RESET : process begin + wait until rising_edge(clk_i); + reset_i <= '0'; + if reset_cnt /= x"F" then + reset_cnt <= reset_cnt + 1; + reset_i <= '1'; + end if; +end process; + +--------------------------------------------------------------------------- +-- Clock +--------------------------------------------------------------------------- +clk_source: OSCH +-- synthesis translate_off + generic map ( NOM_FREQ => "133.00" ) +-- synthesis translate_on + port map ( + STDBY => '0', + OSC => clk_i, + SEDSTDBY => open + ); + + +--------------------------------------------------------------------------- +-- SPI Interface +--------------------------------------------------------------------------- +THE_SPI_SLAVE : spi_slave + port map( + CLK => clk_i, + SPI_CLK => SPI_CLK, + SPI_CS => SPI_CS, + SPI_IN => SPI_IN, + SPI_OUT => SPI_OUT, + DATA_OUT => spi_data_i, + REG00_IN => spi_reg00_i, + REG10_IN => spi_reg10_i, + REG20_IN => spi_reg20_i, + REG40_IN => spi_reg40_i, + OPERATION_OUT => spi_operation_i, + CHANNEL_OUT => spi_channel_i, + WRITE_OUT => spi_write_i, + DEBUG_OUT => open + ); + +ram_write_i <= spi_write_i(4); --or signal from Flash entity +ram_data_i <= spi_data_i; --or signal from Flash entity +ram_addr_i <= to_integer(unsigned(spi_channel_i(3 downto 0))); --or signal from Flash entity + +PROC_RAM : process begin + wait until rising_edge(clk_i); + if ram_write_i = '1' then + ram(ram_addr_i) <= ram_data_i; + end if; + ram_data_o <= ram(ram_addr_i); + spi_reg40_i <= ram(to_integer(unsigned(spi_channel_i(3 downto 0)))); +end process; + +--------------------------------------------------------------------------- +-- PWM +--------------------------------------------------------------------------- + +THE_PWM_GEN : pwm_generator + port map( + CLK => clk_i, + DATA_IN => spi_data_i, + DATA_OUT => spi_reg00_i, + WRITE_IN => spi_write_i(0), + ADDR_IN => spi_channel_i(3 downto 0), + PWM => pwm_i + ); + + +PWM_ODDR : oddr16 + port map( + clk => clk_i, + clkout => open, + reset => '0', + sclk => open, + dataout => pwm_i, + dout => PWM + ); + + + +--------------------------------------------------------------------------- +-- Temperature Sensor +--------------------------------------------------------------------------- + +THE_ONEWIRE : trb_net_onewire + port map( + CLK => clk_i, + RESET => reset_i, + READOUT_ENABLE_IN => '1', + ONEWIRE => TEMP_LINE, + MONITOR_OUT => open, + --connection to id ram, according to memory map in TrbNetRegIO + DATA_OUT => id_data_i, + ADDR_OUT => id_addr_i, + WRITE_OUT=> id_write_i, + TEMP_OUT => temperature_i, + ID_OUT => open, + STAT => open + ); + +PROC_IDMEM : process begin + wait until rising_edge(clk_i); + if id_write_i = '1' then + idram(to_integer(unsigned(id_addr_i))) <= id_data_i; + else + idram(4) <= "0000" & temperature_i; + end if; + spi_reg10_i <= idram(to_integer(unsigned(spi_channel_i(3 downto 0)))); +end process; + + +--------------------------------------------------------------------------- +-- Rest of the I/O +--------------------------------------------------------------------------- +CON <= INP; + + +SPARE_LINE <= (others => '0'); + +TEST_LINE(0) <= clk_i; +TEST_LINE(15 downto 1) <= (others => '0'); + +LED_GREEN <= '0'; +LED_ORANGE <= '0'; +LED_RED <= '0'; +LED_YELLOW <= '0'; + +end architecture; + diff --git a/wasa/sim/machxo.mpf b/wasa/sim/machxo.mpf new file mode 100644 index 0000000..b1dad6d --- /dev/null +++ b/wasa/sim/machxo.mpf @@ -0,0 +1,1715 @@ +; Copyright 1991-2011 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +std = $MODEL_TECH/../std +ieee = $MODEL_TECH/../ieee +vital2000 = $MODEL_TECH/../vital2000 +; +; VITAL concerns: +; +; The library ieee contains (among other packages) the packages of the +; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use +; the physical library ieee (recommended), or use the physical library +; vital2000, but not both. The design can use logical library ieee and/or +; vital2000 as long as each of these maps to the same physical library, either +; ieee or vital2000. +; +; A design using the 1995 version of the VITAL packages, whether or not +; it also uses the 2000 version of the VITAL packages, must have logical library +; name ieee mapped to physical library vital1995. (A design cannot use library +; vital1995 directly because some packages in this library use logical name ieee +; when referring to the other packages in the library.) The design source +; should use logical name ieee when referring to any packages there except the +; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical +; name vital2000 (mapped to physical library vital2000) to refer to those +; packages. +; ieee = $MODEL_TECH/../vital1995 +; +; For compatiblity with previous releases, logical library name vital2000 maps +; to library vital2000 (a different library than library ieee, containing the +; same packages). +; A design should not reference VITAL from both the ieee library and the +; vital2000 library because the vital packages are effectively different. +; A design that references both the ieee and vital2000 libraries must have +; both logical names ieee and vital2000 mapped to the same library, either of +; these: +; $MODEL_TECH/../ieee +; $MODEL_TECH/../vital2000 +; +verilog = $MODEL_TECH/../verilog +std_developerskit = $MODEL_TECH/../std_developerskit +synopsys = $MODEL_TECH/../synopsys +modelsim_lib = $MODEL_TECH/../modelsim_lib +sv_std = $MODEL_TECH/../sv_std +mtiAvm = $MODEL_TECH/../avm +mtiOvm = $MODEL_TECH/../ovm-2.1.2 +mtiUvm = $MODEL_TECH/../uvm-1.1 +mtiUPF = $MODEL_TECH/../upf_lib +mtiPA = $MODEL_TECH/../pa_lib +floatfixlib = $MODEL_TECH/../floatfixlib +mc2_lib = $MODEL_TECH/../mc2_lib +;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release +;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release +;mvc_lib = $MODEL_TECH/../mvc_lib + +work = work +machxo2 = /d/jspc29/lattice/diamond/1.4.2.105/ispfpga/vhdl/data/machxo2/mti/machxo2 +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Value of 3 or 2008 for VHDL-2008 +VHDL93 = 2002 + +; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. +; ignoreStandardRealVector = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Turn off PSL assertion warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Perform default binding at compile time. +; Default is to do default binding at load time. +; BindAtCompile = 1; + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +; Run the 0-in compiler on the VHDL source files +; Default is off. +; ZeroIn = 1 + +; Set the options to be passed to the 0-in compiler. +; Default is "". +; ZeroInOptions = "" + +; Set the synthesis prefix to be honored for synthesis pragma recognition. +; Default is "". +; SynthPrefix = "" + +; Turn on code coverage in VHDL design units. Default is off. +; Coverage = sbceft + +; Turn off code coverage in VHDL subprograms. Default is on. +; CoverageSub = 0 + +; Automatically exclude VHDL case statement OTHERS choice branches. +; This includes OTHERS choices in selected signal assigment statements. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Turn on or off clkOpt optimization for code coverage. Default is on. +; CoverClkOpt = 1 + +; Turn on or off clkOpt optimization builtins for code coverage. Default is on. +; CoverClkOptBuiltins = 0 + +; Inform code coverage optimizations to respect VHDL 'H' and 'L' +; values on signals in conditions and expressions, and to not automatically +; convert them to '1' and '0'. Default is to not convert. +; CoverRespectHandL = 0 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is provided by default when expression and/or condition +; coverage is active. +; CoverUDP = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Use this directory for compiler temporary files instead of "work/_temp" +; CompilerTempDir = /tmp + +; Set this to cause the compilers to force data to be committed to disk +; when the files are closed. +; SyncCompilerFiles = 1 + +; Add VHDL-AMS declarations to package STANDARD +; Default is not to add +; AmsStandard = 1 + +; Range and length checking will be performed on array indices and discrete +; ranges, and when violations are found within subprograms, errors will be +; reported. Default is to issue warnings for violations, because subprograms +; may not be invoked. +; NoDeferSubpgmCheck = 0 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; Controls whether or not to show immediate assertions with constant expressions +; in GUI/report/UCDB etc. By default, immediate assertions with constant +; expressions are shown in GUI/report/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls how VHDL basic identifiers are stored with the design unit. +; Does not make the language case-sensitive, effects only how declarations +; declared with basic identifiers have their names stored and printed +; (examine, etc.). +; Default is to preserve the case as originally depicted in the VHDL source. +; Value of 0 indicates to change basic identifiers to lower case. +; PreserveCase = 0 + +; For Configuration Declarations, controls the effect that USE clauses have +; on visibility inside the configuration items being configured. If 1 +; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance +; extend the visibility of objects made visible through USE clauses into nested +; component configurations. +; OldVHDLConfigurationVisibility = 0 + +; Allows VHDL configuration declarations to be in a different library from +; the corresponding configured entity. Default is to not allow this for +; stricter LRM-compliance +; SeparateConfigLibrary = 1; + +; Change how subprogram out parameter of type array and record are treated. +; If 1, always initial the out parameter to its default value. +; If 2, do not initialize the out parameter. +; The value 0 indicates use the default for the langauge version being compiled. +; Prior to 10.1 all langauge version did not initialize out composite parameters. +; 10.1 and later files compile with -2008 initialize by default +; InitOutCompositeParam = 0 + +[vlog] +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn on `protect compiler directive processing. +; Default is to ignore `protect directives. +; Protect = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn on bad option warning. Default is off. +; Show_BadOptionWarning = 1 + +; Revert back to IEEE 1364-1995 syntax, default is 0 (off). +; vlog95compat = 1 + +; Turn off PSL warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Set the threshold for automatically identifying sparse Verilog memories. +; A memory with depth equal to or more than the sparse memory threshold gets +; marked as sparse automatically, unless specified otherwise in source code +; or by +nosparse commandline option of vlog or vopt. +; The default is 1M. (i.e. memories with depth equal +; to or greater than 1M are marked as sparse) +; SparseMemThreshold = 1048576 + +; Run the 0-in compiler on the Verilog source files +; Default is off. +; ZeroIn = 1 + +; Set the options to be passed to the 0-in compiler. +; Default is "". +; ZeroInOptions = "" + +; Set the synthesis prefix to be honored for synthesis pragma recognition. +; Default is "". +; SynthPrefix = "" + +; Set the option to treat all files specified in a vlog invocation as a +; single compilation unit. The default value is set to 0 which will treat +; each file as a separate compilation unit as specified in the P1800 draft standard. +; MultiFileCompilationUnit = 1 + +; Turn on code coverage in Verilog design units. Default is off. +; Coverage = sbceft + +; Automatically exclude Verilog case statement default branches. +; Default is to not automatically exclude defaults. +; CoverExcludeDefault = 1 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a Verilog condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is provided by default when expression and/or condition +; coverage is active. +; CoverUDP = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + + +; Turn on code coverage in VLOG `celldefine modules and modules included +; using vlog -v and -y. Default is off. +; CoverCells = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. This is a number from 1 to 4, with the following +; meanings (the default is 3): +; 1 -- Turn off all optimizations that affect coverage reports. +; 2 -- Allow optimizations that allow large performance improvements +; by invoking sequential processes only when the data changes. +; This may make major reductions in coverage counts. +; 3 -- In addition, allow optimizations that may change expressions or +; remove some statements. Allow constant propagation. Allow VHDL +; subprogram inlining and VHDL FF recognition. +; 4 -- In addition, allow optimizations that may remove major regions of +; code by changing assignments to built-ins or removing unused +; signals. Change Verilog gates to continuous assignments. +; CoverOpt = 3 + +; Specify the override for the default value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then LRM default +; value of 0 (zero) is used. This is a compile time option. +; SVCrossNumPrintMissingDefault = 0 + +; Setting following to 1 would cause creation of variables which +; would represent the value of Coverpoint expressions. This is used +; in conjunction with "SVCoverpointExprVariablePrefix" option +; in the modelsim.ini +; EnableSVCoverpointExprVariable = 0 + +; Specify the override for the prefix used in forming the variable names +; which represent the Coverpoint expressions. This is used in conjunction with +; "EnableSVCoverpointExprVariable" option of the modelsim.ini +; The default prefix is "expr". +; The variable name is +; variable name => _ +; SVCoverpointExprVariablePrefix = expr + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross option.goal (defined to be 100 in the LRM). +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" +; in the [vsim] section can override this value. +; SVCovergroupGoalDefault = 100 + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" +; in the [vsim] section can override this value. +; SVCovergroupTypeGoalDefault = 100 + +; Specify the override for the default value of "strobe" option for the +; Covergroup Type. This is a compile time option which forces "strobe" to +; a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. +; SVCovergroupStrobeDefault = 0 + +; Specify the override for the default value of "merge_instances" option for +; the Covergroup Type. This is a compile time option which forces +; "merge_instances" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupMergeInstancesDefault = 0 + +; Specify the override for the default value of "per_instance" option for the +; Covergroup variables. This is a compile time option which forces "per_instance" +; to a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). +; SVCovergroupPerInstanceDefault = 0 + +; Specify the override for the default value of "get_inst_coverage" option for the +; Covergroup variables. This is a compile time option which forces +; "get_inst_coverage" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupGetInstCoverageDefault = 0 + +; +; A space separated list of resource libraries that contain precompiled +; packages. The behavior is identical to using the "-L" switch. +; +; LibrarySearchPath = [ ...] +LibrarySearchPath = mtiAvm mtiOvm mtiUvm mtiUPF + +; The behavior is identical to the "-mixedansiports" switch. Default is off. +; MixedAnsiPorts = 1 + +; Enable SystemVerilog 3.1a $typeof() function. Default is off. +; EnableTypeOf = 1 + +; Only allow lower case pragmas. Default is disabled. +; AcceptLowerCasePragmaOnly = 1 + +; Set the maximum depth permitted for a recursive include file nesting. +; IncludeRecursionDepthMax = 5 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn off detections of FSMs having x-assignment. +; FsmXAssign = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; List of file suffixes which will be read as SystemVerilog. White space +; in extensions can be specified with a back-slash: "\ ". Back-slashes +; can be specified with two consecutive back-slashes: "\\"; +; SVFileExtensions = sv svp svh + +; This setting is the same as the vlog -sv command line switch. +; Enables SystemVerilog features and keywords when true (1). +; When false (0), the rules of IEEE Std 1364-2001 are followed and +; SystemVerilog keywords are ignored. +; Svlog = 0 + +; Prints attribute placed upon SV packages during package import +; when true (1). The attribute will be ignored when this +; entry is false (0). The attribute name is "package_load_message". +; The value of this attribute is a string literal. +; Default is true (1). +; PrintSVPackageLoadingAttribute = 1 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls if untyped parameters that are initialized with values greater +; than 2147483647 are mapped to generics of type INTEGER or ignored. +; If mapped to VHDL Integers, values greater than 2147483647 +; are mapped to negative values. +; Default is to map these parameter to generic of type INTEGER +; ForceUnsignedToVHDLInteger = 1 + +; Enable AMS wreal (wired real) extensions. Default is 0. +; WrealType = 1 + +[sccom] +; Enable use of SCV include files and library. Default is off. +; UseScv = 1 + +; Add C++ compiler options to the sccom command line by using this variable. +; CppOptions = -g + +; Use custom C++ compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; CppPath = /usr/bin/g++ + +; Enable verbose messages from sccom. Default is off. +; SccomVerbose = 1 + +; sccom logfile. Default is no logfile. +; SccomLogfile = sccom.log + +; Enable use of SC_MS include files and library. Default is off. +; UseScMs = 1 + +[vopt] +; Turn on code coverage in vopt. Default is off. +; Coverage = sbceft + +; Control compiler optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a vopt condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Set the maximum number of iterations permitted for a generate loop. +; Restricting this permits the implementation to recognize infinite +; generate loops. +; GenerateLoopIterationMax = 100000 + +; Set the maximum depth permitted for a recursive generate instantiation. +; Restricting this permits the implementation to recognize infinite +; recursions. +; GenerateRecursionDepthMax = 200 + + +[vsim] +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is on +VoptFlow = 1 + +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ns + +; Disable certain code coverage exclusions automatically. +; Assertions and FSM are exluded from the code coverage by default +; Set AutoExclusionsDisable = fsm to enable code coverage for fsm +; Set AutoExclusionsDisable = assertions to enable code coverage for assertions +; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions +; Or specify comma or space separated list +;AutoExclusionsDisable = fsm,assertions + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 30 us + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Control PSL and Verilog Assume directives during simulation +; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts +; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts +; SimulateAssumeDirectives = 1 + +; Control the simulation of PSL and SVA +; These switches can be overridden by the vsim command line switches: +; -psl, -nopsl, -sva, -nosva. +; Set SimulatePSL = 0 to disable PSL simulation +; Set SimulatePSL = 1 to enable PSL simulation (default) +; SimulatePSL = 1 +; Set SimulateSVA = 0 to disable SVA simulation +; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) +; SimulateSVA = 1 + +; Directives to license manager can be set either as single value or as +; space separated multi-values: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; noqueue Do not wait in the license queue when a license is not available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license (PE ONLY) +; noviewer Disable checkout of msimviewer and vsim-viewer license +; features (PE ONLY) +; noslvhdl Disable checkout of qhsimvh and vsim license features +; noslvlog Disable checkout of qhsimvl and vsimvlog license features +; nomix Disable checkout of msimhdlmix and hdlmix license features +; nolnl Disable checkout of msimhdlsim and hdlsim license features +; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license +; features +; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix, +; hdlmix license features +; Single value: +; License = plus +; Multi-value: +; License = noqueue plus + +; Severity level of a VHDL assertion message or of a SystemVerilog immediate assertion +; which will cause a running simulation to stop. +; VHDL assertions and SystemVerilog immediate assertions that occur with the +; given severity or higher will cause a running simulation to stop. +; This value is ignored during elaboration. +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Message Format conversion specifications: +; %S - Severity Level of message/assertion +; %R - Text of message +; %T - Time of message +; %D - Delta value (iteration number) of Time +; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected +; %i - Instance/Region/Signal pathname with Process name (if available) +; %I - shorthand for one of these: +; " %K: %i" +; " %K: %i File: %F" (when path is not Process or Signal) +; except that the %i in this case does not report the Process name +; %O - Process name +; %P - Instance/Region path without leaf process +; %F - File name +; %L - Line number; if assertion message, then line number of assertion or, if +; assertion is in a subprogram, line from which the call is made +; %u - Design unit name in form library.primary +; %U - Design unit name in form library.primary(secondary) +; %% - The '%' character itself +; +; If specific format for Severity Level is defined, use that format. +; Else, for a message that occurs during elaboration: +; -- Failure/Fatal message in VHDL region that is not a Process, and in +; certain non-VHDL regions, uses MessageFormatBreakLine; +; -- Failure/Fatal message otherwise uses MessageFormatBreak; +; -- Note/Warning/Error message uses MessageFormat. +; Else, for a message that occurs during runtime and triggers a breakpoint because +; of the BreakOnAssertion setting: +; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; +; -- otherwise uses MessageFormatBreak. +; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. +; +; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" +; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Error File - alternate file for storing error messages +; ErrorFile = error.log + +; Simulation Breakpoint messages +; This flag controls the display of function names when reporting the location +; where the simulator stops because of a breakpoint or fatal error. +; Example with function name: # Break in Process ctr at counter.vhd line 44 +; Example without function name: # Break at counter.vhd line 44 +; Default value is 1. +ShowFunctions = 1 + +; Default radix for all windows and commands. +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; VSIM Shutdown file +; Filename to save u/i formats and configurations. +; ShutdownFile = restart.do +; To explicitly disable auto save: +; ShutdownFile = --disable-auto-save + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example: sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Specify a unique path separator for the Signal Spy set of functions. +; The default will be to use the PathSeparator variable. +; Must not be the same character as DatasetSeparator. +; SignalSpyPathSeparator = / + +; Used to control parsing of HDL identifiers input to the tool. +; This includes CLI commands, vsim/vopt/vlog/vcom options, +; string arguments to FLI/VPI/DPI calls, etc. +; If set to 1, accept either Verilog escaped Id syntax or +; VHDL extended id syntax, regardless of source language. +; If set to 0, the syntax of the source language must be used. +; Each identifier in a hierarchical name may need different syntax, +; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or +; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" +; GenerousIdentifierParsing = 1 + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Disable SystemVerilog assertion messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Do not print any additional information from Severity System tasks. +; Only the message provided by the user is printed along with severity +; information. +; SVAPrintOnlyUserMessage = 1; + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; Control the iteration of events when a VHDL signal is forced to a value +; This flag can be set to honour the signal update event in next iteration, +; the default is to update and propagate in the same iteration. +; ForceSigNextIter = 1 + + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings when changing VHDL constants and generics +; Default is 1 to generate warning messages +; WarnConstantChange = 0 + +; Turn off warnings from accelerated versions of the std_logic_arith, +; std_logic_unsigned, and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from accelerated versions of the IEEE numeric_std +; and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Use old-style (pre-6.6) VHDL FOR generate statement iteration names +; in the design hierarchy. +; This style is controlled by the value of the GenerateFormat +; value described next. Default is to use new-style names, which +; comprise the generate statement label, '(', the value of the generate +; parameter, and a closing ')'. +; Uncomment this to use old-style names. +; OldVhdlForGenNames = 1 + +; Enable changes in VHDL elaboration to allow for Variable Logging +; This trades off simulation performance for the ability to log variables +; efficiently. By default this is disable for maximum simulation performance +; VhdlVariableLogging = 1 + +; Control the format of the old-style VHDL FOR generate statement region +; name for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate statement label; the %d represents the generate parameter value +; at a particular iteration (this is the position number if the generate parameter +; is of an enumeration type). Embedded whitespace is allowed (but discouraged); +; leading and trailing whitespace is ignored. +; Application of the format must result in a unique region name over all +; loop iterations for a particular immediately enclosing scope so that name +; lookup can function properly. The default is %s__%d. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. +; Use custom gcc compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; DpiCppPath = /bin/gcc + +; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. +; The term "out-of-the-blue" refers to SystemVerilog export function calls +; made from C functions that don't have the proper context setup +; (as is the case when running under "DPI-C" import functions). +; When this is enabled, one can call a DPI export function +; (but not task) from any C code. +; the setting of this variable can be one of the following values: +; 0 : dpioutoftheblue call is disabled (default) +; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. +; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. +; DpiOutOfTheBlue = 1 + +; Specify whether continuous assignments are run before other normal priority +; processes scheduled in the same iteration. This event ordering minimizes race +; differences between optimized and non-optimized designs, and is the default +; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set +; ImmediateContinuousAssign to 0. +; The default is 1 (enabled). +; ImmediateContinuousAssign = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Which default VPI object model should the tool conform to? +; The 1364 modes are Verilog-only, for backwards compatibility with older +; libraries, and SystemVerilog objects are not available in these modes. +; +; In the absence of a user-specified default, the tool default is the +; latest available LRM behavior. +; Options for PliCompatDefault are: +; VPI_COMPATIBILITY_VERSION_1364v1995 +; VPI_COMPATIBILITY_VERSION_1364v2001 +; VPI_COMPATIBILITY_VERSION_1364v2005 +; VPI_COMPATIBILITY_VERSION_1800v2005 +; VPI_COMPATIBILITY_VERSION_1800v2008 +; +; Synonyms for each string are also recognized: +; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) +; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) +; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) +; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) +; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) + + +; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions +; DefaultRestartOptions = -force + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Specify whether or not a WLF file should be optimized during +; simulation. If set to 0, the WLF file will not be optimized. +; The default is 1, optimize the WLF file. +; WLFOptimize = 0 + +; Specify the name of the WLF file. +; The default is vsim.wlf +; WLFFilename = vsim.wlf + +; Specify whether to lock the WLF file. +; Locking the file prevents other invocations of ModelSim/Questa tools from +; inadvertently overwriting the WLF file. +; The default is 1, lock the WLF file. +; WLFFileLock = 0 + +; Specify the WLF reader cache size limit for each open WLF file. +; The size is giving in megabytes. A value of 0 turns off the +; WLF cache. +; WLFSimCacheSize allows a different cache size to be set for +; simulation WLF file independent of post-simulation WLF file +; viewing. If WLFSimCacheSize is not set it defaults to the +; WLFCacheSize setting. +; The default WLFCacheSize setting is enabled to 256M per open WLF file. +; WLFCacheSize = 2000 +; WLFSimCacheSize = 500 + +; Specify the WLF file event collapse mode. +; 0 = Preserve all events and event order. (same as -wlfnocollapse) +; 1 = Only record values of logged objects at the end of a simulator iteration. +; (same as -wlfcollapsedelta) +; 2 = Only record values of logged objects at the end of a simulator time step. +; (same as -wlfcollapsetime) +; The default is 1. +; WLFCollapseMode = 0 + +; Specify whether WLF file logging can use threads on multi-processor machines +; if 0, no threads will be used, if 1, threads will be used if the system has +; more than one processor +; WLFUseThreads = 1 + +; Turn on/off undebuggable SystemC type warnings. Default is on. +; ShowUndebuggableScTypeWarning = 0 + +; Turn on/off unassociated SystemC name warnings. Default is off. +; ShowUnassociatedScNameWarning = 1 + +; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. +; ScShowIeeeDeprecationWarnings = 1 + +; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. +; ScEnableScSignalWriteCheck = 1 + +; Set SystemC default time unit. +; Set to fs, ps, ns, us, ms, or sec with optional +; prefix of 1, 10, or 100. The default is 1 ns. +; The ScTimeUnit value is honored if it is coarser than Resolution. +; If ScTimeUnit is finer than Resolution, it is set to the value +; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, +; then the default time unit will be 1 ns. However if Resolution +; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. +ScTimeUnit = ns + +; Set SystemC sc_main stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends +; on the amount of data on the sc_main() stack and the memory required +; to succesfully execute the longest function call chain of sc_main(). +ScMainStackSize = 10 Mb + +; Turn on/off execution of remainder of sc_main upon quitting the current +; simulation session. If the cumulative length of sc_main() in terms of +; simulation time units is less than the length of the current simulation +; run upon quit or restart, sc_main() will be in the middle of execution. +; This switch gives the option to execute the remainder of sc_main upon +; quitting simulation. The drawback of not running sc_main till the end +; is memory leaks for objects created by sc_main. If on, the remainder of +; sc_main will be executed ignoring all delays. This may cause the simulator +; to crash if the code in sc_main is dependent on some simulation state. +; Default is on. +ScMainFinishOnQuit = 1 + +; Set the SCV relationship name that will be used to identify phase +; relations. If the name given to a transactor relation matches this +; name, the transactions involved will be treated as phase transactions +ScvPhaseRelationName = mti_phase + +; Customize the vsim kernel shutdown behavior at the end of the simulation. +; Some common causes of the end of simulation are $finish (implicit or explicit), +; sc_stop(), tf_dofinish(), and assertion failures. +; This should be set to "ask", "exit", or "stop". The default is "ask". +; "ask" -- In batch mode, the vsim kernel will abruptly exit. +; In GUI mode, a dialog box will pop up and ask for user confirmation +; whether or not to quit the simulation. +; "stop" -- Cause the simulation to stay loaded in memory. This can make some +; post-simulation tasks easier. +; "exit" -- The simulation will abruptly exit without asking for any confirmation. +; "final" -- Run SystemVerilog final blocks then behave as "stop". +; Note: This variable can be overridden with the vsim "-onfinish" command line switch. +OnFinish = ask + +; Print pending deferred assertion messages. +; Deferred assertion messages may be scheduled after the $finish in the same +; time step. Deferred assertions scheduled to print after the $finish are +; printed before exiting with severity level NOTE since it's not known whether +; the assertion is still valid due to being printed in the active region +; instead of the reactive region where they are normally printed. +; OnFinishPendingAssert = 1; + +; Print "simstats" result +; 0 == do not print simstats +; 1 == print at end of simulation +; 2 == print at end of run +; 3 == print at end of run and end of simulation +; default == 0 +; PrintSimStats = 1 + + +; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages +; AssertFile = assert.log + +; Enable assertion counts. Default is off. +; AssertionCover = 1 + +; Run simulator in assertion debug mode. Default is off. +; AssertionDebug = 1 + +; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. +; AssertionEnable = 0 + +; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionLimit = 1 + +; Turn on/off concurrent assertion pass log. Default is off. +; Assertion pass logging is only enabled when assertion is browseable +; and assertion debug is enabled. +; AssertionPassLog = 1 + +; Turn on/off PSL concurrent assertion fail log. Default is on. +; The flag does not affect SVA +; AssertionFailLog = 0 + +; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. +; AssertionFailLocalVarLog = 0 + +; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. +; 0 = Continue 1 = Break 2 = Exit +; AssertionFailAction = 1 + +; Enable the active thread monitor in the waveform display when assertion debug is enabled. +; AssertionActiveThreadMonitor = 1 + +; Control how many waveform rows will be used for displaying the active threads. Default is 5. +; AssertionActiveThreadMonitorLimit = 5 + +; Assertion thread limit after which assertion would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for an assertion go +; beyond this limit, the assertion would be either switched off or killed. This +; limit applies to only assert directives. +;AssertionThreadLimit = -1 + +; Action to be taken once the assertion thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only assert directives. +;AssertionThreadLimitAction = kill + +; Cover thread limit after which cover would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for a cover go +; beyond this limit, the cover would be either switched off or killed. This +; limit applies to only cover directives. +;CoverThreadLimit = -1 + +; Action to be taken once the cover thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only cover directives. +;CoverThreadLimitAction = kill + + +; By default immediate assertions do not participate in Assertion Coverage calculations +; unless they are executed. This switch causes all immediate assertions in the design +; to participate in Assertion Coverage calculations, whether attempted or not. +; UnattemptedImmediateAssertions = 0 + +; By default immediate covers participate in Coverage calculations +; whether they are attempted or not. This switch causes all unattempted +; immediate covers in the design to stop participating in Coverage +; calculations. +; UnattemptedImmediateCovers = 0 + +; By default pass action block is not executed for assertions on vacuous +; success. The following variable is provided to enable execution of +; pass action block on vacuous success. The following variable is only effective +; if the user does not disable pass action block execution by using either +; system tasks or CLI. Also there is a performance penalty for enabling +; the following variable. +;AssertionEnableVacuousPassActionBlock = 1 + +; As per strict 1850-2005 PSL LRM, an always property can either pass +; or fail. However, by default, Questa reports multiple passes and +; multiple fails on top always/never property (always/never operator +; is the top operator under Verification Directive). The reason +; being that Questa reports passes and fails on per attempt of the +; top always/never property. Use the following flag to instruct +; Questa to strictly follow LRM. With this flag, all assert/never +; directives will start an attempt once at start of simulation. +; The attempt can either fail, match or match vacuously. +; For e.g. if always is the top operator under assert, the always will +; keep on checking the property at every clock. If the property under +; always fails, the directive will be considered failed and no more +; checking will be done for that directive. A top always property, +; if it does not fail, will show a pass at end of simulation. +; The default value is '0' (i.e. zero is off). For example: +; PslOneAttempt = 1 + +; Specify the number of clock ticks to represent infinite clock ticks. +; This affects eventually!, until! and until_!. If at End of Simulation +; (EOS) an active strong-property has not clocked this number of +; clock ticks then neither pass or fail (vacuous match) is returned +; else respective fail/pass is returned. The default value is '0' (zero) +; which effectively does not check for clock tick condition. For example: +; PslInfinityThreshold = 5000 + +; Control how many thread start times will be preserved for ATV viewing for a given assertion +; instance. Default is -1 (ALL). +; ATVStartTimeKeepCount = -1 + +; Turn on/off code coverage +; CodeCoverage = 0 + +; Count all code coverage condition and expression truth table rows that match. +; CoverCountAll = 1 + +; Turn off automatic inclusion of VHDL integers in toggle coverage. Default +; is to include them. +; ToggleNoIntegers = 1 + +; Set the maximum number of values that are collected for toggle coverage of +; VHDL integers. Default is 100; +; ToggleMaxIntValues = 100 + +; Set the maximum number of values that are collected for toggle coverage of +; Verilog real. Default is 100; +; ToggleMaxRealValues = 100 + +; Turn on automatic inclusion of Verilog integers in toggle coverage, except +; for enumeration types. Default is to include them. +; ToggleVlogIntegers = 0 + +; Turn on automatic inclusion of Verilog real type in toggle coverage, except +; for shortreal types. Default is to not include them. +; ToggleVlogReal = 1 + +; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays +; and VHDL arrays-of-arrays in toggle coverage. +; Default is to not include them. +; ToggleFixedSizeArray = 1 + +; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, +; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. +; This leads to a longer simulation time with bigger arrays covered with toggle coverage. +; Default is 1024. +; ToggleMaxFixedSizeArray = 1024 + +; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized +; one-dimensional packed vectors for toggle coverage. Default is 0. +; TogglePackedAsVec = 0 + +; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for +; toggle coverage. Default is 0. +; ToggleVlogEnumBits = 0 + +; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. +; For unlimited width, set to 0. +; ToggleWidthLimit = 128 + +; Limit the counts that are tracked for toggle coverage. When all edges for a bit have +; reached this count, further activity on the bit is ignored. Default is 1. +; For unlimited counts, set to 0. +; ToggleCountLimit = 1 + +; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. +; Following is the toggle coverage calculation criteria based on extended toggle mode: +; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). +; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. +; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. +; ExtendedToggleMode = 3 + +; Enable toggle statistics collection only for ports. Default is 0. +; TogglePortsOnly = 1 + +; Turn on/off all PSL/SVA cover directive enables. Default is on. +; CoverEnable = 0 + +; Turn on/off PSL/SVA cover log. Default is off "0". +; CoverLog = 1 + +; Set "at_least" value for all PSL/SVA cover directives. Default is 1. +; CoverAtLeast = 2 + +; Set "limit" value for all PSL/SVA cover directives. Default is -1. +; Any positive integer, -1 for infinity. +; CoverLimit = 1 + +; Specify the coverage database filename. +; Default is "" (i.e. database is NOT automatically saved on close). +; UCDBFilename = vsim.ucdb + +; Specify the maximum limit for the number of Cross (bin) products reported +; in XML and UCDB report against a Cross. A warning is issued if the limit +; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this +; setting. +; MaxReportRhsSVCrossProducts = 1000 + +; Specify the override for the "auto_bin_max" option for the Covergroups. +; If not specified then value from Covergroup "option" is used. +; SVCoverpointAutoBinMax = 64 + +; Specify the override for the value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then value +; specified in the "option.cross_num_print_missing" is used. This +; is a runtime option. NOTE: This overrides any "cross_num_print_missing" +; value specified by user in source file and any SVCrossNumPrintMissingDefault +; specified in modelsim.ini. +; SVCrossNumPrintMissing = 0 + +; Specify whether to use the value of "cross_num_print_missing" +; option in report and GUI for the Cross in Covergroups. If not specified then +; cross_num_print_missing is ignored for creating reports and displaying +; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". +; UseSVCrossNumPrintMissing = 0 + +; Specify the threshold of Coverpoint wildcard bin value range size, above which +; a warning will be triggered. The default is 4K -- 12 wildcard bits. +; SVCoverpointWildCardBinValueSizeWarn = 4096 + +; Specify the override for the value of "strobe" option for the +; Covergroup Type. If not specified then value in "type_option.strobe" +; will be used. This is runtime option which forces "strobe" to +; user specified value and supersedes user specified values in the +; SystemVerilog Code. NOTE: This also overrides the compile time +; default value override specified using "SVCovergroupStrobeDefault" +; SVCovergroupStrobe = 0 + +; Override for explicit assignments in source code to "option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". +; SVCovergroupGoal = 100 + +; Override for explicit assignments in source code to "type_option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "type_option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". +; SVCovergroupTypeGoal = 100 + +; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() +; builtin functions, and report. This setting changes the default values of +; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 +; behavior if explicit assignments are not made on option.get_inst_coverage and +; type_option.merge_instances by the user. There are two vsim command line +; options, -cvg63 and -nocvg63 to override this setting from vsim command line. +; The default value of this variable from release 6.6 onwards is 0. This default +; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. +; SVCovergroup63Compatibility = 0 + +; Enforce the 6.5 default behavior of covergroup get_coverage() builtin +; functions, GUI, and report. This setting changes the default values of +; type_option.merge_instances to ensure the 6.5 default behavior if explicit +; assignments are not made on type_option.merge_instances by the user. +; There are two vsim command line options, -cvgmergeinstances and +; -nocvgmergeinstances to override this setting from vsim command line. +; The default value of this variable from release 6.6 onwards is 0. This default +; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. +; SvCovergroupMergeInstancesDefault = 1 + +; Enable or disable generation of more detailed information about the sampling +; of covergroup, cross, and coverpoints. It provides the details of the number +; of times the covergroup instance and type were sampled, as well as details +; about why covergroup, cross and coverpoint were not covered. A non-zero value +; is to enable this feature. 0 is to disable this feature. Default is 0 +; SVCovergroupSampleInfo = 0 + +; Specify the maximum number of Coverpoint bins in whole design for +; all Covergroups. +; MaxSVCoverpointBinsDesign = 2147483648 + +; Specify maximum number of Coverpoint bins in any instance of a Covergroup +; MaxSVCoverpointBinsInst = 2147483648 + +; Specify the maximum number of Cross bins in whole design for +; all Covergroups. +; MaxSVCrossBinsDesign = 2147483648 + +; Specify maximum number of Cross bins in any instance of a Covergroup +; MaxSVCrossBinsInst = 2147483648 + +; Specify a space delimited list of double quoted TCL style +; regular expressions which will be matched against the text of all messages. +; If any regular expression is found to be contained within any message, the +; status for that message will not be propagated to the UCDB TESTSTATUS. +; If no match is detected, then the status will be propagated to the +; UCDB TESTSTATUS. More than one such regular expression text is allowed, +; and each message text is compared for each regular expression in the list. +; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" + +; Set weight for all PSL/SVA cover directives. Default is 1. +; CoverWeight = 2 + +; Check vsim plusargs. Default is 0 (off). +; 0 = Don't check plusargs +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Run the 0in tools from within the simulator. +; Default is off. +; ZeroIn = 1 + +; Set the options to be passed to the 0in runtime tool. +; Default value set to "". +; ZeroInOptions = "" + +; Initial seed for the random number generator of the root thread (SystemVerilog). +; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. +; The default value is 0. +; Sv_Seed = 0 + +; Specify the solver "engine" that vsim will select for constrained random +; generation. +; Valid values are: +; "auto" - automatically select the best engine for the current +; constraint scenario +; "bdd" - evaluate all constraint scenarios using the BDD solver engine +; "act" - evaluate all constraint scenarios using the ACT solver engine +; While the BDD solver engine is generally efficient with constraint scenarios +; involving bitwise logical relationships, the ACT solver engine can exhibit +; superior performance with constraint scenarios involving large numbers of +; random variables related via arithmetic operators (+, *, etc). +; NOTE: This variable can be overridden with the vsim "-solveengine" command +; line switch. +; The default value is "auto". +; SolveEngine = auto + +; Specify if the solver should attempt to ignore overflow/underflow semantics +; for arithmetic constraints (multiply, addition, subtraction) in order to +; improve performance. The "solveignoreoverflow" attribute can be specified on +; a per-call basis to randomize() to override this setting. +; The default value is 0 (overflow/underflow is not ignored). Set to 1 to +; ignore overflow/underflow. +; SolveIgnoreOverflow = 0 + +; Specifies the maximum size that a dynamic array may be resized to by the +; solver. If the solver attempts to resize a dynamic array to a size greater +; than the specified limit, the solver will abort with an error. +; The default value is 2000. A value of 0 indicates no limit. +; SolveArrayResizeMax = 2000 + +; Error message severity when randomize() failure is detected (SystemVerilog). +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; The default is 0 (no error). +; SolveFailSeverity = 0 + +; Enable/disable debug information for randomize() failures. +; NOTE: This variable can be overridden with the vsim "-solvefaildbug" command +; line switch. +; The default is 0 (disabled). Set to 1 to enable. +; SolveFailDebug = 0 + +; Specify the maximum size of the solution graph generated by the BDD solver. +; This value can be used to force the BDD solver to abort the evaluation of a +; complex constraint scenario that cannot be evaluated with finite memory. +; This value is specified in 1000s of nodes. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxSize = 10000 + +; Specify the maximum number of evaluations that may be performed on the +; solution graph by the BDD solver. This value can be used to force the BDD +; solver to abort the evaluation of a complex constraint scenario that cannot +; be evaluated in finite time. This value is specified in 10000s of evaluations. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxEval = 10000 + +; Specify the maximum number of tests that the ACT solver may evaluate before +; abandoning an attempt to solve a particular constraint scenario. +; The default value is 20000000. A value of 0 indicates no limit. +; SolveACTMaxTests = 20000000 + +; Specify the maximum number of operations that the ACT solver may perform +; before abandoning an attempt to solve a particular constraint scenario. The +; value is specified in 1000000s of operations. The default value is 1000. A +; value of 0 indicates no limit. +; SolveACTMaxOps = 1000 + +; Specify the number of times the ACT solver will retry to evaluate a constraint +; scenario that fails due to the SolveACTMaxTests threshold. +; The default value is 0 (no retry). +; SolveACTRetryCount = 0 + +; SolveSpeculateLevel controls whether or not the solver performs speculation +; during the evaluation of a constraint scenario. +; Speculation is an attempt to partition complex constraint scenarios by +; choosing a 'speculation' subset of the variables and constraints. This +; 'speculation' set is solved independently of the remaining constraints. +; The solver then attempts to solve the remaining variables and constraints +; (the 'dependent' set). If this attempt fails, the solver backs up and +; re-solves the 'speculation' set, then retries the 'dependent' set. +; Valid values are: +; 0 - no speculation +; 1 - enable speculation that maintains LRM specified distribution +; 2 - enable other speculation - may yield non-LRM distribution +; Currently, distribution constraints and solve-before constraints are +; used in selecting the 'speculation' sets for speculation level 1. Non-LRM +; compliant speculation includes random variables in condition expressions. +; The default value is 0. +; SolveSpeculateLevel = 0 + +; By default, when speculation is enabled, the solver first tries to solve a +; constraint scenario *without* speculation. If the solver fails to evaluate +; the constraint scenario (due to time/memory limits) then the solver will +; re-evaluate the constraint scenario with speculation. If SolveSpeculateFirst +; is set to 1, the solver will skip the initial non-speculative attempt to +; evaluate the constraint scenario. (Only applies when SolveSpeculateLevel is +; non-zero) +; The default value is 0. +; SolveSpeculateFirst = 0 + +; Specify the maximum bit width of a variable in a conditional expression that +; may be considered as the basis for "conditional" speculation. (Only applies +; when SolveSpeculateLevel=2) +; The default value is 6. +; SolveSpeculateMaxCondWidth = 6 + +; Specify the maximum number of attempts to solve a speculative set of random +; variables and constraints. Exceeding this limit will cause the solver to +; abandon the current speculative set. (Only applies when SolveSpeculateLevel +; is non-zero) +; The default value is 100. +; SolveSpeculateMaxIterations = 100 + +; Specifies whether to attempt speculation on solve-before constraints or +; distribution constraints first. A value of 0 specifies that solve-before +; constraints are attempted first as the basis for speculative randomization. +; A value of 1 specifies that distribution constraints are attempted first +; as the basis for speculative randomization. +; The default value is 0. +; SolveSpeculateDistFirst = 0 + +; If the non-speculative BDD solver fails to evaluate a constraint scenario +; (due to time/memory limits) then the solver can be instructed to automatically +; re-evaluate the constraint scenario with the ACT solver engine. Set +; SolveACTbeforeSpeculate to 1 to enable this feature. +; The default value is 0 (do not re-evaluate with the ACT solver). +; SolveACTbeforeSpeculate = 0 + +; Use SolveFlags to specify options that will guide the behavior of the +; constraint solver. These options may improve the performance of the +; constraint solver for some testcases, and decrease the performance of the +; constraint solver for others. +; Valid flags are: +; i = disable bit interleaving for >, >=, <, <= constraints (BDD engine) +; n = disable bit interleaving for all constraints (BDD engine) +; r = reverse bit interleaving (BDD engine) +; The default value is "" (no options). +; SolveFlags = + +; Specify random sequence compatiblity with a prior letter release. This +; option is used to get the same random sequences during simulation as +; as a prior letter release. Only prior letter releases (of the current +; number release) are allowed. +; NOTE: Only those random sequence changes due to solver optimizations are +; reverted by this variable. Random sequence changes due to solver bugfixes +; cannot be un-done. +; NOTE: This variable can be overridden with the vsim "-solverev" command +; line switch. +; Default value set to "" (no compatibility). +; SolveRev = + +; Environment variable expansion of command line arguments has been depricated +; in favor shell level expansion. Universal environment variable expansion +; inside -f files is support and continued support for MGC Location Maps provide +; alternative methods for handling flexible pathnames. +; The following line may be uncommented and the value set to 1 to re-enable this +; deprecated behavior. The default value is 0. +; DeprecatedEnvironmentVariableExpansion = 0 + +; Turn on/off collapsing of bus ports in VCD dumpports output +DumpportsCollapse = 1 + +; Location of Multi-Level Verification Component (MVC) installation. +; The default location is the product installation directory. +; MvcHome = $MODEL_TECH/... + +; Initialize SystemVerilog enums using the base type's default value +; instead of the leftmost value. +; EnumBaseInit = 1 + +[lmc] +; The simulator's interface to Logic Modeling's SmartModel SWIFT software +libsm = $MODEL_TECH/libsm.sl +; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) +; libsm = $MODEL_TECH/libsm.dll +; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) +; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl +; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) +; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o +; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) +; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Windows NT) +; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll +; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/linux.lib/libswift.so + +; The simulator's interface to Logic Modeling's hardware modeler SFI software +libhm = $MODEL_TECH/libhm.sl +; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) +; libhm = $MODEL_TECH/libhm.dll +; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) +; libsfi = /lib/hp700/libsfi.sl +; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) +; libsfi = /lib/rs6000/libsfi.a +; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) +; libsfi = /lib/sun4.solaris/libsfi.so +; Logic Modeling's hardware modeler SFI software (Windows NT) +; libsfi = /lib/pcnt/lm_sfi.dll +; Logic Modeling's hardware modeler SFI software (Linux) +; libsfi = /lib/linux/libsfi.so + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; suppress can be used to achieve +nowarn functionality +; The format is: suppress = ,,[,,...] +; Examples: +suppress = 8780 +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; suppress = 3009,CNNODP,3043,TFMPC +; suppress = 8683,8684 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of Verilog display system task messages and +; PLI/FLI print function call messages. The system tasks include +; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They +; also include the analogous file I/O tasks that write to STDOUT +; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, +; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default +; is to have messages appear only in the transcript. The other +; settings are to send messages to the wlf file only (messages that +; are recorded in the wlf file can be viewed in the MsgViewer) or +; to both the transcript and the wlf file. The valid values are +; tran {transcript only (default)} +; wlf {wlf file only} +; both {transcript and wlf file} +; displaymsgmode = tran + +; Control transcripting of elaboration/runtime messages not +; addressed by the displaymsgmode setting. The default is to +; have messages appear in the transcript and recorded in the wlf +; file (messages that are recorded in the wlf file can be viewed +; in the MsgViewer). The other settings are to send messages +; only to the transcript or only to the wlf file. The valid +; values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both +[Project] +; Warning -- Do not edit the project properties directly. +; Property names are dynamic in nature and property +; values have special syntax. Changing property data directly +; can result in a corrupt MPF file. All project properties +; can be modified through project window dialogs. +Project_Version = 6 +Project_DefaultLib = work +Project_SortMethod = unused +Project_Files_Count = 13 +Project_File_0 = /d/jspc22/trb/cvs/trbnet/trb_net_components.vhd +Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1343057812 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 11 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_1 = /d/jspc22/trb/cvs/trb3/wasa/source/pwm.vhd +Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344343677 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 4 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_2 = /d/jspc22/trb/cvs/trb3/wasa/source/tb/full_tb.vhd +Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344350435 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 7 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_3 = /d/jspc22/trb/cvs/trb3/wasa/source/spi_slave.vhd +Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344350118 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_4 = /d/jspc22/trb/cvs/trb3/wasa/version.vhd +Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1342609010 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_5 = /d/jspc22/trb/cvs/trb3/base/trb3_components.vhd +Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344271888 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 9 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_6 = /d/jspc22/trb/cvs/trb3/wasa/panda_dirc_wasa.vhd +Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344343599 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 0 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_7 = /d/jspc22/trb/cvs/trbnet/trb_net_std.vhd +Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1308757058 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_8 = /d/jspc22/trb/cvs/trb3/wasa/source/tb/pwm_tb.vhd +Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344272681 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_9 = /d/jspc22/trb/cvs/trbnet/trb_net_onewire.vhd +Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344350049 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 12 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_10 = /d/jspc22/trb/cvs/trbnet/special/spi_ltc2600.vhd +Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1339672931 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_11 = /d/jspc22/trb/cvs/trb3/wasa/cores/flash.vhd +Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1343999155 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_12 = /d/jspc22/trb/cvs/trb3/wasa/cores/oddr16.vhd +Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344002544 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_Sim_Count = 0 +Project_Folder_Count = 0 +Echo_Compile_Output = 0 +Save_Compile_Report = 1 +Project_Opt_Count = 0 +ForceSoftPaths = 0 +ProjectStatusDelay = 5000 +VERILOG_DoubleClick = Edit +VERILOG_CustomDoubleClick = +SYSTEMVERILOG_DoubleClick = Edit +SYSTEMVERILOG_CustomDoubleClick = +VHDL_DoubleClick = Edit +VHDL_CustomDoubleClick = +PSL_DoubleClick = Edit +PSL_CustomDoubleClick = +TEXT_DoubleClick = Edit +TEXT_CustomDoubleClick = +SYSTEMC_DoubleClick = Edit +SYSTEMC_CustomDoubleClick = +TCL_DoubleClick = Edit +TCL_CustomDoubleClick = +MACRO_DoubleClick = Edit +MACRO_CustomDoubleClick = +VCD_DoubleClick = Edit +VCD_CustomDoubleClick = +SDF_DoubleClick = Edit +SDF_CustomDoubleClick = +XML_DoubleClick = Edit +XML_CustomDoubleClick = +LOGFILE_DoubleClick = Edit +LOGFILE_CustomDoubleClick = +UCDB_DoubleClick = Edit +UCDB_CustomDoubleClick = +UPF_DoubleClick = Edit +UPF_CustomDoubleClick = +PCF_DoubleClick = Edit +PCF_CustomDoubleClick = +PROJECT_DoubleClick = Edit +PROJECT_CustomDoubleClick = +Project_Major_Version = 10 +Project_Minor_Version = 0 diff --git a/wasa/source/.cvsignore b/wasa/source/.cvsignore new file mode 100644 index 0000000..c36ae2e --- /dev/null +++ b/wasa/source/.cvsignore @@ -0,0 +1,12 @@ +*.log +*.rpt +stdout.log +workdir +version.vhd +*.jhd +*.naf +*.sort +*.srp +*.sym +*tmpl.vhd +*.log diff --git a/wasa/source/pwm.vhd b/wasa/source/pwm.vhd new file mode 100644 index 0000000..b773a8d --- /dev/null +++ b/wasa/source/pwm.vhd @@ -0,0 +1,59 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + + +entity pwm_generator is + port( + CLK : in std_logic; + + DATA_IN : in std_logic_vector(15 downto 0) := (others => '0'); + DATA_OUT : out std_logic_vector(15 downto 0); + WRITE_IN : in std_logic := '0'; + ADDR_IN : in std_logic_vector(3 downto 0) := (others => '0'); + + PWM : out std_logic_vector(31 downto 0) + + ); +end entity; + + + +architecture pwm_arch of pwm_generator is + +type ram_t is array(0 to 15) of unsigned(16 downto 0); +signal set : ram_t := (others => (others => '0')); + +type cnt_t is array(0 to 15) of unsigned(16 downto 0); +signal cnt : cnt_t := (others => (others => '0')); + +signal last_flag : std_logic_vector(15 downto 0) := (others => '0'); +signal flag : std_logic_vector(15 downto 0) := (others => '0'); +signal pwm_i : std_logic_vector(15 downto 0) := (others => '0'); + + +begin + +PROC_MEM : process begin + wait until rising_edge(CLK); + if WRITE_IN = '1' then + set(to_integer(unsigned(ADDR_IN)))(16) <= '0'; + set(to_integer(unsigned(ADDR_IN)))(15 downto 0) <= unsigned(DATA_IN); + end if; + DATA_OUT <= std_logic_vector(set(to_integer(unsigned(ADDR_IN)))(15 downto 0)); +end process; + + +gen_channels : for i in 0 to 15 generate + flag(i) <= cnt(i)(16); + last_flag(i) <= flag(i) when rising_edge(CLK); + pwm_i(i) <= (last_flag(i) xor flag(i)) when rising_edge(CLK); + cnt(i) <= cnt(i) + set(i) when rising_edge(CLK); +end generate; + + +PWM(31 downto 16) <= pwm_i(15 downto 0); --no high-res yet +PWM(15 downto 0 ) <= pwm_i(15 downto 0); + +end architecture; \ No newline at end of file diff --git a/wasa/source/spi_slave.vhd b/wasa/source/spi_slave.vhd new file mode 100644 index 0000000..dfcd009 --- /dev/null +++ b/wasa/source/spi_slave.vhd @@ -0,0 +1,152 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.version.all; + +library machxo2; +use machxo2.all; + + +entity spi_slave is + port( + CLK : in std_logic; + + SPI_CLK : in std_logic; + SPI_CS : in std_logic; + SPI_IN : in std_logic; + SPI_OUT : out std_logic; + + DATA_OUT : out std_logic_vector(15 downto 0); + REG00_IN : in std_logic_vector(15 downto 0); + REG10_IN : in std_logic_vector(15 downto 0); + REG20_IN : in std_logic_vector(15 downto 0); + REG40_IN : in std_logic_vector(15 downto 0); + + OPERATION_OUT : out std_logic_vector(3 downto 0); + CHANNEL_OUT : out std_logic_vector(7 downto 0); + WRITE_OUT : out std_logic_vector(15 downto 0); + + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end entity; + + + +architecture spi_slave_arch of spi_slave is +signal spi_clk_last : std_logic; +signal spi_clk_reg : std_logic; +signal spi_cs_reg : std_logic; +signal spi_in_reg : std_logic; + +signal input : std_logic_vector(31 downto 0); +signal output_data : std_logic_vector(31 downto 0); +signal data_write : std_logic_vector(15 downto 0); +signal write_i : std_logic_vector(15 downto 0) := x"0000"; +signal last_input : std_logic; +signal bitcnt : integer range 0 to 31 := 31; + +signal next_output : std_logic; +signal operation_i : std_logic_vector(3 downto 0) := x"0"; +signal channel_i : std_logic_vector(7 downto 0) := x"00"; + +type state_t is (IDLE, WAIT_FOR_CMD, GET_DATA, PREPARE_OUTPUT, WRITE_DATA, WAIT_FINISH); +signal state : state_t; + +begin + +spi_clk_last <= spi_clk_reg when rising_edge(CLK); +spi_clk_reg <= SPI_CLK when rising_edge(CLK); +spi_cs_reg <= SPI_CS when rising_edge(CLK); +spi_in_reg <= SPI_IN when rising_edge(CLK); + +OPERATION_OUT <= operation_i; +CHANNEL_OUT <= channel_i; +DATA_OUT <= data_write; +WRITE_OUT <= write_i; + +PROC_OUTPUT : process begin + wait until rising_edge(CLK); + next_output <= output_data(bitcnt); + if spi_clk_reg = '0' and spi_clk_last = '1' then + SPI_OUT <= last_input; + if operation_i = x"8" and bitcnt <= 15 then + SPI_OUT <= next_output; + end if; + end if; +end process; + + +PROC_INPUT_SHIFT : process begin + wait until rising_edge(CLK); + if spi_cs_reg = '1' then + bitcnt <= 31; + else + if spi_clk_reg = '1' and spi_clk_last = '0' then + if bitcnt /= 0 then + bitcnt <= bitcnt - 1; + else + bitcnt <= 31; + end if; + last_input <= spi_in_reg; + input(bitcnt) <= spi_in_reg; + end if; + end if; +end process; + + +PROC_GEN_SIGNALS : process begin + wait until rising_edge(CLK); + write_i <= (others => '0'); + case state is + when IDLE => + operation_i <= x"F"; + if spi_cs_reg = '0' then + state <= WAIT_FOR_CMD; + end if; + when WAIT_FOR_CMD => + if bitcnt = 15 then + operation_i <= input(23 downto 20); + channel_i <= input(27 downto 24) & input(19 downto 16); + state <= GET_DATA; + end if; + when GET_DATA => + state <= PREPARE_OUTPUT; + when PREPARE_OUTPUT => + if input(31 downto 28) = x"0" then + output_data(15 downto 0) <= REG00_IN; + elsif input(31 downto 28) = x"1" then + output_data(15 downto 0) <= REG10_IN; + elsif input(31 downto 28) = x"2" then + output_data(15 downto 0) <= REG20_IN; + else + output_data(15 downto 0) <= REG40_IN; + end if; + state <= WRITE_DATA; + when WRITE_DATA => + if bitcnt = 31 then + if operation_i(3) = '0' then + data_write <= input(15 downto 0); + write_i(to_integer(unsigned(input(31 downto 28)))) <= '1'; + end if; + state <= WAIT_FINISH; + end if; + when WAIT_FINISH => + if spi_cs_reg = '1' then + state <= IDLE; + end if; + end case; + + if spi_cs_reg = '1' then + state <= IDLE; + operation_i <= x"F"; + end if; +end process; + + + +end architecture; \ No newline at end of file diff --git a/wasa/source/tb/.cvsignore b/wasa/source/tb/.cvsignore new file mode 100644 index 0000000..c36ae2e --- /dev/null +++ b/wasa/source/tb/.cvsignore @@ -0,0 +1,12 @@ +*.log +*.rpt +stdout.log +workdir +version.vhd +*.jhd +*.naf +*.sort +*.srp +*.sym +*tmpl.vhd +*.log diff --git a/wasa/source/tb/full_tb.vhd b/wasa/source/tb/full_tb.vhd new file mode 100644 index 0000000..978ffbe --- /dev/null +++ b/wasa/source/tb/full_tb.vhd @@ -0,0 +1,175 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + + + +entity tb is +end entity; + + + +architecture full_tb of tb is + +signal clk, reset : std_logic := '1'; + +signal spi_clk, spi_in, spi_out : std_logic; + +signal spi_cs : std_logic_vector(15 downto 0) := x"ffff"; +signal bus_addr : std_logic_vector( 4 downto 0) := "00000"; +signal bus_data : std_logic_vector(31 downto 0) := (others => '0'); +signal bus_write: std_logic := '0'; + +component spi_ltc2600 is + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + BUS_READ_IN : in std_logic; + BUS_WRITE_IN : in std_logic; + BUS_BUSY_OUT : out std_logic; + BUS_ACK_OUT : out std_logic; + BUS_ADDR_IN : in std_logic_vector(4 downto 0); + BUS_DATA_IN : in std_logic_vector(31 downto 0); + BUS_DATA_OUT : out std_logic_vector(31 downto 0); + -- SPI connections + SPI_CS_OUT : out std_logic_vector(15 downto 0); + SPI_SDI_IN : in std_logic; + SPI_SDO_OUT : out std_logic; + SPI_SCK_OUT : out std_logic + ); +end component; + + +component panda_dirc_wasa is + port( + CON : out std_logic_vector(16 downto 1); + INP : in std_logic_vector(16 downto 1); + PWM : out std_logic_vector(16 downto 1); + SPARE_LINE : out std_logic_vector(5 downto 0); + LED_GREEN : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_YELLOW : out std_logic; + SPI_CLK : in std_logic; + SPI_CS : in std_logic; + SPI_IN : in std_logic; + SPI_OUT : out std_logic; + TEMP_LINE : inout std_logic; + TEST_LINE : out std_logic_vector(15 downto 0) + ); +end component; + +begin + +clk <= not clk after 5 ns; +reset <= '0' after 30 ns; + +process begin + wait for 101 ns; + bus_addr <= "00000"; + bus_data <= x"0010abcd"; + bus_write <= '1'; + wait for 10 ns; + bus_write <= '0'; + + wait for 101 ns; + bus_addr <= "10000"; + bus_data <= x"00000001"; + bus_write <= '1'; + wait for 10 ns; + bus_write <= '0'; + + wait for 101 ns; + bus_addr <= "10001"; + bus_data <= x"00000001"; + bus_write <= '1'; + wait for 10 ns; + bus_write <= '0'; + + wait for 10010 ns; + bus_addr <= "00000"; + bus_data <= x"0013cd46"; + bus_write <= '1'; + wait for 10 ns; + bus_write <= '0'; + + wait for 101 ns; + bus_addr <= "10000"; + bus_data <= x"00000001"; + bus_write <= '1'; + wait for 10 ns; + bus_write <= '0'; + + wait for 101 ns; + bus_addr <= "10001"; + bus_data <= x"00000001"; + bus_write <= '1'; + wait for 10 ns; + bus_write <= '0'; + + wait for 10010 ns; + bus_addr <= "00000"; + bus_data <= x"0080ffff"; + bus_write <= '1'; + wait for 10 ns; + bus_write <= '0'; + + wait for 101 ns; + bus_addr <= "10000"; + bus_data <= x"00000001"; + bus_write <= '1'; + wait for 10 ns; + bus_write <= '0'; + + wait for 101 ns; + bus_addr <= "10001"; + bus_data <= x"00000001"; + bus_write <= '1'; + wait for 10 ns; + bus_write <= '0'; + wait; +end process; + +PWM : panda_dirc_wasa + port map( + CON => open, + INP => (others => '0'), + PWM => open, + SPARE_LINE => open, + LED_GREEN => open, + LED_ORANGE => open, + LED_RED => open, + LED_YELLOW => open, + SPI_CLK => spi_clk, + SPI_CS => spi_cs(0), + SPI_IN => spi_in, + SPI_OUT => spi_out, + TEMP_LINE => open, + TEST_LINE => open + ); + + +THE_SPI : spi_ltc2600 + port map( + CLK_IN => clk, + RESET_IN => reset, + -- Slave bus + BUS_READ_IN => '0', + BUS_WRITE_IN => bus_write, + BUS_BUSY_OUT => open, + BUS_ACK_OUT => open, + BUS_ADDR_IN => bus_addr, + BUS_DATA_IN => bus_data, + BUS_DATA_OUT => open, + -- SPI connections + SPI_CS_OUT => spi_cs, + SPI_SDI_IN => spi_out, + SPI_SDO_OUT => spi_in, + SPI_SCK_OUT => spi_clk + ); + + + +end architecture; \ No newline at end of file diff --git a/wasa/source/tb/pwm_tb.vhd b/wasa/source/tb/pwm_tb.vhd new file mode 100644 index 0000000..3858640 --- /dev/null +++ b/wasa/source/tb/pwm_tb.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + + + +entity tb is +end entity; + + + +architecture arch of tb is + +signal clk : std_logic := '1'; + +signal data : std_logic_vector(15 downto 0) := (others => '0'); +signal write : std_logic := '0'; +signal addr : std_logic_vector(3 downto 0) := (others => '0'); + + + +component pwm_generator is + port( + CLK : in std_logic; + + DATA_IN : in std_logic_vector(15 downto 0); + DATA_OUT : out std_logic_vector(15 downto 0); + WRITE_IN : in std_logic; + ADDR_IN : in std_logic_vector(3 downto 0); + + PWM : out std_logic_vector(31 downto 0) + + ); +end component; + +begin + +clk<= not clk after 5 ns; + + + + +process begin + wait for 101 ns; + data <= x"6234"; + write <= '1'; + addr <= x"0"; + wait for 10 ns; + write <= '0'; + wait; +end process; + +PWM : pwm_generator + port map( + CLK => clk, + DATA_IN => data, + DATA_OUT => open, + WRITE_IN => write, + ADDR_IN => addr, + PWM => open + ); + + +end architecture; \ No newline at end of file -- 2.43.0