From a3e9b483b4a6c3a030cd0fe9dec6891f54ce1aa9 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 13 Apr 2011 22:48:05 +0000 Subject: [PATCH] *** empty log message *** --- gbe_ecp2m/trb_net16_gbe_buf.vhd | 7 +- gbe_ecp2m/trb_net16_gbe_frame_constr.vhd | 38 +++++- gbe_ecp2m/trb_net16_gbe_packet_constr.vhd | 139 +++++++++++++++++----- gbe_ecp2m/trb_net16_gbe_setup.vhd | 15 ++- gbe_ecp2m/trb_net16_ipu2gbe.vhd | 129 ++++++++++++++++++-- gbe_ecp2m/trb_net_gbe_components.vhd | 2 + 6 files changed, 284 insertions(+), 46 deletions(-) diff --git a/gbe_ecp2m/trb_net16_gbe_buf.vhd b/gbe_ecp2m/trb_net16_gbe_buf.vhd index ad46d18..a8f68b8 100755 --- a/gbe_ecp2m/trb_net16_gbe_buf.vhd +++ b/gbe_ecp2m/trb_net16_gbe_buf.vhd @@ -460,6 +460,9 @@ signal monitor_empty : std_logic_vector(31 downto 0); -- gk 07.10.10 signal pc_eos : std_logic; +-- gk 09.12.10 +signal frame_delay : std_logic_vector(31 downto 0); + begin stage_ctrl_regs <= STAGE_CTRL_REGS_IN; @@ -512,6 +515,7 @@ port map( GBE_READOUT_CTR_VALID_OUT => readout_ctr_valid, -- gk 26.04.10 GBE_DELAY_OUT => pc_delay, GBE_ALLOW_LARGE_OUT => allow_large, -- gk 21.07.10 + GBE_FRAME_DELAY_OUT => frame_delay, -- gk 09.12.10 -- gk 28.07.10 MONITOR_BYTES_IN => bytes_sent_ctr, MONITOR_SENT_IN => monitor_sent, @@ -671,7 +675,6 @@ port map( -- ports for user logic RESET => RESET, CLK => CLK, - MULT_EVT_ENABLE_IN => use_multievents, -- gk 06.10.10 PC_WR_EN_IN => pc_wr_en, PC_DATA_IN => pc_data, PC_READY_OUT => pc_ready, @@ -687,6 +690,7 @@ port map( PC_QUEUE_DEC_IN => pc_queue_dec, PC_MAX_FRAME_SIZE_IN => pc_max_frame_size, PC_DELAY_IN => pc_delay, -- gk 28.04.10 + MULT_EVT_ENABLE_IN => use_multievents, -- gk 06.10.10 -- NEW PORTS FC_WR_EN_OUT => fc_wr_en, FC_DATA_OUT => fc_data, @@ -759,6 +763,7 @@ port map( FLAGS_OFFSET_IN => fc_flags_offset, TTL_IN => fc_ttl, PROTOCOL_IN => fc_protocol, + FRAME_DELAY_IN => frame_delay, -- gk 09.12.10 -- ports for packetTransmitter RD_CLK => serdes_clk_125, FT_DATA_OUT => ft_data, diff --git a/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd b/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd index 5d554d9..4a7a56f 100755 --- a/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd +++ b/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd @@ -36,6 +36,7 @@ port( FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0); TTL_IN : in std_logic_vector(7 downto 0); PROTOCOL_IN : in std_logic_vector(7 downto 0); + FRAME_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 09.12.10 -- ports for packetTransmitter RD_CLK : in std_logic; -- 125MHz clock!!! FT_DATA_OUT : out std_logic_vector(8 downto 0); @@ -78,7 +79,7 @@ attribute sys_encoding : string; type constructStates is (IDLE, DEST_MAC_ADDR, SRC_MAC_ADDR, FRAME_TYPE_S, VERSION, TOS_S, IP_LENGTH, IDENT, FLAGS, TTL_S, PROTO, HEADER_CS, SRC_IP_ADDR, DEST_IP_ADDR, SRC_PORT, DEST_PORT, UDP_LENGTH, - UDP_CS, SAVE_DATA, CLEANUP); + UDP_CS, SAVE_DATA, CLEANUP, DELAY); signal constructCurrentState, constructNextState : constructStates; signal bsm_constr : std_logic_vector(7 downto 0); attribute sys_encoding of constructCurrentState: signal is "safe,gray"; @@ -113,6 +114,10 @@ signal ip_cs_temp_right : std_logic_vector(15 downto 0); -- gk 29.03.10 signal fpf_reset : std_logic; -- gk 01.01.01 +-- gk 09.12.10 +signal delay_ctr : std_logic_vector(31 downto 0); +signal frame_delay_reg : std_logic_vector(31 downto 0); + begin -- Fakes @@ -228,7 +233,7 @@ begin end process constructMachineProc; --find next state of construct machine -constructMachine: process( constructCurrentState, START_OF_DATA_IN, END_OF_DATA_IN, headers_int_counter, put_udp_headers, CUR_MAX ) +constructMachine: process( constructCurrentState, START_OF_DATA_IN, END_OF_DATA_IN, headers_int_counter, put_udp_headers, CUR_MAX, delay_ctr, FRAME_DELAY_IN ) begin constructNextState <= constructCurrentState; if( headers_int_counter = cur_max ) then --can be checked everytime - if not in use, counter and cur_max are 0 @@ -280,13 +285,36 @@ begin constructNextState <= CLEANUP; end if; when CLEANUP => - constructNextState <= IDLE; + constructNextState <= DELAY; -- gk 10.12.10 IDLE; + + -- gk 09.12.10 + when DELAY => + if (delay_ctr = FRAME_DELAY_IN) then + constructNextState <= IDLE; + else + constructNextState <= DELAY; + end if; + when others => constructNextState <= IDLE; end case; end if; end process constructMachine; +-- gk 09.12.10 +delayCtrProc : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') or (constructCurrentState = IDLE) or (constructCurrentState = CLEANUP) then + delay_ctr <= (others => '0'); + elsif (constructCurrentState = DELAY) then + delay_ctr <= delay_ctr + x"1"; + end if; + + frame_delay_reg <= FRAME_DELAY_IN; + end if; +end process delayCtrProc; + bsmConstrProc : process(constructCurrentState) begin @@ -312,6 +340,7 @@ begin when UDP_CS => cur_max <= 1; bsm_constr <= x"12"; when SAVE_DATA => cur_max <= 0; bsm_constr <= x"13"; when CLEANUP => cur_max <= 0; bsm_constr <= x"14"; + when DELAY => cur_max <= 0; bsm_constr <= x"15"; when others => cur_max <= 0; bsm_constr <= x"1f"; end case; end process; @@ -350,7 +379,7 @@ fpfWrEnProc : process(constructCurrentState, WR_EN_IN, RESET, LINK_OK_IN) begin if (RESET = '1') or (LINK_OK_IN = '0') then -- gk 01.10.10 fpf_wr_en <= '0'; - elsif (constructCurrentState /= IDLE) and (constructCurrentState /= CLEANUP) and (constructCurrentState /= SAVE_DATA) then + elsif (constructCurrentState /= IDLE) and (constructCurrentState /= CLEANUP) and (constructCurrentState /= SAVE_DATA) and (constructCurrentState /= DELAY) then fpf_wr_en <= '1'; elsif (constructCurrentState = SAVE_DATA) and (WR_EN_IN = '1') then fpf_wr_en <= '1'; @@ -385,6 +414,7 @@ begin when UDP_CS => fpf_data <= udp_checksum(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8); when SAVE_DATA => fpf_data <= DATA_IN; when CLEANUP => fpf_data <= x"ab"; + when DELAY => fpf_data <= x"ac"; when others => fpf_data <= x"00"; end case; end process fpfDataProc; diff --git a/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd b/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd index 1102f44..ba2f4da 100755 --- a/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd +++ b/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd @@ -28,6 +28,8 @@ port( PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); -- DO NOT SWAP PC_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 28.04.10 + MULT_EVT_ENABLE_IN : in std_logic; -- gk 08.11.10 + PC_END_OF_SUB_IN : in std_logic; -- gk 08.10.11 -- FrameConstructor ports FC_WR_EN_OUT : out std_logic; FC_DATA_OUT : out std_logic_vector(7 downto 0); @@ -66,7 +68,8 @@ port ( end component; -- FIFO for SubEventHeader information -component fifo_2048x8 is +-- gk 06.12.10 component fifo_2048x8 is +component fifo_16kx8 is port ( Data : in std_logic_vector(7 downto 0); WrClock : in std_logic; @@ -148,6 +151,14 @@ signal ticks_ctr : std_logic_vector(7 downto 0); -- gk 28.04.10 signal load_eod : std_logic; signal load_eod_q : std_logic; +-- gk 08.11.11 +signal df_eod : std_logic; + +-- gk 04.12.10 +signal first_sub_in_multi : std_logic; +signal from_divide_state : std_logic; +signal disable_prep : std_logic; + begin -- Fakes @@ -184,7 +195,7 @@ end process; DATA_FIFO : fifo_64kx9 port map( Data(7 downto 0) => PC_DATA_IN, - Data(8) => PC_END_OF_DATA_IN, + Data(8) => df_eod, --PC_END_OF_DATA_IN, -- gk 08.11.10 WrClock => CLK, RdClock => CLK, WrEn => df_wr_en, @@ -197,6 +208,11 @@ port map( Full => df_full ); +-- gk 08.11.10 +df_eod <= '1' when ((MULT_EVT_ENABLE_IN = '0') and (PC_END_OF_DATA_IN = '1')) + or ((MULT_EVT_ENABLE_IN = '1') and (PC_END_OF_SUB_IN = '1')) + else '0'; + LOAD_EOD_PROC : process(CLK) begin if rising_edge(CLK) then @@ -239,7 +255,9 @@ begin case constructCurrentState is when CIDLE => constr_state <= x"0"; - if( PC_WR_EN_IN = '1' ) then + --if( PC_WR_EN_IN = '1' ) then + -- gk 04.12.10 + if (PC_START_OF_SUB_IN = '1') then constructNextState <= SAVE_DATA; else constructNextState <= CIDLE; @@ -286,7 +304,6 @@ begin end if; end process queueSizeProc; - --*********************** -- LOAD DATA COMBINED WITH HEADERS INTO FC, QUEUE TRANSMISSION --*********************** @@ -347,25 +364,44 @@ begin when PREP_DATA => load_state <= x"5"; loadNextState <= LOAD_DATA; +-- when LOAD_DATA => +-- load_state <= x"6"; +-- if (bytes_loaded = max_frame_size - 1) then +-- loadNextState <= DIVIDE; +-- -- gk 26.07.10 +-- -- close packet after one event loaded +-- elsif (load_eod_q = '1') then +-- loadNextState <= LOAD_TERM; +-- -- elsif (sub_bytes_loaded = sub_size_loaded) then -- if all subevent bytes are loaded +-- -- if (size_left = x"00000021") then -- and there is no more data, only termination left +-- -- -- gk 21.07.10 +-- -- if (PC_SKIP_TERM_IN = '0') then +-- -- loadNextState <= LOAD_TERM; -- add termination and close packet +-- -- else +-- -- loadNextState <= CLEANUP; +-- -- end if; +-- -- else -- there is more data in fifo +-- -- loadNextState <= LOAD_SUB; -- add another subevent +-- -- end if; +-- else +-- loadNextState <= LOAD_DATA; +-- end if; + -- gk 04.12.10 when LOAD_DATA => load_state <= x"6"; if (bytes_loaded = max_frame_size - 1) then loadNextState <= DIVIDE; - -- gk 26.07.10 - -- close packet after one event loaded + -- gk 07.10.10 elsif (load_eod_q = '1') then - loadNextState <= LOAD_TERM; --- elsif (sub_bytes_loaded = sub_size_loaded) then -- if all subevent bytes are loaded --- if (size_left = x"00000021") then -- and there is no more data, only termination left --- -- gk 21.07.10 --- if (PC_SKIP_TERM_IN = '0') then --- loadNextState <= LOAD_TERM; -- add termination and close packet --- else --- loadNextState <= CLEANUP; --- end if; --- else -- there is more data in fifo --- loadNextState <= LOAD_SUB; -- add another subevent --- end if; + if (MULT_EVT_ENABLE_IN = '1') then + if (size_left < x"0000_0030") then + loadNextState <= LOAD_TERM; + else + loadNextState <= LOAD_SUB; + end if; + else + loadNextState <= LOAD_TERM; + end if; else loadNextState <= LOAD_DATA; end if; @@ -413,6 +449,32 @@ begin end case; end process loadMachine; +-- gk 04.12.10 +firstSubInMultiProc : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') or (loadCurrentState = LOAD_TERM) then + first_sub_in_multi <= '1'; + elsif (loadCurrentState = LOAD_DATA) then + first_sub_in_multi <= '0'; + end if; + end if; +end process; + +-- gk 04.12.10 +fromDivideStateProc : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + from_divide_state <= '0'; + elsif (loadCurrentState = DIVIDE) then + from_divide_state <= '1'; + elsif (loadCurrentState = PREP_DATA) then + from_divide_state <= '0'; + end if; + end if; +end process fromDivideStateProc; + dividePositionProc : process(CLK) begin if rising_edge(CLK) then @@ -421,28 +483,39 @@ begin elsif (bytes_loaded = max_frame_size - 1) then if (loadCurrentState = LIDLE) then divide_position <= "00"; + disable_prep <= '0'; -- gk 05.12.10 elsif (loadCurrentState = LOAD_DATA) then + -- gk 05.12.10 -- gk 26.07.10 - if (load_eod_q = '1') then -- if termination is about to be loaded divide on term + if (MULT_EVT_ENABLE_IN = '0') and (load_eod_q = '1') then -- if termination is about to be loaded divide on term divide_position <= "11"; + disable_prep <= '0'; -- gk 05.12.10 + elsif (MULT_EVT_ENABLE_IN = '1') and (load_eod_q = '1') then + if (size_left > x"0000_0028") then + divide_position <= "01"; + disable_prep <= '0'; -- gk 05.12.10 + else + divide_position <= "11"; + disable_prep <= '0'; -- gk 05.12.10 + end if; else divide_position <= "00"; -- still data loaded divide on data --- if (sub_bytes_loaded = sub_size_loaded) and (size_left = x"00000021") then --- divide_position <= "11"; --- elsif (sub_bytes_loaded = sub_size_loaded) and (size_left /= x"00000021") then --- divide_position <= "01"; --- else --- divide_position <= "00"; + disable_prep <= '1'; -- gk 05.12.10 end if; elsif (loadCurrentState = LOAD_SUB) then if (all_int_ctr = 15) then divide_position <= "00"; + disable_prep <= '1'; -- gk 05.12.10 else divide_position <= "01"; + disable_prep <= '0'; -- gk 05.12.10 end if; elsif (loadCurrentState = LOAD_TERM) then divide_position <= "11"; + disable_prep <= '0'; -- gk 05.12.10 end if; + elsif (loadCurrentState = PREP_DATA) then -- gk 06.12.10 reset disable_prep + disable_prep <= '0'; end if; end if; end process dividePositionProc; @@ -547,7 +620,7 @@ begin end process shfRdEnProc; -fcWrEnProc : process(loadCurrentState, RESET) +fcWrEnProc : process(loadCurrentState, RESET, first_sub_in_multi, from_divide_state, MULT_EVT_ENABLE_IN, divide_position, disable_prep) begin if (RESET = '1') then -- gk 31.05.10 fc_wr_en <= '0'; @@ -555,6 +628,11 @@ begin fc_wr_en <= '1'; elsif (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_TERM) then fc_wr_en <= '1'; + -- gk 04.12.10 + elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') and (disable_prep = '0') then + fc_wr_en <= '1'; + elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (from_divide_state = '1') and ((divide_position = "00") or (divide_position = "01")) and (disable_prep = '0') then + fc_wr_en <= '1'; else fc_wr_en <= '0'; end if; @@ -636,6 +714,13 @@ begin bytes_loaded <= x"0000"; elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_TERM) then bytes_loaded <= bytes_loaded + x"1"; + -- gk 05.12.10 +-- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') then +-- bytes_loaded <= bytes_loaded + x"1"; + elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') and (disable_prep = '0') then + bytes_loaded <= bytes_loaded + x"1"; + elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (from_divide_state = '1') and ((divide_position = "00") or (divide_position = "01")) and (disable_prep = '0') then + bytes_loaded <= bytes_loaded + x"1"; end if; end if; end process bytesLoadedProc; @@ -810,7 +895,7 @@ end process fcUDPSizeProc; -- SUBEVENT HEADERS WRITE AND READ --*********************** -SUBEVENT_HEADERS_FIFO : fifo_2048x8 +SUBEVENT_HEADERS_FIFO : fifo_16kx8 -- gk 06.12.10 fifo_2048x8 port map( Data => shf_data, WrClock => CLK, diff --git a/gbe_ecp2m/trb_net16_gbe_setup.vhd b/gbe_ecp2m/trb_net16_gbe_setup.vhd index aff9fec..42d5d73 100644 --- a/gbe_ecp2m/trb_net16_gbe_setup.vhd +++ b/gbe_ecp2m/trb_net16_gbe_setup.vhd @@ -41,6 +41,7 @@ port( GBE_READOUT_CTR_VALID_OUT : out std_logic; -- gk 26.04.10 GBE_DELAY_OUT : out std_logic_vector(31 downto 0); GBE_ALLOW_LARGE_OUT : out std_logic; + GBE_FRAME_DELAY_OUT : out std_logic_vector(31 downto 0); -- gk 09.12.10 -- gk 28.07.10 MONITOR_BYTES_IN : in std_logic_vector(31 downto 0); MONITOR_SENT_IN : in std_logic_vector(31 downto 0); @@ -103,6 +104,7 @@ signal data_out : std_logic_vector(31 downto 0); -- gk 26.04.10 signal delay : std_logic_vector(31 downto 0); -- gk 28.04.10 signal allow_large : std_logic; -- gk 21.07.10 signal reset_fifo : std_logic; -- gk 28.09.10 +signal frame_delay : std_logic_vector(31 downto 0); -- gk 09.12.10 begin @@ -126,6 +128,7 @@ begin GBE_DELAY_OUT <= delay; -- gk 28.04.10 GBE_ALLOW_LARGE_OUT <= allow_large; -- gk 21.07.10 --DBG_RESET_FIFO_OUT <= reset_fifo; -- gk 28.09.10 + GBE_FRAME_DELAY_OUT <= frame_delay; -- gk 09.12.10 end if; end process OUT_PROC; @@ -152,7 +155,7 @@ begin subevent_id <= x"0000_00cf"; subevent_dec <= x"0002_0001"; queue_dec <= x"0003_0062"; - max_packet <= x"0000_fde8"; --x"0000_fde8"; -- 65k --x"0000_fde8"; -- tester + max_packet <= x"0000_ea60"; --x"0000_fde8"; --x"0000_fde8"; -- 65k --x"0000_fde8"; -- tester min_packet <= x"0000_0007"; -- gk 20.07.10 max_frame <= x"0578"; use_gbe <= '0'; --'1'; -- gk 27.08.10 -- blocks the transmission until gbe gets configured @@ -165,6 +168,7 @@ begin DBG_FIFO_RD_EN_OUT <= '0'; allow_large <= '0'; -- gk 21.07.10 reset_fifo <= '0'; -- gk 28.09.10 + frame_delay <= x"0000_0000"; -- gk 09.12.10 elsif (BUS_WRITE_EN_IN = '1') then case BUS_ADDR_IN is @@ -229,6 +233,10 @@ begin allow_large <= '1'; end if; + -- gk 09.12.10 + when x"0d" => + frame_delay <= BUS_DATA_IN; + -- gk 28.09.10 when x"fe" => if (BUS_DATA_IN = x"ffff_ffff") then @@ -261,6 +269,7 @@ begin DBG_FIFO_RD_EN_OUT <= '0'; allow_large <= allow_large; reset_fifo <= reset_fifo; -- gk 28.09.10 + frame_delay <= frame_delay; end case; else reset_values <= '0'; @@ -333,6 +342,10 @@ begin data_out <= x"0000_0001"; end if; + -- gk 09.12.10 + when x"0d" => + data_out <= frame_delay; + -- gk 01.06.10 when x"e0" => data_out <= DBG_IPU2GBE1_IN; diff --git a/gbe_ecp2m/trb_net16_ipu2gbe.vhd b/gbe_ecp2m/trb_net16_ipu2gbe.vhd index 73c8d7a..e1b3035 100755 --- a/gbe_ecp2m/trb_net16_ipu2gbe.vhd +++ b/gbe_ecp2m/trb_net16_ipu2gbe.vhd @@ -45,6 +45,7 @@ port( PC_DATA_OUT : out std_logic_vector (7 downto 0); PC_READY_IN : in std_logic; PC_SOS_OUT : out std_logic; + PC_EOS_OUT : out std_logic; -- gk 08.11.10 PC_EOD_OUT : out std_logic; PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0); PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0); @@ -252,6 +253,13 @@ signal found_empty_evt : std_logic; signal found_empty_evt_comb : std_logic; signal found_empty_evt_ctr : std_logic_vector(31 downto 0); +-- gk 06.10.10 +signal message_size : std_logic_vector(31 downto 0); + +-- gk 07.12.10 +signal prev_bank_select : std_logic_vector(3 downto 0); +signal first_event : std_logic; + begin BANK_SELECT_OUT <= bank_select; -- gk 27.03.10 @@ -705,7 +713,7 @@ begin end if; end process loadMachineProc; -loadMachine : process( loadCurrentState, sf_aempty, remove_done, read_done, padding_needed, PC_READY_IN, load_sub_done, pc_sub_size, MIN_MESSAGE_SIZE_IN, MAX_MESSAGE_SIZE_IN, pc_trig_nr, first_run_trg, endpoint_addr, first_run_addr, load_eod, event_waiting) +loadMachine : process( loadCurrentState, sf_aempty, remove_done, read_done, padding_needed, PC_READY_IN, load_sub_done, pc_sub_size, MIN_MESSAGE_SIZE_IN, MAX_MESSAGE_SIZE_IN, pc_trig_nr, first_run_trg, endpoint_addr, first_run_addr, load_eod, event_waiting, bank_select, prev_bank_select) begin loadNextState <= LIDLE; rst_rem_ctr_comb <= '0'; @@ -729,7 +737,9 @@ begin when LIDLE => state2 <= x"0"; -- gk 23.07.10 - if( (sf_aempty = '0') and (PC_READY_IN = '1') and (event_waiting = '1') and (DATA_GBE_ENABLE_IN = '1') ) then -- gk 06.08.10 + --if( (sf_aempty = '0') and (PC_READY_IN = '1') and (event_waiting = '1') and (DATA_GBE_ENABLE_IN = '1') ) then -- gk 06.08.10 + -- gk 04.12.10 + if( (sf_aempty = '0') and (event_waiting = '1') and (DATA_GBE_ENABLE_IN = '1') ) then loadNextState <= INIT; rst_rem_ctr_comb <= '1'; rst_regs_comb <= '1'; @@ -740,15 +750,40 @@ begin state2 <= x"1"; loadNextState <= REMOVE; rem_phase_comb <= '1'; +-- when REMOVE => +-- state2 <= x"2"; +-- if( remove_done = '1' ) then +-- loadNextState <= WAIT_TO_REMOVE; +-- inc_trg_ctr_comb <= '1'; +-- else +-- loadNextState <= REMOVE; +-- rem_phase_comb <= '1'; +-- end if; + -- gk 03.12.10 when REMOVE => state2 <= x"2"; if( remove_done = '1' ) then - loadNextState <= WAIT_TO_REMOVE; + -- gk 06.10.10 + if (MULT_EVT_ENABLE_IN = '1') then + if (message_size + pc_sub_size < MAX_MESSAGE_SIZE_IN) then + -- gk 07.12.10 + if (first_event = '0') and (prev_bank_select /= bank_select) then -- check if event builder address changed, if so close the current packet + loadNextState <= WAIT_PC; + else + loadNextState <= WAIT_TO_REMOVE; + end if; + else + loadNextState <= WAIT_PC; + end if; + else + loadNextState <= WAIT_TO_REMOVE; + end if; inc_trg_ctr_comb <= '1'; else loadNextState <= REMOVE; rem_phase_comb <= '1'; end if; + when WAIT_TO_REMOVE => if (rem_ctr = x"a") then loadNextState <= DECIDE; @@ -826,18 +861,40 @@ begin state2 <= x"9"; loadNextState <= CALCC; pad_data_comb <= '1'; +-- when CALCC => +-- state2 <= x"a"; +-- loadNextState <= CLOSE; +-- pc_eod_comb <= '1'; + -- gk 04.12.10 when CALCC => state2 <= x"a"; - loadNextState <= CLOSE; + if (MULT_EVT_ENABLE_IN = '1') then + loadNextState <= LIDLE; + else + loadNextState <= CLOSE; + end if; pc_eod_comb <= '1'; when CLOSE => state2 <= x"b"; loadNextState <= WAIT_PC; rst_regs_comb <= '1'; +-- when WAIT_PC => +-- state2 <= x"c"; +-- if( PC_READY_IN = '1' ) then +-- loadNextState <= LIDLE; +-- else +-- loadNextState <= WAIT_PC; +-- end if; + -- gk 03.12.10 when WAIT_PC => state2 <= x"c"; if( PC_READY_IN = '1' ) then - loadNextState <= LIDLE; + -- gk 06.10.10 + if (MULT_EVT_ENABLE_IN = '1') then + loadNextState <= WAIT_TO_REMOVE; + else + loadNextState <= LIDLE; + end if; else loadNextState <= WAIT_PC; end if; @@ -876,6 +933,9 @@ begin end case; end process loadMachine; +-- gk 07.10.10 +PC_EOS_OUT <= '1' when (MULT_EVT_ENABLE_IN = '1') and (pc_eod = '1') else '0'; + -- gk 25.07.10 INVALID_STATS_PROC : process(CLK) begin @@ -939,22 +999,44 @@ bank_select_proc : process( CLK ) begin if rising_edge( CLK ) then -- gk 29.03.10 - if( (RESET = '1') or (rst_regs = '1') ) then + if ((RESET = '1') or (rst_regs = '1')) then bank_select <= "0000"; -- gk 01.06.10 THERE WAS A BUG, IT SHOUDL BE TAKEN FROM SF_Q - elsif( (sf_rd_en = '1') and (rem_ctr = x"2") ) then + elsif ((sf_rd_en = '1') and (rem_ctr = x"2")) then bank_select <= pc_data(3 downto 0); --CTS_INFORMATION_IN(3 downto 0); end if; end if; end process bank_select_proc; +-- gk 07.12.10 +first_event_proc : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') or (loadCurrentState = WAIT_PC) then + first_event <= '1'; + elsif (remove_done = '1') then + first_event <= '0'; + end if; + end if; +end process first_event_proc; + +-- gk 07.12.10 +prev_bank_proc : process(CLK) +begin + if (RESET = '1') or (loadCurrentState = WAIT_PC) then + prev_bank_select <= "0000"; + elsif ((sf_rd_en = '1') and (rem_ctr = x"3") and (first_event = '1')) then + prev_bank_select <= bank_select; + end if; +end process prev_bank_proc; + -- gk 29.03.10 start_config_proc : process( CLK ) begin if rising_edge( CLK ) then - if( (RESET = '1') or (config_done = '1') or (rst_regs = '1') ) then + if ((RESET = '1') or (config_done = '1') or (rst_regs = '1')) then start_config <= '0'; - elsif( (sf_rd_en = '1') and (rem_ctr = x"2") ) then -- gk 01.06.10 + elsif ((sf_rd_en = '1') and (rem_ctr = x"2") and (first_event = '1')) then -- gk 01.06.10 start_config <= '1'; end if; end if; @@ -1076,6 +1158,22 @@ begin end if; end process THE_SUB_SIZE_PROC; +-- gk 06.10.10 +MESSAGE_SIZE_PROC : process(CLK) +begin + if rising_edge(CLK) then + if (RESET = '1') then + message_size <= x"0000_0028"; + elsif ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1')) then + message_size <= x"0000_0028"; + elsif ((MULT_EVT_ENABLE_IN = '1') and (prev_bank_select /= bank_select) and (remove_done = '1')) then + message_size <= x"0000_0028"; + elsif (pc_sos = '1') then + message_size <= message_size + pc_sub_size + x"10"; -- gk 06.12.10 add 16B for subevent headers + end if; + end if; +end process MESSAGE_SIZE_PROC; + -- gk 25.07.10 ENDP_ADDRESS_PROC : process(CLK) begin @@ -1175,16 +1273,16 @@ debug(11 downto 8) <= state; dbg_bs_proc : process(CLK) begin if rising_edge(CLK) then - if RESET = '1' then + if (RESET = '1') then debug(15 downto 12) <= (others => '0'); - elsif ( (sf_rd_en = '1') and (rem_ctr = x"3") ) then + elsif ((sf_rd_en = '1') and (rem_ctr = x"3")) then debug(15 downto 12) <= bank_select; end if; end if; end process dbg_bs_proc; debug(16) <= config_done; -debug(17) <= remove_done; +debug(17) <= '0'; --remove_done; debug(18) <= read_done; debug(19) <= padding_needed; @@ -1302,7 +1400,12 @@ CTS_READOUT_FINISHED_OUT <= cts_readout_finished; CTS_LENGTH_OUT <= cts_length; PC_SOS_OUT <= pc_sos; -PC_EOD_OUT <= pc_eod; -- gk 26.07.10 --pc_eod_q; +--PC_EOD_OUT <= pc_eod; -- gk 26.07.10 --pc_eod_q; +PC_EOD_OUT <= '1' when ((MULT_EVT_ENABLE_IN = '0') and (pc_eod = '1')) + or ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1')) + -- gk 07.12.10 + or ((MULT_EVT_ENABLE_IN = '1') and (prev_bank_select /= bank_select) and (remove_done = '1')) + else '0'; -- gk 07.10.10 PC_DATA_OUT <= pc_data_q; PC_WR_EN_OUT <= pc_wr_en_qq; diff --git a/gbe_ecp2m/trb_net_gbe_components.vhd b/gbe_ecp2m/trb_net_gbe_components.vhd index daafa85..2091080 100644 --- a/gbe_ecp2m/trb_net_gbe_components.vhd +++ b/gbe_ecp2m/trb_net_gbe_components.vhd @@ -121,6 +121,7 @@ port( FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0); TTL_IN : in std_logic_vector(7 downto 0); PROTOCOL_IN : in std_logic_vector(7 downto 0); + FRAME_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 09.12.10 -- ports for packetTransmitter RD_CLK : in std_logic; -- 125MHz clock!!! FT_DATA_OUT : out std_logic_vector(8 downto 0); @@ -243,6 +244,7 @@ port( GBE_READOUT_CTR_VALID_OUT : out std_logic; -- gk 26.04.10 GBE_DELAY_OUT : out std_logic_vector(31 downto 0); GBE_ALLOW_LARGE_OUT : out std_logic; + GBE_FRAME_DELAY_OUT : out std_logic_vector(31 downto 0); -- gk 09.12.10 -- gk 28.07.10 MONITOR_BYTES_IN : in std_logic_vector(31 downto 0); MONITOR_SENT_IN : in std_logic_vector(31 downto 0); -- 2.43.0