From a422c142a132d09882d4c2859caf7715511b3036 Mon Sep 17 00:00:00 2001 From: "a.weber" Date: Tue, 24 Jul 2018 13:54:56 +0200 Subject: [PATCH] New Project: combiner with internal calibration - AW --- combiner_calib/combiner.lpf | 71 ++ combiner_calib/combiner.prj | 207 ++++ combiner_calib/combiner.vhd | 1047 ++++++++++++++++++++ combiner_calib/compile.pl | 1 + combiner_calib/config.vhd | 121 +++ combiner_calib/config_compile_frankfurt.pl | 20 + combiner_calib/config_compile_gsi.pl | 22 + combiner_calib/core/FIFO_36x128.ipx | 9 + combiner_calib/core/FIFO_36x128.lpc | 48 + combiner_calib/core/FIFO_36x128.vhd | 764 ++++++++++++++ combiner_calib/core/FIFO_36x64.ipx | 9 + combiner_calib/core/FIFO_36x64.lpc | 48 + combiner_calib/core/FIFO_36x64.vhd | 743 ++++++++++++++ combiner_calib/par.p2t | 21 + combiner_calib/synplify.fdc | 50 + 15 files changed, 3181 insertions(+) create mode 100644 combiner_calib/combiner.lpf create mode 100644 combiner_calib/combiner.prj create mode 100644 combiner_calib/combiner.vhd create mode 120000 combiner_calib/compile.pl create mode 100644 combiner_calib/config.vhd create mode 100644 combiner_calib/config_compile_frankfurt.pl create mode 100644 combiner_calib/config_compile_gsi.pl create mode 100644 combiner_calib/core/FIFO_36x128.ipx create mode 100644 combiner_calib/core/FIFO_36x128.lpc create mode 100644 combiner_calib/core/FIFO_36x128.vhd create mode 100644 combiner_calib/core/FIFO_36x64.ipx create mode 100644 combiner_calib/core/FIFO_36x64.lpc create mode 100644 combiner_calib/core/FIFO_36x64.vhd create mode 100644 combiner_calib/par.p2t create mode 100644 combiner_calib/synplify.fdc diff --git a/combiner_calib/combiner.lpf b/combiner_calib/combiner.lpf new file mode 100644 index 0000000..921a7a0 --- /dev/null +++ b/combiner_calib/combiner.lpf @@ -0,0 +1,71 @@ +COMMERCIAL ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +SYSCONFIG MCCLK_FREQ = 20; + +FREQUENCY PORT CLOCK_PLL 200 MHz; +FREQUENCY PORT CLOCK_PCLK 200 MHz; + + +FREQUENCY NET "THE_MEDIA*/clk_rx_full" 200 MHz; # HOLD_MARGIN 500 ps +FREQUENCY NET "THE_MEDIA*/clk_tx_full" 200 MHz; # HOLD_MARGIN 500 ps + + + +LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/PCSD_INST" SITE "PCSC" ; +LOCATE COMP "THE_MEDIA_4_DOWN_A/THE_SERDES/PCSD_INST" SITE "PCSA" ; +LOCATE COMP "THE_MEDIA_4_DOWN_B/THE_SERDES/PCSD_INST" SITE "PCSB" ; +LOCATE COMP "THE_MEDIA_4_DOWN_D/THE_SERDES/PCSD_INST" SITE "PCSD" ; + +REGION "MEDIA_A" "R87C91D" 28 36; +REGION "MEDIA_B" "R87C55D" 28 36; +REGION "MEDIA_C" "R87C127D" 28 36; +REGION "MEDIA_D" "R87C19D" 28 36; + + +#REGION "MEDIA_DOWN1" "R93C10D" 22 160; +LOCATE UGROUP "THE_MEDIA_4_DOWN_A/media_interface_group" REGION "MEDIA_A" ; +LOCATE UGROUP "THE_MEDIA_4_DOWN_B/media_interface_group" REGION "MEDIA_B" ; +LOCATE UGROUP "THE_MEDIA_4_DOWN_D/media_interface_group" REGION "MEDIA_D" ; +LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA_C" ; + + + + +MULTICYCLE TO CELL "THE_MEDIA*/sci*" 20 ns; +MULTICYCLE FROM CELL "THE_MEDIA*/sci*" 20 ns; +MULTICYCLE TO CELL "THE_MEDIA*/PROC_SCI_CTRL.wa*" 20 ns; +BLOCK PATH TO CLKNET "THE_MEDIA*/sci_write_i"; +BLOCK PATH FROM CLKNET "THE_MEDIA*/sci_write_i"; +BLOCK PATH TO CLKNET "THE_MEDIA*/sci_read_i"; +BLOCK PATH FROM CLKNET "THE_MEDIA*/sci_read_i"; +MULTICYCLE TO CLKNET "THE_MEDIA*/sci_read_i" 15 ns; +MULTICYCLE FROM CLKNET "THE_MEDIA*/sci_read_i" 15 ns; +MULTICYCLE TO CLKNET "THE_MEDIA*/sci_write_i" 15 ns; +MULTICYCLE FROM CLKNET "THE_MEDIA*/sci_write_i" 15 ns; + +MULTICYCLE FROM CELL "THE_MEDIA*/gen_control.*.gen_used_control.THE_MED_CONTROL/THE_RX_FSM/cs*" TO CELL "THE_MEDIA*/THE_SCI_READER/*" 20 ns; + +MULTICYCLE TO ASIC "THE_MEDIA*/THE_SERDES/PCSD_INST" PIN SCIRD 15 ns; +MAXDELAY TO ASIC "THE_MEDIA*/THE_SERDES/PCSD_INST" PIN SCIRD 15 ns; + + +#If these signals do not exist, somebody messed around with the design... +MULTICYCLE TO CELL "THE_TOOLS/THE_SPI_RELOAD_THE_SPI_MASTER_THE_SPI_SLIM_tx_sreg_oregio[*]" 20 ns; +MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 20 ns; +# # # # MULTICYCLE FROM CELL "THE_CLOCK_RESET/gen_norecov_clock.clear_n_i" 20 ns; +MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns; +MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; +# # # # MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; +GSR_NET NET "GSR_N"; + +BLOCK PATH TO PORT "LED*"; +BLOCK PATH TO PORT "SFP*"; +BLOCK PATH FROM PORT "SFP*"; +BLOCK PATH TO PORT "PROGRAMN"; +BLOCK PATH TO PORT "TEMPSENS"; +BLOCK PATH FROM PORT "TEMPSENS"; +BLOCK PATH TO PORT "TEST_LINE"; + diff --git a/combiner_calib/combiner.prj b/combiner_calib/combiner.prj new file mode 100644 index 0000000..2589fc9 --- /dev/null +++ b/combiner_calib/combiner.prj @@ -0,0 +1,207 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology LATTICE-ECP3 +set_option -part LFE3_150EA +set_option -package FN1156C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "combiner" +set_option -resource_sharing false + +# map options +set_option -frequency 120 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 1 +set_option -pipe 1 +set_option -force_gsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true + +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/combiner.edf" + +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + + + +#Packages +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd" + +#Basic Infrastructure +add_file -vhdl -lib work "../cores/pll_200_100.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd" +add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd" +add_file -vhdl -lib work "../code/clock_reset_handler_combiner.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd" +add_file -vhdl -lib work "../../trbnet/basics/priority_arbiter.vhd" + + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/ram_18x256_oreg.vhd" +add_file -vhdl -lib work "./core/FIFO_36x64.vhd" + +#Flash & Reload, Tools +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../dirich/code/ltc2600_handler.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_4.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_4_slave3.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_4.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd" + +#TrbNet Endpoint +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +#Hub +add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic_2.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd" +add_file -vhdl -lib work "../../trbnet/basics/wide_adder_17x16.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + + + + +add_file -vhdl -lib work "./combiner.vhd" +add_file -fpga_constraint "./synplify.fdc" + + + diff --git a/combiner_calib/combiner.vhd b/combiner_calib/combiner.vhd new file mode 100644 index 0000000..8f2b68c --- /dev/null +++ b/combiner_calib/combiner.vhd @@ -0,0 +1,1047 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.trb_net16_hub_func.all; +use work.trb_net_gbe_components.all; +use work.med_sync_define.all; + +entity combiner is + port( + CLOCK_PCLK : in std_logic; + CLOCK_PLL : in std_logic; + + TRIGGER_IN : in std_logic; + TRIGGER_OUT : out std_logic; + TRIGGER_TO_CTS : out std_logic; + + --Additional IO + RJ_CLOCK : inout std_logic_vector( 3 downto 0); --1 not available here + RJ_TRIG : inout std_logic_vector( 2 downto 1); --0,3 not available here + POWER_BOARD_IO : inout std_logic_vector( 4 downto 1); + RJ45_SIG_1 : in std_logic; + RJ45_SIG_2 : out std_logic; + RJ45_SIG_3 : out std_logic; + RJ45_SIG_4 : out std_logic; + RJ45_SIG_5 : out std_logic; + --RJ45_SIG : in std_logic_vector( 5 downto 2); + + --Lines to slaves + BACK_MASTER_READY : out std_logic_vector(12 downto 1); --sig_1 + BACK_SLAVE_READY : in std_logic_vector(12 downto 1); --sig_2 + BACK_TRIG1 : in std_logic_vector(12 downto 1); --sig_3 + BACK_TRIG2 : in std_logic_vector(12 downto 1); --sig_4 + BACK_LDO_EN : out std_logic_vector(12 downto 1); --en_ldo + BACK_SPARE : inout std_logic_vector(12 downto 1); --sig_5 + + --LED + LED_GREEN : out std_logic; + LED_YELLOW : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_RJ_GREEN : out std_logic_vector( 1 downto 0); --0: clock, 1:trigger + LED_RJ_RED : out std_logic_vector( 1 downto 0); + LED_SFP_GREEN : out std_logic; + LED_SFP_RED : out std_logic; + + --SFP + SFP_LOS : in std_logic; + SFP_MOD0 : in std_logic; + SFP_MOD1 : inout std_logic := 'Z'; + SFP_MOD2 : inout std_logic := 'Z'; + SFP_TX_DIS : out std_logic := '0'; + + --Switch + CLOCK_SELECT_IN : in std_logic; + TRIGGER_SEL_OUT : out std_logic_vector( 2 downto 1); --1 to FPGA, 2 to Backplane, + --'0' from FPGA, '1' from connector + --ADC + ADC_CLK : out std_logic; + ADC_CS : out std_logic; + ADC_DIN : out std_logic; + ADC_DOUT : in std_logic; + + --Flash, 1-wire, Reload + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_IN : out std_logic; + FLASH_OUT : in std_logic; + PROGRAMN : out std_logic; + TEMPSENS : inout std_logic; + POWER_GOOD : in std_logic; + + --Test Connectors + TEST_LINE : inout std_logic_vector(18 downto 1); + TEST_JTAG : out std_logic_vector(20 downto 7) + ); + + attribute syn_useioff : boolean; + attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_IN : signal is true; + attribute syn_useioff of FLASH_OUT : signal is true; + +end entity; + +architecture arch of combiner is + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys, clk_full, clk_full_osc : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + + signal time_counter : unsigned(31 downto 0) := (others => '0'); + signal led : std_logic_vector(1 downto 0); + signal debug_clock_reset : std_logic_vector(31 downto 0); + signal trigger_select_i : std_logic_vector(1 downto 0); + signal select_i : std_logic_vector(1 downto 0); + signal led_off_i : std_logic; + signal enable_ldo_i : std_logic_vector(11 downto 0); + + signal spi_cs, spi_miso, spi_mosi, spi_clk : std_logic_vector(15 downto 0); + --Media Interface + signal med2int : med2int_array_t(0 to INTERFACE_NUM-1); + signal int2med : int2med_array_t(0 to INTERFACE_NUM-1); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + + signal ctrlbus_rx, bustools_rx, bustc_rx, bus_master_out, handlerbus_rx : CTRLBUS_RX; + signal ctrlbus_tx, bustools_tx, bustc_tx, bus_master_in : CTRLBUS_TX; + + signal bussci_tx : ctrlbus_tx_array_t(0 to 3); + signal bussci_rx : ctrlbus_rx_array_t(0 to 3); + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal sed_error_i : std_logic; + signal bus_master_active : std_logic; + + signal uart_tx, uart_rx : std_logic; + + signal timer : TIMERS; + signal lcd_data : std_logic_vector(511 downto 0); + signal header_io : std_logic_vector(10 downto 1); + + signal trig_gen_out_i : std_logic_vector(1 downto 0); + signal monitor_inputs_i : std_logic_vector(25 downto 0); + + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + + signal med_dataready_out : std_logic_vector (INTERFACE_NUM-1 downto 0); + signal med_data_out : std_logic_vector (INTERFACE_NUM*c_DATA_WIDTH-1 downto 0); + signal med_packet_num_out : std_logic_vector (INTERFACE_NUM*c_NUM_WIDTH-1 downto 0); + signal med_read_in : std_logic_vector (INTERFACE_NUM-1 downto 0); + signal med_dataready_in : std_logic_vector (INTERFACE_NUM-1 downto 0); + signal med_data_in : std_logic_vector (INTERFACE_NUM*c_DATA_WIDTH-1 downto 0); + signal med_packet_num_in : std_logic_vector (INTERFACE_NUM*c_NUM_WIDTH-1 downto 0); + signal med_read_out : std_logic_vector (INTERFACE_NUM-1 downto 0); + signal med_stat_op : std_logic_vector (INTERFACE_NUM*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (INTERFACE_NUM*16-1 downto 0); + signal rdack, wrack : std_logic; + signal back_master_ready_i : std_logic_vector(12 downto 1); + signal back_slave_ready_i : std_logic_vector(12 downto 1); + signal master_ready_override_i : std_logic_vector(12 downto 1); + + signal fee_data : std_logic_vector(15 downto 0); + signal fee_dataready : std_logic; + signal fee_busy : std_logic; + signal fee_read : std_logic; + signal fee_status_bits : std_logic_vector(31 downto 0); + + signal fee_packer_cnt : std_logic_vector(16 downto 0) := (others => '0'); + signal fee_packer_data : std_logic_vector(31 downto 0); + signal fee_packer_dataready : std_logic; + + signal cts_start_readout : std_logic; + signal Data_stream : std_logic_vector(31 downto 0); + signal packer_cnt_HL : std_logic := '0'; + signal fee_length : std_logic_vector(15 downto 0); + signal fee_packer_data_finished : std_logic; + signal fee_packer_statusBits : std_logic_vector(31 downto 0); + + + ------- + type pckr_RX_state_type is (IDLE, WAITING, EVINF_H, EVINF_L, LENGTH, SOURCE, SSE_LENGTH, SSE_FEE_ID, SSE_DATA_H, SSE_DATA_L, STAT_BITS); + type pckr_TX_state_type is (EVNT, DATA, FINISH); + signal pckr_RX_state : pckr_RX_state_type; + signal pckr_TX_state : pckr_TX_state_type; + + signal EvInf_data : std_logic_vector(31 downto 0); + signal EvStatBits : std_logic_vector(31 downto 0); + signal pckr_Data : std_logic_vector(31 downto 0); + signal pckr_Data_ready : std_logic; + signal pckr_Data_Length_Ev : std_logic_vector(15 downto 0); + signal pckr_Data_Source : std_logic_vector(15 downto 0); + signal sse_fee_addr : std_logic_vector(15 downto 0); + signal pckr_Data_type : std_logic_vector( 3 downto 0); + + signal cts_data : std_logic_vector(31 downto 0); + signal cts_length : std_logic_vector(15 downto 0); + signal cts_read : std_logic; + signal cts_dataready : std_logic; + signal cts_finished : std_logic; + + signal pckr_fifo_full : std_logic; + signal pckr_fifo_empty : std_logic; + signal fifo_rdEn : std_logic; + signal fifo_rdEn_r, fifo_rdEn_2r, fifo_rdEn_3r : std_logic; + signal fifo_data_out : std_logic_vector(35 downto 0); + + component FIFO_36x64 is + port ( + Data: in std_logic_vector(35 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(35 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic; + AlmostFull: out std_logic); + end component FIFO_36x64; + + component fifo_36x32k_oreg + port ( + Data : in std_logic_vector(35 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + AmFullThresh : in std_logic_vector(14 downto 0); + Q : out std_logic_vector(35 downto 0); + WCNT : out std_logic_vector(15 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic); +end component; + +begin + +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- +THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + CLOCK_IN => CLOCK_PCLK, + RESET_FROM_NET => med2int(12).stat_op(13), + CLOCK_SELECT_IN => CLOCK_SELECT_IN, + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + RAW_CLK_OUT => open, + SYS_CLK_OUT => clk_sys, + REF_CLK_OUT => clk_full_osc, + + DEBUG_OUT => debug_clock_reset + ); + +--------------------------------------------------------------------------- +-- TrbNet Uplink +--------------------------------------------------------------------------- + +THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync + generic map( + SERDES_NUM => 0, + IS_SYNC_SLAVE => c_YES + ) + port map( + CLK_REF_FULL => med2int(12).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MEDIA_MED2INT => med2int(12), + MEDIA_INT2MED => int2med(12), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN => SFP_MOD0, + SD_LOS_IN => SFP_LOS, + SD_TXDIS_OUT => SFP_TX_DIS, + --Control Interface + BUS_RX => bussci_rx(2), + BUS_TX => bussci_tx(2), + -- Status and control port + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- TrbNet Downlink +--------------------------------------------------------------------------- + +THE_MEDIA_4_DOWN_A : entity work.med_ecp3_sfp_sync_4 + generic map( + IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO), + IS_USED => (c_YES,c_YES,c_YES,c_YES) + ) + port map( + CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + + --Internal Connection + MEDIA_MED2INT(0) => med2int(6), + MEDIA_MED2INT(1) => med2int(7), + MEDIA_MED2INT(2) => med2int(10), + MEDIA_MED2INT(3) => med2int(11), + MEDIA_INT2MED(0) => int2med(6), + MEDIA_INT2MED(1) => int2med(7), + MEDIA_INT2MED(2) => int2med(10), + MEDIA_INT2MED(3) => int2med(11), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN(0) => back_slave_ready_i(7), + SD_PRSNT_N_IN(1) => back_slave_ready_i(8), + SD_PRSNT_N_IN(2) => back_slave_ready_i(11), + SD_PRSNT_N_IN(3) => back_slave_ready_i(12), + SD_LOS_IN(0) => back_slave_ready_i(7), + SD_LOS_IN(1) => back_slave_ready_i(8), + SD_LOS_IN(2) => back_slave_ready_i(11), + SD_LOS_IN(3) => back_slave_ready_i(12), + SD_TXDIS_OUT(0) => back_master_ready_i(7), + SD_TXDIS_OUT(1) => back_master_ready_i(8), + SD_TXDIS_OUT(2) => back_master_ready_i(11), + SD_TXDIS_OUT(3) => back_master_ready_i(12), + + --Control Interface + BUS_RX => bussci_rx(0), + BUS_TX => bussci_tx(0), + + -- Status and control port + STAT_DEBUG => open, --med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + + +THE_MEDIA_4_DOWN_B : entity work.med_ecp3_sfp_sync_4 + generic map( + IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO), + IS_USED => (c_YES,c_YES,c_YES,c_YES) + ) + port map( + CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + + --Internal Connection + MEDIA_MED2INT(0) => med2int(8), + MEDIA_MED2INT(1) => med2int(9), + MEDIA_MED2INT(2) => med2int(3), + MEDIA_MED2INT(3) => med2int(2), + MEDIA_INT2MED(0) => int2med(8), + MEDIA_INT2MED(1) => int2med(9), + MEDIA_INT2MED(2) => int2med(3), + MEDIA_INT2MED(3) => int2med(2), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN(0) => back_slave_ready_i(9), + SD_PRSNT_N_IN(1) => back_slave_ready_i(10), + SD_PRSNT_N_IN(2) => back_slave_ready_i(4), + SD_PRSNT_N_IN(3) => back_slave_ready_i(3), + SD_LOS_IN(0) => back_slave_ready_i(9), + SD_LOS_IN(1) => back_slave_ready_i(10), + SD_LOS_IN(2) => back_slave_ready_i(4), + SD_LOS_IN(3) => back_slave_ready_i(3), + SD_TXDIS_OUT(0) => back_master_ready_i(9), + SD_TXDIS_OUT(1) => back_master_ready_i(10), + SD_TXDIS_OUT(2) => back_master_ready_i(4), + SD_TXDIS_OUT(3) => back_master_ready_i(3), + + --Control Interface + BUS_RX => bussci_rx(1), + BUS_TX => bussci_tx(1), + + -- Status and control port + STAT_DEBUG => open, --med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + + +THE_MEDIA_4_DOWN_D : entity work.med_ecp3_sfp_sync_4 + generic map( + IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO), + IS_USED => (c_YES,c_YES,c_YES,c_YES) + ) + port map( + CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + + --Internal Connection + MEDIA_MED2INT(0) => med2int(5), + MEDIA_MED2INT(1) => med2int(4), + MEDIA_MED2INT(2) => med2int(1), + MEDIA_MED2INT(3) => med2int(0), + MEDIA_INT2MED(0) => int2med(5), + MEDIA_INT2MED(1) => int2med(4), + MEDIA_INT2MED(2) => int2med(1), + MEDIA_INT2MED(3) => int2med(0), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN(0) => back_slave_ready_i(6), + SD_PRSNT_N_IN(1) => back_slave_ready_i(5), + SD_PRSNT_N_IN(2) => back_slave_ready_i(2), + SD_PRSNT_N_IN(3) => back_slave_ready_i(1), + SD_LOS_IN(0) => back_slave_ready_i(6), + SD_LOS_IN(1) => back_slave_ready_i(5), + SD_LOS_IN(2) => back_slave_ready_i(2), + SD_LOS_IN(3) => back_slave_ready_i(1), + SD_TXDIS_OUT(0) => back_master_ready_i(6), + SD_TXDIS_OUT(1) => back_master_ready_i(5), + SD_TXDIS_OUT(2) => back_master_ready_i(2), + SD_TXDIS_OUT(3) => back_master_ready_i(1), + + --Control Interface + BUS_RX => bussci_rx(3), + BUS_TX => bussci_tx(3), + + -- Status and control port + STAT_DEBUG => open, --med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + + +BACK_MASTER_READY <= back_master_ready_i or master_ready_override_i; +back_slave_ready_i <= BACK_SLAVE_READY; + +--------------------------------------------------------------------------- +-- Hub +--------------------------------------------------------------------------- +-- +-- THE_HUB : trb_net16_hub_base +-- generic map ( +-- HUB_USED_CHANNELS => (c_YES,c_YES,c_NO,c_YES), +-- IBUF_SECURE_MODE => c_YES, +-- MII_NUMBER => INTERFACE_NUM, +-- MII_IS_UPLINK => MII_IS_UPLINK, +-- MII_IS_DOWNLINK => MII_IS_DOWNLINK, +-- MII_IS_UPLINK_ONLY => MII_IS_UPLINK_ONLY, +-- INT_NUMBER => 0, +-- USE_ONEWIRE => c_YES, +-- COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)), +-- HARDWARE_VERSION => HARDWARE_INFO, +-- INIT_ENDPOINT_ID => x"0000", +-- INIT_ADDRESS => INIT_ADDRESS, +-- USE_VAR_ENDPOINT_ID => c_NO, +-- BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, +-- INIT_CTRL_REGS => x"00000000_00000000_00000000_00000000" & +-- x"00000000_00000000_00000000_00000000" & +-- x"00000000_00000000_000040FF_00000000" & +-- x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF", +-- RESET_IOBUF_AT_TIMEOUT => c_YES +-- ) +-- port map ( +-- CLK => clk_sys, +-- RESET => reset_i, +-- CLK_EN => '1', +-- +-- --Media interfacces +-- MED_DATAREADY_OUT(13*1-1 downto 0) => med_dataready_out, +-- MED_DATA_OUT(13*16-1 downto 0) => med_data_out, +-- MED_PACKET_NUM_OUT(13*3-1 downto 0) => med_packet_num_out, +-- MED_READ_IN(13*1-1 downto 0) => med_read_in, +-- MED_DATAREADY_IN(13*1-1 downto 0) => med_dataready_in, +-- MED_DATA_IN(13*16-1 downto 0) => med_data_in, +-- MED_PACKET_NUM_IN(13*3-1 downto 0) => med_packet_num_in, +-- MED_READ_OUT(13*1-1 downto 0) => med_read_out, +-- MED_STAT_OP(13*16-1 downto 0) => med_stat_op, +-- MED_CTRL_OP(13*16-1 downto 0) => med_ctrl_op, +-- +-- COMMON_STAT_REGS => common_stat_reg, +-- COMMON_CTRL_REGS => common_ctrl_reg, +-- MY_ADDRESS_OUT => timer.network_address, +-- UNIQUE_ID_OUT => timer.uid, +-- TEMPERATURE_OUT => timer.temperature, +-- --REGIO INTERFACE +-- REGIO_ADDR_OUT => ctrlbus_rx.addr, +-- REGIO_READ_ENABLE_OUT => ctrlbus_rx.read, +-- REGIO_WRITE_ENABLE_OUT => ctrlbus_rx.write, +-- REGIO_DATA_OUT => ctrlbus_rx.data, +-- REGIO_DATA_IN => ctrlbus_tx.data, +-- REGIO_DATAREADY_IN => rdack, +-- REGIO_NO_MORE_DATA_IN => ctrlbus_tx.nack, +-- REGIO_WRITE_ACK_IN => wrack, +-- REGIO_UNKNOWN_ADDR_IN => ctrlbus_tx.unknown, +-- REGIO_TIMEOUT_OUT => ctrlbus_rx.timeout, +-- +-- TIMER_TICKS_OUT(0) => timer.tick_us, +-- TIMER_TICKS_OUT(1) => timer.tick_ms, +-- ONEWIRE => TEMPSENS, +-- --Status ports (for debugging) +-- MPLEX_CTRL => (others => '0'), +-- CTRL_DEBUG => (others => '0'), +-- STAT_DEBUG => open +-- ); +-- + + THE_HUB: entity work.trb_net16_hub_streaming_port_sctrl_record + generic map( + HUB_USED_CHANNELS => (1,1,0,1), + INIT_ADDRESS => INIT_ADDRESS, + MII_NUMBER => INTERFACE_NUM, + MII_IS_UPLINK => MII_IS_UPLINK, + MII_IS_DOWNLINK => MII_IS_DOWNLINK, + MII_IS_UPLINK_ONLY => MII_IS_UPLINK_ONLY, + USE_ONEWIRE => c_YES, + HARDWARE_VERSION => HARDWARE_INFO, + INCLUDED_FEATURES => INCLUDED_FEATURES, + INIT_ENDPOINT_ID => x"0000", + CLOCK_FREQUENCY => CLOCK_FREQUENCY, + BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, + COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)) + ) + port map( + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + + --Media interfacces + MEDIA_MED2INT => med2int, + MEDIA_INT2MED => int2med, + + --Event information coming from CTS + CTS_NUMBER_OUT => open, + CTS_CODE_OUT => open, + CTS_INFORMATION_OUT => open, --wichtig für GBE + CTS_READOUT_TYPE_OUT => open, + CTS_START_READOUT_OUT => cts_start_readout, + --Information sent to CTS + --status data, equipped with DHDR + CTS_DATA_IN => cts_data, + CTS_DATAREADY_IN => cts_dataready, + CTS_READOUT_FINISHED_IN => cts_finished, + CTS_READ_OUT => cts_read,--sagt, ob lese bereit + CTS_LENGTH_IN => cts_length, -- lenge der Daten ohne ertsen Header + CTS_STATUS_BITS_IN => EvStatBits, + -- Data from Frontends + FEE_DATA_OUT => fee_data, + FEE_DATAREADY_OUT => fee_dataready, + FEE_READ_IN => fee_read, --'1' for FEE data receiving (page 49) + FEE_STATUS_BITS_OUT => fee_status_bits, + FEE_BUSY_OUT => fee_busy, + MY_ADDRESS_IN => timer.network_address, + COMMON_STAT_REGS => common_stat_reg, --open, + COMMON_CTRL_REGS => common_ctrl_reg, --open, + ONEWIRE => TEMPSENS, + MY_ADDRESS_OUT => timer.network_address, + UNIQUE_ID_OUT => timer.uid, + EXTERNAL_SEND_RESET => '0', + + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + TIMER => timer, + + --Gbe Sctrl Input + GSC_INIT_DATAREADY_IN => '0', + GSC_INIT_DATA_IN => x"0000", + GSC_INIT_PACKET_NUM_IN => "000", + GSC_INIT_READ_OUT => open, + GSC_REPLY_DATAREADY_OUT => open, + GSC_REPLY_DATA_OUT => open, + GSC_REPLY_PACKET_NUM_OUT => open, + GSC_REPLY_READ_IN => '1', + GSC_BUSY_OUT => open, + + --status and control ports + HUB_STAT_CHANNEL => open, + HUB_STAT_GEN => open, + MPLEX_CTRL => (others => '0'), + MPLEX_STAT => open, + STAT_REGS => open, + STAT_CTRL_REGS => open, + + --Fixed status and control ports + STAT_DEBUG => open, + CTRL_DEBUG => (others => '0') + ); + + + + THE_DATAPACKER_FSM_RX : process + variable sse_length_cntr : unsigned(15 downto 0); + variable pckr_Data_Length_Ev_cntr : unsigned(15 downto 0); + begin + wait until rising_edge(clk_sys); + + pckr_Data_ready <= '0'; + + if reset_i = '1' then + pckr_RX_state <= IDLE; + else + + case pckr_RX_state is + when IDLE => + if cts_start_readout = '1' then + pckr_RX_state <= WAITING; + EvInf_data <= (others => '0'); + end if; + + when WAITING => + if fee_busy = '1' then + pckr_RX_state <= EVINF_H; + end if; + + when EVINF_H => + if (fee_dataready and fee_read) = '1' then + EvInf_data(31 downto 16) <= fee_data; --not necessry + pckr_Data(31 downto 16) <= fee_data; + pckr_RX_state <= EVINF_L; + end if; + + when EVINF_L => + if (fee_dataready and fee_read) = '1' then + EvInf_data(15 downto 0) <= fee_data; --not necessry + pckr_Data(15 downto 0) <= fee_data; + pckr_Data_type <= x"1"; + pckr_Data_ready <= '1'; + pckr_RX_state <= LENGTH; + end if; + + when LENGTH => + if (fee_dataready and fee_read) = '1' then + pckr_Data(31 downto 16) <= fee_data; + pckr_Data_Length_Ev <= fee_data; --for CTS + pckr_Data_Length_Ev_cntr := unsigned(fee_data); + pckr_RX_state <= SOURCE; + end if; + + when SOURCE => + if (fee_dataready and fee_read) = '1' then + pckr_Data_Source <= fee_data; --not necessary + pckr_Data(15 downto 0) <= fee_data; + pckr_Data_type <= x"2"; + pckr_Data_ready <= '1'; + pckr_RX_state <= SSE_LENGTH; + end if; + + when SSE_LENGTH => + if (fee_dataready and fee_read) = '1' then + pckr_Data(31 downto 16) <= fee_data; + --see_length <= fee_data; + sse_length_cntr := unsigned(fee_data); + pckr_RX_state <= SSE_FEE_ID; + end if; + + when SSE_FEE_ID => --Analysing Data + if (fee_dataready and fee_read) = '1' then + pckr_Data(15 downto 0) <= fee_data; + pckr_Data_type <= x"3"; --SSE_HDR + pckr_Data_ready <= '1'; + sse_fee_addr <= fee_data; + pckr_RX_state <= SSE_DATA_H; + + pckr_Data_Length_Ev_cntr := pckr_Data_Length_Ev_cntr - 1; + if sse_length_cntr = x"0000" then + pckr_RX_state <= SSE_LENGTH; + end if; + end if; + + when SSE_DATA_H => + if (fee_dataready and fee_read) = '1' then + pckr_Data(31 downto 16) <= fee_data; + pckr_RX_state <= SSE_DATA_L; + end if; + + when SSE_DATA_L => --Analysing Data + if (fee_dataready and fee_read) = '1' then + pckr_Data(15 downto 0) <= fee_data; + pckr_Data_type <= x"4"; --SSE_DATA + pckr_Data_ready <= '1'; + sse_length_cntr := sse_length_cntr - 1; + pckr_Data_Length_Ev_cntr := pckr_Data_Length_Ev_cntr - 1; + + -- data handling + if sse_length_cntr = x"0000" then + if pckr_Data_Length_Ev_cntr = x"0000" then + pckr_RX_state <= STAT_BITS; + else + pckr_RX_state <= SSE_LENGTH; + end if; + else + --if pckr_Data_Length_Ev_cntr = x"0000" then + -- Problem ?!? + --else + pckr_RX_state <= SSE_DATA_H; + --end if; + end if; + end if; + + when STAT_BITS => --Analysing Data + if (fee_busy) = '0' then + EvStatBits <= fee_status_bits; + pckr_RX_state <= IDLE; + end if; + + when others => + null; + + end case; + end if; + end process; + + + --pckr_TX_data <= pckr_Data when rising_edge(clk_sys); + --pckr_TX_data_ready <= pckr_Data_ready_r when rising_edge(clk_sys); + -- pckr_TX_data_type <= pckr_Data_type when rising_edge(clk_sys); + --fifo_rdEn_r <= fifo_rdEn when rising_edge(clk_sys); + THE_DATAPACKER_FSM_TX : process --data buffer is necessary + variable EvInf_TX : std_logic_vector(31 downto 0); + variable EvLength_TX : std_logic_vector(15 downto 0); + variable EvLength_TX_cntr : unsigned(15 downto 0); + variable Header_ready : std_logic:='0'; + variable Data_Fifo : std_logic_vector(35 downto 0); + variable pckr_TX_data : std_logic_vector(31 downto 0); + variable pckr_TX_data_type : std_logic_vector( 3 downto 0); + variable buf_fifo_0 : std_logic_vector(35 downto 0); + variable buf_fifo_1 : std_logic_vector(35 downto 0); + variable buf_fifo_2 : std_logic_vector(35 downto 0); + variable buf_fifo_cnt : std_logic_vector( 1 downto 0) := "00"; + variable enable_fifo_rdEn : std_logic; + variable pckr_TX_data_ready : std_logic; + + begin + wait until rising_edge(clk_sys); + + cts_dataready <= '0'; + cts_finished <= '0'; + fifo_rdEn <= '0'; + fifo_rdEn_r <= fifo_rdEn; + fifo_rdEn_2r <= fifo_rdEn_r; + fifo_rdEn_3r <= fifo_rdEn_2r; + pckr_TX_data_ready := fifo_rdEn_3r; + Data_Fifo := fifo_data_out; + enable_fifo_rdEn := '1'; + + if reset_i='1' then + pckr_TX_state <= EVNT; + -- ToDo + else + --BEGIN OF FIFO MANAGEMENT + if (cts_read = '0') then + case buf_fifo_cnt is + when "00" => buf_fifo_0 := fifo_data_out(35 downto 0); + buf_fifo_cnt := "01"; + + when "01" => buf_fifo_1 := fifo_data_out(35 downto 0); + buf_fifo_cnt := "10"; + + when "10" => buf_fifo_2 := fifo_data_out(35 downto 0); + buf_fifo_cnt := "11"; + + when "11" => null; + end case; + else + if buf_fifo_cnt /= "00" then + pckr_TX_data := buf_fifo_0(31 downto 0); + pckr_TX_data_type := buf_fifo_0(35 downto 32); + buf_fifo_0 := buf_fifo_1; + buf_fifo_1 := buf_fifo_2; + buf_fifo_cnt := std_logic_vector(unsigned(buf_fifo_cnt) - 1); + else -- buffer empty + pckr_TX_data := fifo_data_out(31 downto 0); + pckr_TX_data_type := fifo_data_out(35 downto 32); + end if; + end if; + + if buf_fifo_cnt = "11" then + enable_fifo_rdEn := '0'; + end if; + --END OF FIFO MANAGEMENT + + if (pckr_TX_data_ready = '1') and (pckr_TX_data_type = x"1") then + EvInf_TX := pckr_TX_data; + end if; + + if (pckr_TX_data_ready = '1') and (pckr_TX_data_type = x"2") then + EvLength_TX := pckr_TX_data(31 downto 16); + EvLength_TX_cntr := pckr_TX_data(31 downto 16); + Header_ready := '1'; + end if; + + + case pckr_TX_state is + when EVNT => + if cts_start_readout = '1' then + cts_data <= EvInf_TX; + cts_length <= EvLength_TX; + + if Header_ready = '1' then + cts_dataready <= '1'; + if cts_read = '1' then + pckr_TX_state <= DATA; + end if; + else + cts_dataready <= '0'; + end if; + + if (pckr_fifo_empty = '0' and cts_read = '1' and enable_fifo_rdEn = '1') then --could be optimised with deleting cts_read + fifo_rdEn <= '1'; + end if; + --EvInf_data <= (others => '0'); + --Header_ready := '0'; + end if; + when DATA => + if pckr_TX_data_type = x"3" then + cts_data <= pckr_TX_data; + cts_dataready <= '1'; + if cts_read = '1' then + EvLength_TX_cntr := EvLength_TX_cntr - 1; + + if enable_fifo_rdEn = '1' then + fifo_rdEn <= '1'; + end if; + + end if; + if EvLength_TX_cntr = x"0000" then + pckr_TX_state <= FINISH; + end if; + end if; + + when FINISH => + cts_finished <= '1'; + pckr_TX_state <= EVNT; + + when others => + null; + end case; + end if; + end process; + + + THE_FIFO_36x64 : fifo_36x32k_oreg + port map ( + Data(31 downto 0) => pckr_Data, + Data(35 downto 32) => pckr_Data_type, + Clock => clk_sys, + WrEn => pckr_Data_ready, + RdEn => fifo_rdEn, + Reset => reset_i, + AmFullThresh(14 downto 0)=> b"111111111111111", + Q => fifo_data_out, + WCNT(15 downto 0) => open, + Empty => pckr_fifo_empty, + Full => pckr_fifo_full, + AlmostFull => open); + +--rdack <= ctrlbus_tx.rack or ctrlbus_tx.ack; +--wrack <= ctrlbus_tx.wack or ctrlbus_tx.ack; + +-- gen_media_record : for i in 0 to INTERFACE_NUM-1 generate +-- med_data_in(i*16+15 downto i*16) <= med2int(i).data; +-- med_packet_num_in(i*3+2 downto i*3) <= med2int(i).packet_num; +-- med_dataready_in(i) <= med2int(i).dataready; +-- med_read_in(i) <= med2int(i).tx_read; +-- med_stat_op(i*16+15 downto i*16) <= med2int(i).stat_op; +-- +-- int2med(i).data <= med_data_out(i*16+15 downto i*16); +-- int2med(i).packet_num <= med_packet_num_out(i*3+2 downto i*3); +-- int2med(i).dataready <= med_dataready_out(i); +-- int2med(i).ctrl_op <= med_ctrl_op(i*16+15 downto i*16); +-- end generate; + + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 6, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"b600", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 9, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => handlerbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bustc_rx, --Clock switch + BUS_RX(2) => bussci_rx(0), --SCI Serdes + BUS_RX(3) => bussci_rx(1), + BUS_RX(4) => bussci_rx(2), + BUS_RX(5) => bussci_rx(3), + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bustc_tx, + BUS_TX(2) => bussci_tx(0), + BUS_TX(3) => bussci_tx(1), + BUS_TX(4) => bussci_tx(2), + BUS_TX(5) => bussci_tx(3), + STAT_DEBUG => open + ); + + handlerbus_rx <= ctrlbus_rx when bus_master_active = '0' else bus_master_out; + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS: entity work.trb3sc_tools + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => FLASH_CS, + FLASH_CLK => FLASH_CLK, + FLASH_IN => FLASH_OUT, + FLASH_OUT => FLASH_IN, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15), + --SPI + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT=> spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, + --Header + HEADER_IO => header_io, + ADDITIONAL_REG(0) => led_off_i, + ADDITIONAL_REG(2 downto 1) => trigger_select_i, + ADDITIONAL_REG(15 downto 4) => master_ready_override_i, + ADDITIONAL_REG(27 downto 16)=> enable_ldo_i, + --LCD + LCD_DATA_IN => lcd_data, + --ADC + ADC_CS => ADC_CS, + ADC_MOSI => ADC_DIN, + ADC_MISO => ADC_DOUT, + ADC_CLK => ADC_CLK, + --Trigger & Monitor + MONITOR_INPUTS => monitor_inputs_i(25 downto 0), + TRIG_GEN_INPUTS => monitor_inputs_i(23 downto 0), + TRIG_GEN_OUTPUTS => trig_gen_out_i, + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => ctrlbus_tx, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => open + ); + + + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + --LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2) + LED_GREEN <= debug_clock_reset(0) or led_off_i; + LED_ORANGE <= debug_clock_reset(1) or led_off_i; + LED_RED <= not sed_error_i or led_off_i; + LED_YELLOW <= debug_clock_reset(2) or led_off_i; + + LED_SFP_GREEN <= not med2int(12).stat_op(9) or led_off_i; --SFP Link Status + LED_SFP_RED <= not (med2int(12).stat_op(10) or med2int(12).stat_op(11)) or led_off_i; --SFP RX/TX + + LED_RJ_GREEN <= (CLOCK_SELECT_IN or led_off_i) & (not trigger_select_i(0) or led_off_i); + LED_RJ_RED <= (not reset_i or led_off_i) & (not trigger_select_i(1) or led_off_i); + + + TRIGGER_SEL_OUT(1) <= trigger_select_i(0); -- older version: not + TRIGGER_SEL_OUT(2) <= trigger_select_i(1); -- older version: not + BACK_LDO_EN <= not enable_ldo_i; + BACK_SPARE <= (others => 'Z'); --this is programn on dirich! + +--------------------------------------------------------------------------- +-- LCD Data to display +--------------------------------------------------------------------------- +-- lcd_data(15 downto 0) <= timer.network_address; +-- lcd_data(47 downto 16) <= timer.microsecond; +-- lcd_data(79 downto 48) <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)); +-- lcd_data(91 downto 80) <= timer.temperature; +-- lcd_data(95 downto 92) <= x"0"; +-- lcd_data(159 downto 96) <= timer.uid; +-- lcd_data(511 downto 160) <= (others => '0'); + +--------------------------------------------------------------------------- +-- Monitoring & Trigger +--------------------------------------------------------------------------- + + TRIGGER_TO_CTS <= trig_gen_out_i(1); + RJ45_SIG_4 <= trig_gen_out_i(0); + TRIGGER_OUT <= RJ45_SIG_1; + + monitor_inputs_i(11 downto 0) <= BACK_TRIG1; + monitor_inputs_i(23 downto 12) <= BACK_TRIG2; + monitor_inputs_i(25 downto 24) <= trig_gen_out_i(1 downto 0); + + +--------------------------------------------------------------------------- +-- Test Circuits +--------------------------------------------------------------------------- + process begin + wait until rising_edge(clk_sys); + time_counter <= time_counter + 1; + if reset_i = '1' then + time_counter <= (others => '0'); + end if; + end process; + + + TEST_LINE(10 downto 1) <= header_io; + TEST_LINE(18 downto 11) <= (others => '0'); + + TEST_JTAG(20 downto 7) <= (others => '0'); + + POWER_BOARD_IO(1) <= spi_clk(6); + POWER_BOARD_IO(2) <= spi_mosi(6); + POWER_BOARD_IO(3) <= spi_cs(6); + spi_miso(5) <= POWER_BOARD_IO(4); + spi_miso(6) <= POWER_BOARD_IO(4); + + +end architecture; + + + diff --git a/combiner_calib/compile.pl b/combiner_calib/compile.pl new file mode 120000 index 0000000..8a19aa6 --- /dev/null +++ b/combiner_calib/compile.pl @@ -0,0 +1 @@ +../../trb3sc/scripts/compile.pl \ No newline at end of file diff --git a/combiner_calib/config.vhd b/combiner_calib/config.vhd new file mode 100644 index 0000000..a2b9139 --- /dev/null +++ b/combiner_calib/config.vhd @@ -0,0 +1,121 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; +use work.trb_net16_hub_func.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; + constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented. + constant CLOCK_FAST_SELECT : integer := c_YES; --fast clock select (135us) or slow (280ms)? + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F3DC"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"52"; + + constant INCLUDE_ADC : integer := c_NO; + constant INCLUDE_UART : integer := c_YES; + constant INCLUDE_SPI : integer := c_YES; + constant INCLUDE_LCD : integer := c_NO; + constant INCLUDE_DEBUG_INTERFACE: integer := c_YES; + + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; + constant INCLUDE_STATISTICS : integer := c_YES; + constant TRIG_GEN_INPUT_NUM : integer := 24; + constant TRIG_GEN_OUTPUT_NUM : integer := 2; + constant MONITOR_INPUT_NUM : integer := 26; + + constant INCLUDE_GBE : integer := c_NO; + + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + type data_t is array (0 to 1023) of std_logic_vector(7 downto 0); + constant LCD_DATA : data_t := ( + x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00", --config don't touch + x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C", --config don't touch + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch + + x"54", x"72", x"62", x"33", x"73", x"63", x"0a", + x"0a", + x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"80", x"0a", + x"55", x"49", x"44", x"20", x"20", x"89", x"88", x"87", x"86", x"0a", + x"43", x"6f", x"6d", x"70", x"69", x"6c", x"65", x"54", x"69", x"6d", x"65", x"20", x"20", x"84", x"83", x"0a", + x"54", x"69", x"6d", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"82", x"81", x"0a", + x"54", x"65", x"6d", x"70", x"65", x"72", x"61", x"74", x"75", x"72", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"85", x"0a", + others => x"00"); + + + + + constant INTERFACE_NUM : integer := 13; + constant MII_IS_UPLINK : hub_mii_config_t := (0,0,0,0, 0,0,0,0, 0,0,0,0, 1,1,1,0,0); + constant MII_IS_DOWNLINK : hub_mii_config_t := (1,1,1,1, 1,1,1,1, 1,1,1,1, 1,0,0,0,0); + constant MII_IS_UPLINK_ONLY : hub_mii_config_t := (0,0,0,0, 0,0,0,0, 0,0,0,0, 0,1,1,0,0); + + + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"97000000"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( + HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1 +-- t(16 downto 16) := std_logic_vector(to_unsigned(USE_ETHERNET,1)); + t(17 downto 17) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); --sctrl via GbE + t(23 downto 23) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); + t(26 downto 24) := std_logic_vector(to_unsigned(1,3)); --num SFPs with TrbNet + t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/combiner_calib/config_compile_frankfurt.pl b/combiner_calib/config_compile_frankfurt.pl new file mode 100644 index 0000000..c92c501 --- /dev/null +++ b/combiner_calib/config_compile_frankfurt.pl @@ -0,0 +1,20 @@ +TOPNAME => "combiner", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1702\@jspc29", +lattice_path => '/d/jspc29/lattice/diamond/3.9_x64', +synplify_path => '/d/jspc29/lattice/synplify/K-2015.09/', +# synplify_command => "/d/jspc29/lattice/diamond/3.7_x64/bin/lin64/synpwrap -fg -options", +#synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", +#synplify_command => "ssh -p 52238 jmichel\@cerberus \"cd /home/jmichel/git/dirich/combiner/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/L-2016.09-1/bin/synplify_premier_dp -batch ../combiner.prj\" #", +nodelist_file => 'nodelist_frankfurt.txt', + + +#Include only necessary lpf files +#pinout_file => '', #name of pin-out file, if not equal TOPNAME +include_TDC => 0, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, + diff --git a/combiner_calib/config_compile_gsi.pl b/combiner_calib/config_compile_gsi.pl new file mode 100644 index 0000000..4a4edb6 --- /dev/null +++ b/combiner_calib/config_compile_gsi.pl @@ -0,0 +1,22 @@ +#Familyname => 'ECP5UM', +#Devicename => 'LFE5UM-85F', +#Package => 'CABGA381', +#Speedgrade => '8', + +TOPNAME => "combiner", +lm_license_file_for_synplify => "27000\@lxcad03.gsi.de", +lm_license_file_for_par => "1702\@hadeb05.gsi.de", +lattice_path => '/opt/lattice/diamond/3.8_x64', +synplify_path => '/opt/synplicity/K-2015.09', +##synplify_command => "/opt/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options", +#synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp", + +nodelist_file => '../nodes_lxhadeb07.txt', +#pinout_file => 'dirich', + + +include_TDC => 0, +include_GBE => 0, + +firefox_open => 0, +twr_number_of_errors => 20, diff --git a/combiner_calib/core/FIFO_36x128.ipx b/combiner_calib/core/FIFO_36x128.ipx new file mode 100644 index 0000000..455cd64 --- /dev/null +++ b/combiner_calib/core/FIFO_36x128.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/combiner_calib/core/FIFO_36x128.lpc b/combiner_calib/core/FIFO_36x128.lpc new file mode 100644 index 0000000..e957cf9 --- /dev/null +++ b/combiner_calib/core/FIFO_36x128.lpc @@ -0,0 +1,48 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=5.1 +ModuleName=FIFO_36x128 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=07/18/2018 +Time=14:24:04 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=128 +Width=36 +regout=0 +CtrlByRdEn=0 +EmpFlg=1 +PeMode=Static - Dual Threshold +PeAssert=2 +PeDeassert=4 +FullFlg=1 +PfMode=Static - Dual Threshold +PfAssert=126 +PfDeassert=124 +RDataCount=0 +EnECC=0 +EnFWFT=0 + +[Command] +cmd_line= -w -n FIFO_36x128 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 7 -data_width 36 -num_words 128 -no_enable -pe 2 -pe2 4 -pf 126 -pf2 124 diff --git a/combiner_calib/core/FIFO_36x128.vhd b/combiner_calib/core/FIFO_36x128.vhd new file mode 100644 index 0000000..2d4ee0a --- /dev/null +++ b/combiner_calib/core/FIFO_36x128.vhd @@ -0,0 +1,764 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.1.502 +-- Module Version: 5.1 +--/home/soft/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x128 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 128 -width 36 -depth 128 -no_enable -pe 2 -pe2 4 -pf 126 -pf2 124 + +-- Wed Jul 18 14:24:04 2018 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity FIFO_36x128 is + port ( + Data: in std_logic_vector(35 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(35 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic; + AlmostFull: out std_logic); +end FIFO_36x128; + +architecture Structure of FIFO_36x128 is + + -- internal signal declarations + signal invout_2: std_logic; + signal invout_1: std_logic; + signal rden_i_inv: std_logic; + signal invout_0: std_logic; + signal r_nw_inv: std_logic; + signal r_nw: std_logic; + signal fcnt_en_inv: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal ae: std_logic; + signal ae_d: std_logic; + signal af: std_logic; + signal af_d: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal ifcount_5: std_logic; + signal co1: std_logic; + signal ifcount_6: std_logic; + signal ifcount_7: std_logic; + signal co3: std_logic; + signal co2: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal co2_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal co0_2: std_logic; + signal co1_2: std_logic; + signal co2_2: std_logic; + signal wren_i: std_logic; + signal wren_i_inv: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1_3: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co3_1: std_logic; + signal co2_3: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co3_2: std_logic; + signal co2_4: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal cmp_ci_2: std_logic; + signal co0_5: std_logic; + signal co1_5: std_logic; + signal co2_5: std_logic; + signal ae_set_d: std_logic; + signal ae_set_d_c: std_logic; + signal cmp_ci_3: std_logic; + signal co0_6: std_logic; + signal co1_6: std_logic; + signal co2_6: std_logic; + signal ae_clr_d: std_logic; + signal ae_clr_d_c: std_logic; + signal cmp_ci_4: std_logic; + signal co0_7: std_logic; + signal co1_7: std_logic; + signal co2_7: std_logic; + signal af_set_d: std_logic; + signal af_set_d_c: std_logic; + signal cmp_ci_5: std_logic; + signal fcnt_en_inv_inv: std_logic; + signal cnt_con: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_8: std_logic; + signal cnt_con_inv: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_8: std_logic; + signal fcount_4: std_logic; + signal fcount_5: std_logic; + signal co2_8: std_logic; + signal scuba_vhi: std_logic; + signal fcount_6: std_logic; + signal fcount_7: std_logic; + signal af_clr_d: std_logic; + signal af_clr_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component ALEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; LE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component CB2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CON: in std_logic; CO: out std_logic; NC0: out std_logic; + NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component PDPW16KC + generic (GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_36x128.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t4: AND2 + port map (A=>WrEn, B=>invout_2, Z=>wren_i); + + INV_8: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t3: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_7: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t2: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t1: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_6: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_5: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_3: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_2: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + AND2_t0: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_4: INV + port map (A=>wren_i, Z=>invout_0); + + INV_3: INV + port map (A=>fcnt_en, Z=>fcnt_en_inv); + + INV_2: INV + port map (A=>cnt_con, Z=>cnt_con_inv); + + INV_1: INV + port map (A=>r_nw, Z=>r_nw_inv); + + INV_0: INV + port map (A=>fcnt_en_inv, Z=>fcnt_en_inv_inv); + + LUT4_1: ROM16X1A + generic map (initval=> X"4450") + port map (AD3=>ae, AD2=>ae_set_d, AD1=>ae_clr_d, AD0=>scuba_vlo, + DO0=>ae_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"4450") + port map (AD3=>af, AD2=>af_set_d, AD1=>af_clr_d, AD0=>scuba_vlo, + DO0=>af_d); + + pdp_ram_0_0_0: PDPW16KC + generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), + DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), + DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), + DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), + DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), + DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), + ADW0=>wcount_0, ADW1=>wcount_1, ADW2=>wcount_2, + ADW3=>wcount_3, ADW4=>wcount_4, ADW5=>wcount_5, + ADW6=>wcount_6, ADW7=>scuba_vlo, ADW8=>scuba_vlo, + BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, + BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW0=>scuba_vhi, + CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, + ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, + ADR4=>scuba_vlo, ADR5=>rcount_0, ADR6=>rcount_1, + ADR7=>rcount_2, ADR8=>rcount_3, ADR9=>rcount_4, + ADR10=>rcount_5, ADR11=>rcount_6, ADR12=>scuba_vlo, + ADR13=>scuba_vlo, CER=>rden_i, CLKR=>Clock, CSR0=>scuba_vlo, + CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), + DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), + DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), + DO11=>Q(29), DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), + DO15=>Q(33), DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), + DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), + DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), + DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), + DO33=>Q(15), DO34=>Q(16), DO35=>Q(17)); + + FF_27: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_26: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_25: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_24: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_23: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_22: FD1P3DX + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_21: FD1P3DX + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_20: FD1P3DX + port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_7); + + FF_19: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_18: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_17: FD1P3DX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_0); + + FF_16: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_15: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_14: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_13: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_12: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_11: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_10: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_7); + + FF_9: FD1P3DX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_0); + + FF_8: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_7: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_6: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_5: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_4: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_3: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_2: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_7); + + FF_1: FD1S3BX + port map (D=>ae_d, CK=>Clock, PD=>Reset, Q=>ae); + + FF_0: FD1S3DX + port map (D=>af_d, CK=>Clock, CD=>Reset, Q=>af); + + bdcnt_bctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open); + + bdcnt_bctr_0: CB2 + port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1, + CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1); + + bdcnt_bctr_1: CB2 + port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con, + CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3); + + bdcnt_bctr_2: CB2 + port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con, + CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5); + + bdcnt_bctr_3: CB2 + port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con, + CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7); + + e_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, + S1=>open); + + e_cmp_0: ALEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo, + CI=>cmp_ci, LE=>co0_1); + + e_cmp_1: ALEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co0_1, LE=>co1_1); + + e_cmp_2: ALEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co1_1, LE=>co2_1); + + e_cmp_3: ALEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co2_1, LE=>cmp_le_1_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1, + S1=>open); + + g_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, + S1=>open); + + g_cmp_0: AGEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + CI=>cmp_ci_1, GE=>co0_2); + + g_cmp_1: AGEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + CI=>co0_2, GE=>co1_2); + + g_cmp_2: AGEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + CI=>co1_2, GE=>co2_2); + + g_cmp_3: AGEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i_inv, + CI=>co2_2, GE=>cmp_ge_d1_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1, + S1=>open); + + w_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open, + S1=>open); + + w_ctr_0: CU2 + port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_ctr_1: CU2 + port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_ctr_2: CU2 + port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_ctr_3: CU2 + port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_1, + NC0=>iwcount_6, NC1=>iwcount_7); + + r_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open, + S1=>open); + + r_ctr_0: CU2 + port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4, + NC0=>ircount_0, NC1=>ircount_1); + + r_ctr_1: CU2 + port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4, + NC0=>ircount_2, NC1=>ircount_3); + + r_ctr_2: CU2 + port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4, + NC0=>ircount_4, NC1=>ircount_5); + + r_ctr_3: CU2 + port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_2, + NC0=>ircount_6, NC1=>ircount_7); + + ae_set_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, + S1=>open); + + ae_set_cmp_0: ALEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv, + B1=>cnt_con_inv, CI=>cmp_ci_2, LE=>co0_5); + + ae_set_cmp_1: ALEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co0_5, LE=>co1_5); + + ae_set_cmp_2: ALEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co1_5, LE=>co2_5); + + ae_set_cmp_3: ALEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co2_5, LE=>ae_set_d_c); + + a2: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>ae_set_d_c, COUT=>open, S0=>ae_set_d, + S1=>open); + + ae_clr_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, + S1=>open); + + ae_clr_cmp_0: ALEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv, + B1=>cnt_con, CI=>cmp_ci_3, LE=>co0_6); + + ae_clr_cmp_1: ALEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con_inv, + B1=>scuba_vlo, CI=>co0_6, LE=>co1_6); + + ae_clr_cmp_2: ALEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co1_6, LE=>co2_6); + + ae_clr_cmp_3: ALEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co2_6, LE=>ae_clr_d_c); + + a3: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>ae_clr_d_c, COUT=>open, S0=>ae_clr_d, + S1=>open); + + af_set_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_4, S0=>open, + S1=>open); + + af_set_cmp_0: AGEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv, + B1=>cnt_con_inv, CI=>cmp_ci_4, GE=>co0_7); + + af_set_cmp_1: AGEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>co0_7, GE=>co1_7); + + af_set_cmp_2: AGEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>co1_7, GE=>co2_7); + + af_set_cmp_3: AGEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vhi, + B1=>scuba_vlo, CI=>co2_7, GE=>af_set_d_c); + + a4: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_set_d_c, COUT=>open, S0=>af_set_d, + S1=>open); + + af_clr_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_5, S0=>open, + S1=>open); + + af_clr_cmp_0: AGEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv, + B1=>cnt_con, CI=>cmp_ci_5, GE=>co0_8); + + af_clr_cmp_1: AGEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con_inv, + B1=>scuba_vhi, CI=>co0_8, GE=>co1_8); + + af_clr_cmp_2: AGEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>co1_8, GE=>co2_8); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + af_clr_cmp_3: AGEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vhi, + B1=>scuba_vlo, CI=>co2_8, GE=>af_clr_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a5: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_clr_d_c, COUT=>open, S0=>af_clr_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; + AlmostEmpty <= ae; + AlmostFull <= af; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of FIFO_36x128 is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:ALEB2 use entity ecp3.ALEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:CB2 use entity ecp3.CB2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/combiner_calib/core/FIFO_36x64.ipx b/combiner_calib/core/FIFO_36x64.ipx new file mode 100644 index 0000000..c52a28e --- /dev/null +++ b/combiner_calib/core/FIFO_36x64.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/combiner_calib/core/FIFO_36x64.lpc b/combiner_calib/core/FIFO_36x64.lpc new file mode 100644 index 0000000..29d7df3 --- /dev/null +++ b/combiner_calib/core/FIFO_36x64.lpc @@ -0,0 +1,48 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=5.1 +ModuleName=FIFO_36x64 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=07/18/2018 +Time=14:24:47 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=64 +Width=36 +regout=0 +CtrlByRdEn=0 +EmpFlg=1 +PeMode=Static - Dual Threshold +PeAssert=2 +PeDeassert=4 +FullFlg=1 +PfMode=Static - Dual Threshold +PfAssert=62 +PfDeassert=60 +RDataCount=0 +EnECC=0 +EnFWFT=0 + +[Command] +cmd_line= -w -n FIFO_36x64 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -addr_width 6 -data_width 36 -num_words 64 -no_enable -pe 2 -pe2 4 -pf 62 -pf2 60 diff --git a/combiner_calib/core/FIFO_36x64.vhd b/combiner_calib/core/FIFO_36x64.vhd new file mode 100644 index 0000000..9f604b5 --- /dev/null +++ b/combiner_calib/core/FIFO_36x64.vhd @@ -0,0 +1,743 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.1.502 +-- Module Version: 5.1 +--/home/soft/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n FIFO_36x64 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 64 -width 36 -depth 64 -no_enable -pe 2 -pe2 4 -pf 62 -pf2 60 + +-- Wed Jul 18 14:24:47 2018 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity FIFO_36x64 is + port ( + Data: in std_logic_vector(35 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(35 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic; + AlmostFull: out std_logic); +end FIFO_36x64; + +architecture Structure of FIFO_36x64 is + + -- internal signal declarations + signal invout_2: std_logic; + signal invout_1: std_logic; + signal rden_i_inv: std_logic; + signal invout_0: std_logic; + signal r_nw_inv: std_logic; + signal r_nw: std_logic; + signal fcnt_en_inv: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal ae: std_logic; + signal ae_d: std_logic; + signal af: std_logic; + signal af_d: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal ifcount_5: std_logic; + signal co1: std_logic; + signal ifcount_6: std_logic; + signal co3: std_logic; + signal co2: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal co2_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal co0_2: std_logic; + signal co1_2: std_logic; + signal wren_i: std_logic; + signal co2_2: std_logic; + signal wren_i_inv: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1_3: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal iwcount_6: std_logic; + signal co3_1: std_logic; + signal co2_3: std_logic; + signal wcount_6: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal ircount_6: std_logic; + signal co3_2: std_logic; + signal co2_4: std_logic; + signal rcount_6: std_logic; + signal cmp_ci_2: std_logic; + signal co0_5: std_logic; + signal co1_5: std_logic; + signal co2_5: std_logic; + signal ae_set_d: std_logic; + signal ae_set_d_c: std_logic; + signal cmp_ci_3: std_logic; + signal co0_6: std_logic; + signal co1_6: std_logic; + signal co2_6: std_logic; + signal ae_clr_d: std_logic; + signal ae_clr_d_c: std_logic; + signal cmp_ci_4: std_logic; + signal co0_7: std_logic; + signal co1_7: std_logic; + signal co2_7: std_logic; + signal af_set_d: std_logic; + signal af_set_d_c: std_logic; + signal cmp_ci_5: std_logic; + signal fcnt_en_inv_inv: std_logic; + signal cnt_con: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_8: std_logic; + signal cnt_con_inv: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_8: std_logic; + signal scuba_vhi: std_logic; + signal fcount_4: std_logic; + signal fcount_5: std_logic; + signal co2_8: std_logic; + signal fcount_6: std_logic; + signal af_clr_d: std_logic; + signal af_clr_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component ALEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; LE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component CB2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CON: in std_logic; CO: out std_logic; NC0: out std_logic; + NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component PDPW16KC + generic (GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_36x64.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t4: AND2 + port map (A=>WrEn, B=>invout_2, Z=>wren_i); + + INV_8: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t3: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_7: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t2: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t1: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_6: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_5: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_3: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_2: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + AND2_t0: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_4: INV + port map (A=>wren_i, Z=>invout_0); + + INV_3: INV + port map (A=>fcnt_en, Z=>fcnt_en_inv); + + INV_2: INV + port map (A=>cnt_con, Z=>cnt_con_inv); + + INV_1: INV + port map (A=>r_nw, Z=>r_nw_inv); + + INV_0: INV + port map (A=>fcnt_en_inv, Z=>fcnt_en_inv_inv); + + LUT4_1: ROM16X1A + generic map (initval=> X"4450") + port map (AD3=>ae, AD2=>ae_set_d, AD1=>ae_clr_d, AD0=>scuba_vlo, + DO0=>ae_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"4450") + port map (AD3=>af, AD2=>af_set_d, AD1=>af_clr_d, AD0=>scuba_vlo, + DO0=>af_d); + + pdp_ram_0_0_0: PDPW16KC + generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), + DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), + DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), + DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), + DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), + DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), + ADW0=>wcount_0, ADW1=>wcount_1, ADW2=>wcount_2, + ADW3=>wcount_3, ADW4=>wcount_4, ADW5=>wcount_5, + ADW6=>scuba_vlo, ADW7=>scuba_vlo, ADW8=>scuba_vlo, + BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, + BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW0=>scuba_vhi, + CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, + ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, + ADR4=>scuba_vlo, ADR5=>rcount_0, ADR6=>rcount_1, + ADR7=>rcount_2, ADR8=>rcount_3, ADR9=>rcount_4, + ADR10=>rcount_5, ADR11=>scuba_vlo, ADR12=>scuba_vlo, + ADR13=>scuba_vlo, CER=>rden_i, CLKR=>Clock, CSR0=>scuba_vlo, + CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), + DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), + DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), + DO11=>Q(29), DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), + DO15=>Q(33), DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), + DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), + DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), + DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), + DO33=>Q(15), DO34=>Q(16), DO35=>Q(17)); + + FF_24: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_23: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_22: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_21: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_20: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_19: FD1P3DX + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_18: FD1P3DX + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_17: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_16: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_15: FD1P3DX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_0); + + FF_14: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_13: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_12: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_11: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_10: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_9: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_8: FD1P3DX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_0); + + FF_7: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_6: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_5: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_4: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_3: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_2: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_1: FD1S3BX + port map (D=>ae_d, CK=>Clock, PD=>Reset, Q=>ae); + + FF_0: FD1S3DX + port map (D=>af_d, CK=>Clock, CD=>Reset, Q=>af); + + bdcnt_bctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open); + + bdcnt_bctr_0: CB2 + port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1, + CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1); + + bdcnt_bctr_1: CB2 + port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con, + CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3); + + bdcnt_bctr_2: CB2 + port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con, + CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5); + + bdcnt_bctr_3: CB2 + port map (CI=>co2, PC0=>fcount_6, PC1=>scuba_vlo, CON=>cnt_con, + CO=>co3, NC0=>ifcount_6, NC1=>open); + + e_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, + S1=>open); + + e_cmp_0: ALEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo, + CI=>cmp_ci, LE=>co0_1); + + e_cmp_1: ALEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co0_1, LE=>co1_1); + + e_cmp_2: ALEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co1_1, LE=>co2_1); + + e_cmp_3: ALEB2 + port map (A0=>fcount_6, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co2_1, LE=>cmp_le_1_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1, + S1=>open); + + g_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, + S1=>open); + + g_cmp_0: AGEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + CI=>cmp_ci_1, GE=>co0_2); + + g_cmp_1: AGEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + CI=>co0_2, GE=>co1_2); + + g_cmp_2: AGEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + CI=>co1_2, GE=>co2_2); + + g_cmp_3: AGEB2 + port map (A0=>fcount_6, A1=>scuba_vlo, B0=>wren_i_inv, + B1=>scuba_vlo, CI=>co2_2, GE=>cmp_ge_d1_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1, + S1=>open); + + w_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open, + S1=>open); + + w_ctr_0: CU2 + port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_ctr_1: CU2 + port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_ctr_2: CU2 + port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_ctr_3: CU2 + port map (CI=>co2_3, PC0=>wcount_6, PC1=>scuba_vlo, CO=>co3_1, + NC0=>iwcount_6, NC1=>open); + + r_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open, + S1=>open); + + r_ctr_0: CU2 + port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4, + NC0=>ircount_0, NC1=>ircount_1); + + r_ctr_1: CU2 + port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4, + NC0=>ircount_2, NC1=>ircount_3); + + r_ctr_2: CU2 + port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4, + NC0=>ircount_4, NC1=>ircount_5); + + r_ctr_3: CU2 + port map (CI=>co2_4, PC0=>rcount_6, PC1=>scuba_vlo, CO=>co3_2, + NC0=>ircount_6, NC1=>open); + + ae_set_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, + S1=>open); + + ae_set_cmp_0: ALEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv, + B1=>cnt_con_inv, CI=>cmp_ci_2, LE=>co0_5); + + ae_set_cmp_1: ALEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co0_5, LE=>co1_5); + + ae_set_cmp_2: ALEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co1_5, LE=>co2_5); + + ae_set_cmp_3: ALEB2 + port map (A0=>fcount_6, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co2_5, LE=>ae_set_d_c); + + a2: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>ae_set_d_c, COUT=>open, S0=>ae_set_d, + S1=>open); + + ae_clr_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, + S1=>open); + + ae_clr_cmp_0: ALEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv, + B1=>cnt_con, CI=>cmp_ci_3, LE=>co0_6); + + ae_clr_cmp_1: ALEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con_inv, + B1=>scuba_vlo, CI=>co0_6, LE=>co1_6); + + ae_clr_cmp_2: ALEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co1_6, LE=>co2_6); + + ae_clr_cmp_3: ALEB2 + port map (A0=>fcount_6, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co2_6, LE=>ae_clr_d_c); + + a3: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>ae_clr_d_c, COUT=>open, S0=>ae_clr_d, + S1=>open); + + af_set_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_4, S0=>open, + S1=>open); + + af_set_cmp_0: AGEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv, + B1=>cnt_con_inv, CI=>cmp_ci_4, GE=>co0_7); + + af_set_cmp_1: AGEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>co0_7, GE=>co1_7); + + af_set_cmp_2: AGEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>co1_7, GE=>co2_7); + + af_set_cmp_3: AGEB2 + port map (A0=>fcount_6, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co2_7, GE=>af_set_d_c); + + a4: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_set_d_c, COUT=>open, S0=>af_set_d, + S1=>open); + + af_clr_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_5, S0=>open, + S1=>open); + + af_clr_cmp_0: AGEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv, + B1=>cnt_con, CI=>cmp_ci_5, GE=>co0_8); + + af_clr_cmp_1: AGEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con_inv, + B1=>scuba_vhi, CI=>co0_8, GE=>co1_8); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + af_clr_cmp_2: AGEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>co1_8, GE=>co2_8); + + af_clr_cmp_3: AGEB2 + port map (A0=>fcount_6, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co2_8, GE=>af_clr_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a5: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_clr_d_c, COUT=>open, S0=>af_clr_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; + AlmostEmpty <= ae; + AlmostFull <= af; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of FIFO_36x64 is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:ALEB2 use entity ecp3.ALEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:CB2 use entity ecp3.CB2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/combiner_calib/par.p2t b/combiner_calib/par.p2t new file mode 100644 index 0000000..c251db6 --- /dev/null +++ b/combiner_calib/par.p2t @@ -0,0 +1,21 @@ +-w +-i 15 +-l 5 +-n 1 +-y +-s 12 +-t 42 +-c 1 +-e 2 +#-g guidefile.ncd +#-m nodelist.txt +# -w +# -i 6 +# -l 5 +# -n 1 +# -t 1 +# -s 1 +# -c 0 +# -e 0 +# +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1 diff --git a/combiner_calib/synplify.fdc b/combiner_calib/synplify.fdc new file mode 100644 index 0000000..facf858 --- /dev/null +++ b/combiner_calib/synplify.fdc @@ -0,0 +1,50 @@ +###==== BEGIN Header + +# Synopsys, Inc. constraint file +# /d/jspc22/trb/git/trb3sc/template/synplify.fdc +# Written on Thu Jun 18 11:51:05 2015 +# by Synplify Pro, I-2014.03L-SP1 FDC Constraint Editor + +# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END. +# These sections are generated from SCOPE spreadsheet tabs. + +###==== END Header + +###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit) +###==== END Collections + +###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit) +create_clock -name {clk240} {p:CLOCK_PCLK} -period {5} +create_clock -name {clkfull} {n:THE_CLOCK_RESET.THE_INT_PLL.CLKOS} -period {5} +create_clock -name {clksys} {n:THE_CLOCK_RESET.THE_INT_PLL.CLKOP} -period {10} +create_clock -name {clkrxfull} {n:THE_MEDIA_INTERFACE.gen_pcs0\.THE_SERDES.rx_full_clk_ch0} -period {5} + +###==== END Clocks + +###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit) +###==== END "Generated Clocks" + +###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit) +###==== END Inputs/Outputs + + +###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit) +###==== END "Delay Paths" + +###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit) +###==== END Attributes + +###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit) +###==== END "I/O Standards" + +###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit) +###==== END "Compile Points" + + + + + + + + + -- 2.43.0