From a42d8ffd616d95ef310108bc37ce29a7c1de2a5b Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 18 Sep 2023 12:27:38 +0200 Subject: [PATCH] add few debug ports to GbE --- gbe_trb/base/gbe_logic_wrapper.vhd | 6 ++++-- gbe_trb/base/gbe_wrapper.vhd | 14 +++++++++----- 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/gbe_trb/base/gbe_logic_wrapper.vhd b/gbe_trb/base/gbe_logic_wrapper.vhd index 362a16e..4eea034 100644 --- a/gbe_trb/base/gbe_logic_wrapper.vhd +++ b/gbe_trb/base/gbe_logic_wrapper.vhd @@ -144,7 +144,8 @@ entity gbe_logic_wrapper is MONITOR_TX_PACKETS_OUT : out std_logic_vector(31 downto 0); MONITOR_DROPPED_OUT : out std_logic_vector(31 downto 0); MONITOR_GEN_DBG_OUT : out std_logic_vector(2 * c_MAX_PROTOCOLS * 32 - 1 downto 0); - MAKE_RESET_OUT : out std_logic + MAKE_RESET_OUT : out std_logic; + DEBUG_MAINCONTROL : out std_logic_vector(63 downto 0) ); end entity gbe_logic_wrapper; @@ -432,7 +433,8 @@ begin MONITOR_SELECT_DROP_OUT_OUT => dbg_select_drop_out, MONITOR_SELECT_GEN_DBG_OUT => dbg_select_gen, DATA_HIST_OUT => dbg_hist, - SCTRL_HIST_OUT => dbg_hist2 + SCTRL_HIST_OUT => dbg_hist2, + DEBUG_OUT => DEBUG_MAINCONTROL ); end generate main_gen; diff --git a/gbe_trb/base/gbe_wrapper.vhd b/gbe_trb/base/gbe_wrapper.vhd index 1faac46..2f50be9 100644 --- a/gbe_trb/base/gbe_wrapper.vhd +++ b/gbe_trb/base/gbe_wrapper.vhd @@ -208,6 +208,9 @@ architecture RTL of gbe_wrapper is signal issue_reboot : std_logic_vector(3 downto 0); signal my_ip : std_logic_vector(127 downto 0); + signal debug_maincontrol_i : std_logic_vector(63 downto 0); + + begin mac_impl_gen : if DO_SIMULATION = 0 generate mac_0 <= MC_UNIQUE_ID_IN(15 downto 8) & MC_UNIQUE_ID_IN(23 downto 16) & MC_UNIQUE_ID_IN(31 downto 24) & x"0" & MC_UNIQUE_ID_IN(35 downto 32) & x"7ada"; @@ -852,7 +855,8 @@ FWD_FULL_OUT => FWD_FULL_OUT(0), MONITOR_TX_PACKETS_OUT => monitor_tx_packets(1 * 32 - 1 downto 0 * 32), MONITOR_DROPPED_OUT => monitor_dropped(1 * 32 - 1 downto 0 * 32), MONITOR_GEN_DBG_OUT => open, - MAKE_RESET_OUT => make_reset0 + MAKE_RESET_OUT => make_reset0, + DEBUG_MAINCONTROL => debug_maincontrol_i ); end generate GEN_LINK_0; @@ -1193,10 +1197,10 @@ FWD_FULL_OUT => FWD_FULL_OUT(0), sum_tx_packets <= monitor_tx_packets(4 * 32 - 1 downto 3 * 32) + monitor_tx_packets(3 * 32 - 1 downto 2 * 32) + monitor_tx_packets(2 * 32 - 1 downto 1 * 32) + monitor_tx_packets(1 * 32 - 1 downto 0 * 32); sum_dropped <= monitor_dropped(4 * 32 - 1 downto 3 * 32) + monitor_dropped(3 * 32 - 1 downto 2 * 32) + monitor_dropped(2 * 32 - 1 downto 1 * 32) + monitor_dropped(1 * 32 - 1 downto 0 * 32); - include_debug_gen : if (INCLUDE_DEBUG = 1) generate - DEBUG_OUT(63 downto 0) <= monitor_gen_dbg(4 * 64 - 1 downto 3 * 64); - DEBUG_OUT(127 downto 65) <= (others => '0'); - end generate; + --include_debug_gen : if (INCLUDE_DEBUG = 1) generate + DEBUG_OUT(63 downto 0) <= monitor_gen_dbg(4 * 64 - 1 downto 3 * 64); + DEBUG_OUT(127 downto 64) <= debug_maincontrol_i; + --end generate; testbench_sim : if DO_SIMULATION = 1 generate clk_125_rx_from_pcs(0) <= CLK_125_IN; -- 2.43.0