From a4aa83457f98dc1776e412996de23c347b3ddbab Mon Sep 17 00:00:00 2001 From: Manuel Penschuck Date: Tue, 22 Oct 2013 18:15:05 +0200 Subject: [PATCH] Changes in order to simulate design --- cbmnet/code/cbmnet_interface_pkg.vhd | 6 +- cbmnet/code/cbmnet_phy_ecp3.vhd | 23 ++- cbmnet/code/cbmnet_phy_ecp3_rx_reset_fsm.vhd | 37 ++-- cbmnet/code/cbmnet_phy_ecp3_tx_reset_fsm.vhd | 174 +++++++++++++++++++ cbmnet/code/cbmnet_phy_pkg.vhd | 30 +++- cbmnet/code/cbmnet_phy_rx_gear.vhd | 143 +++++++-------- cbmnet/code/cbmnet_phy_tx_gear.vhd | 21 +-- cbmnet/code/tb_cbmnet_phy_rx_gear.vhd | 62 +++++++ cbmnet/code/tb_cbmnet_phy_tx_gear.vhd | 50 ++++++ cbmnet/code/tb_phy_ecp3.vhd | 39 +---- cbmnet/test/info | 4 +- cbmnet/test/start | 6 +- cbmnet/trb3_periph_cbmnet.prj | 3 +- 13 files changed, 450 insertions(+), 148 deletions(-) create mode 100644 cbmnet/code/cbmnet_phy_ecp3_tx_reset_fsm.vhd create mode 100644 cbmnet/code/tb_cbmnet_phy_rx_gear.vhd create mode 100644 cbmnet/code/tb_cbmnet_phy_tx_gear.vhd diff --git a/cbmnet/code/cbmnet_interface_pkg.vhd b/cbmnet/code/cbmnet_interface_pkg.vhd index 9160d06..5ec8f55 100644 --- a/cbmnet/code/cbmnet_interface_pkg.vhd +++ b/cbmnet/code/cbmnet_interface_pkg.vhd @@ -54,9 +54,9 @@ package cbmnet_interface_pkg is component gtp_tx_ready_module is generic ( - READY_CHAR0 : std_logic_vector(7 downto 0) := K284; - READY_CHAR1 : std_logic_vector(7 downto 0) := K287; - ALIGN_CHAR : std_logic_vector(7 downto 0) := K285; +-- READY_CHAR0 : std_logic_vector(7 downto 0) := K284; +-- READY_CHAR1 : std_logic_vector(7 downto 0) := K287; +-- ALIGN_CHAR : std_logic_vector(7 downto 0) := K285; DATAWIDTH : integer := 16; WORDS :integer := 2 --DATAWIDTH/8; ); diff --git a/cbmnet/code/cbmnet_phy_ecp3.vhd b/cbmnet/code/cbmnet_phy_ecp3.vhd index 5937722..50256bb 100644 --- a/cbmnet/code/cbmnet_phy_ecp3.vhd +++ b/cbmnet/code/cbmnet_phy_ecp3.vhd @@ -14,6 +14,7 @@ use work.cbmnet_phy_pkg.all; entity cbmnet_phy_ecp3 is generic( IS_SYNC_SLAVE : integer := c_NO; --select slave mode + IS_SIMULATED : integer := c_NO; INCL_DEBUG_AIDS : integer := c_YES ); port( @@ -155,7 +156,8 @@ architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is signal tx_data_i : std_logic_vector(17 downto 0); -- 16(+2) bit word generated fed to gear signal tx_gear_reset_i : std_logic; - + signal rx_gear_debug_i : std_logic_vector(15 downto 0); + -- CBMNet Ready Managers signal rm_rx_ready_i : std_logic; signal rm_rx_almost_ready_i : std_logic; @@ -283,6 +285,9 @@ begin -- Reset FSM & Link states ------------------------------------------------- THE_RX_FSM : cbmnet_phy_ecp3_rx_reset_fsm + generic map ( + IS_SIMULATED => IS_SIMULATED + ) port map( RST_N => rst_n_i, RX_REFCLK => clk_125_local, @@ -303,7 +308,10 @@ begin rx_error_delay <= rx_error_delay(rx_error_delay'high - 1 downto 0) & rx_dec_error_i when rising_edge(clk_125_local); - THE_TX_FSM : tx_reset_fsm + THE_TX_FSM : cbmnet_phy_ecp3_tx_reset_fsm + generic map ( + IS_SIMULATED => IS_SIMULATED + ) port map( RST_N => rst_n_i, TX_REFCLK => clk_125_local, @@ -337,7 +345,9 @@ begin RM_RESET_IN => rm_rx_to_gear_reset_i, -- in std_logic; CLK_125_OUT => rclk_125_i, -- out std_logic; RESET_OUT => gear_to_rm_rst_i, -- out std_logic; - DATA_OUT => rx_data_from_gear_i -- out std_logic_vector(17 downto 0) + DATA_OUT => rx_data_from_gear_i, -- out std_logic_vector(17 downto 0) + + DEBUG_OUT => rx_gear_debug_i ); rx_data_i <= rx_data_from_gear_i when rising_edge(clk_125_local) or (IS_SYNC_SLAVE = c_YES); @@ -345,8 +355,8 @@ begin THE_TX_GEAR: CBMNET_PHY_TX_GEAR generic map (IS_SYNC_SLAVE => IS_SYNC_SLAVE) port map ( - CLK_250_IN => clk_tx_full_i, -- in std_logic; - CLK_125_IN => clk_125_i, -- in std_logic; + CLK_250_IN => clk_tx_full_i, -- in std_logic; + CLK_125_IN => clk_serdes_tx_ref, -- in std_logic; CLK_125_OUT => clk_tx_half_i, RESET_IN => tx_gear_reset_i, -- in std_logic; @@ -624,6 +634,9 @@ begin DEBUG_OUT(59 downto 52) <= rx_rst_fsm_state_i & tx_rst_fsm_state_i; DEBUG_OUT(63 downto 60) <= serdes_ready_i & rm_rx_ready_i & rm_tx_ready_i & rm_tx_almost_ready_i; + + DEBUG_OUT(71 downto 64) <= rx_gear_debug_i(7 downto 0); + DEBUG_OUT(99 downto 96) <= rm_rx_almost_ready_i & rm_rx_see_ready0_i & rm_rx_saw_ready1_i & rm_rx_valid_char_i; DEBUG_OUT(103 downto 100) <= wa_position_i(3 downto 0); DEBUG_OUT(107 downto 104) <= "00" & rm_rx_to_gear_reset_i & gear_to_rm_rst_i; diff --git a/cbmnet/code/cbmnet_phy_ecp3_rx_reset_fsm.vhd b/cbmnet/code/cbmnet_phy_ecp3_rx_reset_fsm.vhd index 0e30bf8..3f5ec86 100644 --- a/cbmnet/code/cbmnet_phy_ecp3_rx_reset_fsm.vhd +++ b/cbmnet/code/cbmnet_phy_ecp3_rx_reset_fsm.vhd @@ -7,24 +7,29 @@ LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.all; + use work.trb_net_std.all; + entity cbmnet_phy_ecp3_rx_reset_fsm is - port ( - RST_N : in std_logic; - RX_REFCLK : in std_logic; - TX_PLL_LOL_QD_S : in std_logic; - RX_CDR_LOL_CH_S : in std_logic; - RX_LOS_LOW_CH_S : in std_logic; - - RM_RESET_IN : in std_logic := '0'; - PROPER_BYTE_ALIGN_IN : in std_logic := '1'; - PROPER_WORD_ALIGN_IN : in std_logic := '1'; - - RX_SERDES_RST_CH_C: out std_logic; - RX_PCS_RST_CH_C : out std_logic; - STATE_OUT : out std_logic_vector(3 downto 0) - ); + generic ( + IS_SIMULATED : integer range 0 to 1 := c_NO + ); + port ( + RST_N : in std_logic; + RX_REFCLK : in std_logic; + TX_PLL_LOL_QD_S : in std_logic; + RX_CDR_LOL_CH_S : in std_logic; + RX_LOS_LOW_CH_S : in std_logic; + + RM_RESET_IN : in std_logic := '0'; + PROPER_BYTE_ALIGN_IN : in std_logic := '1'; + PROPER_WORD_ALIGN_IN : in std_logic := '1'; + + RX_SERDES_RST_CH_C: out std_logic; + RX_PCS_RST_CH_C : out std_logic; + STATE_OUT : out std_logic_vector(3 downto 0) + ); end entity ; architecture rx_reset_fsm_arch of cbmnet_phy_ecp3_rx_reset_fsm is @@ -92,7 +97,7 @@ begin counter2 <= "00000000000000000000"; timer2 <= '0'; else - if counter2(count_index) = '1' then + if counter2(count_index) = '1' or (IS_SIMULATED = c_YES and counter2(5) = '1') then timer2 <='1'; else timer2 <='0'; diff --git a/cbmnet/code/cbmnet_phy_ecp3_tx_reset_fsm.vhd b/cbmnet/code/cbmnet_phy_ecp3_tx_reset_fsm.vhd new file mode 100644 index 0000000..d690727 --- /dev/null +++ b/cbmnet/code/cbmnet_phy_ecp3_tx_reset_fsm.vhd @@ -0,0 +1,174 @@ +--Media interface TX state machine + + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.all; + use work.trb_net_std.all; + + +entity cbmnet_phy_ecp3_tx_reset_fsm is + generic ( + IS_SIMULATED : integer range 0 to 1 := c_NO + ); + port ( + RST_N : in std_logic; + TX_REFCLK : in std_logic; + TX_PLL_LOL_QD_S : in std_logic; + RST_QD_C : out std_logic; + TX_PCS_RST_CH_C : out std_logic; + STATE_OUT : out std_logic_vector(3 downto 0) + + ); +end entity; + +architecture tx_reset_fsm_arch of cbmnet_phy_ecp3_tx_reset_fsm is + constant count_index : integer := 19; + type statetype is (QUAD_RESET, WAIT_FOR_TIMER1, CHECK_PLOL, WAIT_FOR_TIMER2, NORMAL); + + signal cs: statetype; -- current state of lsm + signal ns: statetype; -- next state of lsm + + signal tx_pll_lol_qd_s_int : std_logic; + signal tx_pcs_rst_ch_c_int : std_logic; + signal RST_QD_C_int : std_logic; + + signal reset_timer1: std_logic; + signal reset_timer2: std_logic; + + signal counter1: unsigned(2 downto 0); + signal TIMER1: std_logic; + + signal counter2: unsigned(19 downto 0); + signal TIMER2: std_logic; + +begin + +process (TX_REFCLK, RST_N) +begin + if RST_N = '0' then + cs <= QUAD_RESET; + tx_pll_lol_qd_s_int <= '1'; + tx_pcs_rst_ch_c <= '1'; + RST_QD_C <= '1'; + else if rising_edge(TX_REFCLK) then + cs <= ns; + tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s; + tx_pcs_rst_ch_c <= tx_pcs_rst_ch_c_int; + RST_QD_C <= RST_QD_C_int; + end if; + end if; +end process; +--TIMER1 = 20ns; +--Fastest REFLCK =312 MHZ, or 3 ns. We need 8 REFCLK cycles or 4 REFCLKDIV2 cycles +-- A 2 bit counter ([1:0]) counts 4 cycles, so a 3 bit ([2:0]) counter will do if we set TIMER1 = bit[2] + + +process (TX_REFCLK) +begin + if rising_edge(TX_REFCLK) then + if reset_timer1 = '1' then + counter1 <= "000"; + TIMER1 <= '0'; + else + if counter1(2) = '1' then + TIMER1 <= '1'; + else + TIMER1 <='0'; + counter1 <= counter1 + 1 ; + end if; + end if; + end if; +end process; + + +--TIMER2 = 1,400,000 UI; +--WORST CASE CYCLES is with smallest multipier factor. +-- This would be with X8 clock multiplier in DIV2 mode +-- IN this casse, 1 UI = 2/8 REFCLK CYCLES = 1/8 REFCLKDIV2 CYCLES +-- SO 1,400,000 UI =1,400,000/8 = 175,000 REFCLKDIV2 CYCLES +-- An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18] + + +process(TX_REFCLK, reset_timer2) +begin + if rising_edge(TX_REFCLK) then + if reset_timer2 = '1' then + counter2 <= "00000000000000000000"; + TIMER2 <= '0'; + else + if counter2(count_index) = '1' or (IS_SIMULATED = c_YES and counter2(5) = '1') then + TIMER2 <='1'; + else + TIMER2 <='0'; + counter2 <= counter2 + 1 ; + end if; + end if; + end if; +end process; + +process(cs, TIMER1, TIMER2, tx_pll_lol_qd_s_int) +begin + + reset_timer1 <= '0'; + reset_timer2 <= '0'; + STATE_OUT <= x"F"; + + case cs is + + when QUAD_RESET => + STATE_OUT <= x"1"; + tx_pcs_rst_ch_c_int <= '1'; + RST_QD_C_int <= '1'; + reset_timer1 <= '1'; + ns <= WAIT_FOR_TIMER1; + + when WAIT_FOR_TIMER1 => + STATE_OUT <= x"2"; + tx_pcs_rst_ch_c_int <= '1'; + RST_QD_C_int <= '1'; + if TIMER1 = '1' then + ns <= CHECK_PLOL; + else + ns <= WAIT_FOR_TIMER1; + end if; + + when CHECK_PLOL => + STATE_OUT <= x"3"; + tx_pcs_rst_ch_c_int <= '1'; + RST_QD_C_int <= '0'; + reset_timer2 <= '1'; + ns <= WAIT_FOR_TIMER2; + + when WAIT_FOR_TIMER2 => + STATE_OUT <= x"4"; + tx_pcs_rst_ch_c_int <= '1'; + RST_QD_C_int <= '0'; + if TIMER2 = '1' then + if tx_pll_lol_qd_s_int = '1' then + ns <= QUAD_RESET; + else + ns <= NORMAL; + end if; + else + ns <= WAIT_FOR_TIMER2; + end if; + + when NORMAL => + STATE_OUT <= x"5"; + tx_pcs_rst_ch_c_int <= '0'; + RST_QD_C_int <= '0'; + if tx_pll_lol_qd_s_int = '1' then + ns <= QUAD_RESET; + else + ns <= NORMAL; + end if; + + when others => + ns <= QUAD_RESET; + + end case; + +end process; + +end architecture; \ No newline at end of file diff --git a/cbmnet/code/cbmnet_phy_pkg.vhd b/cbmnet/code/cbmnet_phy_pkg.vhd index 8c1336b..98db4cc 100644 --- a/cbmnet/code/cbmnet_phy_pkg.vhd +++ b/cbmnet/code/cbmnet_phy_pkg.vhd @@ -8,7 +8,9 @@ library ieee; package cbmnet_phy_pkg is component cbmnet_phy_ecp3 is generic( - IS_SYNC_SLAVE : integer := c_NO --select slave mode + IS_SYNC_SLAVE : integer := c_NO; --select slave mode + IS_SIMULATED : integer := c_NO; + INCL_DEBUG_AIDS : integer := c_YES ); port( CLK : in std_logic; -- *internal* 125 MHz reference clock @@ -66,7 +68,10 @@ package cbmnet_phy_pkg is RM_RESET_IN : in std_logic; CLK_125_OUT : out std_logic; RESET_OUT : out std_logic; - DATA_OUT : out std_logic_vector(17 downto 0) + DATA_OUT : out std_logic_vector(17 downto 0); + + -- DEBUG + DEBUG_OUT : out std_logic_vector(15 downto 0) := (others => '0') ); end component; @@ -78,6 +83,7 @@ package cbmnet_phy_pkg is CLK_250_IN : in std_logic; CLK_125_IN : in std_logic; CLK_125_OUT : out std_logic; + RESET_IN : in std_logic; DATA_IN : in std_logic_vector(17 downto 0); @@ -134,6 +140,9 @@ package cbmnet_phy_pkg is END COMPONENT; component cbmnet_phy_ecp3_rx_reset_fsm is + generic ( + IS_SIMULATED : integer range 0 to 1 := c_NO + ); port ( RST_N : in std_logic; RX_REFCLK : in std_logic; @@ -149,7 +158,22 @@ package cbmnet_phy_pkg is RX_PCS_RST_CH_C : out std_logic; STATE_OUT : out std_logic_vector(3 downto 0) ); - end component ; + end component; + + component cbmnet_phy_ecp3_tx_reset_fsm is + generic ( + IS_SIMULATED : integer range 0 to 1 := c_NO + ); + port ( + RST_N : in std_logic; + TX_REFCLK : in std_logic; + TX_PLL_LOL_QD_S : in std_logic; + RST_QD_C : out std_logic; + TX_PCS_RST_CH_C : out std_logic; + STATE_OUT : out std_logic_vector(3 downto 0) + + ); + end component; end package cbmnet_phy_pkg; package body cbmnet_phy_pkg is diff --git a/cbmnet/code/cbmnet_phy_rx_gear.vhd b/cbmnet/code/cbmnet_phy_rx_gear.vhd index f8f16a0..051c57d 100644 --- a/cbmnet/code/cbmnet_phy_rx_gear.vhd +++ b/cbmnet/code/cbmnet_phy_rx_gear.vhd @@ -3,9 +3,9 @@ LIBRARY IEEE; USE IEEE.numeric_std.all; library work; - use work.trb_net_std.all; - use work.trb_net_components.all; - use work.med_sync_define.all; +-- use work.trb_net_std.all; +-- use work.trb_net_components.all; +-- use work.med_sync_define.all; use work.cbmnet_interface_pkg.all; use work.cbmnet_phy_pkg.all; @@ -21,13 +21,17 @@ entity CBMNET_PHY_RX_GEAR is RM_RESET_IN : in std_logic; CLK_125_OUT : out std_logic; RESET_OUT : out std_logic; - DATA_OUT : out std_logic_vector(17 downto 0) + DATA_OUT : out std_logic_vector(17 downto 0); + + -- DEBUG + DEBUG_OUT : out std_logic_vector(15 downto 0) := (others => '0') ); end entity; architecture CBMNET_PHY_RX_GEAR_ARCH of CBMNET_PHY_RX_GEAR is - type FSM_STATES_T is (FSM_START, FSM_WAIT_FOR_LOCK, FSM_RESET, FSM_DELAY, FSM_LOCKED); - signal fsm_i, fsm_next_i : FSM_STATES_T; + type FSM_STATES_T is (FSM_START, FSM_WAIT_FOR_LOCK, FSM_RESET, FSM_LOCKED); + signal fsm_i : FSM_STATES_T; + signal fsm_state_i : std_logic_vector(3 downto 0); signal delay_clock_i : std_logic; @@ -41,65 +45,67 @@ architecture CBMNET_PHY_RX_GEAR_ARCH of CBMNET_PHY_RX_GEAR is signal reset_timer_i : std_logic; signal timeout_i : std_logic; begin --- FSM sych part - proc_sych: process is begin +-- FSM sync part + process is begin wait until rising_edge(clk_125_i); if PCS_READY_IN = '0' then fsm_i <= FSM_START; - else - fsm_i <= fsm_next_i; - end if; - end process; - - - process(fsm_i, timeout_i, indi_alignment_i, indi_misalignment_i, RM_RESET_IN) is begin - fsm_next_i <= fsm_i; - - SERDES_RESET_OUT <= '0'; - RESET_OUT <= '1'; - reset_timer_i <= '0'; - delay_clock_i <= '0'; - - case (fsm_i) is - when FSM_START => - reset_timer_i <= '1'; - fsm_next_i <= FSM_WAIT_FOR_LOCK; - - when FSM_WAIT_FOR_LOCK => - if indi_alignment_i = '1' then - -- already correctly aligned, so just fix current state - fsm_next_i <= FSM_LOCKED; + + RESET_OUT <= '1'; + delay_clock_i <= '0'; + fsm_state_i <= x"0"; + + elsif rising_edge(clk_125_i) then + SERDES_RESET_OUT <= '0'; + RESET_OUT <= '1'; + reset_timer_i <= '0'; + delay_clock_i <= '0'; + + case (fsm_i) is + when FSM_START => + fsm_state_i <= x"0"; + reset_timer_i <= '1'; + fsm_i <= FSM_WAIT_FOR_LOCK; - elsif indi_misalignment_i = '1' then - -- we're off by one word. just wait a single frame - delay_clock_i <= '1'; - fsm_next_i <= FSM_LOCKED; - - elsif timeout_i = '1' then - fsm_next_i <= FSM_RESET; + when FSM_WAIT_FOR_LOCK => + fsm_state_i <= x"1"; + if indi_alignment_i = '1' then + -- already correctly aligned, so just fix current state + fsm_i <= FSM_LOCKED; + + elsif indi_misalignment_i = '1' then + -- we're off by one word. just wait a single frame + delay_clock_i <= '1'; + -- fsm_i <= FSM_LOCKED; - end if; + elsif timeout_i = '1' then + fsm_i <= FSM_RESET; + + end if; - when FSM_LOCKED => - RESET_OUT <= '0'; + when FSM_LOCKED => + fsm_state_i <= x"2"; + RESET_OUT <= '0'; + + if RM_RESET_IN = '1' then + fsm_i <= FSM_RESET; + + elsif indi_misalignment_i = '1' then + -- in this state we should already have a stable and correct lock. + -- if we, however detect a missalignment, something is terribly wrong. + -- in this case, will perform a resychronisation + + fsm_i <= FSM_RESET; + end if; - if RM_RESET_IN = '1' then - fsm_next_i <= FSM_RESET; - elsif indi_misalignment_i = '1' then - -- in this state we should already have a stable and correct lock. - -- if we, however detect a missalignment, something is terribly wrong. - -- in this case, will perform a resychronisation - - fsm_next_i <= FSM_RESET; - end if; - - - when FSM_RESET => - SERDES_RESET_OUT <= '1'; - - end case; + when FSM_RESET => + fsm_state_i <= x"3"; + SERDES_RESET_OUT <= '1'; + + end case; + end if; end process; -- Timeout (approx. 1ms) @@ -122,23 +128,19 @@ begin -- Implement the 2:1 gearing and clock down-sampling proc_gear: process is variable last_delay_clock_v : std_logic := '0'; - variable word_idx_v : std_logic; + variable word_idx_v : std_logic := '0'; begin wait until rising_edge(CLK_250_IN); - if (delay_clock_i = '1' and last_delay_clock_v = '0') then - -- just wait + if word_idx_v = '0' then + data_delay_i <= DATA_IN; + clk_125_i <= '0'; else - if word_idx_v = '0' then - data_delay_i <= DATA_IN; - clk_125_i <= '0'; - - else - data_out_buf_i <= data_delay_i(8) & DATA_IN(8) & data_delay_i(7 downto 0) & DATA_IN(7 downto 0); - clk_125_i <= '1'; - - end if; - + data_out_buf_i <= data_delay_i(8) & DATA_IN(8) & data_delay_i(7 downto 0) & DATA_IN(7 downto 0); + clk_125_i <= '1'; + end if; + + if not (delay_clock_i = '1' and last_delay_clock_v = '0') then word_idx_v := not word_idx_v; end if; @@ -148,6 +150,9 @@ begin DATA_OUT <= data_out_buf_i; CLK_125_OUT <= clk_125_i; + DEBUG_OUT(3 downto 0) <= STD_LOGIC_VECTOR(fsm_state_i); + DEBUG_OUT(4) <= delay_clock_i; + -- Detect Indications for correct or wrong alignment indi_alignment_i <= '1' when data_out_buf_i(17 downto 16) = "01" and data_out_buf_i(15 downto 8) = x"00" and (data_out_buf_i(7 downto 0) = CBMNET_READY_CHAR0 or data_out_buf_i(7 downto 0) = CBMNET_READY_CHAR1 or data_out_buf_i(7 downto 0) = CBMNET_ALIGN_CHAR) else '0'; diff --git a/cbmnet/code/cbmnet_phy_tx_gear.vhd b/cbmnet/code/cbmnet_phy_tx_gear.vhd index f6d0e46..dae2a76 100644 --- a/cbmnet/code/cbmnet_phy_tx_gear.vhd +++ b/cbmnet/code/cbmnet_phy_tx_gear.vhd @@ -28,7 +28,7 @@ entity CBMNET_PHY_TX_GEAR is end entity; architecture CBMNET_PHY_TX_GEAR_ARCH of CBMNET_PHY_TX_GEAR is - type FSM_STATES is (FSM_WAIT, FSM_HIGH, FSM_LOW); + type FSM_STATES is (FSM_HIGH, FSM_LOW); signal fsm_i : FSM_STATES; signal data_in_buf125_i : std_logic_vector(17 downto 0); @@ -48,26 +48,23 @@ begin CLK_125_OUT <= '0'; case fsm_i is - when FSM_WAIT => - if clk_125_xfer_buf_i /= clk_125_xfer_del_i or IS_SYNC_SLAVE = c_NO then - fsm_i <= FSM_HIGH; - end if; - when FSM_HIGH => CLK_125_OUT <= '1'; + DATA_OUT <= data_in_buf125_i(17) & data_in_buf125_i(15 downto 8); low_data_i <= data_in_buf125_i(16) & data_in_buf125_i( 7 downto 0); fsm_i <= FSM_LOW; + + if clk_125_xfer_buf_i /= clk_125_xfer_del_i then + fsm_i <= FSM_HIGH; + end if; + - when FSM_LOW => + when others => DATA_OUT <= low_data_i; fsm_i <= FSM_HIGH; end case; - - if RESET_IN = '1' then - fsm_i <= FSM_WAIT; - end if; - end process; + end process; process is begin wait until rising_edge(CLK_125_IN); diff --git a/cbmnet/code/tb_cbmnet_phy_rx_gear.vhd b/cbmnet/code/tb_cbmnet_phy_rx_gear.vhd new file mode 100644 index 0000000..12fc871 --- /dev/null +++ b/cbmnet/code/tb_cbmnet_phy_rx_gear.vhd @@ -0,0 +1,62 @@ +LIBRARY IEEE; + USE IEEE.std_logic_1164.ALL; + USE IEEE.numeric_std.all; + +library work; + use work.cbmnet_phy_pkg.all; + +entity TB_CBMNET_PHY_RX_GEAR is +end entity; + +architecture TB of TB_CBMNET_PHY_RX_GEAR is + -- SERDES PORT + signal CLK_250_IN : std_logic := '0'; + signal PCS_READY_IN: std_logic := '0'; + signal SERDES_RESET_OUT : std_logic := '0'; + signal DATA_IN : std_logic_vector( 8 downto 0); + + -- RM PORT + signal RM_RESET_IN : std_logic := '0'; + signal CLK_125_OUT : std_logic := '0'; + signal RESET_OUT : std_logic := '0'; + signal DATA_OUT : std_logic_vector(17 downto 0); + + -- DEBUG + signal DEBUG_OUT : std_logic_vector(15 downto 0) := (others => '0'); + +begin + THE_RX_GEAR: CBMNET_PHY_RX_GEAR port map ( + -- SERDES PORT + CLK_250_IN => CLK_250_IN, -- in std_logic; + PCS_READY_IN => PCS_READY_IN, -- in std_logic; + SERDES_RESET_OUT=> SERDES_RESET_OUT, -- out std_logic; + DATA_IN => DATA_IN, -- in std_logic_vector( 8 downto 0); + + -- RM PORT + RM_RESET_IN => RM_RESET_IN, -- in std_logic; + CLK_125_OUT => CLK_125_OUT, -- out std_logic; + RESET_OUT => RESET_OUT, -- out std_logic; + DATA_OUT => DATA_OUT, -- out std_logic_vector(17 downto 0) + + DEBUG_OUT => DEBUG_OUT + ); + + CLK_250_IN <= not CLK_250_IN after 2 ns; + PCS_READY_IN <= '1' after 100 ns; + + process is + variable counter_v : UNSIGNED(7 downto 0) := x"00"; + begin + wait until rising_edge(CLK_250_IN); + + counter_v := counter_v + TO_UNSIGNED(1,1); + if counter_v(0) = '1' then + DATA_IN <= "0" & x"00"; + elsif counter_v(0) = '0' then + DATA_IN <= "1" & x"9c"; + else + DATA_IN <= "0" & STD_LOGIC_VECTOR(counter_v); + end if; + end process; + +end architecture; \ No newline at end of file diff --git a/cbmnet/code/tb_cbmnet_phy_tx_gear.vhd b/cbmnet/code/tb_cbmnet_phy_tx_gear.vhd new file mode 100644 index 0000000..7d398c3 --- /dev/null +++ b/cbmnet/code/tb_cbmnet_phy_tx_gear.vhd @@ -0,0 +1,50 @@ +LIBRARY IEEE; + USE IEEE.std_logic_1164.ALL; + USE IEEE.numeric_std.all; + +library work; + use work.trb_net_std.all; + use work.cbmnet_phy_pkg.all; + +entity TB_CBMNET_PHY_TX_GEAR is +end entity; + +architecture TB of TB_CBMNET_PHY_TX_GEAR is + constant IS_SYNC_SLAVE : integer range 0 to 1 := c_YES; + signal CLK_250_IN : std_logic := '0'; + signal CLK_125_IN : std_logic := '0'; + signal CLK_125_OUT : std_logic; + signal RESET_IN : std_logic := '1'; + signal DATA_IN : std_logic_vector(17 downto 0) := (others => '0'); + signal DATA_OUT : std_logic_vector(8 downto 0); +begin + THE_GEAR: CBMNET_PHY_TX_GEAR + generic map (IS_SYNC_SLAVE => IS_SYNC_SLAVE) + port map ( + CLK_250_IN => CLK_250_IN, + CLK_125_IN => CLK_125_IN, + CLK_125_OUT => CLK_125_OUT, + RESET_IN => RESET_IN, + DATA_IN => DATA_IN, + DATA_OUT => DATA_OUT + ); + + CLK_250_IN <= not CLK_250_IN after 2 ns; + RESET_IN <= '0' after 50 ns; + + proc_clk: process is + begin + wait until rising_edge(CLK_250_IN); + wait for 1 ns; + CLK_125_IN <= not CLK_125_IN; + end process; + + process is + variable counter : unsigned(7 downto 0) := (others => '0'); + begin + wait until rising_edge(CLK_125_IN); + DATA_IN(7 downto 0) <= STD_LOGIC_VECTOR(counter); + DATA_IN(15 downto 8) <= STD_LOGIC_VECTOR(counter + TO_UNSIGNED(1,1)); + counter := counter + TO_UNSIGNED(2,2); + end process; +end architecture; \ No newline at end of file diff --git a/cbmnet/code/tb_phy_ecp3.vhd b/cbmnet/code/tb_phy_ecp3.vhd index 2b2a844..bbd82b9 100644 --- a/cbmnet/code/tb_phy_ecp3.vhd +++ b/cbmnet/code/tb_phy_ecp3.vhd @@ -42,15 +42,6 @@ architecture TB of TB_PHY_ECP3 is signal m_SD_LOS_IN, s_SD_LOS_IN : std_logic; signal m_SD_TXDIS_OUT, s_SD_TXDIS_OUT : std_logic := '0'; - --Control Interface - signal m_SCI_DATA_IN, s_SCI_DATA_IN : std_logic_vector(7 downto 0) := (others => '0'); - signal m_SCI_DATA_OUT, s_SCI_DATA_OUT : std_logic_vector(7 downto 0) := (others => '0'); - signal m_SCI_ADDR, s_SCI_ADDR : std_logic_vector(8 downto 0) := (others => '0'); - signal m_SCI_READ, s_SCI_READ : std_logic := '0'; - signal m_SCI_WRITE, s_SCI_WRITE : std_logic := '0'; - signal m_SCI_ACK, s_SCI_ACK : std_logic := '0'; - signal m_SCI_NACK, s_SCI_NACK : std_logic := '0'; - -- Status and control port signal m_STAT_OP, s_STAT_OP : std_logic_vector (15 downto 0); signal m_CTRL_OP, s_CTRL_OP : std_logic_vector (15 downto 0) := (others => '0'); @@ -58,7 +49,7 @@ architecture TB of TB_PHY_ECP3 is signal m_CTRL_DEBUG, s_CTRL_DEBUG : std_logic_vector (63 downto 0) := (others => '0'); begin THE_MASTER: CBMNET_PHY_ECP3 - generic map (IS_SYNC_SLAVE => c_YES) + generic map (IS_SYNC_SLAVE => c_NO, IS_SIMULATED => c_YES) port map ( CLK => m_CLK, RESET => m_RESET, @@ -89,25 +80,14 @@ begin SD_LOS_IN => m_SD_LOS_IN, SD_TXDIS_OUT => m_SD_TXDIS_OUT, - --Control Interface - SCI_DATA_IN => m_SCI_DATA_IN, - SCI_DATA_OUT => m_SCI_DATA_OUT, - SCI_ADDR => m_SCI_ADDR, - SCI_READ => m_SCI_READ, - SCI_WRITE => m_SCI_WRITE, - SCI_ACK => m_SCI_ACK, - SCI_NACK => m_SCI_NACK, - -- Status and control port STAT_OP => m_STAT_OP, - CTRL_OP => m_CTRL_OP, - STAT_DEBUG => m_STAT_DEBUG, - CTRL_DEBUG => m_CTRL_DEBUG + CTRL_OP => m_CTRL_OP ); THE_CLIENT: CBMNET_PHY_ECP3 - generic map (IS_SYNC_SLAVE => c_NO) + generic map (IS_SYNC_SLAVE => c_YES, IS_SIMULATED => c_YES) port map ( CLK => s_CLK, RESET => s_RESET, @@ -138,20 +118,9 @@ begin SD_LOS_IN => s_SD_LOS_IN, SD_TXDIS_OUT => s_SD_TXDIS_OUT, - --Control Interface - SCI_DATA_IN => s_SCI_DATA_IN, - SCI_DATA_OUT => s_SCI_DATA_OUT, - SCI_ADDR => s_SCI_ADDR, - SCI_READ => s_SCI_READ, - SCI_WRITE => s_SCI_WRITE, - SCI_ACK => s_SCI_ACK, - SCI_NACK => s_SCI_NACK, - -- Status and control port STAT_OP => s_STAT_OP, - CTRL_OP => s_CTRL_OP, - STAT_DEBUG => s_STAT_DEBUG, - CTRL_DEBUG => s_CTRL_DEBUG + CTRL_OP => s_CTRL_OP ); m_CLK <= not m_CLK after 8 ns; diff --git a/cbmnet/test/info b/cbmnet/test/info index 536c945..9871d61 100755 --- a/cbmnet/test/info +++ b/cbmnet/test/info @@ -1,7 +1,7 @@ #!/usr/bin/env bash echo "MASTER" -trbcmd rm 0x8000 0xa008 8 0 +trbcmd rm 0x8000 0xa008 5 0 echo "SLAVE" -trbcmd rm 0x8001 0xa008 8 0 \ No newline at end of file +trbcmd rm 0x8001 0xa008 5 0 \ No newline at end of file diff --git a/cbmnet/test/start b/cbmnet/test/start index befd24b..f27f1a2 100755 --- a/cbmnet/test/start +++ b/cbmnet/test/start @@ -11,4 +11,8 @@ system "trbcmd i 0xffff"; print "Checks\n"; my $ver_reg = "0xa006"; print "\nWRONG VERSION IN MASTER\n" unless(`trbcmd r 0x8000 $ver_reg` =~ m/0x00000000/); -print "\nWRONG VERSION IN SLAVE\n" unless(`trbcmd r 0x8001 $ver_reg` =~ m/0x00000001/); \ No newline at end of file +print "\nWRONG VERSION IN SLAVE\n" unless(`trbcmd r 0x8001 $ver_reg` =~ m/0x00000001/); + +system "compiletime.pl 0x8000"; +system "compiletime.pl 0x8001"; + diff --git a/cbmnet/trb3_periph_cbmnet.prj b/cbmnet/trb3_periph_cbmnet.prj index 65e3320..fc75d2e 100644 --- a/cbmnet/trb3_periph_cbmnet.prj +++ b/cbmnet/trb3_periph_cbmnet.prj @@ -143,9 +143,8 @@ add_file -vhdl -lib work "./code/cbmnet_interface_pkg.vhd" add_file -vhdl -lib work "./code/cbmnet_phy_pkg.vhd" add_file -vhdl -lib work "./cores/cbmnet_sfp1.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" add_file -vhdl -lib work "./code/cbmnet_phy_ecp3_rx_reset_fsm.vhd" +add_file -vhdl -lib work "./code/cbmnet_phy_ecp3_tx_reset_fsm.vhd" add_file -vhdl -lib work "./code/cbmnet_phy_rx_gear.vhd" add_file -vhdl -lib work "./code/cbmnet_phy_tx_gear.vhd" add_file -vhdl -lib work "./code/cbmnet_phy_ecp3.vhd" -- 2.43.0