From a53d8777bf10000e1400da3a57d75a3ff00afb5e Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Wed, 25 May 2016 11:15:11 +0200 Subject: [PATCH] cores and components for MDC FEE --- .gitignore | 25 ++++++ code/pwm.vhd | 72 +++++++++++++++ cores/fifo_36x1k.ipx | 9 ++ cores/fifo_36x1k.lpc | 53 +++++++++++ cores/fifo_36x1k.vhd | 191 ++++++++++++++++++++++++++++++++++++++++ cores/generate_core.tcl | 100 --------------------- cores/generate_ngd.tcl | 115 ------------------------ cores/msg_file.log | 29 ------ cores/pll_4x266.vhd | 5 +- 9 files changed, 354 insertions(+), 245 deletions(-) create mode 100644 .gitignore create mode 100644 code/pwm.vhd create mode 100644 cores/fifo_36x1k.ipx create mode 100644 cores/fifo_36x1k.lpc create mode 100644 cores/fifo_36x1k.vhd delete mode 100644 cores/generate_core.tcl delete mode 100644 cores/generate_ngd.tcl delete mode 100644 cores/msg_file.log diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..cd0e262 --- /dev/null +++ b/.gitignore @@ -0,0 +1,25 @@ +*~ +*.tcl +*.log +*.rpt +netlists +version.vhd +*.jhd +*.naf +*.sort +*.srp +*.sym +*tmpl.vhd +*.log +workdir +workdir_* +*.bit +*.kate-swp* +*.kate-swap* +.run_manager.ini +reportview.xml +.kateproject.d +*/project/ +*/project2/ +design +*.dir diff --git a/code/pwm.vhd b/code/pwm.vhd new file mode 100644 index 0000000..7fd33d2 --- /dev/null +++ b/code/pwm.vhd @@ -0,0 +1,72 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + + +entity pwm_generator is + generic( + CHANNELS : integer := 32 + ); + port( + CLK : in std_logic; + + DATA_IN : in std_logic_vector(15 downto 0) := (others => '0'); + DATA_OUT : out std_logic_vector(15 downto 0); + WRITE_IN : in std_logic := '0'; + COMP_IN : in signed(15 downto 0); + ADDR_IN : in std_logic_vector(4 downto 0) := (others => '0'); + + + PWM : out std_logic_vector(CHANNELS-1 downto 0) + + ); +end entity; + + + +architecture pwm_arch of pwm_generator is + +type ram_t is array(0 to CHANNELS-1) of unsigned(15 downto 0); +signal set : ram_t := (others => x"87C1"); +signal set_tmp : ram_t; + +type cnt_t is array(0 to CHANNELS-1) of unsigned(16 downto 0); +signal cnt : cnt_t := (others => (others => '0')); + +signal last_flag : std_logic_vector(CHANNELS-1 downto 0) := (others => '0'); +signal flag : std_logic_vector(CHANNELS-1 downto 0) := (others => '0'); +signal pwm_i : std_logic_vector(CHANNELS-1 downto 0) := (others => '0'); + +signal i : integer range 0 to CHANNELS-1 := 0; + +begin + +PROC_MEM : process begin + wait until rising_edge(CLK); + if WRITE_IN = '1' then + set(to_integer(unsigned(ADDR_IN))) <= unsigned(DATA_IN); + end if; + DATA_OUT <= std_logic_vector(set(to_integer(unsigned(ADDR_IN)))); +end process; + + +GEN_REAL_VALUES : process begin + wait until rising_edge(CLK); + set_tmp(i) <= unsigned(signed(set(i)) + COMP_IN); + i <= i + 1; +end process; + + + +gen_channels : for i in 0 to CHANNELS-1 generate + flag(i) <= cnt(i)(16); + last_flag(i) <= flag(i) when rising_edge(CLK); + pwm_i(i) <= (last_flag(i) xor flag(i)) when rising_edge(CLK); + cnt(i) <= cnt(i) + resize(set_tmp(i),17) when rising_edge(CLK); +end generate; + + +PWM(CHANNELS-1 downto 0 ) <= pwm_i(CHANNELS-1 downto 0); + +end architecture; \ No newline at end of file diff --git a/cores/fifo_36x1k.ipx b/cores/fifo_36x1k.ipx new file mode 100644 index 0000000..bc4b723 --- /dev/null +++ b/cores/fifo_36x1k.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/cores/fifo_36x1k.lpc b/cores/fifo_36x1k.lpc new file mode 100644 index 0000000..b15bc91 --- /dev/null +++ b/cores/fifo_36x1k.lpc @@ -0,0 +1,53 @@ +[Device] +Family=machxo3lf +PartType=LCMXO3LF-2100E +PartName=LCMXO3LF-2100E-5UWG49CTR +SpeedGrade=5 +Package=WLCSP49 +OperatingCondition=COM +Status=S + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.8 +ModuleName=fifo_36x1k +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=05/10/2016 +Time=16:52:51 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Only +RDepth=1024 +RWidth=36 +WDepth=1024 +WWidth=36 +regout=1 +CtrlByRdEn=0 +ClockEn=0 +EmpFlg=1 +PeMode=Static - Single Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Static - Single Threshold +PfAssert=508 +PfDeassert=506 +Reset=Async +Reset1=Sync +RDataCount=0 +WDataCount=0 +EnECC=0 + +[Command] +cmd_line= -w -n fifo_36x1k -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo3c00f -type ebfifo -depth 1024 -width 36 -rwidth 36 -regout -resetmode ASYNC -reset_rel SYNC -no_enable -pe 10 -pf 508 diff --git a/cores/fifo_36x1k.vhd b/cores/fifo_36x1k.vhd new file mode 100644 index 0000000..8eaabdc --- /dev/null +++ b/cores/fifo_36x1k.vhd @@ -0,0 +1,191 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.0.96.1 +-- Module Version: 5.8 +--/d/jspc29/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x1k -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo3c00f -type ebfifo -depth 1024 -width 36 -rwidth 36 -regout -resetmode ASYNC -reset_rel SYNC -no_enable -pe 10 -pf 508 + +-- Tue May 10 16:52:51 2016 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library MACHXO3L; +use MACHXO3L.components.all; +-- synopsys translate_on + +entity fifo_36x1k is + port ( + Data: in std_logic_vector(35 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(35 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic; + AlmostFull: out std_logic); +end fifo_36x1k; + +architecture Structure of fifo_36x1k is + + -- internal signal declarations + signal Empty_int: std_logic; + signal Full_int: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component FIFO8KB + generic (FULLPOINTER1 : in String; FULLPOINTER : in String; + AFPOINTER1 : in String; AFPOINTER : in String; + AEPOINTER1 : in String; AEPOINTER : in String; + ASYNC_RESET_RELEASE : in String; RESETMODE : in String; + GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + CSW0: in std_logic; CSW1: in std_logic; + CSR0: in std_logic; CSR1: in std_logic; + FULLI: in std_logic; EMPTYI: in std_logic; + WE: in std_logic; RE: in std_logic; ORE: in std_logic; + CLKW: in std_logic; CLKR: in std_logic; RST: in std_logic; + RPRST: in std_logic; DO0: out std_logic; + DO1: out std_logic; DO2: out std_logic; + DO3: out std_logic; DO4: out std_logic; + DO5: out std_logic; DO6: out std_logic; + DO7: out std_logic; DO8: out std_logic; + DO9: out std_logic; DO10: out std_logic; + DO11: out std_logic; DO12: out std_logic; + DO13: out std_logic; DO14: out std_logic; + DO15: out std_logic; DO16: out std_logic; + DO17: out std_logic; EF: out std_logic; + AEF: out std_logic; AFF: out std_logic; FF: out std_logic); + end component; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + fifo_36x1k_0_3: FIFO8KB + generic map (FULLPOINTER1=> "0b01111111111000", FULLPOINTER=> "0b10000000000000", + AFPOINTER1=> "0b00111111011000", AFPOINTER=> "0b00111111100000", + AEPOINTER1=> "0b00000001011000", AEPOINTER=> "0b00000001010000", + ASYNC_RESET_RELEASE=> "SYNC", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE=> "OUTREG", CSDECODE_R=> "0b11", CSDECODE_W=> "0b11", + DATA_WIDTH_R=> 9, DATA_WIDTH_W=> 9) + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo, + DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo, + DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo, + DI17=>scuba_vlo, CSW0=>scuba_vhi, CSW1=>scuba_vhi, + CSR0=>RdEn, CSR1=>scuba_vhi, FULLI=>Full_int, + EMPTYI=>Empty_int, WE=>WrEn, RE=>scuba_vhi, ORE=>scuba_vhi, + CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, RPRST=>RPReset, + DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3), DO4=>Q(4), + DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), DO8=>Q(8), DO9=>open, + DO10=>open, DO11=>open, DO12=>open, DO13=>open, DO14=>open, + DO15=>open, DO16=>open, DO17=>open, EF=>Empty_int, + AEF=>AlmostEmpty, AFF=>AlmostFull, FF=>Full_int); + + fifo_36x1k_1_2: FIFO8KB + generic map (FULLPOINTER1=> "0b00000000000000", FULLPOINTER=> "0b11111111111000", + AFPOINTER1=> "0b00000000000000", AFPOINTER=> "0b11111111111000", + AEPOINTER1=> "0b00000000000000", AEPOINTER=> "0b11111111111000", + ASYNC_RESET_RELEASE=> "SYNC", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE=> "OUTREG", CSDECODE_R=> "0b11", CSDECODE_W=> "0b11", + DATA_WIDTH_R=> 9, DATA_WIDTH_W=> 9) + port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11), + DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15), + DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo, + DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo, + DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo, + DI16=>scuba_vlo, DI17=>scuba_vlo, CSW0=>scuba_vhi, + CSW1=>scuba_vhi, CSR0=>RdEn, CSR1=>scuba_vhi, + FULLI=>Full_int, EMPTYI=>Empty_int, WE=>WrEn, RE=>scuba_vhi, + ORE=>scuba_vhi, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, + RPRST=>RPReset, DO0=>Q(9), DO1=>Q(10), DO2=>Q(11), + DO3=>Q(12), DO4=>Q(13), DO5=>Q(14), DO6=>Q(15), DO7=>Q(16), + DO8=>Q(17), DO9=>open, DO10=>open, DO11=>open, DO12=>open, + DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open, + EF=>open, AEF=>open, AFF=>open, FF=>open); + + fifo_36x1k_2_1: FIFO8KB + generic map (FULLPOINTER1=> "0b00000000000000", FULLPOINTER=> "0b11111111111000", + AFPOINTER1=> "0b00000000000000", AFPOINTER=> "0b11111111111000", + AEPOINTER1=> "0b00000000000000", AEPOINTER=> "0b11111111111000", + ASYNC_RESET_RELEASE=> "SYNC", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE=> "OUTREG", CSDECODE_R=> "0b11", CSDECODE_W=> "0b11", + DATA_WIDTH_R=> 9, DATA_WIDTH_W=> 9) + port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20), + DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24), + DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo, + DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo, + DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo, + DI16=>scuba_vlo, DI17=>scuba_vlo, CSW0=>scuba_vhi, + CSW1=>scuba_vhi, CSR0=>RdEn, CSR1=>scuba_vhi, + FULLI=>Full_int, EMPTYI=>Empty_int, WE=>WrEn, RE=>scuba_vhi, + ORE=>scuba_vhi, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, + RPRST=>RPReset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), + DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), + DO8=>Q(26), DO9=>open, DO10=>open, DO11=>open, DO12=>open, + DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open, + EF=>open, AEF=>open, AFF=>open, FF=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + fifo_36x1k_3_0: FIFO8KB + generic map (FULLPOINTER1=> "0b00000000000000", FULLPOINTER=> "0b11111111111000", + AFPOINTER1=> "0b00000000000000", AFPOINTER=> "0b11111111111000", + AEPOINTER1=> "0b00000000000000", AEPOINTER=> "0b11111111111000", + ASYNC_RESET_RELEASE=> "SYNC", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE=> "OUTREG", CSDECODE_R=> "0b11", CSDECODE_W=> "0b11", + DATA_WIDTH_R=> 9, DATA_WIDTH_W=> 9) + port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29), + DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33), + DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo, + DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo, + DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo, + DI16=>scuba_vlo, DI17=>scuba_vlo, CSW0=>scuba_vhi, + CSW1=>scuba_vhi, CSR0=>RdEn, CSR1=>scuba_vhi, + FULLI=>Full_int, EMPTYI=>Empty_int, WE=>WrEn, RE=>scuba_vhi, + ORE=>scuba_vhi, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, + RPRST=>RPReset, DO0=>Q(27), DO1=>Q(28), DO2=>Q(29), + DO3=>Q(30), DO4=>Q(31), DO5=>Q(32), DO6=>Q(33), DO7=>Q(34), + DO8=>Q(35), DO9=>open, DO10=>open, DO11=>open, DO12=>open, + DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open, + EF=>open, AEF=>open, AFF=>open, FF=>open); + + Empty <= Empty_int; + Full <= Full_int; +end Structure; + +-- synopsys translate_off +library MACHXO3L; +configuration Structure_CON of fifo_36x1k is + for Structure + for all:VHI use entity MACHXO3L.VHI(V); end for; + for all:VLO use entity MACHXO3L.VLO(V); end for; + for all:FIFO8KB use entity MACHXO3L.FIFO8KB(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/cores/generate_core.tcl b/cores/generate_core.tcl deleted file mode 100644 index 1905d5d..0000000 --- a/cores/generate_core.tcl +++ /dev/null @@ -1,100 +0,0 @@ -#!/usr/local/bin/wish - -proc GetPlatform {} { - global tcl_platform - - set cpu $tcl_platform(machine) - - switch $cpu { - intel - - i*86* { - set cpu ix86 - } - x86_64 { - if {$tcl_platform(wordSize) == 4} { - set cpu ix86 - } - } - } - - switch $tcl_platform(platform) { - windows { - if {$cpu == "amd64"} { - # Do not check wordSize, win32-x64 is an IL32P64 platform. - set cpu x86_64 - } - if {$cpu == "x86_64"} { - return "nt64" - } else { - return "nt" - } - } - unix { - if {$tcl_platform(os) == "Linux"} { - if {$cpu == "x86_64"} { - return "lin64" - } else { - return "lin" - } - } else { - return "sol" - } - } - } - return "nt" -} - -proc GetCmdLine {lpcfile} { - global Para - - if [catch {open $lpcfile r} fileid] { - puts "Cannot open $para_file file!" - exit -1 - } - - seek $fileid 0 start - set default_match 0 - while {[gets $fileid line] >= 0} { - if {[string first "\[Command\]" $line] == 0} { - set default_match 1 - continue - } - if {[string first "\[" $line] == 0} { - set default_match 0 - } - if {$default_match == 1} { - if [regexp {([^=]*)=(.*)} $line match parameter value] { - if [regexp {([ |\t]*;)} $parameter match] {continue} - if [regexp {(.*)[ |\t]*;} $value match temp] { - set Para($parameter) $temp - } else { - set Para($parameter) $value - } - } - } - } - set default_match 0 - close $fileid - - return $Para(cmd_line) -} - -set platformpath [GetPlatform] -set Para(sbp_path) [file dirname [info script]] -set Para(install_dir) $env(TOOLRTF) -set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" - -set scuba "$Para(FPGAPath)/scuba" -set modulename "pll_4x266" -set lang "vhdl" -set lpcfile "$Para(sbp_path)/$modulename.lpc" -set arch "xo3c00f" -set cmd_line [GetCmdLine $lpcfile] -set fdcfile "$Para(sbp_path)/$modulename.fdc" -if {[file exists $fdcfile] == 0} { - append scuba " " $cmd_line -} else { - append scuba " " $cmd_line " " -fdc " " \"$fdcfile\" -} -set Para(result) [catch {eval exec "$scuba"} msg] -#puts $msg diff --git a/cores/generate_ngd.tcl b/cores/generate_ngd.tcl deleted file mode 100644 index 6232bea..0000000 --- a/cores/generate_ngd.tcl +++ /dev/null @@ -1,115 +0,0 @@ -#!/usr/local/bin/wish - -proc GetPlatform {} { - global tcl_platform - - set cpu $tcl_platform(machine) - - switch $cpu { - intel - - i*86* { - set cpu ix86 - } - x86_64 { - if {$tcl_platform(wordSize) == 4} { - set cpu ix86 - } - } - } - - switch $tcl_platform(platform) { - windows { - if {$cpu == "amd64"} { - # Do not check wordSize, win32-x64 is an IL32P64 platform. - set cpu x86_64 - } - if {$cpu == "x86_64"} { - return "nt64" - } else { - return "nt" - } - } - unix { - if {$tcl_platform(os) == "Linux"} { - if {$cpu == "x86_64"} { - return "lin64" - } else { - return "lin" - } - } else { - return "sol" - } - } - } - return "nt" -} - -set platformpath [GetPlatform] -set Para(sbp_path) [file dirname [info script]] -set Para(install_dir) $env(TOOLRTF) -set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" -set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]" - -set Para(ModuleName) "pll_4x266" -set Para(Module) "PLL" -set Para(libname) machxo3lf -set Para(arch_name) xo3c00f -set Para(PartType) "LCMXO3LF-2100E" - -set Para(tech_syn) machxo3lf -set Para(tech_cae) machxo3lf -set Para(Package) "WLCSP49" -set Para(SpeedGrade) "5" -set Para(FMax) "100" -set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc" - -#create response file(*.cmd) for Synpwrap -proc CreateCmdFile {} { - global Para - - file mkdir "$Para(sbp_path)/syn_results" - if [catch {open $Para(ModuleName).cmd w} rspFile] { - puts "Cannot create response file $Para(ModuleName).cmd." - exit -1 - } else { - puts $rspFile "PROJECT: $Para(ModuleName) - working_path: \"$Para(sbp_path)/syn_results\" - module: $Para(ModuleName) - verilog_file_list: \"$Para(sbp_path)/$Para(ModuleName).vhd\" - vlog_std_v2001: true - constraint_file_name: \"$Para(sbp_path)/$Para(ModuleName).fdc\" - suffix_name: edn - output_file_name: $Para(ModuleName) - write_prf: true - disable_io_insertion: true - force_gsr: false - frequency: $Para(FMax) - fanout_limit: 50 - retiming: false - pipe: false - part: $Para(PartType) - speed_grade: $Para(SpeedGrade) - " - close $rspFile - } -} - -#synpwrap -CreateCmdFile -set synpwrap "$Para(bin_dir)/synpwrap" -if {[file exists $fdcfile] == 0} { - set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn)} msg] -} else { - set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn) -fdc $fdcfile} msg] -} -#puts $msg - -#edif2ngd -set edif2ngd "$Para(FPGAPath)/edif2ngd" -set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn \"syn_results/$Para(ModuleName).edn\" $Para(ModuleName).ngo} msg] -#puts $msg - -#ngdbuild -set ngdbuild "$Para(FPGAPath)/ngdbuild" -set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg] -#puts $msg diff --git a/cores/msg_file.log b/cores/msg_file.log deleted file mode 100644 index 56ba57d..0000000 --- a/cores/msg_file.log +++ /dev/null @@ -1,29 +0,0 @@ -SCUBA, Version Diamond (64-bit) 3.7.0.96.1 -Tue Apr 5 17:14:32 2016 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /d/jspc29/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n pll_4x266 -lang vhdl -synth synplify -arch xo3c00f -type pll -fin 125 -fclkop 250 -fclkop_tol 1.0 -fclkos 250 -fclkos_tol 0.0 -fclkos2 250 -fclkos2_tol 0.0 -fclkos3 250 -fclkos3_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 45 -trims_r -phases2 90 -phases3 135 -phase_cntl STATIC -fb_mode 5 - Circuit name : pll_4x266 - Module type : pll - Module Version : 5.7 - Ports : - Inputs : CLKI - Outputs : CLKOP, CLKOS, CLKOS2, CLKOS3 - I/O buffer : not inserted - EDIF output : pll_4x266.edn - VHDL output : pll_4x266.vhd - VHDL template : pll_4x266_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : pll_4x266.srp - Estimated Resource Usage: - -END SCUBA Module Synthesis - diff --git a/cores/pll_4x266.vhd b/cores/pll_4x266.vhd index 7ff3200..05773b5 100644 --- a/cores/pll_4x266.vhd +++ b/cores/pll_4x266.vhd @@ -1,6 +1,9 @@ -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.0.96.1 -- Module Version: 5.7 ---/d/jspc29/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n pll_4x266 -lang vhdl -synth synplify -arch xo3c00f -type pll -fin 125 -fclkop 250 -fclkop_tol 1.0 -fclkos 250 -fclkos_tol 0.0 -fclkos2 250 -fclkos2_tol 0.0 -fclkos3 250 -fclkos3_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 45 -trims_r -phases2 90 -phases3 135 -phase_cntl STATIC -fb_mode 5 +--/d/jspc29/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n pll_4x266 -lang vhdl +-- -synth synplify -arch xo3c00f -type pll -fin 125 -fclkop 250 -fclkop_tol 1.0 -fclkos 250 +-- -fclkos_tol 0.0 -fclkos2 250 -fclkos2_tol 0.0 -fclkos3 250 -fclkos3_tol 0.0 -trimp 0 +-- -phasep 0 -trimp_r -trims 0 -phases 45 -trims_r -phases2 90 -phases3 135 -phase_cntl STATIC -fb_mode 5 -- Tue Apr 5 17:14:32 2016 -- 2.43.0