From a6447067b7c622c807ba185b5734b2d8839b4793 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 11 Jan 2016 11:50:59 +0100 Subject: [PATCH] changing ecp5 fifo name to ecp3 for compatibility --- .../lattice_ecp3_fifo_18x16_dualport_oreg.cst | 3 +++ ...lattice_ecp3_fifo_18x16_dualport_oreg.fdc} | 0 ...lattice_ecp3_fifo_18x16_dualport_oreg.lpc} | 8 ++++---- ...lattice_ecp3_fifo_18x16_dualport_oreg.sbx} | 20 +++++++++---------- ...lattice_ecp3_fifo_18x16_dualport_oreg.vhd} | 12 +++++------ .../lattice_ecp5_fifo_18x16_dualport_oreg.cst | 3 --- 6 files changed, 23 insertions(+), 23 deletions(-) create mode 100644 lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.cst rename lattice/ecp5/FIFO/{lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.fdc => lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.fdc} (100%) rename lattice/ecp5/FIFO/{lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.lpc => lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.lpc} (85%) rename lattice/ecp5/FIFO/{lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.sbx => lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.sbx} (96%) rename lattice/ecp5/FIFO/{lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.vhd => lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd} (98%) delete mode 100644 lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.cst diff --git a/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.cst b/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.cst new file mode 100644 index 0000000..78f3412 --- /dev/null +++ b/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.cst @@ -0,0 +1,3 @@ +Date=01/11/2016 +Time=11:48:07 + diff --git a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.fdc b/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.fdc similarity index 100% rename from lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.fdc rename to lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.fdc diff --git a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.lpc b/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.lpc similarity index 85% rename from lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.lpc rename to lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.lpc index 133ab93..0ac45ac 100644 --- a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.lpc +++ b/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.lpc @@ -13,11 +13,11 @@ CoreType=LPM CoreStatus=Demo CoreName=FIFO_DC CoreRevision=5.8 -ModuleName=lattice_ecp5_fifo_18x16_dualport_oreg +ModuleName=lattice_ecp3_fifo_18x16_dualport_oreg SourceFormat=vhdl ParameterFileVersion=1.0 -Date=01/04/2016 -Time=13:35:37 +Date=01/11/2016 +Time=11:48:07 [Parameters] Verilog=0 @@ -50,4 +50,4 @@ WDataCount=0 EnECC=0 [Command] -cmd_line= -w -n lattice_ecp5_fifo_18x16_dualport_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 18 -rwidth 18 -regout -no_enable -reset_rel SYNC -pe -1 -pf 7 +cmd_line= -w -n lattice_ecp3_fifo_18x16_dualport_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 18 -rwidth 18 -regout -no_enable -reset_rel SYNC -pe -1 -pf 7 diff --git a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.sbx b/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.sbx similarity index 96% rename from lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.sbx rename to lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.sbx index 1aea6d1..1a899bb 100644 --- a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.sbx +++ b/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.sbx @@ -1,4 +1,4 @@ - + Lattice Semiconductor Corporation @@ -10,7 +10,7 @@ Diamond_Simulation simulation - ./lattice_ecp5_fifo_18x16_dualport_oreg.vhd + ./lattice_ecp3_fifo_18x16_dualport_oreg.vhd vhdlSource @@ -18,7 +18,7 @@ Diamond_Synthesis synthesis - ./lattice_ecp5_fifo_18x16_dualport_oreg.vhd + ./lattice_ecp3_fifo_18x16_dualport_oreg.vhd vhdlSource @@ -38,8 +38,8 @@ LFE5UM-85F-8BG381C synplify - 2016-01-04.01:35:39 PM - 2016-01-04.01:35:39 PM + 2016-01-11.11:48:08 AM + 2016-01-11.11:48:08 AM 3.6.0.83.4 VHDL @@ -109,11 +109,11 @@ Date - 01/04/2016 + 01/11/2016 ModuleName - lattice_ecp5_fifo_18x16_dualport_oreg + lattice_ecp3_fifo_18x16_dualport_oreg ParameterFileVersion @@ -125,7 +125,7 @@ Time - 13:35:37 + 11:48:07 VendorName @@ -247,7 +247,7 @@ cmd_line - -w -n lattice_ecp5_fifo_18x16_dualport_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 18 -rwidth 18 -regout -no_enable -reset_rel SYNC -pe -1 -pf 7 + -w -n lattice_ecp3_fifo_18x16_dualport_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 18 -rwidth 18 -regout -no_enable -reset_rel SYNC -pe -1 -pf 7 @@ -256,7 +256,7 @@ LATTICE LOCAL - lattice_ecp5_fifo_18x16_dualport_oreg + lattice_ecp3_fifo_18x16_dualport_oreg 1.0 diff --git a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.vhd b/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd similarity index 98% rename from lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.vhd rename to lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd index 61a801b..d1ce8ab 100644 --- a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.vhd +++ b/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd @@ -1,15 +1,15 @@ -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.6.0.83.4 -- Module Version: 5.8 ---/d/jspc29/lattice/diamond/3.6_x64/ispfpga/bin/lin64/scuba -w -n lattice_ecp5_fifo_18x16_dualport_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 18 -rwidth 18 -regout -no_enable -reset_rel SYNC -pe -1 -pf 7 -fdc /d/jspc22/trb/git/trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.fdc +--/d/jspc29/lattice/diamond/3.6_x64/ispfpga/bin/lin64/scuba -w -n lattice_ecp3_fifo_18x16_dualport_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 18 -rwidth 18 -regout -no_enable -reset_rel SYNC -pe -1 -pf 7 -fdc /d/jspc22/trb/git/trbnet/lattice/ecp5/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.fdc --- Mon Jan 4 13:35:39 2016 +-- Mon Jan 11 11:48:08 2016 library IEEE; use IEEE.std_logic_1164.all; library ecp5um; use ecp5um.components.all; -entity lattice_ecp5_fifo_18x16_dualport_oreg is +entity lattice_ecp3_fifo_18x16_dualport_oreg is port ( Data: in std_logic_vector(17 downto 0); WrClock: in std_logic; @@ -22,9 +22,9 @@ entity lattice_ecp5_fifo_18x16_dualport_oreg is Empty: out std_logic; Full: out std_logic; AlmostFull: out std_logic); -end lattice_ecp5_fifo_18x16_dualport_oreg; +end lattice_ecp3_fifo_18x16_dualport_oreg; -architecture Structure of lattice_ecp5_fifo_18x16_dualport_oreg is +architecture Structure of lattice_ecp3_fifo_18x16_dualport_oreg is -- internal signal declarations signal invout_1: std_logic; @@ -159,7 +159,7 @@ architecture Structure of lattice_ecp5_fifo_18x16_dualport_oreg is attribute MEM_LPC_FILE : string; attribute MEM_INIT_FILE : string; attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "lattice_ecp5_fifo_18x16_dualport_oreg.lpc"; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "lattice_ecp3_fifo_18x16_dualport_oreg.lpc"; attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; attribute GSR of FF_57 : label is "ENABLED"; attribute GSR of FF_56 : label is "ENABLED"; diff --git a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.cst b/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.cst deleted file mode 100644 index ca5c7e3..0000000 --- a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.cst +++ /dev/null @@ -1,3 +0,0 @@ -Date=01/04/2016 -Time=13:35:37 - -- 2.43.0