From a67cf060afe92d7234d11d599564fc488732eda3 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Mon, 6 Aug 2007 11:54:30 +0000 Subject: [PATCH] tested passive api, Jan --- testbench/trb_net_dummy_passive_apl.vhd | 165 +++++++++ trb_net_base_api.vhd | 92 ++--- trb_net_med_13bit_slow.vhd | 6 +- trb_net_passive_apimbuf.vhd | 466 ++++++++++++++++++++++++ 4 files changed, 667 insertions(+), 62 deletions(-) create mode 100644 testbench/trb_net_dummy_passive_apl.vhd create mode 100644 trb_net_passive_apimbuf.vhd diff --git a/testbench/trb_net_dummy_passive_apl.vhd b/testbench/trb_net_dummy_passive_apl.vhd new file mode 100644 index 0000000..ba65322 --- /dev/null +++ b/testbench/trb_net_dummy_passive_apl.vhd @@ -0,0 +1,165 @@ +-- this is a dummy apl, just sending data into an active api + + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +use work.trb_net_std.all; + + +entity trb_net_dummy_passive_apl is + generic (TARGET_ADDRESS : STD_LOGIC_VECTOR (15 downto 0) := x"ffff"; + PREFILL_LENGTH : integer := 3; + TRANSFER_LENGTH : integer := 6); -- length of dummy data + -- might not work with transfer_length > api_fifo + -- because of incorrect handling of fifo_full_in! + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- APL Transmitter port + APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" + APL_WRITE_OUT: out STD_LOGIC; -- Data word is valid and should be transmitted + APL_FIFO_FULL_IN: in STD_LOGIC; -- Stop transfer, the fifo is full + APL_SHORT_TRANSFER_OUT: out STD_LOGIC; -- + APL_DTYPE_OUT: out STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_OUT: out STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEND_OUT: out STD_LOGIC; -- Release sending of the data + APL_TARGET_ADDRESS_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Address of + -- the target (only for active APIs) + + -- Receiver port + APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" + APL_TYP_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM + APL_DATAREADY_IN: in STD_LOGIC; -- Data word is valid and might be read out + APL_READ_OUT: out STD_LOGIC; -- Read data word + + -- APL Control port + APL_RUN_IN: in STD_LOGIC; -- Data transfer is running +-- APL_MY_ADDRESS_OUT: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!) + APL_SEQNR_IN: in STD_LOGIC_VECTOR (7 downto 0) + + ); +END trb_net_dummy_passive_apl; + +architecture trb_net_dummy_passive_apl_arch of trb_net_dummy_passive_apl is + + type SENDER_STATE is (IDLE, RUNNING, WAITING, MY_ERROR); + signal current_state, next_state : SENDER_STATE; + signal next_counter, reg_counter : std_logic_vector(23 downto 0); + signal buf_APL_DATA_OUT, next_APL_DATA_OUT : std_logic_vector(23 downto 0); + signal buf_APL_WRITE_OUT, next_APL_WRITE_OUT : std_logic; + signal buf_APL_SEND_OUT, next_APL_SEND_OUT : std_logic; + signal state_bits : std_logic_vector(1 downto 0); + + begin + + APL_READ_OUT <= '1'; --just read, do not check + APL_DTYPE_OUT <= x"1"; + APL_ERROR_PATTERN_OUT <= x"12345678"; + APL_TARGET_ADDRESS_OUT <= TARGET_ADDRESS; + --APL_DATA_OUT <= reg_counter; + + CHECK_1:if TRANSFER_LENGTH >0 generate + APL_SHORT_TRANSFER_OUT <= '0'; + end generate; + CHECK_2:if TRANSFER_LENGTH =0 generate + APL_SHORT_TRANSFER_OUT <= '1'; + end generate; + + + SENDER_CTRL: process (current_state, APL_FIFO_FULL_IN, reg_counter, APL_RUN_IN, RESET, APL_TYP_IN) + begin -- process + next_APL_SEND_OUT <= '0'; + next_state <= MY_ERROR; + next_counter <= reg_counter; + next_APL_WRITE_OUT <= '0'; +------------------------------------------------------------------------- +-- IDLE +------------------------------------------------------------------------- + if current_state = IDLE then + if APL_FIFO_FULL_IN = '1' or reg_counter = PREFILL_LENGTH then + next_state <= RUNNING; + else + next_state <= IDLE; + next_counter <= reg_counter +1; + next_APL_WRITE_OUT <= '1'; + end if; +----------------------------------------------------------------------- +-- RUNNING +----------------------------------------------------------------------- + elsif current_state = RUNNING then + next_APL_SEND_OUT <= '1'; + if reg_counter = TRANSFER_LENGTH then + next_state <= WAITING; + else + next_state <= RUNNING; + if APL_FIFO_FULL_IN = '0' then + next_counter <= reg_counter +1; + next_APL_WRITE_OUT <= '1'; + end if; + end if; +----------------------------------------------------------------------- +-- WAITING +----------------------------------------------------------------------- + elsif current_state = WAITING then + if APL_TYP_IN = TYPE_TRM and APL_DATAREADY_IN = '1' then --always reading! + next_state <= IDLE; + next_counter <= (others => '0'); + else + next_state <= WAITING; + end if; + end if; -- end state switch + if RESET = '1' then + next_APL_WRITE_OUT <= '0'; + end if; + end process; + + +process(current_state, next_state) + begin + case current_state is + when IDLE => state_bits <= "00"; + when RUNNING => state_bits <= "01"; + when WAITING => state_bits <= "11"; + when others => state_bits <= "10"; + end case; + end process; + +APL_DATA_OUT(47 downto 24) <= (others => '0'); +APL_DATA_OUT(23 downto 0) <= buf_APL_DATA_OUT; +APL_WRITE_OUT <= buf_APL_WRITE_OUT; +APL_SEND_OUT <= buf_APL_SEND_OUT; + + CLK_REG: process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + current_state <= WAITING; + reg_counter <= (others => '0'); + buf_APL_DATA_OUT <= (others => '0'); + buf_APL_WRITE_OUT <= '0'; + buf_APL_SEND_OUT <= '0'; + + elsif CLK_EN = '1' then + reg_counter <= next_counter; + current_state <= next_state; + buf_APL_DATA_OUT <= reg_counter; + buf_APL_WRITE_OUT <= next_APL_WRITE_OUT; + buf_APL_SEND_OUT <= next_APL_SEND_OUT; + else + reg_counter <= reg_counter; + current_state <= current_state; + buf_APL_DATA_OUT <= buf_APL_DATA_OUT; + buf_APL_WRITE_OUT <= buf_APL_WRITE_OUT; + buf_APL_SEND_OUT <= buf_APL_SEND_OUT; + end if; + end if; + end process; + +end trb_net_dummy_passive_apl_arch; diff --git a/trb_net_base_api.vhd b/trb_net_base_api.vhd index 3e6b835..4a51d9c 100644 --- a/trb_net_base_api.vhd +++ b/trb_net_base_api.vhd @@ -49,6 +49,7 @@ entity trb_net_base_api is -- Internal direction port -- the ports with active or passive in their name are to be mapped by the active api -- to the init respectivly the reply path and vice versa in the passive api. + -- lets say: the "active" path is the path that I send data on. INT_ACTIVE_DATAREADY_OUT: out STD_LOGIC; INT_ACTIVE_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word INT_ACTIVE_READ_IN: in STD_LOGIC; @@ -194,10 +195,12 @@ architecture trb_net_base_api_arch of trb_net_base_api is signal fifo_term_buffer_full : std_logic; signal fifo_term_buffer_empty : std_logic; + signal state_bits : std_logic_vector(2 downto 0); type API_STATE is (IDLE, SEND_HEADER, RUNNING, SHUTDOWN, SEND_SHORT, SEND_TRAILER, WAITING,MY_ERROR); type TERM_BUFFER_STATE is (IDLE, RUNNING, SEND_TRAILER, MY_ERROR); signal current_state, next_state : API_STATE; signal tb_current_state, tb_next_state : TERM_BUFFER_STATE; + signal passive_running, next_passive_running : std_logic; signal combined_header: std_logic_vector(47 downto 0); --stored in sbuf -- , registered_header, next_registered_header: std_logic_vector(47 downto 0); @@ -420,6 +423,7 @@ begin fifo_to_apl_write <= '0'; next_APL_DATAREADY_OUT <= '0'; fifo_to_apl_read <= '0'; + next_passive_running <= passive_running; ------------------------------------------------------------------------------- -- IDLE ------------------------------------------------------------------------------- @@ -517,6 +521,7 @@ begin next_state <= WAITING; out_select <= TRM; next_INT_ACTIVE_DATAREADY_OUT <= '0'; + next_passive_running <= '0'; else next_state <= SEND_TRAILER; end if; @@ -542,7 +547,10 @@ begin if reg_APL_DATAREADY_OUT = '1' and APL_READ_IN = '1' then -- valid read fifo_to_apl_read <= '1'; - if reg_APL_TYP_OUT = TYPE_TRM and (fifo_to_apl_read = '1' and reg_APL_DATAREADY_OUT = '1') then -- transfer completely finished + if reg_APL_TYP_OUT = TYPE_TRM or reg_APL_TYP_OUT = TYPE_HDR then + next_passive_running <= '1'; + end if; + if reg_APL_TYP_OUT = TYPE_TRM and (fifo_to_apl_read = '1' and reg_APL_DATAREADY_OUT = '1') then next_state <= IDLE; end if; end if; @@ -552,60 +560,6 @@ begin end process; -- end generate; ---------------------------------------- --- the state machine for the passive part ---------------------------------------- --- gen_passive_fsm : if API_TYPE = 0 generate --- STATE_COMB : process(current_state, APL_SEND_IN, combined_header, --- INT_ACTIVE_READ_IN, APL_WRITE_IN, fifo_to_int_empty, --- fifo_to_int_data_out, combined_trailer, --- next_registered_trailer, fifo_to_int_data_out, --- fifo_to_apl_empty, INT_PASSIVE_DATAREADY_IN, --- reg_INT_PASSIVE_READ_OUT,fifo_to_apl_read, --- reg_APL_DATAREADY_OUT, fifo_to_apl_data_out, --- reg_APL_DATAREADY_OUT, APL_READ_IN, sbuf_free, --- reg_APL_TYP_OUT, APL_SHORT_TRANSFER_IN, fifo_to_apl_full) --- begin --- next_state <= MY_ERROR; --- next_INT_ACTIVE_DATAREADY_OUT <= '0'; --- out_select <= DAT; --- update_registered_trailer <= '0'; --- fifo_to_int_read <= '0'; --- next_INT_PASSIVE_READ_OUT <= '0'; --- fifo_to_apl_write <= '0'; --- next_APL_DATAREADY_OUT <= '0'; --- fifo_to_apl_read <= '0'; --- --- if current_state = then --- next_state <= WAITING; --- -- here we have to supply the receiver port --- -- part 1: connection to network --- if fifo_to_apl_full = '0' or (fifo_to_apl_read = '1' and reg_APL_DATAREADY_OUT = '1') then --- next_INT_PASSIVE_READ_OUT <= '1'; --- end if; --- if reg_INT_PASSIVE_READ_OUT = '1' and INT_PASSIVE_DATAREADY_IN = '1' then --- fifo_to_apl_write <= '1'; -- use fifo as the pipe --- end if; --- --- -- part 2: connection to apl --- if (fifo_to_apl_empty = '0') then --- next_APL_DATAREADY_OUT <= '1'; --- end if; -- read/no read --- --- if reg_APL_DATAREADY_OUT = '1' and APL_READ_IN = '1' then --- -- valid read --- fifo_to_apl_read <= '1'; --- if reg_APL_TYP_OUT = TYPE_TRM and (fifo_to_apl_read = '1' and reg_APL_DATAREADY_OUT = '1') then -- transfer completely finished --- next_state <= IDLE; --- end if; --- end if; --- -- MISSING: SEQNR check --- -- OPEN QUESTION: Address matching? makes sense for a reply transfer? --- --- --- end if; --- end process; --- end generate; --------------------------------------- @@ -648,8 +602,10 @@ begin APL_DATAREADY_OUT <= reg_APL_DATAREADY_OUT; APL_DATA_OUT <= reg_APL_DATA_OUT; APL_TYP_OUT <= reg_APL_TYP_OUT; - APL_RUN_OUT <= '0' when (current_state = IDLE) - else '1'; +-- APL_RUN_OUT <= '0' when ((current_state = IDLE )) + APL_RUN_OUT <= '0' when ((current_state = IDLE and API_TYPE = 1) + or (passive_running = '0' and API_TYPE = 0)) + else '1'; APL_SEQNR_OUT <= sequence_counter; -- generate the sequence counter @@ -672,10 +628,11 @@ begin sequence_counter <= (others => '0'); reg_INT_PASSIVE_READ_OUT <= '0'; if API_TYPE = 1 then - current_state <= IDLE; + current_state <= IDLE; else - current_state <= WAITING; + current_state <= WAITING; end if; + passive_running <= '0'; tb_current_state <= IDLE; tb_registered_trailer <= (others => '0'); tb_registered_target <= ILLEGAL_ADRESS; @@ -683,6 +640,7 @@ begin sequence_counter <= next_sequence_counter; reg_INT_PASSIVE_READ_OUT <= next_INT_PASSIVE_READ_OUT; current_state <= next_state; + passive_running <= next_passive_running; tb_current_state <= tb_next_state; tb_registered_trailer <= tb_next_registered_trailer; tb_registered_target <= tb_next_registered_target; @@ -690,6 +648,7 @@ begin sequence_counter <= sequence_counter; reg_INT_PASSIVE_READ_OUT <= reg_INT_PASSIVE_READ_OUT; current_state <= current_state; + passive_running <= passive_running; tb_current_state <= tb_current_state; tb_registered_trailer <= tb_registered_trailer; tb_registered_target <= tb_registered_target; @@ -710,6 +669,21 @@ begin end if; end process; +process(current_state) + begin + case current_state is + when IDLE => state_bits <= "000"; + when SEND_HEADER => state_bits <= "001"; + when RUNNING => state_bits <= "010"; + when SHUTDOWN => state_bits <= "011"; + when SEND_SHORT => state_bits <= "100"; + when SEND_TRAILER => state_bits <= "101"; + when WAITING => state_bits <= "110"; + when others => state_bits <= "111"; + end case; + end process; + + end architecture trb_net_base_api_arch; diff --git a/trb_net_med_13bit_slow.vhd b/trb_net_med_13bit_slow.vhd index 94d9335..23a09e0 100755 --- a/trb_net_med_13bit_slow.vhd +++ b/trb_net_med_13bit_slow.vhd @@ -499,9 +499,9 @@ begin case MED2INT_state is when IDLE => med2int_state_sig <= "000"; when RECV2 => med2int_state_sig <= "001"; - when RECV3 => med2int_state_sig <= "002"; - when RECV4 => med2int_state_sig <= "003"; - when RECV5 => med2int_state_sig <= "004"; + when RECV3 => med2int_state_sig <= "010"; + when RECV4 => med2int_state_sig <= "011"; + when RECV5 => med2int_state_sig <= "100"; end case; end process; diff --git a/trb_net_passive_apimbuf.vhd b/trb_net_passive_apimbuf.vhd new file mode 100644 index 0000000..383e6f9 --- /dev/null +++ b/trb_net_passive_apimbuf.vhd @@ -0,0 +1,466 @@ +-- an active api together with an iobuf + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +use work.trb_net_std.all; + +--Entity decalaration for clock generator +entity trb_net_passive_apimbuf is + + generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if + -- the initibuf + REPLY_DEPTH : integer := 3; -- or the replyibuf + FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), + -- for the direction to + -- internal world + FIFO_TO_APL_DEPTH : integer := 3; -- direction to application + FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of + -- the master path, if set to 0 + -- no buffer is used at all + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out + --by the media (via the TrbNetIOMultiplexer) + MED_DATA_OUT: out STD_LOGIC_VECTOR (51 downto 0); -- Data word + MED_READ_IN: in STD_LOGIC; -- Media is reading + + MED_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media + -- (the IOBUF MUST read) + MED_DATA_IN: in STD_LOGIC_VECTOR (51 downto 0); -- Data word + MED_READ_OUT: out STD_LOGIC; -- buffer reads a word from media + MED_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits + + + -- APL Transmitter port + APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" + APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted + APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full + APL_SHORT_TRANSFER_IN: in STD_LOGIC; -- + APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEND_IN: in STD_LOGIC; -- Release sending of the data + APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of + -- the target (only for active APIs) + + -- Receiver port + APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" + APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM + APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out + APL_READ_IN: in STD_LOGIC; -- Read data word + + -- APL Control port + APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running + APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!) + APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); + + -- Status and control port => just coming from the iobuf for debugging + STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status + STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control + STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control + STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status + STAT_api_control_signals: out std_logic_vector(31 downto 0); + CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0); + CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0); + STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0); + STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0); + MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0); + API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); + API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) + ); +end trb_net_passive_apimbuf; + +architecture trb_net_passive_apimbuf_arch of trb_net_passive_apimbuf is + +component trb_net_iobuf is + + generic (INIT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), if + -- the initibuf + REPLY_DEPTH : integer := 3); -- or the replyibuf + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_INIT_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out + --by the media (via the TrbNetIOMultiplexer) + MED_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word + MED_INIT_READ_IN: in STD_LOGIC; -- Media is reading + + MED_INIT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media + -- (the IOBUF MUST read) + MED_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word + MED_INIT_READ_OUT: out STD_LOGIC; -- buffer reads a word from media + MED_INIT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits + + MED_REPLY_DATAREADY_OUT: out STD_LOGIC; --Data word ready to be read out + --by the media (via the TrbNetIOMultiplexer) + MED_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word + MED_REPLY_READ_IN: in STD_LOGIC; -- Media is reading + + MED_REPLY_DATAREADY_IN: in STD_LOGIC; -- Data word is offered by the Media + -- (the IOBUF MUST read) + MED_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word + MED_REPLY_READ_OUT: out STD_LOGIC; -- buffer reads a word from media + MED_REPLY_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits + + -- Internal direction port + + INT_INIT_DATAREADY_OUT: out STD_LOGIC; + INT_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_INIT_READ_IN: in STD_LOGIC; + + INT_INIT_DATAREADY_IN: in STD_LOGIC; + INT_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_INIT_READ_OUT: out STD_LOGIC; + + INT_REPLY_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last + -- header (only for the reply path) + INT_REPLY_DATAREADY_OUT: out STD_LOGIC; + INT_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_REPLY_READ_IN: in STD_LOGIC; + + INT_REPLY_DATAREADY_IN: in STD_LOGIC; + INT_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_REPLY_READ_OUT: out STD_LOGIC; + + -- Status and control port + STAT_GEN: out STD_LOGIC_VECTOR (31 downto 0); -- General Status + STAT_LOCKED: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control + STAT_INIT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- Status of the handshake and buffer control + STAT_REPLY_BUFFER: out STD_LOGIC_VECTOR (31 downto 0); -- General Status + CTRL_GEN: in STD_LOGIC_VECTOR (31 downto 0); + CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0); + STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0); + STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0) + ); +END component; + +component trb_net_passive_api is + + generic (FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), + -- for the direction to + -- internal world + FIFO_TO_APL_DEPTH : integer := 3; -- direction to application + FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of + -- the master path, if set to 0 + -- no buffer is used at all + + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- APL Transmitter port + APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network" + APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted + APL_FIFO_FULL_OUT: out STD_LOGIC; -- Stop transfer, the fifo is full + APL_SHORT_TRANSFER_IN: in STD_LOGIC; -- + APL_DTYPE_IN: in STD_LOGIC_VECTOR (3 downto 0); -- see NewTriggerBusNetworkDescr + APL_ERROR_PATTERN_IN: in STD_LOGIC_VECTOR (31 downto 0); -- see NewTriggerBusNetworkDescr + APL_SEND_IN: in STD_LOGIC; -- Release sending of the data + APL_TARGET_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Address of + -- the target (only for active APIs) + + -- Receiver port + APL_DATA_OUT: out STD_LOGIC_VECTOR (47 downto 0); -- Data word "network to application" + APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM + APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out + APL_READ_IN: in STD_LOGIC; -- Read data word + + -- APL Control port + APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running + APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!) + APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); + + -- Internal direction port + -- This is just a clone from trb_net_iobuf + + INT_INIT_DATAREADY_OUT: out STD_LOGIC; + INT_INIT_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_INIT_READ_IN: in STD_LOGIC; + + INT_INIT_DATAREADY_IN: in STD_LOGIC; + INT_INIT_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_INIT_READ_OUT: out STD_LOGIC; + + + INT_REPLY_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last + -- header (only for the reply path) + INT_REPLY_DATAREADY_OUT: out STD_LOGIC; + INT_REPLY_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_REPLY_READ_IN: in STD_LOGIC; + + INT_REPLY_DATAREADY_IN: in STD_LOGIC; + INT_REPLY_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_REPLY_READ_OUT: out STD_LOGIC; + + -- Status and control port + STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); + STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) + ); +END component; + +component trb_net_io_multiplexer is + + generic (BUS_WIDTH : integer := 56; + MULT_WIDTH : integer := 5); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_IN: in STD_LOGIC; + MED_DATA_IN: in STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0); + -- highest bits are mult. + MED_READ_OUT: out STD_LOGIC; + + MED_DATAREADY_OUT: out STD_LOGIC; + MED_DATA_OUT: out STD_LOGIC_VECTOR (BUS_WIDTH-1 downto 0); + MED_READ_IN: in STD_LOGIC; + + -- Internal direction port + INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0); + INT_DATA_OUT: out STD_LOGIC_VECTOR ((BUS_WIDTH-MULT_WIDTH)*(2**MULT_WIDTH)-1 downto 0); + INT_READ_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0); + + INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0); + INT_DATA_IN: in STD_LOGIC_VECTOR ((BUS_WIDTH-MULT_WIDTH)*(2**MULT_WIDTH)-1 downto 0); + INT_READ_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0); + + -- Status and control port + CTRL: in STD_LOGIC_VECTOR (31 downto 0); + STAT: out STD_LOGIC_VECTOR (31 downto 0) + ); +END component; + +signal apl_to_buf_INIT_DATAREADY: STD_LOGIC; +signal apl_to_buf_INIT_DATA : STD_LOGIC_VECTOR (50 downto 0); +signal apl_to_buf_INIT_READ : STD_LOGIC; + +signal buf_to_apl_INIT_DATAREADY: STD_LOGIC; +signal buf_to_apl_INIT_DATA : STD_LOGIC_VECTOR (50 downto 0); +signal buf_to_apl_INIT_READ : STD_LOGIC; + +signal apl_to_buf_REPLY_DATAREADY: STD_LOGIC; +signal apl_to_buf_REPLY_DATA : STD_LOGIC_VECTOR (50 downto 0); +signal apl_to_buf_REPLY_READ : STD_LOGIC; + +signal buf_to_apl_REPLY_DATAREADY: STD_LOGIC; +signal buf_to_apl_REPLY_DATA : STD_LOGIC_VECTOR (50 downto 0); +signal buf_to_apl_REPLY_READ : STD_LOGIC; + +-- for the connection to the multiplexer +signal MED_INIT_DATAREADY_OUT : STD_LOGIC; +signal MED_INIT_DATA_OUT : STD_LOGIC_VECTOR (50 downto 0); +signal MED_INIT_READ_IN : STD_LOGIC; + +signal MED_INIT_DATAREADY_IN : STD_LOGIC; +signal MED_INIT_DATA_IN : STD_LOGIC_VECTOR (50 downto 0); +signal MED_INIT_READ_OUT : STD_LOGIC; + +signal MED_REPLY_DATAREADY_OUT : STD_LOGIC; +signal MED_REPLY_DATA_OUT : STD_LOGIC_VECTOR (50 downto 0); +signal MED_REPLY_READ_IN : STD_LOGIC; + +signal MED_REPLY_DATAREADY_IN : STD_LOGIC; +signal MED_REPLY_DATA_IN : STD_LOGIC_VECTOR (50 downto 0); +signal MED_REPLY_READ_OUT : STD_LOGIC; + +signal m_DATAREADY_OUT : STD_LOGIC_VECTOR (1 downto 0); +signal m_DATA_OUT : STD_LOGIC_VECTOR (101 downto 0); +signal m_READ_IN : STD_LOGIC_VECTOR (1 downto 0); + +signal m_DATAREADY_IN : STD_LOGIC_VECTOR (1 downto 0); +signal m_DATA_IN : STD_LOGIC_VECTOR (101 downto 0); +signal m_READ_OUT : STD_LOGIC_VECTOR (1 downto 0); + +begin + + m_DATAREADY_OUT(0) <= MED_INIT_DATAREADY_OUT; + m_DATAREADY_OUT(1) <= MED_REPLY_DATAREADY_OUT; + m_DATA_OUT(50 downto 0) <= MED_INIT_DATA_OUT; + m_DATA_OUT(101 downto 51) <= MED_REPLY_DATA_OUT; + MED_INIT_READ_IN <= m_READ_IN(0); + MED_REPLY_READ_IN <= m_READ_IN(1); + + MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(0); + MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(1); + MED_INIT_DATA_IN <= m_DATA_IN(50 downto 0); + MED_REPLY_DATA_IN <= m_DATA_IN(101 downto 51); + m_READ_OUT(0) <= MED_INIT_READ_OUT; + m_READ_OUT(1) <= MED_REPLY_READ_OUT; + + + PASSIVE_API: trb_net_passive_api + + generic map (FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH, + FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH, + FIFO_TERM_BUFFER_DEPTH => FIFO_TERM_BUFFER_DEPTH) + + port map ( + -- Misc + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + + -- APL Transmitter port + APL_DATA_IN => APL_DATA_IN, + APL_WRITE_IN => APL_WRITE_IN, + APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT, + APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN, + APL_DTYPE_IN => APL_DTYPE_IN, + APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN, + APL_SEND_IN => APL_SEND_IN, + APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN, + + -- Receiver port + APL_DATA_OUT => APL_DATA_OUT, + APL_TYP_OUT => APL_TYP_OUT, + APL_DATAREADY_OUT => APL_DATAREADY_OUT, + APL_READ_IN => APL_READ_IN, + + -- APL Control port + APL_RUN_OUT => APL_RUN_OUT, + APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN, + APL_SEQNR_OUT => APL_SEQNR_OUT, + + -- Internal direction port + -- connect via private signals + + INT_INIT_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY, + INT_INIT_DATA_OUT => apl_to_buf_INIT_DATA, + INT_INIT_READ_IN => apl_to_buf_INIT_READ, + + INT_INIT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY, + INT_INIT_DATA_IN => buf_to_apl_INIT_DATA, + INT_INIT_READ_OUT => buf_to_apl_INIT_READ, + + INT_REPLY_HEADER_IN => '0', + INT_REPLY_DATAREADY_OUT =>apl_to_buf_REPLY_DATAREADY, + INT_REPLY_DATA_OUT => apl_to_buf_REPLY_DATA, + INT_REPLY_READ_IN => apl_to_buf_REPLY_READ, + + INT_REPLY_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY, + INT_REPLY_DATA_IN => buf_to_apl_REPLY_DATA, + INT_REPLY_READ_OUT => buf_to_apl_REPLY_READ, + + -- Status and control port + STAT_FIFO_TO_INT => api_stat_fifo_to_int, + STAT_FIFO_TO_APL => api_stat_fifo_to_apl + ); + +STAT_api_control_signals(2 downto 0) <= APL_DATA_IN(2 downto 0); +STAT_api_control_signals(3) <= APL_WRITE_IN; +STAT_api_control_signals(4) <= APL_SEND_IN; +STAT_api_control_signals(7 downto 5) <= (others => '0'); +STAT_api_control_signals(10 downto 8) <= apl_to_buf_INIT_DATA(2 downto 0); +STAT_api_control_signals(11) <= apl_to_buf_INIT_DATAREADY; +STAT_api_control_signals(12) <= apl_to_buf_INIT_READ; +STAT_api_control_signals(31 downto 13) <= (others => '0'); + + + +IOBUF: trb_net_iobuf + + generic map (INIT_DEPTH => INIT_DEPTH, + REPLY_DEPTH => REPLY_DEPTH) + + port map ( + -- Misc + CLK => CLK , + RESET => RESET, + CLK_EN => CLK_EN, + -- Media direction port + MED_INIT_DATAREADY_OUT => MED_INIT_DATAREADY_OUT, + MED_INIT_DATA_OUT => MED_INIT_DATA_OUT, + MED_INIT_READ_IN => MED_INIT_READ_IN, + + MED_INIT_DATAREADY_IN => MED_INIT_DATAREADY_IN, + MED_INIT_DATA_IN => MED_INIT_DATA_IN, + MED_INIT_READ_OUT => MED_INIT_READ_OUT, + MED_INIT_ERROR_IN => (others => '0'), + + MED_REPLY_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT, + MED_REPLY_DATA_OUT => MED_REPLY_DATA_OUT, + MED_REPLY_READ_IN => MED_REPLY_READ_IN, + + MED_REPLY_DATAREADY_IN => MED_REPLY_DATAREADY_IN, + MED_REPLY_DATA_IN => MED_REPLY_DATA_IN, + MED_REPLY_READ_OUT => MED_REPLY_READ_OUT, + MED_REPLY_ERROR_IN => (others => '0'), + + -- Internal direction port + + INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY, + INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA, + INT_INIT_READ_IN => buf_to_apl_INIT_READ, + + INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY, + INT_INIT_DATA_IN => apl_to_buf_INIT_DATA, + INT_INIT_READ_OUT => apl_to_buf_INIT_READ, + + INT_REPLY_HEADER_IN => '0', + INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY, + INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA, + INT_REPLY_READ_IN => buf_to_apl_REPLY_READ, + + INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY, + INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA, + INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ, + + -- Status and control port + STAT_GEN => STAT_GEN, + STAT_LOCKED => STAT_LOCKED, + STAT_INIT_BUFFER => STAT_INIT_BUFFER, + STAT_REPLY_BUFFER => STAT_REPLY_BUFFER, + CTRL_GEN => CTRL_GEN, + CTRL_LOCKED => CTRL_LOCKED, + STAT_CTRL_INIT_BUFFER => STAT_CTRL_INIT_BUFFER, + STAT_CTRL_REPLY_BUFFER => STAT_CTRL_REPLY_BUFFER + ); + + MPLEX: trb_net_io_multiplexer + generic map (BUS_WIDTH => 52, + MULT_WIDTH => 1) + port map ( + CLK => CLK, + RESET => RESET , + CLK_EN => CLK_EN, + + MED_DATAREADY_IN => MED_DATAREADY_IN, + MED_DATA_IN => MED_DATA_IN, + MED_READ_OUT => MED_READ_OUT, + + MED_DATAREADY_OUT => MED_DATAREADY_OUT, + MED_DATA_OUT => MED_DATA_OUT, + MED_READ_IN => MED_READ_IN, + + INT_DATAREADY_OUT => m_DATAREADY_IN, + INT_DATA_OUT =>m_DATA_IN, + INT_READ_IN =>m_READ_OUT, + + INT_DATAREADY_IN =>m_DATAREADY_OUT, + INT_DATA_IN =>m_DATA_OUT, + INT_READ_OUT =>m_READ_IN, + + CTRL => MPLEX_CTRL + + ); + +end trb_net_passive_apimbuf_arch; + -- 2.43.0