From a6e4c347d015338d542521a57e1149956fcedebf Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 11 May 2017 13:30:07 +0200 Subject: [PATCH] Update ADC design with newer entities, e.g. records --- ADC/trb3_periph_adc.vhd | 177 +++++++++++----------------------------- 1 file changed, 47 insertions(+), 130 deletions(-) diff --git a/ADC/trb3_periph_adc.vhd b/ADC/trb3_periph_adc.vhd index c8a7d7d..203a174 100644 --- a/ADC/trb3_periph_adc.vhd +++ b/ADC/trb3_periph_adc.vhd @@ -121,17 +121,9 @@ architecture trb3_periph_adc_arch of trb3_periph_adc is attribute syn_preserve of GSR_N : signal is true; --Media Interface - signal med_stat_op : std_logic_vector (1*16-1 downto 0); - signal med_ctrl_op : std_logic_vector (1*16-1 downto 0); - signal med_stat_debug : std_logic_vector (1*64-1 downto 0); - signal med_data_out : std_logic_vector (1*16-1 downto 0); - signal med_packet_num_out : std_logic_vector (1*3-1 downto 0); - signal med_dataready_out : std_logic; - signal med_read_out : std_logic; - signal med_data_in : std_logic_vector (1*16-1 downto 0); - signal med_packet_num_in : std_logic_vector (1*3-1 downto 0); - signal med_dataready_in : std_logic; - signal med_read_in : std_logic; + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); --LVL1 channel signal timing_trg_received_i : std_logic; @@ -157,13 +149,7 @@ architecture trb3_periph_adc_arch of trb3_periph_adc is signal regio_tx, busadc_tx, busspi_tx, busmem_tx, bussed_tx : CTRLBUS_TX; signal readout_rx : READOUT_RX; signal readout_tx : readout_tx_array_t(0 to 11); - - signal fee_data_finished_in : std_logic_vector(DEVICES-1 downto 0); - signal fee_data_write_in : std_logic_vector(DEVICES-1 downto 0); - signal fee_trg_release_in : std_logic_vector(DEVICES-1 downto 0); - signal fee_data_in : std_logic_vector(32*DEVICES-1 downto 0); - signal fee_trg_statusbits_in : std_logic_vector(32*DEVICES-1 downto 0); - + signal timer : TIMERS; signal sed_debug : std_logic_vector(31 downto 0); begin @@ -184,7 +170,7 @@ begin SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) RESET_IN => '0', -- general reset signal (SYSCLK) - TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) + TRB_RESET_IN => med2int(0).stat_op(13), -- TRBnet reset signal (SYSCLK) CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) DEBUG_OUT => open @@ -224,14 +210,14 @@ begin CLEAR => clear_i, CLK_EN => '1', --Internal Connection - MED_DATA_IN => med_data_out, - MED_PACKET_NUM_IN => med_packet_num_out, - MED_DATAREADY_IN => med_dataready_out, - MED_READ_OUT => med_read_in, - MED_DATA_OUT => med_data_in, - MED_PACKET_NUM_OUT => med_packet_num_in, - MED_DATAREADY_OUT => med_dataready_in, - MED_READ_IN => med_read_out, + MED_DATA_IN => int2med(0).data, + MED_PACKET_NUM_IN => int2med(0).packet_num, + MED_DATAREADY_IN => int2med(0).dataready, + MED_READ_OUT => med2int(0).tx_read, + MED_DATA_OUT => med2int(0).data, + MED_PACKET_NUM_OUT => med2int(0).packet_num, + MED_DATAREADY_OUT => med2int(0).dataready, + MED_READ_IN => '1', REFCLK2CORE_OUT => open, --SFP Connection SD_RXD_P_IN => SERDES_INT_RX(2), @@ -244,8 +230,8 @@ begin SD_LOS_IN => FPGA5_COMM(0), SD_TXDIS_OUT => FPGA5_COMM(2), -- Status and control port - STAT_OP => med_stat_op, - CTRL_OP => med_ctrl_op, + STAT_OP => med2int(0).stat_op, + CTRL_OP => int2med(0).ctrl_op, STAT_DEBUG => med_stat_debug, CTRL_DEBUG => (others => '0') ); @@ -256,17 +242,9 @@ begin THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record generic map( - REGIO_NUM_STAT_REGS => 0, - REGIO_NUM_CTRL_REGS => 0, ADDRESS_MASK => x"FFFF", BROADCAST_BITMASK => x"ff", - BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, - REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), - REGIO_HARDWARE_VERSION => HARDWARE_INFO, - REGIO_INIT_ADDRESS => INIT_ADDRESS, REGIO_USE_VAR_ENDPOINT_ID => c_YES, - REGIO_INCLUDED_FEATURES => INCLUDED_FEATURES, - CLOCK_FREQUENCY => CLOCK_FREQUENCY, TIMING_TRIGGER_RAW => c_YES, --Configure data handler DATA_INTERFACE_NUMBER => 12, @@ -277,96 +255,33 @@ begin HEADER_BUFFER_DEPTH => 9, HEADER_BUFFER_FULL_THRESH => 2**9-16 ) - port map( - CLK => clk_100_i, - RESET => reset_i, - CLK_EN => '1', - MED_DATAREADY_OUT => med_dataready_out, - MED_DATA_OUT => med_data_out, - MED_PACKET_NUM_OUT => med_packet_num_out, - MED_READ_IN => med_read_in, - MED_DATAREADY_IN => med_dataready_in, - MED_DATA_IN => med_data_in, - MED_PACKET_NUM_IN => med_packet_num_in, - MED_READ_OUT => med_read_out, - MED_STAT_OP_IN => med_stat_op, - MED_CTRL_OP_OUT => med_ctrl_op, - - --Timing trigger in - TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i, - --LVL1 trigger to FEE - LVL1_TRG_DATA_VALID_OUT => readout_rx.data_valid, - LVL1_VALID_TIMING_TRG_OUT => readout_rx.valid_timing_trg, - LVL1_VALID_NOTIMING_TRG_OUT => readout_rx.valid_notiming_trg, - LVL1_INVALID_TRG_OUT => readout_rx.invalid_trg, - - LVL1_TRG_TYPE_OUT => readout_rx.trg_type, - LVL1_TRG_NUMBER_OUT => readout_rx.trg_number, - LVL1_TRG_CODE_OUT => readout_rx.trg_code, - LVL1_TRG_INFORMATION_OUT => readout_rx.trg_information, - LVL1_INT_TRG_NUMBER_OUT => readout_rx.trg_int_number, - - --Information about trigger handler errors - TRG_MULTIPLE_TRG_OUT => readout_rx.trg_multiple, - TRG_TIMEOUT_DETECTED_OUT => readout_rx.trg_timeout, - TRG_SPURIOUS_TRG_OUT => readout_rx.trg_spurious, - TRG_MISSING_TMG_TRG_OUT => readout_rx.trg_missing, - TRG_SPIKE_DETECTED_OUT => readout_rx.trg_spike, - - --Response from FEE - FEE_TRG_RELEASE_IN => fee_trg_release_in, - FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_in, - FEE_DATA_IN => fee_data_in, - FEE_DATA_WRITE_IN => fee_data_write_in, - FEE_DATA_FINISHED_IN => fee_data_finished_in, - FEE_DATA_ALMOST_FULL_OUT(0) => readout_rx.buffer_almost_full, - - -- Slow Control Data Port - REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 - REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 - REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe, - REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe, - REGIO_STAT_REG_IN => (others => '0'), - REGIO_CTRL_REG_OUT => open, - REGIO_STAT_STROBE_OUT => open, - REGIO_CTRL_STROBE_OUT => open, - REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE, - REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'), - - BUS_RX => regio_rx, - BUS_TX => regio_tx, - - ONEWIRE_INOUT => TEMPSENS, - ONEWIRE_MONITOR_OUT => open, - - TIME_GLOBAL_OUT => global_time, - TIME_LOCAL_OUT => local_time, - TIME_SINCE_LAST_TRG_OUT => time_since_last_trg, - TIME_TICKS_OUT => timer_ticks --- --- STAT_DEBUG_IPU => open, --- STAT_DEBUG_1 => open, --- STAT_DEBUG_2 => open, --- STAT_DEBUG_DATA_HANDLER_OUT => open, --- STAT_DEBUG_IPU_HANDLER_OUT => open, --- STAT_TRIGGER_OUT => open, --- CTRL_MPLEX => (others => '0'), --- IOBUF_CTRL_GEN => (others => '0'), --- STAT_ONEWIRE => open, --- STAT_ADDR_DEBUG => open, --- DEBUG_LVL1_HANDLER_OUT => open - ); + port map( + CLK => clk_100_i, + RESET => reset_i, + CLK_EN => '1', + -- Media direction port + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => TRIGGER_LEFT, + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + + --Slow Control Port + REGIO_COMMON_STAT_REG_IN => (others => '0'), --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + BUS_RX => regio_rx, + BUS_TX => regio_tx, + BUS_MASTER_IN => open, + BUS_MASTER_OUT => open, + BUS_MASTER_ACTIVE => '0', + ONEWIRE_INOUT => TEMPSENS, + REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE, + --Timing registers + TIMERS_OUT => timer - timing_trg_received_i <= TRIGGER_LEFT; --TRIGGER_RIGHT; -- - common_stat_reg <= (others => '0'); + ); -gen_rdo_tx : for i in 0 to DEVICES-1 generate - fee_trg_release_in(i) <= readout_tx(i).busy_release; - fee_trg_statusbits_in(i*32+31 downto i*32) <= readout_tx(i).statusbits; - fee_data_in(i*32+31 downto i*32) <= readout_tx(i).data; - fee_data_write_in(i) <= readout_tx(i).data_write; - fee_data_finished_in(i) <= readout_tx(i).data_finished; -end generate; --------------------------------------------------------------------------- -- AddOn @@ -376,8 +291,10 @@ gen_reallogic : if USE_DUMMY_READOUT = 0 generate port map( CLK => clk_100_i, CLK_ADCRAW => CLK_PCLK_RIGHT, - - ADCCLK_OUT => P_CLOCK, + CLK_RAW_LEFT => CLK_PCLK_LEFT, + CLK_RAW_RIGHT=> CLK_PCLK_RIGHT, + + ADCCLK_OUT => open, ADC_DATA( 4 downto 0) => ADC1_CH, ADC_DATA( 9 downto 5) => ADC2_CH, ADC_DATA(14 downto 10) => ADC3_CH, @@ -566,10 +483,10 @@ THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- -LED_GREEN <= not med_stat_op(9); -LED_ORANGE <= not med_stat_op(10); +LED_GREEN <= not med2int(0).stat_op(9); +LED_ORANGE <= not med2int(0).stat_op(10); LED_RED <= '1'; -LED_YELLOW <= not med_stat_op(11); +LED_YELLOW <= not med2int(0).stat_op(11); --------------------------------------------------------------------------- -- Test Connector - Logic Analyser -- 2.43.0